iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_ssd1322_nhd31oled_gr.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_ssd1322_nhd31oled_gr.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 2-Bit (4L) Driver for SSD1322 Controller (OLED Display)
iforce2d 0:972874f31c98 6 Tested with NHD-3.12-25664
iforce2d 0:972874f31c98 7
iforce2d 0:972874f31c98 8 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Copyright (c) 2012, olikraus@gmail.com
iforce2d 0:972874f31c98 11 All rights reserved.
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 14 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 17 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 18
iforce2d 0:972874f31c98 19 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 20 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 21 materials provided with the distribution.
iforce2d 0:972874f31c98 22
iforce2d 0:972874f31c98 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 24 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 25 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 26 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 28 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 29 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 33 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 35 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 SSD130x Monochrom OLED Controller
iforce2d 0:972874f31c98 38 SSD131x Character OLED Controller
iforce2d 0:972874f31c98 39 SSD132x Graylevel OLED Controller
iforce2d 0:972874f31c98 40 SSD1331 Color OLED Controller
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42 */
iforce2d 0:972874f31c98 43
iforce2d 0:972874f31c98 44 #include "u8g.h"
iforce2d 0:972874f31c98 45
iforce2d 0:972874f31c98 46 /* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
iforce2d 0:972874f31c98 47 #if defined(U8G_16BIT)
iforce2d 0:972874f31c98 48 #define WIDTH 256
iforce2d 0:972874f31c98 49 #else
iforce2d 0:972874f31c98 50 #define WIDTH 248
iforce2d 0:972874f31c98 51 #endif
iforce2d 0:972874f31c98 52 #define HEIGHT 64
iforce2d 0:972874f31c98 53 //#define PAGE_HEIGHT 8
iforce2d 0:972874f31c98 54
iforce2d 0:972874f31c98 55 /*
iforce2d 0:972874f31c98 56 http://www.newhavendisplay.com/app_notes/OLED_25664.txt
iforce2d 0:972874f31c98 57 http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
iforce2d 0:972874f31c98 58 */
iforce2d 0:972874f31c98 59
iforce2d 0:972874f31c98 60 static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 61 U8G_ESC_DLY(10), /* delay 10 ms */
iforce2d 0:972874f31c98 62 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 63 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 64 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 65 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 66
iforce2d 0:972874f31c98 67 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 68 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 69
iforce2d 0:972874f31c98 70 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 71 0x0fd, /* lock command */
iforce2d 0:972874f31c98 72 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 73 0x012, /* unlock */
iforce2d 0:972874f31c98 74
iforce2d 0:972874f31c98 75 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 76 0x0ae, /* display off, sleep mode */
iforce2d 0:972874f31c98 77
iforce2d 0:972874f31c98 78 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 79 0x0b3,
iforce2d 0:972874f31c98 80 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 81 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
iforce2d 0:972874f31c98 82
iforce2d 0:972874f31c98 83 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 84 0x0ca, /* multiplex ratio */
iforce2d 0:972874f31c98 85 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 86 0x03f, /* 1/64 Duty (0x0F~0x3F) */
iforce2d 0:972874f31c98 87
iforce2d 0:972874f31c98 88 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 89 0x0a2,
iforce2d 0:972874f31c98 90 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 91 0x000, /* display offset, shift mapping ram counter */
iforce2d 0:972874f31c98 92
iforce2d 0:972874f31c98 93 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 94 0x0a1,
iforce2d 0:972874f31c98 95 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 96 0x000, /* display start line */
iforce2d 0:972874f31c98 97
iforce2d 0:972874f31c98 98 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 99 0x0a0, /* Set Re-Map / Dual COM Line Mode */
iforce2d 0:972874f31c98 100 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 101 0x014, /* was 0x014 */
iforce2d 0:972874f31c98 102 0x011, /* was 0x011 */
iforce2d 0:972874f31c98 103
iforce2d 0:972874f31c98 104 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 105 0x0ab,
iforce2d 0:972874f31c98 106 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 107 0x001, /* Enable Internal VDD Regulator */
iforce2d 0:972874f31c98 108
iforce2d 0:972874f31c98 109 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 110 0x0b4, /* Display Enhancement A */
iforce2d 0:972874f31c98 111 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 112 0x0a0,
iforce2d 0:972874f31c98 113 0x005|0x0fd,
iforce2d 0:972874f31c98 114
iforce2d 0:972874f31c98 115 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 116 0x0c1, /* contrast */
iforce2d 0:972874f31c98 117 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 118 0x09f,
iforce2d 0:972874f31c98 119
iforce2d 0:972874f31c98 120 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 121 0x0c7, /* Set Scale Factor of Segment Output Current Control */
iforce2d 0:972874f31c98 122 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 123 0x00f,
iforce2d 0:972874f31c98 124
iforce2d 0:972874f31c98 125 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 126 0x0b9, /* linear gray scale */
iforce2d 0:972874f31c98 127
iforce2d 0:972874f31c98 128 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 129 0x0b1, /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
iforce2d 0:972874f31c98 130 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 131 0x0e2,
iforce2d 0:972874f31c98 132
iforce2d 0:972874f31c98 133 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 134 0x0d1, /* Display Enhancement B */
iforce2d 0:972874f31c98 135 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 136 0x082|0x020,
iforce2d 0:972874f31c98 137 0x020,
iforce2d 0:972874f31c98 138
iforce2d 0:972874f31c98 139 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 140 0x0bb, /* precharge voltage */
iforce2d 0:972874f31c98 141 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 142 0x01f,
iforce2d 0:972874f31c98 143
iforce2d 0:972874f31c98 144 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 145 0x0b6, /* precharge period */
iforce2d 0:972874f31c98 146 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 147 0x008,
iforce2d 0:972874f31c98 148
iforce2d 0:972874f31c98 149 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 150 0x0be, /* vcomh */
iforce2d 0:972874f31c98 151 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 152 0x007,
iforce2d 0:972874f31c98 153
iforce2d 0:972874f31c98 154 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 155 0x0a6, /* normal display */
iforce2d 0:972874f31c98 156
iforce2d 0:972874f31c98 157 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 158 0x0a9, /* exit partial display */
iforce2d 0:972874f31c98 159
iforce2d 0:972874f31c98 160 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 161 0x0af, /* display on */
iforce2d 0:972874f31c98 162
iforce2d 0:972874f31c98 163
iforce2d 0:972874f31c98 164 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 165 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 166 };
iforce2d 0:972874f31c98 167
iforce2d 0:972874f31c98 168 static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq[] PROGMEM = {
iforce2d 0:972874f31c98 169 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 170 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 171 0x015, /* column address... */
iforce2d 0:972874f31c98 172 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 173 0x01c, /* start at column 0 */
iforce2d 0:972874f31c98 174 0x05b, /* end column */
iforce2d 0:972874f31c98 175 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 176 0x075, /* row address... */
iforce2d 0:972874f31c98 177 U8G_ESC_ADR(1), /* data mode */
iforce2d 0:972874f31c98 178 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 179 };
iforce2d 0:972874f31c98 180
iforce2d 0:972874f31c98 181 static void u8g_dev_ssd1322_2bit_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
iforce2d 0:972874f31c98 182 {
iforce2d 0:972874f31c98 183 uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
iforce2d 0:972874f31c98 184
iforce2d 0:972874f31c98 185 row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
iforce2d 0:972874f31c98 186 row += delta_row;
iforce2d 0:972874f31c98 187
iforce2d 0:972874f31c98 188 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq);
iforce2d 0:972874f31c98 189
iforce2d 0:972874f31c98 190 u8g_WriteByte(u8g, dev, row); /* start at the selected row */
iforce2d 0:972874f31c98 191 u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
iforce2d 0:972874f31c98 192
iforce2d 0:972874f31c98 193 u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
iforce2d 0:972874f31c98 194 u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
iforce2d 0:972874f31c98 195 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 196 }
iforce2d 0:972874f31c98 197
iforce2d 0:972874f31c98 198 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
iforce2d 0:972874f31c98 199 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 200 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 201 0x0ae, /* display off */
iforce2d 0:972874f31c98 202 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 203 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 204 };
iforce2d 0:972874f31c98 205
iforce2d 0:972874f31c98 206 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
iforce2d 0:972874f31c98 207 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 208 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 209 0x0af, /* display on */
iforce2d 0:972874f31c98 210 U8G_ESC_DLY(50), /* delay 50 ms */
iforce2d 0:972874f31c98 211 U8G_ESC_CS(1), /* disable chip */
iforce2d 0:972874f31c98 212 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 213 };
iforce2d 0:972874f31c98 214
iforce2d 0:972874f31c98 215 uint8_t u8g_dev_ssd1322_nhd31oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 216 {
iforce2d 0:972874f31c98 217 switch(msg)
iforce2d 0:972874f31c98 218 {
iforce2d 0:972874f31c98 219 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 220 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 221 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
iforce2d 0:972874f31c98 222 break;
iforce2d 0:972874f31c98 223 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 224 break;
iforce2d 0:972874f31c98 225 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 226 {
iforce2d 0:972874f31c98 227 uint8_t i;
iforce2d 0:972874f31c98 228 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 229 uint8_t *p = pb->buf;
iforce2d 0:972874f31c98 230 u8g_uint_t cnt;
iforce2d 0:972874f31c98 231 cnt = pb->width;
iforce2d 0:972874f31c98 232 cnt >>= 2;
iforce2d 0:972874f31c98 233
iforce2d 0:972874f31c98 234 for( i = 0; i < pb->p.page_height; i++ )
iforce2d 0:972874f31c98 235 {
iforce2d 0:972874f31c98 236 u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
iforce2d 0:972874f31c98 237 #if !defined(U8G_16BIT)
iforce2d 0:972874f31c98 238 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 239 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 240 #endif
iforce2d 0:972874f31c98 241 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
iforce2d 0:972874f31c98 242 #if !defined(U8G_16BIT)
iforce2d 0:972874f31c98 243 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 244 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 245 #endif
iforce2d 0:972874f31c98 246 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 247 p+=cnt;
iforce2d 0:972874f31c98 248 }
iforce2d 0:972874f31c98 249 }
iforce2d 0:972874f31c98 250 break;
iforce2d 0:972874f31c98 251 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 252 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 253 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 254 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 255 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 256 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 257 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 258 break;
iforce2d 0:972874f31c98 259 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 260 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 261 return 1;
iforce2d 0:972874f31c98 262 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 263 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 264 return 1;
iforce2d 0:972874f31c98 265 }
iforce2d 0:972874f31c98 266 return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 267 }
iforce2d 0:972874f31c98 268
iforce2d 0:972874f31c98 269
iforce2d 0:972874f31c98 270 uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 271 {
iforce2d 0:972874f31c98 272 switch(msg)
iforce2d 0:972874f31c98 273 {
iforce2d 0:972874f31c98 274 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 275 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 276 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
iforce2d 0:972874f31c98 277 break;
iforce2d 0:972874f31c98 278 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 279 break;
iforce2d 0:972874f31c98 280 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 281 {
iforce2d 0:972874f31c98 282 uint8_t i;
iforce2d 0:972874f31c98 283 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 284 uint8_t *p = pb->buf;
iforce2d 0:972874f31c98 285 u8g_uint_t cnt;
iforce2d 0:972874f31c98 286 cnt = pb->width;
iforce2d 0:972874f31c98 287 cnt >>= 3;
iforce2d 0:972874f31c98 288
iforce2d 0:972874f31c98 289 for( i = 0; i < pb->p.page_height; i++ )
iforce2d 0:972874f31c98 290 {
iforce2d 0:972874f31c98 291 u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
iforce2d 0:972874f31c98 292 #if !defined(U8G_16BIT)
iforce2d 0:972874f31c98 293 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 294 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 295 #endif
iforce2d 0:972874f31c98 296 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
iforce2d 0:972874f31c98 297 #if !defined(U8G_16BIT)
iforce2d 0:972874f31c98 298 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 299 u8g_WriteByte(u8g, dev, 0x00);
iforce2d 0:972874f31c98 300 #endif
iforce2d 0:972874f31c98 301 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 302 p+=cnt;
iforce2d 0:972874f31c98 303 }
iforce2d 0:972874f31c98 304 }
iforce2d 0:972874f31c98 305 break;
iforce2d 0:972874f31c98 306 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 307 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 308 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 309 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 310 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 311 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 312 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 313 break;
iforce2d 0:972874f31c98 314 case U8G_DEV_MSG_SLEEP_ON:
iforce2d 0:972874f31c98 315 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
iforce2d 0:972874f31c98 316 return 1;
iforce2d 0:972874f31c98 317 case U8G_DEV_MSG_SLEEP_OFF:
iforce2d 0:972874f31c98 318 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
iforce2d 0:972874f31c98 319 return 1;
iforce2d 0:972874f31c98 320 }
iforce2d 0:972874f31c98 321 return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 322 }
iforce2d 0:972874f31c98 323
iforce2d 0:972874f31c98 324
iforce2d 0:972874f31c98 325 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 326 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 327 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_parallel , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_FAST_PARALLEL);
iforce2d 0:972874f31c98 328
iforce2d 0:972874f31c98 329
iforce2d 0:972874f31c98 330 #define DWIDTH (WIDTH*2)
iforce2d 0:972874f31c98 331 uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_buf[DWIDTH] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 332 u8g_pb_t u8g_dev_ssd1322_nhd31oled_2x_gr_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1322_nhd31oled_2x_gr_buf};
iforce2d 0:972874f31c98 333 u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_sw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 334 u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_hw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 335
iforce2d 0:972874f31c98 336