hige dura / Mbed 2 deprecated RK4_euler

RK4_euler

Dependencies:   FatFileSystem mbed

Fork of RK4_euler by hige dura

ITG3200.h@7:ec00db826804, 2012-11-29 (annotated)

Committer:
higedura
Date:
Thu Nov 29 15:22:06 2012 +0000
Revision:
7:ec00db826804
Parent:
0:80d32420bc63 
RK4_euler

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UserRevisionLine numberNew contents of line
higedura 0:80d32420bc63 1 /**
higedura 0:80d32420bc63 2 * @author Aaron Berk
higedura 0:80d32420bc63 3 *
higedura 0:80d32420bc63 4 * @section LICENSE
higedura 0:80d32420bc63 5 *
higedura 0:80d32420bc63 6 * Copyright (c) 2010 ARM Limited
higedura 0:80d32420bc63 7 *
higedura 0:80d32420bc63 8 * Permission is hereby granted, free of charge, to any person obtaining a copy
higedura 0:80d32420bc63 9 * of this software and associated documentation files (the "Software"), to deal
higedura 0:80d32420bc63 10 * in the Software without restriction, including without limitation the rights
higedura 0:80d32420bc63 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
higedura 0:80d32420bc63 12 * copies of the Software, and to permit persons to whom the Software is
higedura 0:80d32420bc63 13 * furnished to do so, subject to the following conditions:
higedura 0:80d32420bc63 14 *
higedura 0:80d32420bc63 15 * The above copyright notice and this permission notice shall be included in
higedura 0:80d32420bc63 16 * all copies or substantial portions of the Software.
higedura 0:80d32420bc63 17 *
higedura 0:80d32420bc63 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
higedura 0:80d32420bc63 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
higedura 0:80d32420bc63 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
higedura 0:80d32420bc63 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
higedura 0:80d32420bc63 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
higedura 0:80d32420bc63 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
higedura 0:80d32420bc63 24 * THE SOFTWARE.
higedura 0:80d32420bc63 25 *
higedura 0:80d32420bc63 26 * @section DESCRIPTION
higedura 0:80d32420bc63 27 *
higedura 0:80d32420bc63 28 * ITG-3200 triple axis, digital interface, gyroscope.
higedura 0:80d32420bc63 29 *
higedura 0:80d32420bc63 30 * Datasheet:
higedura 0:80d32420bc63 31 *
higedura 0:80d32420bc63 32 * http://invensense.com/mems/gyro/documents/PS-ITG-3200-00-01.4.pdf
higedura 0:80d32420bc63 33 */
higedura 0:80d32420bc63 34
higedura 0:80d32420bc63 35 #ifndef ITG3200_H
higedura 0:80d32420bc63 36 #define ITG3200_H
higedura 0:80d32420bc63 37
higedura 0:80d32420bc63 38 /**
higedura 0:80d32420bc63 39 * Includes
higedura 0:80d32420bc63 40 */
higedura 0:80d32420bc63 41 #include "mbed.h"
higedura 0:80d32420bc63 42
higedura 0:80d32420bc63 43 /**
higedura 0:80d32420bc63 44 * Defines
higedura 0:80d32420bc63 45 */
higedura 0:80d32420bc63 46 #define ITG3200_I2C_ADDRESS 0x68 //7-bit address.
higedura 0:80d32420bc63 47
higedura 0:80d32420bc63 48 //-----------
higedura 0:80d32420bc63 49 // Registers
higedura 0:80d32420bc63 50 //-----------
higedura 0:80d32420bc63 51 #define WHO_AM_I_REG 0x00
higedura 0:80d32420bc63 52 #define SMPLRT_DIV_REG 0x15
higedura 0:80d32420bc63 53 #define DLPF_FS_REG 0x16
higedura 0:80d32420bc63 54 #define INT_CFG_REG 0x17
higedura 0:80d32420bc63 55 #define INT_STATUS 0x1A
higedura 0:80d32420bc63 56 #define TEMP_OUT_H_REG 0x1B
higedura 0:80d32420bc63 57 #define TEMP_OUT_L_REG 0x1C
higedura 0:80d32420bc63 58 #define GYRO_XOUT_H_REG 0x1D
higedura 0:80d32420bc63 59 #define GYRO_XOUT_L_REG 0x1E
higedura 0:80d32420bc63 60 #define GYRO_YOUT_H_REG 0x1F
higedura 0:80d32420bc63 61 #define GYRO_YOUT_L_REG 0x20
higedura 0:80d32420bc63 62 #define GYRO_ZOUT_H_REG 0x21
higedura 0:80d32420bc63 63 #define GYRO_ZOUT_L_REG 0x22
higedura 0:80d32420bc63 64 #define PWR_MGM_REG 0x3E
higedura 0:80d32420bc63 65
higedura 0:80d32420bc63 66 //----------------------------
higedura 0:80d32420bc63 67 // Low Pass Filter Bandwidths
higedura 0:80d32420bc63 68 //----------------------------
higedura 0:80d32420bc63 69 #define LPFBW_256HZ 0x00
higedura 0:80d32420bc63 70 #define LPFBW_188HZ 0x01
higedura 0:80d32420bc63 71 #define LPFBW_98HZ 0x02
higedura 0:80d32420bc63 72 #define LPFBW_42HZ 0x03
higedura 0:80d32420bc63 73 #define LPFBW_20HZ 0x04
higedura 0:80d32420bc63 74 #define LPFBW_10HZ 0x05
higedura 0:80d32420bc63 75 #define LPFBW_5HZ 0x06
higedura 0:80d32420bc63 76
higedura 0:80d32420bc63 77 /**
higedura 0:80d32420bc63 78 * ITG-3200 triple axis digital gyroscope.
higedura 0:80d32420bc63 79 */
higedura 0:80d32420bc63 80 class ITG3200 {
higedura 0:80d32420bc63 81
higedura 0:80d32420bc63 82 public:
higedura 0:80d32420bc63 83
higedura 0:80d32420bc63 84 /**
higedura 0:80d32420bc63 85 * Constructor.
higedura 0:80d32420bc63 86 *
higedura 0:80d32420bc63 87 * Sets FS_SEL to 0x03 for proper opertaion.
higedura 0:80d32420bc63 88 *
higedura 0:80d32420bc63 89 * @param sda - mbed pin to use for the SDA I2C line.
higedura 0:80d32420bc63 90 * @param scl - mbed pin to use for the SCL I2C line.
higedura 0:80d32420bc63 91 */
higedura 0:80d32420bc63 92 ITG3200(PinName sda, PinName scl);
higedura 0:80d32420bc63 93
higedura 0:80d32420bc63 94 /**
higedura 0:80d32420bc63 95 * Get the identity of the device.
higedura 0:80d32420bc63 96 *
higedura 0:80d32420bc63 97 * @return The contents of the Who Am I register which contains the I2C
higedura 0:80d32420bc63 98 * address of the device.
higedura 0:80d32420bc63 99 */
higedura 0:80d32420bc63 100 char getWhoAmI(void);
higedura 0:80d32420bc63 101
higedura 0:80d32420bc63 102 /**
higedura 0:80d32420bc63 103 * Set the address of the device.
higedura 0:80d32420bc63 104 *
higedura 0:80d32420bc63 105 * @param address The I2C slave address to write to the Who Am I register
higedura 0:80d32420bc63 106 * on the device.
higedura 0:80d32420bc63 107 */
higedura 0:80d32420bc63 108 void setWhoAmI(char address);
higedura 0:80d32420bc63 109
higedura 0:80d32420bc63 110 /**
higedura 0:80d32420bc63 111 * Get the sample rate divider.
higedura 0:80d32420bc63 112 *
higedura 0:80d32420bc63 113 * @return The sample rate divider as a number from 0-255.
higedura 0:80d32420bc63 114 */
higedura 0:80d32420bc63 115 char getSampleRateDivider(void);
higedura 0:80d32420bc63 116
higedura 0:80d32420bc63 117 /**
higedura 0:80d32420bc63 118 * Set the sample rate divider.
higedura 0:80d32420bc63 119 *
higedura 0:80d32420bc63 120 * Fsample = Finternal / (divider + 1), where Finternal = 1kHz or 8kHz,
higedura 0:80d32420bc63 121 * as decidied by the DLPF_FS register.
higedura 0:80d32420bc63 122 *
higedura 0:80d32420bc63 123 * @param The sample rate divider as a number from 0-255.
higedura 0:80d32420bc63 124 */
higedura 0:80d32420bc63 125 void setSampleRateDivider(char divider);
higedura 0:80d32420bc63 126
higedura 0:80d32420bc63 127 /**
higedura 0:80d32420bc63 128 * Get the internal sample rate.
higedura 0:80d32420bc63 129 *
higedura 0:80d32420bc63 130 * @return The internal sample rate in kHz - either 1 or 8.
higedura 0:80d32420bc63 131 */
higedura 0:80d32420bc63 132 int getInternalSampleRate(void);
higedura 0:80d32420bc63 133
higedura 0:80d32420bc63 134 /**
higedura 0:80d32420bc63 135 * Set the low pass filter bandwidth.
higedura 0:80d32420bc63 136 *
higedura 0:80d32420bc63 137 * Also used to set the internal sample rate.
higedura 0:80d32420bc63 138 * Pass the #define bandwidth codes as a parameter.
higedura 0:80d32420bc63 139 *
higedura 0:80d32420bc63 140 * 256Hz -> 8kHz internal sample rate.
higedura 0:80d32420bc63 141 * Everything else -> 1kHz internal rate.
higedura 0:80d32420bc63 142 *
higedura 0:80d32420bc63 143 * @param bandwidth Low pass filter bandwidth code
higedura 0:80d32420bc63 144 */
higedura 0:80d32420bc63 145 void setLpBandwidth(char bandwidth);
higedura 0:80d32420bc63 146
higedura 0:80d32420bc63 147 /**
higedura 0:80d32420bc63 148 * Get the interrupt configuration.
higedura 0:80d32420bc63 149 *
higedura 0:80d32420bc63 150 * See datasheet for register contents details.
higedura 0:80d32420bc63 151 *
higedura 0:80d32420bc63 152 * 7 6 5 4
higedura 0:80d32420bc63 153 * +------+------+--------------+------------------+
higedura 0:80d32420bc63 154 * | ACTL | OPEN | LATCH_INT_EN | INT_ANYRD_2CLEAR |
higedura 0:80d32420bc63 155 * +------+------+--------------+------------------+
higedura 0:80d32420bc63 156 *
higedura 0:80d32420bc63 157 * 3 2 1 0
higedura 0:80d32420bc63 158 * +---+------------+------------+---+
higedura 0:80d32420bc63 159 * | 0 | ITG_RDY_EN | RAW_RDY_EN | 0 |
higedura 0:80d32420bc63 160 * +---+------------+------------+---+
higedura 0:80d32420bc63 161 *
higedura 0:80d32420bc63 162 * ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
higedura 0:80d32420bc63 163 * OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
higedura 0:80d32420bc63 164 * LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
higedura 0:80d32420bc63 165 * 0 = 50us pulse.
higedura 0:80d32420bc63 166 * INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
higedura 0:80d32420bc63 167 * 0 = status register read only.
higedura 0:80d32420bc63 168 * ITG_RDY_EN Enable interrupt when device is ready,
higedura 0:80d32420bc63 169 * (PLL ready after changing clock source).
higedura 0:80d32420bc63 170 * RAW_RDY_EN Enable interrupt when data is available.
higedura 0:80d32420bc63 171 * 0 Bits 1 and 3 of the INT_CFG register should be zero.
higedura 0:80d32420bc63 172 *
higedura 0:80d32420bc63 173 * @return the contents of the INT_CFG register.
higedura 0:80d32420bc63 174 */
higedura 0:80d32420bc63 175 char getInterruptConfiguration(void);
higedura 0:80d32420bc63 176
higedura 0:80d32420bc63 177 /**
higedura 0:80d32420bc63 178 * Set the interrupt configuration.
higedura 0:80d32420bc63 179 *
higedura 0:80d32420bc63 180 * See datasheet for configuration byte details.
higedura 0:80d32420bc63 181 *
higedura 0:80d32420bc63 182 * 7 6 5 4
higedura 0:80d32420bc63 183 * +------+------+--------------+------------------+
higedura 0:80d32420bc63 184 * | ACTL | OPEN | LATCH_INT_EN | INT_ANYRD_2CLEAR |
higedura 0:80d32420bc63 185 * +------+------+--------------+------------------+
higedura 0:80d32420bc63 186 *
higedura 0:80d32420bc63 187 * 3 2 1 0
higedura 0:80d32420bc63 188 * +---+------------+------------+---+
higedura 0:80d32420bc63 189 * | 0 | ITG_RDY_EN | RAW_RDY_EN | 0 |
higedura 0:80d32420bc63 190 * +---+------------+------------+---+
higedura 0:80d32420bc63 191 *
higedura 0:80d32420bc63 192 * ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
higedura 0:80d32420bc63 193 * OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
higedura 0:80d32420bc63 194 * LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
higedura 0:80d32420bc63 195 * 0 = 50us pulse.
higedura 0:80d32420bc63 196 * INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
higedura 0:80d32420bc63 197 * 0 = status register read only.
higedura 0:80d32420bc63 198 * ITG_RDY_EN Enable interrupt when device is ready,
higedura 0:80d32420bc63 199 * (PLL ready after changing clock source).
higedura 0:80d32420bc63 200 * RAW_RDY_EN Enable interrupt when data is available.
higedura 0:80d32420bc63 201 * 0 Bits 1 and 3 of the INT_CFG register should be zero.
higedura 0:80d32420bc63 202 *
higedura 0:80d32420bc63 203 * @param config Configuration byte to write to INT_CFG register.
higedura 0:80d32420bc63 204 */
higedura 0:80d32420bc63 205 void setInterruptConfiguration(char config);
higedura 0:80d32420bc63 206
higedura 0:80d32420bc63 207 /**
higedura 0:80d32420bc63 208 * Check the ITG_RDY bit of the INT_STATUS register.
higedura 0:80d32420bc63 209 *
higedura 0:80d32420bc63 210 * @return True if the ITG_RDY bit is set, corresponding to PLL ready,
higedura 0:80d32420bc63 211 * false if the ITG_RDY bit is not set, corresponding to PLL not
higedura 0:80d32420bc63 212 * ready.
higedura 0:80d32420bc63 213 */
higedura 0:80d32420bc63 214 bool isPllReady(void);
higedura 0:80d32420bc63 215
higedura 0:80d32420bc63 216 /**
higedura 0:80d32420bc63 217 * Check the RAW_DATA_RDY bit of the INT_STATUS register.
higedura 0:80d32420bc63 218 *
higedura 0:80d32420bc63 219 * @return True if the RAW_DATA_RDY bit is set, corresponding to new data
higedura 0:80d32420bc63 220 * in the sensor registers, false if the RAW_DATA_RDY bit is not
higedura 0:80d32420bc63 221 * set, corresponding to no new data yet in the sensor registers.
higedura 0:80d32420bc63 222 */
higedura 0:80d32420bc63 223 bool isRawDataReady(void);
higedura 0:80d32420bc63 224
higedura 0:80d32420bc63 225 /**
higedura 0:80d32420bc63 226 * Get the temperature of the device.
higedura 0:80d32420bc63 227 *
higedura 0:80d32420bc63 228 * @return The temperature in degrees celsius.
higedura 0:80d32420bc63 229 */
higedura 0:80d32420bc63 230 float getTemperature(void);
higedura 0:80d32420bc63 231
higedura 0:80d32420bc63 232 /**
higedura 0:80d32420bc63 233 * Get the output for the x-axis gyroscope.
higedura 0:80d32420bc63 234 *
higedura 0:80d32420bc63 235 * Typical sensitivity is 14.375 LSB/(degrees/sec).
higedura 0:80d32420bc63 236 *
higedura 0:80d32420bc63 237 * @return The output on the x-axis in raw ADC counts.
higedura 0:80d32420bc63 238 */
higedura 0:80d32420bc63 239 int getGyroX(void);
higedura 0:80d32420bc63 240
higedura 0:80d32420bc63 241 /**
higedura 0:80d32420bc63 242 * Get the output for the y-axis gyroscope.
higedura 0:80d32420bc63 243 *
higedura 0:80d32420bc63 244 * Typical sensitivity is 14.375 LSB/(degrees/sec).
higedura 0:80d32420bc63 245 *
higedura 0:80d32420bc63 246 * @return The output on the y-axis in raw ADC counts.
higedura 0:80d32420bc63 247 */
higedura 0:80d32420bc63 248 int getGyroY(void);
higedura 0:80d32420bc63 249
higedura 0:80d32420bc63 250 /**
higedura 0:80d32420bc63 251 * Get the output on the z-axis gyroscope.
higedura 0:80d32420bc63 252 *
higedura 0:80d32420bc63 253 * Typical sensitivity is 14.375 LSB/(degrees/sec).
higedura 0:80d32420bc63 254 *
higedura 0:80d32420bc63 255 * @return The output on the z-axis in raw ADC counts.
higedura 0:80d32420bc63 256 */
higedura 0:80d32420bc63 257 int getGyroZ(void);
higedura 0:80d32420bc63 258
higedura 0:80d32420bc63 259 /**
higedura 0:80d32420bc63 260 * Get the power management configuration.
higedura 0:80d32420bc63 261 *
higedura 0:80d32420bc63 262 * See the datasheet for register contents details.
higedura 0:80d32420bc63 263 *
higedura 0:80d32420bc63 264 * 7 6 5 4
higedura 0:80d32420bc63 265 * +---------+-------+---------+---------+
higedura 0:80d32420bc63 266 * | H_RESET | SLEEP | STBY_XG | STBY_YG |
higedura 0:80d32420bc63 267 * +---------+-------+---------+---------+
higedura 0:80d32420bc63 268 *
higedura 0:80d32420bc63 269 * 3 2 1 0
higedura 0:80d32420bc63 270 * +---------+----------+----------+----------+
higedura 0:80d32420bc63 271 * | STBY_ZG | CLK_SEL2 | CLK_SEL1 | CLK_SEL0 |
higedura 0:80d32420bc63 272 * +---------+----------+----------+----------+
higedura 0:80d32420bc63 273 *
higedura 0:80d32420bc63 274 * H_RESET Reset device and internal registers to the power-up-default settings.
higedura 0:80d32420bc63 275 * SLEEP Enable low power sleep mode.
higedura 0:80d32420bc63 276 * STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 277 * STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 278 * STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 279 * CLK_SEL Select device clock source:
higedura 0:80d32420bc63 280 *
higedura 0:80d32420bc63 281 * CLK_SEL | Clock Source
higedura 0:80d32420bc63 282 * --------+--------------
higedura 0:80d32420bc63 283 * 0 Internal oscillator
higedura 0:80d32420bc63 284 * 1 PLL with X Gyro reference
higedura 0:80d32420bc63 285 * 2 PLL with Y Gyro reference
higedura 0:80d32420bc63 286 * 3 PLL with Z Gyro reference
higedura 0:80d32420bc63 287 * 4 PLL with external 32.768kHz reference
higedura 0:80d32420bc63 288 * 5 PLL with external 19.2MHz reference
higedura 0:80d32420bc63 289 * 6 Reserved
higedura 0:80d32420bc63 290 * 7 Reserved
higedura 0:80d32420bc63 291 *
higedura 0:80d32420bc63 292 * @return The contents of the PWR_MGM register.
higedura 0:80d32420bc63 293 */
higedura 0:80d32420bc63 294 char getPowerManagement(void);
higedura 0:80d32420bc63 295
higedura 0:80d32420bc63 296 /**
higedura 0:80d32420bc63 297 * Set power management configuration.
higedura 0:80d32420bc63 298 *
higedura 0:80d32420bc63 299 * See the datasheet for configuration byte details
higedura 0:80d32420bc63 300 *
higedura 0:80d32420bc63 301 * 7 6 5 4
higedura 0:80d32420bc63 302 * +---------+-------+---------+---------+
higedura 0:80d32420bc63 303 * | H_RESET | SLEEP | STBY_XG | STBY_YG |
higedura 0:80d32420bc63 304 * +---------+-------+---------+---------+
higedura 0:80d32420bc63 305 *
higedura 0:80d32420bc63 306 * 3 2 1 0
higedura 0:80d32420bc63 307 * +---------+----------+----------+----------+
higedura 0:80d32420bc63 308 * | STBY_ZG | CLK_SEL2 | CLK_SEL1 | CLK_SEL0 |
higedura 0:80d32420bc63 309 * +---------+----------+----------+----------+
higedura 0:80d32420bc63 310 *
higedura 0:80d32420bc63 311 * H_RESET Reset device and internal registers to the power-up-default settings.
higedura 0:80d32420bc63 312 * SLEEP Enable low power sleep mode.
higedura 0:80d32420bc63 313 * STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 314 * STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 315 * STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
higedura 0:80d32420bc63 316 * CLK_SEL Select device clock source:
higedura 0:80d32420bc63 317 *
higedura 0:80d32420bc63 318 * CLK_SEL | Clock Source
higedura 0:80d32420bc63 319 * --------+--------------
higedura 0:80d32420bc63 320 * 0 Internal oscillator
higedura 0:80d32420bc63 321 * 1 PLL with X Gyro reference
higedura 0:80d32420bc63 322 * 2 PLL with Y Gyro reference
higedura 0:80d32420bc63 323 * 3 PLL with Z Gyro reference
higedura 0:80d32420bc63 324 * 4 PLL with external 32.768kHz reference
higedura 0:80d32420bc63 325 * 5 PLL with external 19.2MHz reference
higedura 0:80d32420bc63 326 * 6 Reserved
higedura 0:80d32420bc63 327 * 7 Reserved
higedura 0:80d32420bc63 328 *
higedura 0:80d32420bc63 329 * @param config The configuration byte to write to the PWR_MGM register.
higedura 0:80d32420bc63 330 */
higedura 0:80d32420bc63 331 void setPowerManagement(char config);
higedura 0:80d32420bc63 332
higedura 0:80d32420bc63 333 private:
higedura 0:80d32420bc63 334
higedura 0:80d32420bc63 335 I2C i2c_;
higedura 0:80d32420bc63 336
higedura 0:80d32420bc63 337 };
higedura 0:80d32420bc63 338
higedura 0:80d32420bc63 339 #endif /* ITG3200_H */