Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_qei.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_qei.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for QEI firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 2.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 21. May. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup QEI QEI |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_QEI_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_QEI_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "LPC17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 41 | /** @defgroup QEI_Public_Macros QEI Public Macros |
| frank26080115 | 0:84d7747641aa | 42 | * @{ |
| frank26080115 | 0:84d7747641aa | 43 | */ |
| frank26080115 | 0:84d7747641aa | 44 | |
| frank26080115 | 0:84d7747641aa | 45 | /* QEI Reset types */ |
| frank26080115 | 0:84d7747641aa | 46 | #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ |
| frank26080115 | 0:84d7747641aa | 47 | #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ |
| frank26080115 | 0:84d7747641aa | 48 | #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ |
| frank26080115 | 0:84d7747641aa | 49 | #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ |
| frank26080115 | 0:84d7747641aa | 50 | |
| frank26080115 | 0:84d7747641aa | 51 | /* QEI Direction Invert Type Option */ |
| frank26080115 | 0:84d7747641aa | 52 | #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ |
| frank26080115 | 0:84d7747641aa | 53 | #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ |
| frank26080115 | 0:84d7747641aa | 54 | |
| frank26080115 | 0:84d7747641aa | 55 | /* QEI Signal Mode Option */ |
| frank26080115 | 0:84d7747641aa | 56 | #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ |
| frank26080115 | 0:84d7747641aa | 57 | #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ |
| frank26080115 | 0:84d7747641aa | 58 | |
| frank26080115 | 0:84d7747641aa | 59 | /* QEI Capture Mode Option */ |
| frank26080115 | 0:84d7747641aa | 60 | #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ |
| frank26080115 | 0:84d7747641aa | 61 | #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ |
| frank26080115 | 0:84d7747641aa | 62 | |
| frank26080115 | 0:84d7747641aa | 63 | /* QEI Invert Index Signal Option */ |
| frank26080115 | 0:84d7747641aa | 64 | #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ |
| frank26080115 | 0:84d7747641aa | 65 | #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ |
| frank26080115 | 0:84d7747641aa | 66 | |
| frank26080115 | 0:84d7747641aa | 67 | /* QEI timer reload option */ |
| frank26080115 | 0:84d7747641aa | 68 | #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ |
| frank26080115 | 0:84d7747641aa | 69 | #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ |
| frank26080115 | 0:84d7747641aa | 70 | |
| frank26080115 | 0:84d7747641aa | 71 | /* QEI Flag Status type */ |
| frank26080115 | 0:84d7747641aa | 72 | #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ |
| frank26080115 | 0:84d7747641aa | 73 | |
| frank26080115 | 0:84d7747641aa | 74 | /* QEI Compare Position channel option */ |
| frank26080115 | 0:84d7747641aa | 75 | #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ |
| frank26080115 | 0:84d7747641aa | 76 | #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ |
| frank26080115 | 0:84d7747641aa | 77 | #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ |
| frank26080115 | 0:84d7747641aa | 78 | |
| frank26080115 | 0:84d7747641aa | 79 | /* QEI interrupt flag type */ |
| frank26080115 | 0:84d7747641aa | 80 | #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ |
| frank26080115 | 0:84d7747641aa | 81 | #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ |
| frank26080115 | 0:84d7747641aa | 82 | #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ |
| frank26080115 | 0:84d7747641aa | 83 | #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ |
| frank26080115 | 0:84d7747641aa | 84 | #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ |
| frank26080115 | 0:84d7747641aa | 85 | #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ |
| frank26080115 | 0:84d7747641aa | 86 | #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 87 | current position interrupt */ |
| frank26080115 | 0:84d7747641aa | 88 | #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 89 | current position interrupt */ |
| frank26080115 | 0:84d7747641aa | 90 | #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 91 | current position interrupt */ |
| frank26080115 | 0:84d7747641aa | 92 | #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 93 | index count interrupt */ |
| frank26080115 | 0:84d7747641aa | 94 | #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 95 | #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 96 | #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 97 | |
| frank26080115 | 0:84d7747641aa | 98 | /** |
| frank26080115 | 0:84d7747641aa | 99 | * @} |
| frank26080115 | 0:84d7747641aa | 100 | */ |
| frank26080115 | 0:84d7747641aa | 101 | |
| frank26080115 | 0:84d7747641aa | 102 | |
| frank26080115 | 0:84d7747641aa | 103 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 104 | /** @defgroup QEI_Private_Macros QEI Private Macros |
| frank26080115 | 0:84d7747641aa | 105 | * @{ |
| frank26080115 | 0:84d7747641aa | 106 | */ |
| frank26080115 | 0:84d7747641aa | 107 | |
| frank26080115 | 0:84d7747641aa | 108 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 109 | /* Quadrature Encoder Interface Control Register Definition --------------------- */ |
| frank26080115 | 0:84d7747641aa | 110 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 111 | * Macro defines for QEI Control register |
| frank26080115 | 0:84d7747641aa | 112 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 113 | #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ |
| frank26080115 | 0:84d7747641aa | 114 | #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ |
| frank26080115 | 0:84d7747641aa | 115 | #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ |
| frank26080115 | 0:84d7747641aa | 116 | #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ |
| frank26080115 | 0:84d7747641aa | 117 | #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 118 | |
| frank26080115 | 0:84d7747641aa | 119 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 120 | * Macro defines for QEI Configuration register |
| frank26080115 | 0:84d7747641aa | 121 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 122 | #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ |
| frank26080115 | 0:84d7747641aa | 123 | #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ |
| frank26080115 | 0:84d7747641aa | 124 | #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ |
| frank26080115 | 0:84d7747641aa | 125 | #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ |
| frank26080115 | 0:84d7747641aa | 126 | #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 127 | |
| frank26080115 | 0:84d7747641aa | 128 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 129 | * Macro defines for QEI Status register |
| frank26080115 | 0:84d7747641aa | 130 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 131 | #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ |
| frank26080115 | 0:84d7747641aa | 132 | #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 133 | |
| frank26080115 | 0:84d7747641aa | 134 | /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ |
| frank26080115 | 0:84d7747641aa | 135 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 136 | * Macro defines for QEI Interrupt Status register |
| frank26080115 | 0:84d7747641aa | 137 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 138 | #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 139 | #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 140 | #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 141 | #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 142 | #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 143 | #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 144 | #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 145 | current position */ |
| frank26080115 | 0:84d7747641aa | 146 | #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 147 | current position */ |
| frank26080115 | 0:84d7747641aa | 148 | #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 149 | current position */ |
| frank26080115 | 0:84d7747641aa | 150 | #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 151 | index count */ |
| frank26080115 | 0:84d7747641aa | 152 | #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when |
| frank26080115 | 0:84d7747641aa | 153 | both the POS0_Int bit is set and the REV_Int is set */ |
| frank26080115 | 0:84d7747641aa | 154 | #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when |
| frank26080115 | 0:84d7747641aa | 155 | both the POS1_Int bit is set and the REV_Int is set */ |
| frank26080115 | 0:84d7747641aa | 156 | #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when |
| frank26080115 | 0:84d7747641aa | 157 | both the POS2_Int bit is set and the REV_Int is set */ |
| frank26080115 | 0:84d7747641aa | 158 | #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 159 | |
| frank26080115 | 0:84d7747641aa | 160 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 161 | * Macro defines for QEI Interrupt Set register |
| frank26080115 | 0:84d7747641aa | 162 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 163 | #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 164 | #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 165 | #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 166 | #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 167 | #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 168 | #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 169 | #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 170 | current position */ |
| frank26080115 | 0:84d7747641aa | 171 | #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 172 | current position */ |
| frank26080115 | 0:84d7747641aa | 173 | #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 174 | current position */ |
| frank26080115 | 0:84d7747641aa | 175 | #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 176 | index count */ |
| frank26080115 | 0:84d7747641aa | 177 | #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 178 | #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 179 | #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 180 | #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 181 | |
| frank26080115 | 0:84d7747641aa | 182 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 183 | * Macro defines for QEI Interrupt Clear register |
| frank26080115 | 0:84d7747641aa | 184 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 185 | #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 186 | #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 187 | #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 188 | #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 189 | #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 190 | #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 191 | #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 192 | current position */ |
| frank26080115 | 0:84d7747641aa | 193 | #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 194 | current position */ |
| frank26080115 | 0:84d7747641aa | 195 | #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 196 | current position */ |
| frank26080115 | 0:84d7747641aa | 197 | #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 198 | index count */ |
| frank26080115 | 0:84d7747641aa | 199 | #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 200 | #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 201 | #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 202 | #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 203 | |
| frank26080115 | 0:84d7747641aa | 204 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 205 | * Macro defines for QEI Interrupt Enable register |
| frank26080115 | 0:84d7747641aa | 206 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 207 | #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 208 | #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 209 | #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 210 | #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 211 | #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 212 | #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 213 | #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 214 | current position */ |
| frank26080115 | 0:84d7747641aa | 215 | #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 216 | current position */ |
| frank26080115 | 0:84d7747641aa | 217 | #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 218 | current position */ |
| frank26080115 | 0:84d7747641aa | 219 | #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 220 | index count */ |
| frank26080115 | 0:84d7747641aa | 221 | #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 222 | #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 223 | #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 224 | #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 225 | |
| frank26080115 | 0:84d7747641aa | 226 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 227 | * Macro defines for QEI Interrupt Enable Set register |
| frank26080115 | 0:84d7747641aa | 228 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 229 | #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 230 | #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 231 | #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 232 | #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 233 | #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 234 | #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 235 | #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 236 | current position */ |
| frank26080115 | 0:84d7747641aa | 237 | #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 238 | current position */ |
| frank26080115 | 0:84d7747641aa | 239 | #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 240 | current position */ |
| frank26080115 | 0:84d7747641aa | 241 | #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 242 | index count */ |
| frank26080115 | 0:84d7747641aa | 243 | #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 244 | #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 245 | #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 246 | #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 247 | |
| frank26080115 | 0:84d7747641aa | 248 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 249 | * Macro defines for QEI Interrupt Enable Clear register |
| frank26080115 | 0:84d7747641aa | 250 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 251 | #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 252 | #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| frank26080115 | 0:84d7747641aa | 253 | #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| frank26080115 | 0:84d7747641aa | 254 | #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| frank26080115 | 0:84d7747641aa | 255 | #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| frank26080115 | 0:84d7747641aa | 256 | #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| frank26080115 | 0:84d7747641aa | 257 | #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 258 | current position */ |
| frank26080115 | 0:84d7747641aa | 259 | #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 260 | current position */ |
| frank26080115 | 0:84d7747641aa | 261 | #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| frank26080115 | 0:84d7747641aa | 262 | current position */ |
| frank26080115 | 0:84d7747641aa | 263 | #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| frank26080115 | 0:84d7747641aa | 264 | index count */ |
| frank26080115 | 0:84d7747641aa | 265 | #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 266 | #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 267 | #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| frank26080115 | 0:84d7747641aa | 268 | #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ |
| frank26080115 | 0:84d7747641aa | 269 | |
| frank26080115 | 0:84d7747641aa | 270 | |
| frank26080115 | 0:84d7747641aa | 271 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| frank26080115 | 0:84d7747641aa | 272 | /* Macro check QEI peripheral */ |
| frank26080115 | 0:84d7747641aa | 273 | #define PARAM_QEIx(n) ((n==LPC_QEI)) |
| frank26080115 | 0:84d7747641aa | 274 | |
| frank26080115 | 0:84d7747641aa | 275 | /* Macro check QEI reset type */ |
| frank26080115 | 0:84d7747641aa | 276 | #define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \ |
| frank26080115 | 0:84d7747641aa | 277 | || (n==QEI_RESET_POSOnIDX) \ |
| frank26080115 | 0:84d7747641aa | 278 | || (n==QEI_RESET_VEL) \ |
| frank26080115 | 0:84d7747641aa | 279 | || (n==QEI_RESET_IDX)) |
| frank26080115 | 0:84d7747641aa | 280 | |
| frank26080115 | 0:84d7747641aa | 281 | /* Macro check QEI Direction invert mode */ |
| frank26080115 | 0:84d7747641aa | 282 | #define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL)) |
| frank26080115 | 0:84d7747641aa | 283 | |
| frank26080115 | 0:84d7747641aa | 284 | /* Macro check QEI signal mode */ |
| frank26080115 | 0:84d7747641aa | 285 | #define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR)) |
| frank26080115 | 0:84d7747641aa | 286 | |
| frank26080115 | 0:84d7747641aa | 287 | /* Macro check QEI Capture mode */ |
| frank26080115 | 0:84d7747641aa | 288 | #define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X)) |
| frank26080115 | 0:84d7747641aa | 289 | |
| frank26080115 | 0:84d7747641aa | 290 | /* Macro check QEI Invert index mode */ |
| frank26080115 | 0:84d7747641aa | 291 | #define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN)) |
| frank26080115 | 0:84d7747641aa | 292 | |
| frank26080115 | 0:84d7747641aa | 293 | /* Macro check QEI Direction invert mode */ |
| frank26080115 | 0:84d7747641aa | 294 | #define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL)) |
| frank26080115 | 0:84d7747641aa | 295 | |
| frank26080115 | 0:84d7747641aa | 296 | /* Macro check QEI status type */ |
| frank26080115 | 0:84d7747641aa | 297 | #define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR)) |
| frank26080115 | 0:84d7747641aa | 298 | |
| frank26080115 | 0:84d7747641aa | 299 | /* Macro check QEI combine position type */ |
| frank26080115 | 0:84d7747641aa | 300 | #define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2)) |
| frank26080115 | 0:84d7747641aa | 301 | |
| frank26080115 | 0:84d7747641aa | 302 | /* Macro check QEI interrupt flag type */ |
| frank26080115 | 0:84d7747641aa | 303 | #define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \ |
| frank26080115 | 0:84d7747641aa | 304 | || (n==QEI_INTFLAG_TIM_Int) \ |
| frank26080115 | 0:84d7747641aa | 305 | || (n==QEI_INTFLAG_VELC_Int) \ |
| frank26080115 | 0:84d7747641aa | 306 | || (n==QEI_INTFLAG_DIR_Int) \ |
| frank26080115 | 0:84d7747641aa | 307 | || (n==QEI_INTFLAG_ERR_Int) \ |
| frank26080115 | 0:84d7747641aa | 308 | || (n==QEI_INTFLAG_ENCLK_Int) \ |
| frank26080115 | 0:84d7747641aa | 309 | || (n==QEI_INTFLAG_POS0_Int) \ |
| frank26080115 | 0:84d7747641aa | 310 | || (n==QEI_INTFLAG_POS1_Int) \ |
| frank26080115 | 0:84d7747641aa | 311 | || (n==QEI_INTFLAG_POS2_Int) \ |
| frank26080115 | 0:84d7747641aa | 312 | || (n==QEI_INTFLAG_REV_Int) \ |
| frank26080115 | 0:84d7747641aa | 313 | || (n==QEI_INTFLAG_POS0REV_Int) \ |
| frank26080115 | 0:84d7747641aa | 314 | || (n==QEI_INTFLAG_POS1REV_Int) \ |
| frank26080115 | 0:84d7747641aa | 315 | || (n==QEI_INTFLAG_POS2REV_Int)) |
| frank26080115 | 0:84d7747641aa | 316 | /** |
| frank26080115 | 0:84d7747641aa | 317 | * @} |
| frank26080115 | 0:84d7747641aa | 318 | */ |
| frank26080115 | 0:84d7747641aa | 319 | |
| frank26080115 | 0:84d7747641aa | 320 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 321 | /** @defgroup QEI_Public_Types QEI Public Types |
| frank26080115 | 0:84d7747641aa | 322 | * @{ |
| frank26080115 | 0:84d7747641aa | 323 | */ |
| frank26080115 | 0:84d7747641aa | 324 | |
| frank26080115 | 0:84d7747641aa | 325 | /** |
| frank26080115 | 0:84d7747641aa | 326 | * @brief QEI Configuration structure type definition |
| frank26080115 | 0:84d7747641aa | 327 | */ |
| frank26080115 | 0:84d7747641aa | 328 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 329 | uint32_t DirectionInvert :1; /**< Direction invert option: |
| frank26080115 | 0:84d7747641aa | 330 | - QEI_DIRINV_NONE: QEI Direction is normal |
| frank26080115 | 0:84d7747641aa | 331 | - QEI_DIRINV_CMPL: QEI Direction is complemented |
| frank26080115 | 0:84d7747641aa | 332 | */ |
| frank26080115 | 0:84d7747641aa | 333 | uint32_t SignalMode :1; /**< Signal mode Option: |
| frank26080115 | 0:84d7747641aa | 334 | - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode |
| frank26080115 | 0:84d7747641aa | 335 | - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode |
| frank26080115 | 0:84d7747641aa | 336 | */ |
| frank26080115 | 0:84d7747641aa | 337 | uint32_t CaptureMode :1; /**< Capture Mode Option: |
| frank26080115 | 0:84d7747641aa | 338 | - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X) |
| frank26080115 | 0:84d7747641aa | 339 | - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X) |
| frank26080115 | 0:84d7747641aa | 340 | */ |
| frank26080115 | 0:84d7747641aa | 341 | uint32_t InvertIndex :1; /**< Invert Index Option: |
| frank26080115 | 0:84d7747641aa | 342 | - QEI_INVINX_NONE: the sense of the index input is normal |
| frank26080115 | 0:84d7747641aa | 343 | - QEI_INVINX_EN: inverts the sense of the index input |
| frank26080115 | 0:84d7747641aa | 344 | */ |
| frank26080115 | 0:84d7747641aa | 345 | } QEI_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 346 | |
| frank26080115 | 0:84d7747641aa | 347 | /** |
| frank26080115 | 0:84d7747641aa | 348 | * @brief Timer Reload Configuration structure type definition |
| frank26080115 | 0:84d7747641aa | 349 | */ |
| frank26080115 | 0:84d7747641aa | 350 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 351 | |
| frank26080115 | 0:84d7747641aa | 352 | uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be: |
| frank26080115 | 0:84d7747641aa | 353 | - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value |
| frank26080115 | 0:84d7747641aa | 354 | - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value |
| frank26080115 | 0:84d7747641aa | 355 | */ |
| frank26080115 | 0:84d7747641aa | 356 | uint8_t Reserved[3]; |
| frank26080115 | 0:84d7747641aa | 357 | uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched |
| frank26080115 | 0:84d7747641aa | 358 | with Velocity Timer Reload Option |
| frank26080115 | 0:84d7747641aa | 359 | */ |
| frank26080115 | 0:84d7747641aa | 360 | } QEI_RELOADCFG_Type; |
| frank26080115 | 0:84d7747641aa | 361 | |
| frank26080115 | 0:84d7747641aa | 362 | /** |
| frank26080115 | 0:84d7747641aa | 363 | * @} |
| frank26080115 | 0:84d7747641aa | 364 | */ |
| frank26080115 | 0:84d7747641aa | 365 | |
| frank26080115 | 0:84d7747641aa | 366 | |
| frank26080115 | 0:84d7747641aa | 367 | |
| frank26080115 | 0:84d7747641aa | 368 | |
| frank26080115 | 0:84d7747641aa | 369 | |
| frank26080115 | 0:84d7747641aa | 370 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 371 | /** @defgroup QEI_Public_Functions QEI Public Functions |
| frank26080115 | 0:84d7747641aa | 372 | * @{ |
| frank26080115 | 0:84d7747641aa | 373 | */ |
| frank26080115 | 0:84d7747641aa | 374 | |
| frank26080115 | 0:84d7747641aa | 375 | void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType); |
| frank26080115 | 0:84d7747641aa | 376 | void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct); |
| frank26080115 | 0:84d7747641aa | 377 | void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct); |
| frank26080115 | 0:84d7747641aa | 378 | void QEI_DeInit(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 379 | FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType); |
| frank26080115 | 0:84d7747641aa | 380 | uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 381 | void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos); |
| frank26080115 | 0:84d7747641aa | 382 | void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp); |
| frank26080115 | 0:84d7747641aa | 383 | uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 384 | void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp); |
| frank26080115 | 0:84d7747641aa | 385 | void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct); |
| frank26080115 | 0:84d7747641aa | 386 | uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 387 | uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 388 | uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx); |
| frank26080115 | 0:84d7747641aa | 389 | void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp); |
| frank26080115 | 0:84d7747641aa | 390 | void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse); |
| frank26080115 | 0:84d7747641aa | 391 | FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 392 | void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 393 | void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 394 | void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 395 | uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR); |
| frank26080115 | 0:84d7747641aa | 396 | |
| frank26080115 | 0:84d7747641aa | 397 | |
| frank26080115 | 0:84d7747641aa | 398 | /** |
| frank26080115 | 0:84d7747641aa | 399 | * @} |
| frank26080115 | 0:84d7747641aa | 400 | */ |
| frank26080115 | 0:84d7747641aa | 401 | |
| frank26080115 | 0:84d7747641aa | 402 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 403 | } |
| frank26080115 | 0:84d7747641aa | 404 | #endif |
| frank26080115 | 0:84d7747641aa | 405 | |
| frank26080115 | 0:84d7747641aa | 406 | #endif /* LPC17XX_QEI_H_ */ |
| frank26080115 | 0:84d7747641aa | 407 | |
| frank26080115 | 0:84d7747641aa | 408 | /** |
| frank26080115 | 0:84d7747641aa | 409 | * @} |
| frank26080115 | 0:84d7747641aa | 410 | */ |
| frank26080115 | 0:84d7747641aa | 411 | |
| frank26080115 | 0:84d7747641aa | 412 | /* --------------------------------- End Of File ------------------------------ */ |