Filippo Casamassima / mbed

my fork

Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

LPC11U24/uARM/core_cm0.h@39:737756e0b479, 2012-03-12 (annotated)

Committer:
emilmont
Date:
Mon Mar 12 11:16:34 2012 +0000
Revision:
39:737756e0b479
Parent:
31:a7ef757f598c 
[12 March 2012] Update CMSIS core to V3.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cm0.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
emilmont 39:737756e0b479 4 * @version V3.01
emilmont 39:737756e0b479 5 * @date 06. March 2012
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 39:737756e0b479 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 31:a7ef757f598c 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 31:a7ef757f598c 12 * processor based microcontrollers. This file can be freely distributed
emilmont 31:a7ef757f598c 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 31:a7ef757f598c 23 #if defined ( __ICCARM__ )
emilmont 27:7110ebee3484 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 27:7110ebee3484 25 #endif
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 #ifdef __cplusplus
emilmont 27:7110ebee3484 28 extern "C" {
emilmont 31:a7ef757f598c 29 #endif
emilmont 27:7110ebee3484 30
emilmont 27:7110ebee3484 31 #ifndef __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 32 #define __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 33
emilmont 31:a7ef757f598c 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 31:a7ef757f598c 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 39:737756e0b479 36
emilmont 31:a7ef757f598c 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 39:737756e0b479 38 Function definitions in header files are used to allow 'inlining'.
emilmont 27:7110ebee3484 39
emilmont 31:a7ef757f598c 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 31:a7ef757f598c 41 Unions are used for effective representation of core registers.
emilmont 39:737756e0b479 42
emilmont 31:a7ef757f598c 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 39:737756e0b479 44 Function-like macros are used to allow more efficient code.
emilmont 27:7110ebee3484 45 */
emilmont 27:7110ebee3484 46
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48 /*******************************************************************************
emilmont 27:7110ebee3484 49 * CMSIS definitions
emilmont 27:7110ebee3484 50 ******************************************************************************/
emilmont 31:a7ef757f598c 51 /** \ingroup Cortex_M0
emilmont 27:7110ebee3484 52 @{
emilmont 27:7110ebee3484 53 */
emilmont 27:7110ebee3484 54
emilmont 27:7110ebee3484 55 /* CMSIS CM0 definitions */
emilmont 31:a7ef757f598c 56 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 39:737756e0b479 57 #define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
emilmont 31:a7ef757f598c 58 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 31:a7ef757f598c 59 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 27:7110ebee3484 60
emilmont 31:a7ef757f598c 61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 27:7110ebee3484 62
emilmont 27:7110ebee3484 63
emilmont 31:a7ef757f598c 64 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 27:7110ebee3484 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 39:737756e0b479 67 #define __STATIC_INLINE static __inline
emilmont 27:7110ebee3484 68
emilmont 27:7110ebee3484 69 #elif defined ( __ICCARM__ )
emilmont 39:737756e0b479 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 39:737756e0b479 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 39:737756e0b479 72 #define __STATIC_INLINE static inline
emilmont 27:7110ebee3484 73
emilmont 31:a7ef757f598c 74 #elif defined ( __GNUC__ )
emilmont 27:7110ebee3484 75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 27:7110ebee3484 76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 39:737756e0b479 77 #define __STATIC_INLINE static inline
emilmont 27:7110ebee3484 78
emilmont 31:a7ef757f598c 79 #elif defined ( __TASKING__ )
emilmont 27:7110ebee3484 80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 27:7110ebee3484 81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 39:737756e0b479 82 #define __STATIC_INLINE static inline
emilmont 27:7110ebee3484 83
emilmont 27:7110ebee3484 84 #endif
emilmont 27:7110ebee3484 85
emilmont 31:a7ef757f598c 86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 31:a7ef757f598c 87 */
emilmont 31:a7ef757f598c 88 #define __FPU_USED 0
emilmont 31:a7ef757f598c 89
emilmont 31:a7ef757f598c 90 #if defined ( __CC_ARM )
emilmont 31:a7ef757f598c 91 #if defined __TARGET_FPU_VFP
emilmont 31:a7ef757f598c 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 93 #endif
emilmont 31:a7ef757f598c 94
emilmont 31:a7ef757f598c 95 #elif defined ( __ICCARM__ )
emilmont 31:a7ef757f598c 96 #if defined __ARMVFP__
emilmont 31:a7ef757f598c 97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 98 #endif
emilmont 31:a7ef757f598c 99
emilmont 31:a7ef757f598c 100 #elif defined ( __GNUC__ )
emilmont 31:a7ef757f598c 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 31:a7ef757f598c 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 31:a7ef757f598c 103 #endif
emilmont 31:a7ef757f598c 104
emilmont 31:a7ef757f598c 105 #elif defined ( __TASKING__ )
emilmont 31:a7ef757f598c 106 /* add preprocessor checks */
emilmont 31:a7ef757f598c 107 #endif
emilmont 31:a7ef757f598c 108
emilmont 31:a7ef757f598c 109 #include <stdint.h> /* standard types definitions */
emilmont 31:a7ef757f598c 110 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 31:a7ef757f598c 111 #include <core_cmFunc.h> /* Core Function Access */
emilmont 27:7110ebee3484 112
emilmont 27:7110ebee3484 113 #endif /* __CORE_CM0_H_GENERIC */
emilmont 27:7110ebee3484 114
emilmont 27:7110ebee3484 115 #ifndef __CMSIS_GENERIC
emilmont 27:7110ebee3484 116
emilmont 27:7110ebee3484 117 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 118 #define __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 119
emilmont 31:a7ef757f598c 120 /* check device defines and use defaults */
emilmont 31:a7ef757f598c 121 #if defined __CHECK_DEVICE_DEFINES
emilmont 31:a7ef757f598c 122 #ifndef __CM0_REV
emilmont 31:a7ef757f598c 123 #define __CM0_REV 0x0000
emilmont 31:a7ef757f598c 124 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 31:a7ef757f598c 125 #endif
emilmont 31:a7ef757f598c 126
emilmont 31:a7ef757f598c 127 #ifndef __NVIC_PRIO_BITS
emilmont 31:a7ef757f598c 128 #define __NVIC_PRIO_BITS 2
emilmont 31:a7ef757f598c 129 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 31:a7ef757f598c 130 #endif
emilmont 31:a7ef757f598c 131
emilmont 31:a7ef757f598c 132 #ifndef __Vendor_SysTickConfig
emilmont 31:a7ef757f598c 133 #define __Vendor_SysTickConfig 0
emilmont 31:a7ef757f598c 134 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 31:a7ef757f598c 135 #endif
emilmont 31:a7ef757f598c 136 #endif
emilmont 31:a7ef757f598c 137
emilmont 27:7110ebee3484 138 /* IO definitions (access restrictions to peripheral registers) */
emilmont 31:a7ef757f598c 139 /**
emilmont 31:a7ef757f598c 140 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 39:737756e0b479 141
emilmont 31:a7ef757f598c 142 <strong>IO Type Qualifiers</strong> are used
emilmont 31:a7ef757f598c 143 \li to specify the access to peripheral variables.
emilmont 31:a7ef757f598c 144 \li for automatic generation of peripheral register debug information.
emilmont 31:a7ef757f598c 145 */
emilmont 27:7110ebee3484 146 #ifdef __cplusplus
emilmont 31:a7ef757f598c 147 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 27:7110ebee3484 148 #else
emilmont 31:a7ef757f598c 149 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 27:7110ebee3484 150 #endif
emilmont 31:a7ef757f598c 151 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 31:a7ef757f598c 152 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 27:7110ebee3484 153
emilmont 31:a7ef757f598c 154 /*@} end of group Cortex_M0 */
emilmont 27:7110ebee3484 155
emilmont 27:7110ebee3484 156
emilmont 27:7110ebee3484 157
emilmont 27:7110ebee3484 158 /*******************************************************************************
emilmont 27:7110ebee3484 159 * Register Abstraction
emilmont 27:7110ebee3484 160 Core Register contain:
emilmont 27:7110ebee3484 161 - Core Register
emilmont 27:7110ebee3484 162 - Core NVIC Register
emilmont 27:7110ebee3484 163 - Core SCB Register
emilmont 27:7110ebee3484 164 - Core SysTick Register
emilmont 31:a7ef757f598c 165 ******************************************************************************/
emilmont 31:a7ef757f598c 166 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 31:a7ef757f598c 167 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 27:7110ebee3484 168 */
emilmont 27:7110ebee3484 169
emilmont 31:a7ef757f598c 170 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 171 \defgroup CMSIS_CORE Status and Control Registers
emilmont 31:a7ef757f598c 172 \brief Core Register type definitions.
emilmont 27:7110ebee3484 173 @{
emilmont 27:7110ebee3484 174 */
emilmont 27:7110ebee3484 175
emilmont 27:7110ebee3484 176 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 27:7110ebee3484 177 */
emilmont 27:7110ebee3484 178 typedef union
emilmont 27:7110ebee3484 179 {
emilmont 27:7110ebee3484 180 struct
emilmont 27:7110ebee3484 181 {
emilmont 27:7110ebee3484 182 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 183 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 27:7110ebee3484 184 #else
emilmont 27:7110ebee3484 185 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 27:7110ebee3484 186 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 187 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 27:7110ebee3484 188 #endif
emilmont 27:7110ebee3484 189 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 190 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 191 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 192 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 193 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 194 } b; /*!< Structure used for bit access */
emilmont 31:a7ef757f598c 195 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 196 } APSR_Type;
emilmont 27:7110ebee3484 197
emilmont 27:7110ebee3484 198
emilmont 27:7110ebee3484 199 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 27:7110ebee3484 200 */
emilmont 27:7110ebee3484 201 typedef union
emilmont 27:7110ebee3484 202 {
emilmont 27:7110ebee3484 203 struct
emilmont 27:7110ebee3484 204 {
emilmont 27:7110ebee3484 205 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 206 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 27:7110ebee3484 207 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 208 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 209 } IPSR_Type;
emilmont 27:7110ebee3484 210
emilmont 27:7110ebee3484 211
emilmont 27:7110ebee3484 212 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 27:7110ebee3484 213 */
emilmont 27:7110ebee3484 214 typedef union
emilmont 27:7110ebee3484 215 {
emilmont 27:7110ebee3484 216 struct
emilmont 27:7110ebee3484 217 {
emilmont 27:7110ebee3484 218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 219 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 220 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 27:7110ebee3484 221 #else
emilmont 27:7110ebee3484 222 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 27:7110ebee3484 223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 224 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 27:7110ebee3484 225 #endif
emilmont 27:7110ebee3484 226 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 27:7110ebee3484 227 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 27:7110ebee3484 228 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 233 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 234 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 235 } xPSR_Type;
emilmont 27:7110ebee3484 236
emilmont 27:7110ebee3484 237
emilmont 27:7110ebee3484 238 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 27:7110ebee3484 239 */
emilmont 27:7110ebee3484 240 typedef union
emilmont 27:7110ebee3484 241 {
emilmont 27:7110ebee3484 242 struct
emilmont 27:7110ebee3484 243 {
emilmont 27:7110ebee3484 244 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 27:7110ebee3484 245 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 27:7110ebee3484 246 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 27:7110ebee3484 247 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 27:7110ebee3484 248 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 249 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 250 } CONTROL_Type;
emilmont 27:7110ebee3484 251
emilmont 27:7110ebee3484 252 /*@} end of group CMSIS_CORE */
emilmont 27:7110ebee3484 253
emilmont 27:7110ebee3484 254
emilmont 31:a7ef757f598c 255 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 256 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 31:a7ef757f598c 257 \brief Type definitions for the NVIC Registers
emilmont 27:7110ebee3484 258 @{
emilmont 27:7110ebee3484 259 */
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 27:7110ebee3484 262 */
emilmont 27:7110ebee3484 263 typedef struct
emilmont 27:7110ebee3484 264 {
emilmont 27:7110ebee3484 265 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 27:7110ebee3484 266 uint32_t RESERVED0[31];
emilmont 27:7110ebee3484 267 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 27:7110ebee3484 268 uint32_t RSERVED1[31];
emilmont 27:7110ebee3484 269 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 27:7110ebee3484 270 uint32_t RESERVED2[31];
emilmont 27:7110ebee3484 271 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 27:7110ebee3484 272 uint32_t RESERVED3[31];
emilmont 27:7110ebee3484 273 uint32_t RESERVED4[64];
emilmont 31:a7ef757f598c 274 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 27:7110ebee3484 275 } NVIC_Type;
emilmont 27:7110ebee3484 276
emilmont 27:7110ebee3484 277 /*@} end of group CMSIS_NVIC */
emilmont 27:7110ebee3484 278
emilmont 27:7110ebee3484 279
emilmont 31:a7ef757f598c 280 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 281 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 31:a7ef757f598c 282 \brief Type definitions for the System Control Block Registers
emilmont 27:7110ebee3484 283 @{
emilmont 27:7110ebee3484 284 */
emilmont 27:7110ebee3484 285
emilmont 27:7110ebee3484 286 /** \brief Structure type to access the System Control Block (SCB).
emilmont 27:7110ebee3484 287 */
emilmont 27:7110ebee3484 288 typedef struct
emilmont 27:7110ebee3484 289 {
emilmont 31:a7ef757f598c 290 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 31:a7ef757f598c 291 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 31:a7ef757f598c 292 uint32_t RESERVED0;
emilmont 31:a7ef757f598c 293 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 27:7110ebee3484 294 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 27:7110ebee3484 295 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 31:a7ef757f598c 296 uint32_t RESERVED1;
emilmont 27:7110ebee3484 297 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 31:a7ef757f598c 298 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 31:a7ef757f598c 299 } SCB_Type;
emilmont 27:7110ebee3484 300
emilmont 27:7110ebee3484 301 /* SCB CPUID Register Definitions */
emilmont 27:7110ebee3484 302 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 27:7110ebee3484 303 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 27:7110ebee3484 304
emilmont 27:7110ebee3484 305 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 27:7110ebee3484 306 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 27:7110ebee3484 307
emilmont 27:7110ebee3484 308 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 27:7110ebee3484 309 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 27:7110ebee3484 310
emilmont 27:7110ebee3484 311 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 27:7110ebee3484 312 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 27:7110ebee3484 313
emilmont 27:7110ebee3484 314 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 27:7110ebee3484 315 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 27:7110ebee3484 316
emilmont 27:7110ebee3484 317 /* SCB Interrupt Control State Register Definitions */
emilmont 27:7110ebee3484 318 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 27:7110ebee3484 319 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 27:7110ebee3484 320
emilmont 27:7110ebee3484 321 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 27:7110ebee3484 322 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 27:7110ebee3484 323
emilmont 27:7110ebee3484 324 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 27:7110ebee3484 325 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 27:7110ebee3484 326
emilmont 27:7110ebee3484 327 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 27:7110ebee3484 328 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 27:7110ebee3484 329
emilmont 27:7110ebee3484 330 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 27:7110ebee3484 331 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 27:7110ebee3484 332
emilmont 27:7110ebee3484 333 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 27:7110ebee3484 334 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 27:7110ebee3484 335
emilmont 27:7110ebee3484 336 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 27:7110ebee3484 337 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 27:7110ebee3484 338
emilmont 27:7110ebee3484 339 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 27:7110ebee3484 340 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 27:7110ebee3484 341
emilmont 27:7110ebee3484 342 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 27:7110ebee3484 343 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 27:7110ebee3484 344
emilmont 27:7110ebee3484 345 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 27:7110ebee3484 346 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 27:7110ebee3484 347 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 27:7110ebee3484 348
emilmont 27:7110ebee3484 349 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 27:7110ebee3484 350 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 27:7110ebee3484 351
emilmont 27:7110ebee3484 352 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 27:7110ebee3484 353 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 27:7110ebee3484 354
emilmont 27:7110ebee3484 355 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 27:7110ebee3484 356 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 27:7110ebee3484 357
emilmont 27:7110ebee3484 358 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 27:7110ebee3484 359 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 27:7110ebee3484 360
emilmont 27:7110ebee3484 361 /* SCB System Control Register Definitions */
emilmont 27:7110ebee3484 362 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 27:7110ebee3484 363 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 27:7110ebee3484 364
emilmont 27:7110ebee3484 365 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 27:7110ebee3484 366 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 27:7110ebee3484 367
emilmont 27:7110ebee3484 368 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 27:7110ebee3484 369 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 27:7110ebee3484 370
emilmont 27:7110ebee3484 371 /* SCB Configuration Control Register Definitions */
emilmont 27:7110ebee3484 372 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 27:7110ebee3484 373 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 27:7110ebee3484 374
emilmont 27:7110ebee3484 375 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 27:7110ebee3484 376 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 27:7110ebee3484 377
emilmont 31:a7ef757f598c 378 /* SCB System Handler Control and State Register Definitions */
emilmont 31:a7ef757f598c 379 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 31:a7ef757f598c 380 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 31:a7ef757f598c 381
emilmont 27:7110ebee3484 382 /*@} end of group CMSIS_SCB */
emilmont 27:7110ebee3484 383
emilmont 27:7110ebee3484 384
emilmont 31:a7ef757f598c 385 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 386 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 31:a7ef757f598c 387 \brief Type definitions for the System Timer Registers.
emilmont 27:7110ebee3484 388 @{
emilmont 27:7110ebee3484 389 */
emilmont 27:7110ebee3484 390
emilmont 27:7110ebee3484 391 /** \brief Structure type to access the System Timer (SysTick).
emilmont 27:7110ebee3484 392 */
emilmont 27:7110ebee3484 393 typedef struct
emilmont 27:7110ebee3484 394 {
emilmont 27:7110ebee3484 395 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 27:7110ebee3484 396 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 27:7110ebee3484 397 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 27:7110ebee3484 398 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 27:7110ebee3484 399 } SysTick_Type;
emilmont 27:7110ebee3484 400
emilmont 27:7110ebee3484 401 /* SysTick Control / Status Register Definitions */
emilmont 27:7110ebee3484 402 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 27:7110ebee3484 403 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 27:7110ebee3484 404
emilmont 27:7110ebee3484 405 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 27:7110ebee3484 406 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 27:7110ebee3484 407
emilmont 27:7110ebee3484 408 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 27:7110ebee3484 409 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 27:7110ebee3484 410
emilmont 27:7110ebee3484 411 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 27:7110ebee3484 412 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 27:7110ebee3484 413
emilmont 27:7110ebee3484 414 /* SysTick Reload Register Definitions */
emilmont 27:7110ebee3484 415 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 27:7110ebee3484 416 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 27:7110ebee3484 417
emilmont 27:7110ebee3484 418 /* SysTick Current Register Definitions */
emilmont 27:7110ebee3484 419 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 27:7110ebee3484 420 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 27:7110ebee3484 421
emilmont 27:7110ebee3484 422 /* SysTick Calibration Register Definitions */
emilmont 27:7110ebee3484 423 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 27:7110ebee3484 424 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 27:7110ebee3484 425
emilmont 27:7110ebee3484 426 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 27:7110ebee3484 427 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 27:7110ebee3484 428
emilmont 27:7110ebee3484 429 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 27:7110ebee3484 430 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 27:7110ebee3484 431
emilmont 27:7110ebee3484 432 /*@} end of group CMSIS_SysTick */
emilmont 27:7110ebee3484 433
emilmont 27:7110ebee3484 434
emilmont 31:a7ef757f598c 435 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 436 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 31:a7ef757f598c 437 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 31:a7ef757f598c 438 are only accessible over DAP and not via processor. Therefore
emilmont 31:a7ef757f598c 439 they are not covered by the Cortex-M0 header file.
emilmont 31:a7ef757f598c 440 @{
emilmont 31:a7ef757f598c 441 */
emilmont 31:a7ef757f598c 442 /*@} end of group CMSIS_CoreDebug */
emilmont 31:a7ef757f598c 443
emilmont 31:a7ef757f598c 444
emilmont 31:a7ef757f598c 445 /** \ingroup CMSIS_core_register
emilmont 31:a7ef757f598c 446 \defgroup CMSIS_core_base Core Definitions
emilmont 31:a7ef757f598c 447 \brief Definitions for base addresses, unions, and structures.
emilmont 27:7110ebee3484 448 @{
emilmont 27:7110ebee3484 449 */
emilmont 27:7110ebee3484 450
emilmont 27:7110ebee3484 451 /* Memory mapping of Cortex-M0 Hardware */
emilmont 27:7110ebee3484 452 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 27:7110ebee3484 453 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 27:7110ebee3484 454 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 27:7110ebee3484 455 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 27:7110ebee3484 456
emilmont 31:a7ef757f598c 457 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 31:a7ef757f598c 458 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 31:a7ef757f598c 459 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 31:a7ef757f598c 460
emilmont 27:7110ebee3484 461
emilmont 27:7110ebee3484 462 /*@} */
emilmont 27:7110ebee3484 463
emilmont 27:7110ebee3484 464
emilmont 27:7110ebee3484 465
emilmont 27:7110ebee3484 466 /*******************************************************************************
emilmont 27:7110ebee3484 467 * Hardware Abstraction Layer
emilmont 27:7110ebee3484 468 Core Function Interface contains:
emilmont 27:7110ebee3484 469 - Core NVIC Functions
emilmont 27:7110ebee3484 470 - Core SysTick Functions
emilmont 27:7110ebee3484 471 - Core Register Access Functions
emilmont 31:a7ef757f598c 472 ******************************************************************************/
emilmont 31:a7ef757f598c 473 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 27:7110ebee3484 474 */
emilmont 27:7110ebee3484 475
emilmont 27:7110ebee3484 476
emilmont 27:7110ebee3484 477
emilmont 27:7110ebee3484 478 /* ########################## NVIC functions #################################### */
emilmont 31:a7ef757f598c 479 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 31:a7ef757f598c 480 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 31:a7ef757f598c 481 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 31:a7ef757f598c 482 @{
emilmont 27:7110ebee3484 483 */
emilmont 27:7110ebee3484 484
emilmont 27:7110ebee3484 485 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 27:7110ebee3484 486 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 27:7110ebee3484 487 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 27:7110ebee3484 488 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 27:7110ebee3484 489 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 27:7110ebee3484 490
emilmont 27:7110ebee3484 491
emilmont 27:7110ebee3484 492 /** \brief Enable External Interrupt
emilmont 27:7110ebee3484 493
emilmont 31:a7ef757f598c 494 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 495
emilmont 31:a7ef757f598c 496 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 497 */
emilmont 39:737756e0b479 498 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 499 {
emilmont 27:7110ebee3484 500 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 501 }
emilmont 27:7110ebee3484 502
emilmont 27:7110ebee3484 503
emilmont 27:7110ebee3484 504 /** \brief Disable External Interrupt
emilmont 27:7110ebee3484 505
emilmont 31:a7ef757f598c 506 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 507
emilmont 31:a7ef757f598c 508 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 509 */
emilmont 39:737756e0b479 510 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 511 {
emilmont 27:7110ebee3484 512 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 513 }
emilmont 27:7110ebee3484 514
emilmont 27:7110ebee3484 515
emilmont 27:7110ebee3484 516 /** \brief Get Pending Interrupt
emilmont 27:7110ebee3484 517
emilmont 31:a7ef757f598c 518 The function reads the pending register in the NVIC and returns the pending bit
emilmont 31:a7ef757f598c 519 for the specified interrupt.
emilmont 27:7110ebee3484 520
emilmont 31:a7ef757f598c 521 \param [in] IRQn Interrupt number.
emilmont 39:737756e0b479 522
emilmont 31:a7ef757f598c 523 \return 0 Interrupt status is not pending.
emilmont 31:a7ef757f598c 524 \return 1 Interrupt status is pending.
emilmont 27:7110ebee3484 525 */
emilmont 39:737756e0b479 526 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 527 {
emilmont 27:7110ebee3484 528 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 27:7110ebee3484 529 }
emilmont 27:7110ebee3484 530
emilmont 27:7110ebee3484 531
emilmont 27:7110ebee3484 532 /** \brief Set Pending Interrupt
emilmont 27:7110ebee3484 533
emilmont 31:a7ef757f598c 534 The function sets the pending bit of an external interrupt.
emilmont 27:7110ebee3484 535
emilmont 31:a7ef757f598c 536 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 537 */
emilmont 39:737756e0b479 538 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 539 {
emilmont 27:7110ebee3484 540 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 541 }
emilmont 27:7110ebee3484 542
emilmont 27:7110ebee3484 543
emilmont 27:7110ebee3484 544 /** \brief Clear Pending Interrupt
emilmont 27:7110ebee3484 545
emilmont 31:a7ef757f598c 546 The function clears the pending bit of an external interrupt.
emilmont 27:7110ebee3484 547
emilmont 31:a7ef757f598c 548 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 27:7110ebee3484 549 */
emilmont 39:737756e0b479 550 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 551 {
emilmont 27:7110ebee3484 552 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 27:7110ebee3484 553 }
emilmont 27:7110ebee3484 554
emilmont 27:7110ebee3484 555
emilmont 27:7110ebee3484 556 /** \brief Set Interrupt Priority
emilmont 27:7110ebee3484 557
emilmont 39:737756e0b479 558 The function sets the priority of an interrupt.
emilmont 27:7110ebee3484 559
emilmont 31:a7ef757f598c 560 \note The priority cannot be set for every core interrupt.
emilmont 27:7110ebee3484 561
emilmont 39:737756e0b479 562 \param [in] IRQn Interrupt number.
emilmont 31:a7ef757f598c 563 \param [in] priority Priority to set.
emilmont 27:7110ebee3484 564 */
emilmont 39:737756e0b479 565 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 27:7110ebee3484 566 {
emilmont 27:7110ebee3484 567 if(IRQn < 0) {
emilmont 31:a7ef757f598c 568 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 569 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 570 else {
emilmont 31:a7ef757f598c 571 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 572 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 573 }
emilmont 27:7110ebee3484 574
emilmont 27:7110ebee3484 575
emilmont 27:7110ebee3484 576 /** \brief Get Interrupt Priority
emilmont 27:7110ebee3484 577
emilmont 31:a7ef757f598c 578 The function reads the priority of an interrupt. The interrupt
emilmont 31:a7ef757f598c 579 number can be positive to specify an external (device specific)
emilmont 27:7110ebee3484 580 interrupt, or negative to specify an internal (core) interrupt.
emilmont 27:7110ebee3484 581
emilmont 27:7110ebee3484 582
emilmont 31:a7ef757f598c 583 \param [in] IRQn Interrupt number.
emilmont 31:a7ef757f598c 584 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 31:a7ef757f598c 585 priority bits of the microcontroller.
emilmont 27:7110ebee3484 586 */
emilmont 39:737756e0b479 587 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 27:7110ebee3484 588 {
emilmont 27:7110ebee3484 589
emilmont 27:7110ebee3484 590 if(IRQn < 0) {
emilmont 27:7110ebee3484 591 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 27:7110ebee3484 592 else {
emilmont 31:a7ef757f598c 593 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 27:7110ebee3484 594 }
emilmont 27:7110ebee3484 595
emilmont 27:7110ebee3484 596
emilmont 27:7110ebee3484 597 /** \brief System Reset
emilmont 27:7110ebee3484 598
emilmont 31:a7ef757f598c 599 The function initiates a system reset request to reset the MCU.
emilmont 27:7110ebee3484 600 */
emilmont 39:737756e0b479 601 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 27:7110ebee3484 602 {
emilmont 27:7110ebee3484 603 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 31:a7ef757f598c 604 buffered write are completed before reset */
emilmont 31:a7ef757f598c 605 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 27:7110ebee3484 606 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 31:a7ef757f598c 607 __DSB(); /* Ensure completion of memory access */
emilmont 27:7110ebee3484 608 while(1); /* wait until reset */
emilmont 27:7110ebee3484 609 }
emilmont 27:7110ebee3484 610
emilmont 27:7110ebee3484 611 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 27:7110ebee3484 612
emilmont 27:7110ebee3484 613
emilmont 27:7110ebee3484 614
emilmont 27:7110ebee3484 615 /* ################################## SysTick function ############################################ */
emilmont 31:a7ef757f598c 616 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 31:a7ef757f598c 617 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 31:a7ef757f598c 618 \brief Functions that configure the System.
emilmont 27:7110ebee3484 619 @{
emilmont 27:7110ebee3484 620 */
emilmont 27:7110ebee3484 621
emilmont 27:7110ebee3484 622 #if (__Vendor_SysTickConfig == 0)
emilmont 27:7110ebee3484 623
emilmont 27:7110ebee3484 624 /** \brief System Tick Configuration
emilmont 27:7110ebee3484 625
emilmont 31:a7ef757f598c 626 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 39:737756e0b479 627 Counter is in free running mode to generate periodic interrupts.
emilmont 27:7110ebee3484 628
emilmont 31:a7ef757f598c 629 \param [in] ticks Number of ticks between two interrupts.
emilmont 39:737756e0b479 630
emilmont 31:a7ef757f598c 631 \return 0 Function succeeded.
emilmont 31:a7ef757f598c 632 \return 1 Function failed.
emilmont 39:737756e0b479 633
emilmont 39:737756e0b479 634 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 39:737756e0b479 635 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 31:a7ef757f598c 636 must contain a vendor-specific implementation of this function.
emilmont 31:a7ef757f598c 637
emilmont 27:7110ebee3484 638 */
emilmont 39:737756e0b479 639 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 31:a7ef757f598c 640 {
emilmont 27:7110ebee3484 641 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 31:a7ef757f598c 642
emilmont 27:7110ebee3484 643 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont 31:a7ef757f598c 644 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 27:7110ebee3484 645 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 31:a7ef757f598c 646 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 31:a7ef757f598c 647 SysTick_CTRL_TICKINT_Msk |
emilmont 27:7110ebee3484 648 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 27:7110ebee3484 649 return (0); /* Function successful */
emilmont 27:7110ebee3484 650 }
emilmont 27:7110ebee3484 651
emilmont 27:7110ebee3484 652 #endif
emilmont 27:7110ebee3484 653
emilmont 27:7110ebee3484 654 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 27:7110ebee3484 655
emilmont 27:7110ebee3484 656
emilmont 27:7110ebee3484 657
emilmont 27:7110ebee3484 658
emilmont 27:7110ebee3484 659 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 27:7110ebee3484 660
emilmont 27:7110ebee3484 661 #endif /* __CMSIS_GENERIC */
emilmont 27:7110ebee3484 662
emilmont 27:7110ebee3484 663 #ifdef __cplusplus
emilmont 27:7110ebee3484 664 }
emilmont 27:7110ebee3484 665 #endif