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TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 93:e188a91d3eaa

First reale BlueNRG module for nucleo 401 board

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User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_tim.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V1.2.0
Kojto	93:e188a91d3eaa	6	* @date 11-December-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of TIM HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_TIM_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_TIM_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup TIM
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	92:4fc01daae5a5	59	* @{
bogdanm	92:4fc01daae5a5	60	*/
bogdanm	85:024bf7f99721	61
bogdanm	85:024bf7f99721	62	/**
bogdanm	85:024bf7f99721	63	* @brief TIM Time base Configuration Structure definition
bogdanm	85:024bf7f99721	64	*/
bogdanm	85:024bf7f99721	65	typedef struct
bogdanm	85:024bf7f99721	66	{
bogdanm	85:024bf7f99721	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	85:024bf7f99721	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	69
bogdanm	85:024bf7f99721	70	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	85:024bf7f99721	71	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	85:024bf7f99721	72
bogdanm	85:024bf7f99721	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	85:024bf7f99721	74	Auto-Reload Register at the next update event.
bogdanm	85:024bf7f99721	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	85:024bf7f99721	76
bogdanm	85:024bf7f99721	77	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	85:024bf7f99721	78	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	85:024bf7f99721	79
bogdanm	85:024bf7f99721	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	85:024bf7f99721	81	reaches zero, an update event is generated and counting restarts
bogdanm	85:024bf7f99721	82	from the RCR value (N).
bogdanm	85:024bf7f99721	83	This means in PWM mode that (N+1) corresponds to:
bogdanm	85:024bf7f99721	84	- the number of PWM periods in edge-aligned mode
bogdanm	85:024bf7f99721	85	- the number of half PWM period in center-aligned mode
bogdanm	85:024bf7f99721	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	85:024bf7f99721	87	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	88	} TIM_Base_InitTypeDef;
bogdanm	85:024bf7f99721	89
bogdanm	85:024bf7f99721	90	/**
bogdanm	85:024bf7f99721	91	* @brief TIM Output Compare Configuration Structure definition
bogdanm	85:024bf7f99721	92	*/
bogdanm	85:024bf7f99721	93	typedef struct
bogdanm	85:024bf7f99721	94	{
bogdanm	85:024bf7f99721	95	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	85:024bf7f99721	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	85:024bf7f99721	97
bogdanm	85:024bf7f99721	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	85:024bf7f99721	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	100
bogdanm	85:024bf7f99721	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	85:024bf7f99721	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	85:024bf7f99721	103
bogdanm	85:024bf7f99721	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	85:024bf7f99721	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	85:024bf7f99721	106	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	107
bogdanm	85:024bf7f99721	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	85:024bf7f99721	109	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	85:024bf7f99721	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	85:024bf7f99721	111
bogdanm	85:024bf7f99721	112
bogdanm	85:024bf7f99721	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	85:024bf7f99721	115	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	116
bogdanm	85:024bf7f99721	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	85:024bf7f99721	119	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	120	} TIM_OC_InitTypeDef;
bogdanm	85:024bf7f99721	121
bogdanm	85:024bf7f99721	122	/**
bogdanm	85:024bf7f99721	123	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	85:024bf7f99721	124	*/
bogdanm	85:024bf7f99721	125	typedef struct
bogdanm	85:024bf7f99721	126	{
bogdanm	85:024bf7f99721	127	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	85:024bf7f99721	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	85:024bf7f99721	129
bogdanm	85:024bf7f99721	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	85:024bf7f99721	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	132
bogdanm	85:024bf7f99721	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	85:024bf7f99721	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	85:024bf7f99721	135
bogdanm	85:024bf7f99721	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	85:024bf7f99721	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	85:024bf7f99721	138	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	139
bogdanm	85:024bf7f99721	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	85:024bf7f99721	142	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	143
bogdanm	85:024bf7f99721	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	85:024bf7f99721	146	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	147
bogdanm	85:024bf7f99721	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	150
bogdanm	85:024bf7f99721	151	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	153
bogdanm	85:024bf7f99721	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	156	} TIM_OnePulse_InitTypeDef;
bogdanm	85:024bf7f99721	157
bogdanm	85:024bf7f99721	158
bogdanm	85:024bf7f99721	159	/**
bogdanm	85:024bf7f99721	160	* @brief TIM Input Capture Configuration Structure definition
bogdanm	85:024bf7f99721	161	*/
bogdanm	85:024bf7f99721	162	typedef struct
bogdanm	85:024bf7f99721	163	{
bogdanm	85:024bf7f99721	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	166
bogdanm	85:024bf7f99721	167	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	169
bogdanm	85:024bf7f99721	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	172
bogdanm	85:024bf7f99721	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	175	} TIM_IC_InitTypeDef;
bogdanm	85:024bf7f99721	176
bogdanm	85:024bf7f99721	177	/**
bogdanm	85:024bf7f99721	178	* @brief TIM Encoder Configuration Structure definition
bogdanm	85:024bf7f99721	179	*/
bogdanm	85:024bf7f99721	180	typedef struct
bogdanm	85:024bf7f99721	181	{
bogdanm	85:024bf7f99721	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	183	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	85:024bf7f99721	184
bogdanm	85:024bf7f99721	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	187
bogdanm	85:024bf7f99721	188	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	190
bogdanm	85:024bf7f99721	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	193
bogdanm	85:024bf7f99721	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	196
bogdanm	85:024bf7f99721	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	199
bogdanm	85:024bf7f99721	200	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	202
bogdanm	85:024bf7f99721	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	205
bogdanm	85:024bf7f99721	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	208	} TIM_Encoder_InitTypeDef;
bogdanm	85:024bf7f99721	209
bogdanm	85:024bf7f99721	210
bogdanm	85:024bf7f99721	211	/**
bogdanm	85:024bf7f99721	212	* @brief Clock Configuration Handle Structure definition
bogdanm	85:024bf7f99721	213	*/
bogdanm	85:024bf7f99721	214	typedef struct
bogdanm	85:024bf7f99721	215	{
bogdanm	85:024bf7f99721	216	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	85:024bf7f99721	217	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	85:024bf7f99721	218	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	85:024bf7f99721	219	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	85:024bf7f99721	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	85:024bf7f99721	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	85:024bf7f99721	222	uint32_t ClockFilter; /*!< TIM clock filter
bogdanm	85:024bf7f99721	223	This parameter can be a value of @ref TIM_Clock_Filter */
bogdanm	85:024bf7f99721	224	}TIM_ClockConfigTypeDef;
bogdanm	85:024bf7f99721	225
bogdanm	85:024bf7f99721	226	/**
bogdanm	85:024bf7f99721	227	* @brief Clear Input Configuration Handle Structure definition
bogdanm	85:024bf7f99721	228	*/
bogdanm	85:024bf7f99721	229	typedef struct
bogdanm	85:024bf7f99721	230	{
bogdanm	85:024bf7f99721	231	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	85:024bf7f99721	232	This parameter can be ENABLE or DISABLE */
bogdanm	85:024bf7f99721	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	85:024bf7f99721	234	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	85:024bf7f99721	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	85:024bf7f99721	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	85:024bf7f99721	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	85:024bf7f99721	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	85:024bf7f99721	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm	85:024bf7f99721	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
bogdanm	85:024bf7f99721	241	}TIM_ClearInputConfigTypeDef;
bogdanm	85:024bf7f99721	242
bogdanm	85:024bf7f99721	243	/**
bogdanm	85:024bf7f99721	244	* @brief TIM Slave configuration Structure definition
bogdanm	85:024bf7f99721	245	*/
bogdanm	85:024bf7f99721	246	typedef struct {
bogdanm	85:024bf7f99721	247	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	85:024bf7f99721	248	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	85:024bf7f99721	249	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	85:024bf7f99721	250	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	85:024bf7f99721	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	85:024bf7f99721	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	85:024bf7f99721	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	85:024bf7f99721	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	85:024bf7f99721	255	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	85:024bf7f99721	256	This parameter can be a value of @ref TIM_Trigger_Filter */
bogdanm	85:024bf7f99721	257
bogdanm	85:024bf7f99721	258	}TIM_SlaveConfigTypeDef;
bogdanm	85:024bf7f99721	259
bogdanm	85:024bf7f99721	260	/**
bogdanm	85:024bf7f99721	261	* @brief HAL State structures definition
bogdanm	85:024bf7f99721	262	*/
bogdanm	85:024bf7f99721	263	typedef enum
bogdanm	85:024bf7f99721	264	{
bogdanm	85:024bf7f99721	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	85:024bf7f99721	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	85:024bf7f99721	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	85:024bf7f99721	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	85:024bf7f99721	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	85:024bf7f99721	270	}HAL_TIM_StateTypeDef;
bogdanm	85:024bf7f99721	271
bogdanm	85:024bf7f99721	272	/**
bogdanm	85:024bf7f99721	273	* @brief HAL Active channel structures definition
bogdanm	85:024bf7f99721	274	*/
bogdanm	85:024bf7f99721	275	typedef enum
bogdanm	85:024bf7f99721	276	{
bogdanm	85:024bf7f99721	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	85:024bf7f99721	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	85:024bf7f99721	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	85:024bf7f99721	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	85:024bf7f99721	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	85:024bf7f99721	282	}HAL_TIM_ActiveChannel;
bogdanm	85:024bf7f99721	283
bogdanm	85:024bf7f99721	284	/**
bogdanm	85:024bf7f99721	285	* @brief TIM Time Base Handle Structure definition
bogdanm	85:024bf7f99721	286	*/
bogdanm	85:024bf7f99721	287	typedef struct
bogdanm	85:024bf7f99721	288	{
bogdanm	85:024bf7f99721	289	TIM_TypeDef Instance; /!< Register base address */
bogdanm	85:024bf7f99721	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	85:024bf7f99721	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	85:024bf7f99721	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
Kojto	93:e188a91d3eaa	293	This array is accessed by a @ref TIM_DMA_Handle_index */
bogdanm	85:024bf7f99721	294	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	85:024bf7f99721	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	85:024bf7f99721	296	}TIM_HandleTypeDef;
bogdanm	85:024bf7f99721	297
bogdanm	92:4fc01daae5a5	298	/**
bogdanm	92:4fc01daae5a5	299	* @}
bogdanm	92:4fc01daae5a5	300	*/
bogdanm	92:4fc01daae5a5	301
bogdanm	85:024bf7f99721	302	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	85:024bf7f99721	304	* @{
bogdanm	85:024bf7f99721	305	*/
bogdanm	85:024bf7f99721	306
bogdanm	92:4fc01daae5a5	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
bogdanm	85:024bf7f99721	308	* @{
bogdanm	85:024bf7f99721	309	*/
bogdanm	85:024bf7f99721	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	313	/**
bogdanm	85:024bf7f99721	314	* @}
bogdanm	85:024bf7f99721	315	*/
bogdanm	85:024bf7f99721	316
bogdanm	92:4fc01daae5a5	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	85:024bf7f99721	318	* @{
bogdanm	85:024bf7f99721	319	*/
bogdanm	85:024bf7f99721	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	85:024bf7f99721	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	85:024bf7f99721	322	/**
bogdanm	85:024bf7f99721	323	* @}
bogdanm	85:024bf7f99721	324	*/
bogdanm	85:024bf7f99721	325
bogdanm	92:4fc01daae5a5	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	85:024bf7f99721	327	* @{
bogdanm	85:024bf7f99721	328	*/
bogdanm	85:024bf7f99721	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	85:024bf7f99721	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	85:024bf7f99721	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	85:024bf7f99721	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	85:024bf7f99721	333	/**
bogdanm	85:024bf7f99721	334	* @}
bogdanm	85:024bf7f99721	335	*/
bogdanm	85:024bf7f99721	336
bogdanm	92:4fc01daae5a5	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	85:024bf7f99721	338	* @{
bogdanm	85:024bf7f99721	339	*/
bogdanm	92:4fc01daae5a5	340
bogdanm	85:024bf7f99721	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	85:024bf7f99721	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	85:024bf7f99721	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	85:024bf7f99721	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	85:024bf7f99721	346
bogdanm	85:024bf7f99721	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	85:024bf7f99721	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	85:024bf7f99721	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	85:024bf7f99721	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	85:024bf7f99721	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	85:024bf7f99721	352	/**
bogdanm	85:024bf7f99721	353	* @}
bogdanm	85:024bf7f99721	354	*/
bogdanm	85:024bf7f99721	355
bogdanm	92:4fc01daae5a5	356	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	85:024bf7f99721	357	* @{
bogdanm	85:024bf7f99721	358	*/
bogdanm	92:4fc01daae5a5	359
bogdanm	85:024bf7f99721	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	85:024bf7f99721	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	85:024bf7f99721	363
bogdanm	85:024bf7f99721	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	85:024bf7f99721	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	85:024bf7f99721	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	85:024bf7f99721	367	/**
bogdanm	85:024bf7f99721	368	* @}
bogdanm	85:024bf7f99721	369	*/
bogdanm	85:024bf7f99721	370
bogdanm	92:4fc01daae5a5	371	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
bogdanm	85:024bf7f99721	372	* @{
bogdanm	85:024bf7f99721	373	*/
bogdanm	92:4fc01daae5a5	374
bogdanm	85:024bf7f99721	375	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	376	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	85:024bf7f99721	377	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	85:024bf7f99721	378	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	85:024bf7f99721	379	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	380	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	85:024bf7f99721	381	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	382	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	383
bogdanm	85:024bf7f99721	384	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	85:024bf7f99721	385	((MODE) == TIM_OCMODE_PWM2))
bogdanm	85:024bf7f99721	386
bogdanm	85:024bf7f99721	387	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	85:024bf7f99721	388	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	85:024bf7f99721	389	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	85:024bf7f99721	390	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	85:024bf7f99721	391	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	85:024bf7f99721	392	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	85:024bf7f99721	393	/**
bogdanm	85:024bf7f99721	394	* @}
bogdanm	85:024bf7f99721	395	*/
bogdanm	85:024bf7f99721	396
bogdanm	92:4fc01daae5a5	397	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
bogdanm	85:024bf7f99721	398	* @{
bogdanm	85:024bf7f99721	399	*/
bogdanm	92:4fc01daae5a5	400
bogdanm	85:024bf7f99721	401	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	402	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	85:024bf7f99721	403
bogdanm	85:024bf7f99721	404	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	85:024bf7f99721	405	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	85:024bf7f99721	406	/**
bogdanm	85:024bf7f99721	407	* @}
bogdanm	85:024bf7f99721	408	*/
bogdanm	92:4fc01daae5a5	409	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	85:024bf7f99721	410	* @{
bogdanm	85:024bf7f99721	411	*/
bogdanm	85:024bf7f99721	412	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	413	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	85:024bf7f99721	414
bogdanm	85:024bf7f99721	415	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	85:024bf7f99721	416	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	85:024bf7f99721	417	/**
bogdanm	85:024bf7f99721	418	* @}
bogdanm	85:024bf7f99721	419	*/
bogdanm	92:4fc01daae5a5	420	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
bogdanm	85:024bf7f99721	421	* @{
bogdanm	85:024bf7f99721	422	*/
bogdanm	92:4fc01daae5a5	423
bogdanm	85:024bf7f99721	424	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	425	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	85:024bf7f99721	426
bogdanm	85:024bf7f99721	427	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	85:024bf7f99721	428	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	85:024bf7f99721	429	/**
bogdanm	85:024bf7f99721	430	* @}
bogdanm	85:024bf7f99721	431	*/
bogdanm	85:024bf7f99721	432
bogdanm	92:4fc01daae5a5	433	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	85:024bf7f99721	434	* @{
bogdanm	85:024bf7f99721	435	*/
bogdanm	92:4fc01daae5a5	436
bogdanm	85:024bf7f99721	437	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	438	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	85:024bf7f99721	439
bogdanm	85:024bf7f99721	440	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	85:024bf7f99721	441	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	85:024bf7f99721	442	/**
bogdanm	85:024bf7f99721	443	* @}
bogdanm	85:024bf7f99721	444	*/
bogdanm	85:024bf7f99721	445
bogdanm	92:4fc01daae5a5	446	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	85:024bf7f99721	447	* @{
bogdanm	85:024bf7f99721	448	*/
bogdanm	92:4fc01daae5a5	449
bogdanm	85:024bf7f99721	450	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	451	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	85:024bf7f99721	452
bogdanm	85:024bf7f99721	453	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	85:024bf7f99721	454	((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm	85:024bf7f99721	455	/**
bogdanm	85:024bf7f99721	456	* @}
bogdanm	85:024bf7f99721	457	*/
bogdanm	85:024bf7f99721	458
bogdanm	92:4fc01daae5a5	459	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	85:024bf7f99721	460	* @{
bogdanm	85:024bf7f99721	461	*/
bogdanm	92:4fc01daae5a5	462
bogdanm	85:024bf7f99721	463	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	85:024bf7f99721	464	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	465	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	85:024bf7f99721	466	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	85:024bf7f99721	467	/**
bogdanm	85:024bf7f99721	468	* @}
bogdanm	85:024bf7f99721	469	*/
bogdanm	85:024bf7f99721	470
bogdanm	92:4fc01daae5a5	471	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	85:024bf7f99721	472	* @{
bogdanm	85:024bf7f99721	473	*/
bogdanm	92:4fc01daae5a5	474
bogdanm	85:024bf7f99721	475	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	85:024bf7f99721	476	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	477	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	85:024bf7f99721	478	((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm	85:024bf7f99721	479	/**
bogdanm	85:024bf7f99721	480	* @}
bogdanm	85:024bf7f99721	481	*/
bogdanm	85:024bf7f99721	482
bogdanm	92:4fc01daae5a5	483	/** @defgroup TIM_Channel TIM Channel
bogdanm	85:024bf7f99721	484	* @{
bogdanm	85:024bf7f99721	485	*/
bogdanm	85:024bf7f99721	486	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	487	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	85:024bf7f99721	488	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	85:024bf7f99721	489	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	85:024bf7f99721	490	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	85:024bf7f99721	491
bogdanm	85:024bf7f99721	492	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	494	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	85:024bf7f99721	495	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	85:024bf7f99721	496	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	85:024bf7f99721	497
bogdanm	85:024bf7f99721	498	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	499	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	85:024bf7f99721	500
bogdanm	85:024bf7f99721	501	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	502	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	85:024bf7f99721	503
bogdanm	85:024bf7f99721	504	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	505	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	506	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	85:024bf7f99721	507	/**
bogdanm	85:024bf7f99721	508	* @}
bogdanm	85:024bf7f99721	509	*/
bogdanm	85:024bf7f99721	510
bogdanm	92:4fc01daae5a5	511	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	85:024bf7f99721	512	* @{
bogdanm	85:024bf7f99721	513	*/
bogdanm	92:4fc01daae5a5	514
bogdanm	85:024bf7f99721	515	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	85:024bf7f99721	516	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	85:024bf7f99721	517	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	85:024bf7f99721	518
bogdanm	85:024bf7f99721	519	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	85:024bf7f99721	520	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	85:024bf7f99721	521	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	85:024bf7f99721	522	/**
bogdanm	85:024bf7f99721	523	* @}
bogdanm	85:024bf7f99721	524	*/
bogdanm	85:024bf7f99721	525
bogdanm	92:4fc01daae5a5	526	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	85:024bf7f99721	527	* @{
bogdanm	85:024bf7f99721	528	*/
bogdanm	92:4fc01daae5a5	529
bogdanm	85:024bf7f99721	530	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	85:024bf7f99721	531	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	85:024bf7f99721	532	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	85:024bf7f99721	533	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	85:024bf7f99721	534	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	85:024bf7f99721	535
bogdanm	85:024bf7f99721	536	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	85:024bf7f99721	537	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	85:024bf7f99721	538	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	85:024bf7f99721	539	/**
bogdanm	85:024bf7f99721	540	* @}
bogdanm	85:024bf7f99721	541	*/
bogdanm	85:024bf7f99721	542
bogdanm	92:4fc01daae5a5	543	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	85:024bf7f99721	544	* @{
bogdanm	85:024bf7f99721	545	*/
bogdanm	92:4fc01daae5a5	546
bogdanm	85:024bf7f99721	547	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	85:024bf7f99721	548	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	85:024bf7f99721	549	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	85:024bf7f99721	550	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	85:024bf7f99721	551
bogdanm	85:024bf7f99721	552	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	85:024bf7f99721	553	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	85:024bf7f99721	554	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	85:024bf7f99721	555	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	85:024bf7f99721	556	/**
bogdanm	85:024bf7f99721	557	* @}
bogdanm	85:024bf7f99721	558	*/
bogdanm	85:024bf7f99721	559
bogdanm	92:4fc01daae5a5	560	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	85:024bf7f99721	561	* @{
bogdanm	85:024bf7f99721	562	*/
bogdanm	92:4fc01daae5a5	563
bogdanm	85:024bf7f99721	564	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	85:024bf7f99721	565	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	566
bogdanm	85:024bf7f99721	567	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	85:024bf7f99721	568	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	85:024bf7f99721	569	/**
bogdanm	85:024bf7f99721	570	* @}
bogdanm	85:024bf7f99721	571	*/
bogdanm	92:4fc01daae5a5	572	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	85:024bf7f99721	573	* @{
bogdanm	85:024bf7f99721	574	*/
bogdanm	85:024bf7f99721	575	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	85:024bf7f99721	576	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	85:024bf7f99721	577	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	85:024bf7f99721	578
bogdanm	85:024bf7f99721	579	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	85:024bf7f99721	580	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	85:024bf7f99721	581	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	85:024bf7f99721	582	/**
bogdanm	85:024bf7f99721	583	* @}
bogdanm	85:024bf7f99721	584	*/
bogdanm	92:4fc01daae5a5	585	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
bogdanm	85:024bf7f99721	586	* @{
bogdanm	85:024bf7f99721	587	*/
bogdanm	85:024bf7f99721	588	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	85:024bf7f99721	589	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	85:024bf7f99721	590	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	85:024bf7f99721	591	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	85:024bf7f99721	592	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	85:024bf7f99721	593	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	85:024bf7f99721	594	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	85:024bf7f99721	595	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	85:024bf7f99721	596	/**
bogdanm	85:024bf7f99721	597	* @}
bogdanm	85:024bf7f99721	598	*/
bogdanm	85:024bf7f99721	599
bogdanm	92:4fc01daae5a5	600	/** @defgroup TIM_COMMUTATION TIM Commutation
bogdanm	92:4fc01daae5a5	601	* @{
bogdanm	92:4fc01daae5a5	602	*/
bogdanm	85:024bf7f99721	603	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	85:024bf7f99721	604	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	605
bogdanm	92:4fc01daae5a5	606	/**
bogdanm	92:4fc01daae5a5	607	* @}
bogdanm	92:4fc01daae5a5	608	*/
bogdanm	92:4fc01daae5a5	609	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	85:024bf7f99721	610	* @{
bogdanm	85:024bf7f99721	611	*/
bogdanm	92:4fc01daae5a5	612
bogdanm	85:024bf7f99721	613	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	85:024bf7f99721	614	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	85:024bf7f99721	615	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	85:024bf7f99721	616	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	85:024bf7f99721	617	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	85:024bf7f99721	618	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	85:024bf7f99721	619	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	85:024bf7f99721	620
bogdanm	85:024bf7f99721	621	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	85:024bf7f99721	622	/**
bogdanm	85:024bf7f99721	623	* @}
bogdanm	85:024bf7f99721	624	*/
bogdanm	85:024bf7f99721	625
bogdanm	92:4fc01daae5a5	626	/** @defgroup TIM_Event_Source TIM Event Source
bogdanm	85:024bf7f99721	627	* @{
bogdanm	85:024bf7f99721	628	*/
bogdanm	85:024bf7f99721	629	#define TIM_EventSource_Update TIM_EGR_UG
bogdanm	85:024bf7f99721	630	#define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm	85:024bf7f99721	631	#define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm	85:024bf7f99721	632	#define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm	85:024bf7f99721	633	#define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm	85:024bf7f99721	634	#define TIM_EventSource_COM TIM_EGR_COMG
bogdanm	85:024bf7f99721	635	#define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm	85:024bf7f99721	636	#define TIM_EventSource_Break TIM_EGR_BG
bogdanm	85:024bf7f99721	637
bogdanm	85:024bf7f99721	638	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	85:024bf7f99721	639	/**
bogdanm	85:024bf7f99721	640	* @}
bogdanm	85:024bf7f99721	641	*/
bogdanm	85:024bf7f99721	642
bogdanm	92:4fc01daae5a5	643	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	85:024bf7f99721	644	* @{
bogdanm	85:024bf7f99721	645	*/
bogdanm	92:4fc01daae5a5	646
bogdanm	85:024bf7f99721	647	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	85:024bf7f99721	648	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	85:024bf7f99721	649	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	85:024bf7f99721	650	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	85:024bf7f99721	651	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	85:024bf7f99721	652	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	85:024bf7f99721	653	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	85:024bf7f99721	654	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	85:024bf7f99721	655	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	85:024bf7f99721	656	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	85:024bf7f99721	657	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	85:024bf7f99721	658	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	85:024bf7f99721	659
bogdanm	85:024bf7f99721	660	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
bogdanm	85:024bf7f99721	661	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	85:024bf7f99721	662	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	85:024bf7f99721	663	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	85:024bf7f99721	664	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	85:024bf7f99721	665	((FLAG) == TIM_FLAG_COM) \|\| \
bogdanm	85:024bf7f99721	666	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
bogdanm	85:024bf7f99721	667	((FLAG) == TIM_FLAG_BREAK) \|\| \
bogdanm	85:024bf7f99721	668	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	85:024bf7f99721	669	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	85:024bf7f99721	670	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	85:024bf7f99721	671	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	85:024bf7f99721	672	/**
bogdanm	85:024bf7f99721	673	* @}
bogdanm	85:024bf7f99721	674	*/
bogdanm	85:024bf7f99721	675
bogdanm	92:4fc01daae5a5	676	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	85:024bf7f99721	677	* @{
bogdanm	85:024bf7f99721	678	*/
bogdanm	85:024bf7f99721	679	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	85:024bf7f99721	680	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	85:024bf7f99721	681	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	682	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	85:024bf7f99721	683	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	85:024bf7f99721	684	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	85:024bf7f99721	685	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	686	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	687	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	688	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	85:024bf7f99721	689
bogdanm	85:024bf7f99721	690	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	85:024bf7f99721	691	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	85:024bf7f99721	692	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	85:024bf7f99721	693	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	85:024bf7f99721	694	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	85:024bf7f99721	695	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	85:024bf7f99721	696	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	85:024bf7f99721	697	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	85:024bf7f99721	698	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	85:024bf7f99721	699	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	85:024bf7f99721	700	/**
bogdanm	85:024bf7f99721	701	* @}
bogdanm	85:024bf7f99721	702	*/
bogdanm	85:024bf7f99721	703
bogdanm	92:4fc01daae5a5	704	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	85:024bf7f99721	705	* @{
bogdanm	85:024bf7f99721	706	*/
bogdanm	85:024bf7f99721	707	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	85:024bf7f99721	708	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	85:024bf7f99721	709	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	85:024bf7f99721	710	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	85:024bf7f99721	711	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	85:024bf7f99721	712
bogdanm	85:024bf7f99721	713	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	85:024bf7f99721	714	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	85:024bf7f99721	715	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	85:024bf7f99721	716	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	85:024bf7f99721	717	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	85:024bf7f99721	718	/**
bogdanm	85:024bf7f99721	719	* @}
bogdanm	85:024bf7f99721	720	*/
bogdanm	92:4fc01daae5a5	721	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	85:024bf7f99721	722	* @{
bogdanm	85:024bf7f99721	723	*/
bogdanm	85:024bf7f99721	724	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	725	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	726	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	727	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	728
bogdanm	85:024bf7f99721	729	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	85:024bf7f99721	730	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	85:024bf7f99721	731	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	85:024bf7f99721	732	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	85:024bf7f99721	733	/**
bogdanm	85:024bf7f99721	734	* @}
bogdanm	85:024bf7f99721	735	*/
bogdanm	92:4fc01daae5a5	736	/** @defgroup TIM_Clock_Filter TIM Clock Filter
bogdanm	85:024bf7f99721	737	* @{
bogdanm	85:024bf7f99721	738	*/
bogdanm	92:4fc01daae5a5	739
bogdanm	85:024bf7f99721	740	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	85:024bf7f99721	741	/**
bogdanm	85:024bf7f99721	742	* @}
bogdanm	85:024bf7f99721	743	*/
bogdanm	85:024bf7f99721	744
bogdanm	92:4fc01daae5a5	745	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
bogdanm	85:024bf7f99721	746	* @{
bogdanm	85:024bf7f99721	747	*/
bogdanm	85:024bf7f99721	748	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	85:024bf7f99721	749	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	750
bogdanm	85:024bf7f99721	751	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	752	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	85:024bf7f99721	753	/**
bogdanm	85:024bf7f99721	754	* @}
bogdanm	85:024bf7f99721	755	*/
bogdanm	85:024bf7f99721	756
bogdanm	92:4fc01daae5a5	757	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	85:024bf7f99721	758	* @{
bogdanm	85:024bf7f99721	759	*/
bogdanm	85:024bf7f99721	760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	85:024bf7f99721	761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	85:024bf7f99721	762
bogdanm	85:024bf7f99721	763
bogdanm	85:024bf7f99721	764	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	85:024bf7f99721	765	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	85:024bf7f99721	766	/**
bogdanm	85:024bf7f99721	767	* @}
bogdanm	85:024bf7f99721	768	*/
bogdanm	85:024bf7f99721	769
bogdanm	92:4fc01daae5a5	770	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	85:024bf7f99721	771	* @{
bogdanm	85:024bf7f99721	772	*/
bogdanm	85:024bf7f99721	773	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	774	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	775	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	776	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	777
bogdanm	85:024bf7f99721	778	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	85:024bf7f99721	779	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	85:024bf7f99721	780	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	85:024bf7f99721	781	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	85:024bf7f99721	782	/**
bogdanm	85:024bf7f99721	783	* @}
bogdanm	85:024bf7f99721	784	*/
bogdanm	85:024bf7f99721	785
bogdanm	92:4fc01daae5a5	786	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
bogdanm	85:024bf7f99721	787	* @{
bogdanm	85:024bf7f99721	788	*/
bogdanm	92:4fc01daae5a5	789
bogdanm	85:024bf7f99721	790	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	85:024bf7f99721	791	/**
bogdanm	85:024bf7f99721	792	* @}
bogdanm	85:024bf7f99721	793	*/
bogdanm	85:024bf7f99721	794
bogdanm	92:4fc01daae5a5	795	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
bogdanm	85:024bf7f99721	796	* @{
bogdanm	85:024bf7f99721	797	*/
bogdanm	85:024bf7f99721	798	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	85:024bf7f99721	799	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	800
bogdanm	85:024bf7f99721	801	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	85:024bf7f99721	802	((STATE) == TIM_OSSR_DISABLE))
bogdanm	85:024bf7f99721	803	/**
bogdanm	85:024bf7f99721	804	* @}
bogdanm	85:024bf7f99721	805	*/
bogdanm	85:024bf7f99721	806
bogdanm	92:4fc01daae5a5	807	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
bogdanm	85:024bf7f99721	808	* @{
bogdanm	85:024bf7f99721	809	*/
bogdanm	85:024bf7f99721	810	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	85:024bf7f99721	811	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	812
bogdanm	85:024bf7f99721	813	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	85:024bf7f99721	814	((STATE) == TIM_OSSI_DISABLE))
bogdanm	85:024bf7f99721	815	/**
bogdanm	85:024bf7f99721	816	* @}
bogdanm	85:024bf7f99721	817	*/
bogdanm	92:4fc01daae5a5	818	/** @defgroup TIM_Lock_level TIM Lock Configuration
bogdanm	85:024bf7f99721	819	* @{
bogdanm	85:024bf7f99721	820	*/
bogdanm	85:024bf7f99721	821	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	822	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	85:024bf7f99721	823	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	85:024bf7f99721	824	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	85:024bf7f99721	825
bogdanm	85:024bf7f99721	826	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	85:024bf7f99721	827	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	85:024bf7f99721	828	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	85:024bf7f99721	829	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	85:024bf7f99721	830	/**
bogdanm	85:024bf7f99721	831	* @}
bogdanm	85:024bf7f99721	832	*/
bogdanm	92:4fc01daae5a5	833	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
bogdanm	85:024bf7f99721	834	* @{
bogdanm	85:024bf7f99721	835	*/
bogdanm	85:024bf7f99721	836	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	85:024bf7f99721	837	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	838
bogdanm	85:024bf7f99721	839	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
bogdanm	85:024bf7f99721	840	((STATE) == TIM_BREAK_DISABLE))
bogdanm	85:024bf7f99721	841	/**
bogdanm	85:024bf7f99721	842	* @}
bogdanm	85:024bf7f99721	843	*/
bogdanm	92:4fc01daae5a5	844	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	85:024bf7f99721	845	* @{
bogdanm	85:024bf7f99721	846	*/
bogdanm	85:024bf7f99721	847	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	848	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	85:024bf7f99721	849
bogdanm	85:024bf7f99721	850	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	85:024bf7f99721	851	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm	85:024bf7f99721	852	/**
bogdanm	85:024bf7f99721	853	* @}
bogdanm	85:024bf7f99721	854	*/
bogdanm	92:4fc01daae5a5	855	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	85:024bf7f99721	856	* @{
bogdanm	85:024bf7f99721	857	*/
bogdanm	85:024bf7f99721	858	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	85:024bf7f99721	859	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	860
bogdanm	85:024bf7f99721	861	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	85:024bf7f99721	862	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	85:024bf7f99721	863	/**
bogdanm	85:024bf7f99721	864	* @}
bogdanm	85:024bf7f99721	865	*/
bogdanm	85:024bf7f99721	866
bogdanm	92:4fc01daae5a5	867	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	85:024bf7f99721	868	* @{
bogdanm	85:024bf7f99721	869	*/
bogdanm	85:024bf7f99721	870	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	871	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	85:024bf7f99721	872	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	85:024bf7f99721	873	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	85:024bf7f99721	874	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	85:024bf7f99721	875	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	85:024bf7f99721	876	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	85:024bf7f99721	877	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	85:024bf7f99721	878
bogdanm	85:024bf7f99721	879	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	85:024bf7f99721	880	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	85:024bf7f99721	881	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	85:024bf7f99721	882	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	85:024bf7f99721	883	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	85:024bf7f99721	884	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	85:024bf7f99721	885	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	85:024bf7f99721	886	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	92:4fc01daae5a5	887
bogdanm	92:4fc01daae5a5	888
bogdanm	85:024bf7f99721	889	/**
bogdanm	85:024bf7f99721	890	* @}
bogdanm	85:024bf7f99721	891	*/
bogdanm	85:024bf7f99721	892
bogdanm	92:4fc01daae5a5	893	/** @defgroup TIM_Slave_Mode TIM Slave Mode
bogdanm	85:024bf7f99721	894	* @{
bogdanm	85:024bf7f99721	895	*/
bogdanm	92:4fc01daae5a5	896
bogdanm	85:024bf7f99721	897	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	898	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	85:024bf7f99721	899	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	85:024bf7f99721	900	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	85:024bf7f99721	901	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	85:024bf7f99721	902
bogdanm	85:024bf7f99721	903	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	85:024bf7f99721	904	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	85:024bf7f99721	905	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	85:024bf7f99721	906	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	85:024bf7f99721	907	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	85:024bf7f99721	908	/**
bogdanm	85:024bf7f99721	909	* @}
bogdanm	85:024bf7f99721	910	*/
bogdanm	85:024bf7f99721	911
bogdanm	92:4fc01daae5a5	912	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
bogdanm	85:024bf7f99721	913	* @{
bogdanm	85:024bf7f99721	914	*/
bogdanm	92:4fc01daae5a5	915
bogdanm	85:024bf7f99721	916	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	85:024bf7f99721	917	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	918
bogdanm	85:024bf7f99721	919	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	85:024bf7f99721	920	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	85:024bf7f99721	921	/**
bogdanm	85:024bf7f99721	922	* @}
bogdanm	85:024bf7f99721	923	*/
bogdanm	92:4fc01daae5a5	924	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	85:024bf7f99721	925	* @{
bogdanm	85:024bf7f99721	926	*/
bogdanm	92:4fc01daae5a5	927
bogdanm	85:024bf7f99721	928	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	929	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	85:024bf7f99721	930	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	85:024bf7f99721	931	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	85:024bf7f99721	932	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	85:024bf7f99721	933	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	85:024bf7f99721	934	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	85:024bf7f99721	935	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	85:024bf7f99721	936	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	85:024bf7f99721	937
bogdanm	85:024bf7f99721	938	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	85:024bf7f99721	939	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	85:024bf7f99721	940	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	85:024bf7f99721	941	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	85:024bf7f99721	942	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	85:024bf7f99721	943	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	85:024bf7f99721	944	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	85:024bf7f99721	945	((SELECTION) == TIM_TS_ETRF))
bogdanm	85:024bf7f99721	946
bogdanm	85:024bf7f99721	947	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	85:024bf7f99721	948	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	85:024bf7f99721	949	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	85:024bf7f99721	950	((SELECTION) == TIM_TS_ITR3))
bogdanm	85:024bf7f99721	951
bogdanm	85:024bf7f99721	952	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	85:024bf7f99721	953	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	85:024bf7f99721	954	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	85:024bf7f99721	955	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	85:024bf7f99721	956	((SELECTION) == TIM_TS_NONE))
bogdanm	85:024bf7f99721	957	/**
bogdanm	85:024bf7f99721	958	* @}
bogdanm	85:024bf7f99721	959	*/
bogdanm	85:024bf7f99721	960
bogdanm	92:4fc01daae5a5	961	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	85:024bf7f99721	962	* @{
bogdanm	85:024bf7f99721	963	*/
bogdanm	85:024bf7f99721	964	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	85:024bf7f99721	965	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	85:024bf7f99721	966	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	85:024bf7f99721	967	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	85:024bf7f99721	968	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	85:024bf7f99721	969
bogdanm	85:024bf7f99721	970	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	85:024bf7f99721	971	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	85:024bf7f99721	972	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	85:024bf7f99721	973	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	85:024bf7f99721	974	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	85:024bf7f99721	975	/**
bogdanm	85:024bf7f99721	976	* @}
bogdanm	85:024bf7f99721	977	*/
bogdanm	85:024bf7f99721	978
bogdanm	92:4fc01daae5a5	979	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	85:024bf7f99721	980	* @{
bogdanm	85:024bf7f99721	981	*/
bogdanm	85:024bf7f99721	982	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	983	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	984	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	985	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	986
bogdanm	85:024bf7f99721	987	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	85:024bf7f99721	988	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	85:024bf7f99721	989	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	85:024bf7f99721	990	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	85:024bf7f99721	991	/**
bogdanm	85:024bf7f99721	992	* @}
bogdanm	85:024bf7f99721	993	*/
bogdanm	85:024bf7f99721	994
bogdanm	92:4fc01daae5a5	995	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
bogdanm	85:024bf7f99721	996	* @{
bogdanm	85:024bf7f99721	997	*/
bogdanm	92:4fc01daae5a5	998
bogdanm	85:024bf7f99721	999	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	85:024bf7f99721	1000	/**
bogdanm	85:024bf7f99721	1001	* @}
bogdanm	85:024bf7f99721	1002	*/
bogdanm	85:024bf7f99721	1003
bogdanm	92:4fc01daae5a5	1004	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	85:024bf7f99721	1005	* @{
bogdanm	85:024bf7f99721	1006	*/
bogdanm	92:4fc01daae5a5	1007
bogdanm	85:024bf7f99721	1008	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	1009	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	85:024bf7f99721	1010
bogdanm	85:024bf7f99721	1011	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	85:024bf7f99721	1012	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	92:4fc01daae5a5	1013
bogdanm	85:024bf7f99721	1014	/**
bogdanm	85:024bf7f99721	1015	* @}
bogdanm	85:024bf7f99721	1016	*/
bogdanm	85:024bf7f99721	1017
bogdanm	92:4fc01daae5a5	1018	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
bogdanm	85:024bf7f99721	1019	* @{
bogdanm	85:024bf7f99721	1020	*/
bogdanm	85:024bf7f99721	1021	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	85:024bf7f99721	1022	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	85:024bf7f99721	1023	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	85:024bf7f99721	1024	#define TIM_DMABase_DIER (0x00000003)
bogdanm	85:024bf7f99721	1025	#define TIM_DMABase_SR (0x00000004)
bogdanm	85:024bf7f99721	1026	#define TIM_DMABase_EGR (0x00000005)
bogdanm	85:024bf7f99721	1027	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	85:024bf7f99721	1028	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	85:024bf7f99721	1029	#define TIM_DMABase_CCER (0x00000008)
bogdanm	85:024bf7f99721	1030	#define TIM_DMABase_CNT (0x00000009)
bogdanm	85:024bf7f99721	1031	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	85:024bf7f99721	1032	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	85:024bf7f99721	1033	#define TIM_DMABase_RCR (0x0000000C)
bogdanm	85:024bf7f99721	1034	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	85:024bf7f99721	1035	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	85:024bf7f99721	1036	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	85:024bf7f99721	1037	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	85:024bf7f99721	1038	#define TIM_DMABase_BDTR (0x00000011)
bogdanm	85:024bf7f99721	1039	#define TIM_DMABase_DCR (0x00000012)
bogdanm	85:024bf7f99721	1040	#define TIM_DMABase_OR (0x00000013)
bogdanm	85:024bf7f99721	1041
bogdanm	85:024bf7f99721	1042	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	85:024bf7f99721	1043	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	85:024bf7f99721	1044	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	85:024bf7f99721	1045	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	85:024bf7f99721	1046	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	85:024bf7f99721	1047	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	85:024bf7f99721	1048	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	85:024bf7f99721	1049	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	85:024bf7f99721	1050	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	85:024bf7f99721	1051	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	85:024bf7f99721	1052	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	85:024bf7f99721	1053	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	85:024bf7f99721	1054	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	85:024bf7f99721	1055	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	85:024bf7f99721	1056	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	85:024bf7f99721	1057	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	85:024bf7f99721	1058	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	85:024bf7f99721	1059	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	85:024bf7f99721	1060	((BASE) == TIM_DMABase_DCR) \|\| \
bogdanm	85:024bf7f99721	1061	((BASE) == TIM_DMABase_OR))
bogdanm	85:024bf7f99721	1062	/**
bogdanm	85:024bf7f99721	1063	* @}
bogdanm	85:024bf7f99721	1064	*/
bogdanm	85:024bf7f99721	1065
bogdanm	92:4fc01daae5a5	1066	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	85:024bf7f99721	1067	* @{
bogdanm	85:024bf7f99721	1068	*/
bogdanm	92:4fc01daae5a5	1069
bogdanm	85:024bf7f99721	1070	#define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm	85:024bf7f99721	1071	#define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm	85:024bf7f99721	1072	#define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm	85:024bf7f99721	1073	#define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm	85:024bf7f99721	1074	#define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm	85:024bf7f99721	1075	#define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm	85:024bf7f99721	1076	#define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm	85:024bf7f99721	1077	#define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm	85:024bf7f99721	1078	#define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm	85:024bf7f99721	1079	#define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm	85:024bf7f99721	1080	#define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm	85:024bf7f99721	1081	#define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm	85:024bf7f99721	1082	#define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm	85:024bf7f99721	1083	#define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm	85:024bf7f99721	1084	#define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm	85:024bf7f99721	1085	#define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm	85:024bf7f99721	1086	#define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm	85:024bf7f99721	1087	#define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm	85:024bf7f99721	1088
bogdanm	85:024bf7f99721	1089	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	85:024bf7f99721	1090	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	85:024bf7f99721	1091	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	85:024bf7f99721	1092	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	85:024bf7f99721	1093	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	85:024bf7f99721	1094	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	85:024bf7f99721	1095	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	85:024bf7f99721	1096	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	85:024bf7f99721	1097	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	85:024bf7f99721	1098	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	85:024bf7f99721	1099	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	85:024bf7f99721	1100	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	85:024bf7f99721	1101	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	85:024bf7f99721	1102	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	85:024bf7f99721	1103	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	85:024bf7f99721	1104	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	85:024bf7f99721	1105	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	85:024bf7f99721	1106	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	85:024bf7f99721	1107	/**
bogdanm	85:024bf7f99721	1108	* @}
bogdanm	85:024bf7f99721	1109	*/
bogdanm	85:024bf7f99721	1110
bogdanm	92:4fc01daae5a5	1111	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
bogdanm	85:024bf7f99721	1112	* @{
bogdanm	85:024bf7f99721	1113	*/
bogdanm	92:4fc01daae5a5	1114
bogdanm	85:024bf7f99721	1115	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	85:024bf7f99721	1116	/**
bogdanm	85:024bf7f99721	1117	* @}
bogdanm	85:024bf7f99721	1118	*/
bogdanm	85:024bf7f99721	1119
Kojto	93:e188a91d3eaa	1120	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
bogdanm	85:024bf7f99721	1121	* @{
bogdanm	85:024bf7f99721	1122	*/
bogdanm	85:024bf7f99721	1123	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	85:024bf7f99721	1124	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	85:024bf7f99721	1125	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	85:024bf7f99721	1126	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	85:024bf7f99721	1127	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	85:024bf7f99721	1128	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	85:024bf7f99721	1129	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	85:024bf7f99721	1130	/**
bogdanm	85:024bf7f99721	1131	* @}
bogdanm	85:024bf7f99721	1132	*/
bogdanm	85:024bf7f99721	1133
bogdanm	92:4fc01daae5a5	1134	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
bogdanm	85:024bf7f99721	1135	* @{
bogdanm	85:024bf7f99721	1136	*/
bogdanm	85:024bf7f99721	1137	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	85:024bf7f99721	1138	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	1139	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	85:024bf7f99721	1140	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	85:024bf7f99721	1141	/**
bogdanm	85:024bf7f99721	1142	* @}
bogdanm	85:024bf7f99721	1143	*/
bogdanm	85:024bf7f99721	1144
bogdanm	85:024bf7f99721	1145	/**
bogdanm	85:024bf7f99721	1146	* @}
bogdanm	85:024bf7f99721	1147	*/
bogdanm	85:024bf7f99721	1148
bogdanm	85:024bf7f99721	1149	/* Exported macros -----------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1150	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	85:024bf7f99721	1151	* @{
bogdanm	85:024bf7f99721	1152	*/
bogdanm	85:024bf7f99721	1153
bogdanm	85:024bf7f99721	1154	/** @brief Reset TIM handle state
bogdanm	85:024bf7f99721	1155	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1156	* @retval None
bogdanm	85:024bf7f99721	1157	*/
bogdanm	85:024bf7f99721	1158	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	85:024bf7f99721	1159
bogdanm	85:024bf7f99721	1160	/**
bogdanm	85:024bf7f99721	1161	* @brief Enable the TIM peripheral.
bogdanm	85:024bf7f99721	1162	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1163	* @retval None
bogdanm	85:024bf7f99721	1164	*/
bogdanm	85:024bf7f99721	1165	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	85:024bf7f99721	1166
bogdanm	85:024bf7f99721	1167	/**
bogdanm	85:024bf7f99721	1168	* @brief Enable the TIM main Output.
bogdanm	85:024bf7f99721	1169	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1170	* @retval None
bogdanm	85:024bf7f99721	1171	*/
bogdanm	85:024bf7f99721	1172	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	85:024bf7f99721	1173
bogdanm	85:024bf7f99721	1174	/**
bogdanm	85:024bf7f99721	1175	* @brief Disable the TIM peripheral.
bogdanm	85:024bf7f99721	1176	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1177	* @retval None
bogdanm	85:024bf7f99721	1178	*/
bogdanm	85:024bf7f99721	1179	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	85:024bf7f99721	1180	do { \
bogdanm	85:024bf7f99721	1181	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	85:024bf7f99721	1182	{ \
bogdanm	85:024bf7f99721	1183	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	85:024bf7f99721	1184	{ \
bogdanm	92:4fc01daae5a5	1185	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	85:024bf7f99721	1186	} \
bogdanm	85:024bf7f99721	1187	} \
bogdanm	85:024bf7f99721	1188	} while(0)
bogdanm	85:024bf7f99721	1189	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm	85:024bf7f99721	1190	channels have been disabled */
bogdanm	85:024bf7f99721	1191	/**
bogdanm	85:024bf7f99721	1192	* @brief Disable the TIM main Output.
bogdanm	85:024bf7f99721	1193	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1194	* @retval None
bogdanm	85:024bf7f99721	1195	*/
bogdanm	85:024bf7f99721	1196	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	85:024bf7f99721	1197	do { \
bogdanm	85:024bf7f99721	1198	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	85:024bf7f99721	1199	{ \
bogdanm	85:024bf7f99721	1200	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	85:024bf7f99721	1201	{ \
bogdanm	92:4fc01daae5a5	1202	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	85:024bf7f99721	1203	} \
bogdanm	85:024bf7f99721	1204	} \
bogdanm	85:024bf7f99721	1205	} while(0)
bogdanm	85:024bf7f99721	1206
bogdanm	85:024bf7f99721	1207	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	1208	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	92:4fc01daae5a5	1209	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1210	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	85:024bf7f99721	1211	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1212	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	85:024bf7f99721	1213
bogdanm	85:024bf7f99721	1214	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	92:4fc01daae5a5	1215	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	1216
bogdanm	85:024bf7f99721	1217	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	92:4fc01daae5a5	1218	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	85:024bf7f99721	1219
bogdanm	85:024bf7f99721	1220	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	85:024bf7f99721	1221	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	85:024bf7f99721	1222	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	85:024bf7f99721	1223	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	85:024bf7f99721	1224	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	85:024bf7f99721	1225
bogdanm	85:024bf7f99721	1226	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm	92:4fc01daae5a5	1227	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
bogdanm	92:4fc01daae5a5	1228	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
bogdanm	92:4fc01daae5a5	1229	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
bogdanm	92:4fc01daae5a5	1230	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
bogdanm	85:024bf7f99721	1231
bogdanm	85:024bf7f99721	1232	/**
bogdanm	85:024bf7f99721	1233	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	85:024bf7f99721	1234	* calling another time ConfigChannel function.
bogdanm	85:024bf7f99721	1235	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1236	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	85:024bf7f99721	1237	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	85:024bf7f99721	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	85:024bf7f99721	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	85:024bf7f99721	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	85:024bf7f99721	1242	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	85:024bf7f99721	1243	* @retval None
bogdanm	85:024bf7f99721	1244	*/
bogdanm	85:024bf7f99721	1245	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	85:024bf7f99721	1246	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	85:024bf7f99721	1247
bogdanm	85:024bf7f99721	1248	/**
bogdanm	85:024bf7f99721	1249	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	85:024bf7f99721	1250	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1251	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	85:024bf7f99721	1252	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1253	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	85:024bf7f99721	1254	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	85:024bf7f99721	1255	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	85:024bf7f99721	1256	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	85:024bf7f99721	1257	* @retval None
bogdanm	85:024bf7f99721	1258	*/
bogdanm	85:024bf7f99721	1259	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	85:024bf7f99721	1260	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	85:024bf7f99721	1261
bogdanm	85:024bf7f99721	1262	/**
bogdanm	85:024bf7f99721	1263	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	85:024bf7f99721	1264	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1265	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	85:024bf7f99721	1266	* @retval None
bogdanm	85:024bf7f99721	1267	*/
bogdanm	85:024bf7f99721	1268	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	85:024bf7f99721	1269
bogdanm	85:024bf7f99721	1270	/**
bogdanm	85:024bf7f99721	1271	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	85:024bf7f99721	1272	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1273	* @retval None
bogdanm	85:024bf7f99721	1274	*/
bogdanm	85:024bf7f99721	1275	#define __HAL_TIM_GetCounter(__HANDLE__) \
bogdanm	85:024bf7f99721	1276	((__HANDLE__)->Instance->CNT)
bogdanm	85:024bf7f99721	1277
bogdanm	85:024bf7f99721	1278	/**
bogdanm	85:024bf7f99721	1279	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	85:024bf7f99721	1280	* another time any Init function.
bogdanm	85:024bf7f99721	1281	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1282	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	85:024bf7f99721	1283	* @retval None
bogdanm	85:024bf7f99721	1284	*/
bogdanm	85:024bf7f99721	1285	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm	85:024bf7f99721	1286	do{ \
bogdanm	85:024bf7f99721	1287	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	85:024bf7f99721	1288	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	85:024bf7f99721	1289	} while(0)
bogdanm	85:024bf7f99721	1290
bogdanm	85:024bf7f99721	1291	/**
bogdanm	85:024bf7f99721	1292	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	85:024bf7f99721	1293	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1294	* @retval None
bogdanm	85:024bf7f99721	1295	*/
bogdanm	85:024bf7f99721	1296	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
bogdanm	85:024bf7f99721	1297	((__HANDLE__)->Instance->ARR)
bogdanm	85:024bf7f99721	1298
bogdanm	85:024bf7f99721	1299	/**
bogdanm	85:024bf7f99721	1300	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	85:024bf7f99721	1301	* another time any Init function.
bogdanm	85:024bf7f99721	1302	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1303	* @param __CKD__: specifies the clock division value.
bogdanm	85:024bf7f99721	1304	* This parameter can be one of the following value:
bogdanm	85:024bf7f99721	1305	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	85:024bf7f99721	1306	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	85:024bf7f99721	1307	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	85:024bf7f99721	1308	* @retval None
bogdanm	85:024bf7f99721	1309	*/
bogdanm	85:024bf7f99721	1310	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm	85:024bf7f99721	1311	do{ \
bogdanm	92:4fc01daae5a5	1312	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
bogdanm	85:024bf7f99721	1313	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	85:024bf7f99721	1314	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	85:024bf7f99721	1315	} while(0)
bogdanm	85:024bf7f99721	1316
bogdanm	85:024bf7f99721	1317	/**
bogdanm	85:024bf7f99721	1318	* @brief Gets the TIM Clock Division value on runtime
bogdanm	85:024bf7f99721	1319	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1320	* @retval None
bogdanm	85:024bf7f99721	1321	*/
bogdanm	85:024bf7f99721	1322	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
bogdanm	85:024bf7f99721	1323	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	85:024bf7f99721	1324
bogdanm	85:024bf7f99721	1325	/**
bogdanm	85:024bf7f99721	1326	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	85:024bf7f99721	1327	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	85:024bf7f99721	1328	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1329	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	85:024bf7f99721	1330	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1331	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	85:024bf7f99721	1332	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	85:024bf7f99721	1333	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	85:024bf7f99721	1334	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	85:024bf7f99721	1335	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	85:024bf7f99721	1336	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1337	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	85:024bf7f99721	1338	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	85:024bf7f99721	1339	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	85:024bf7f99721	1340	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	85:024bf7f99721	1341	* @retval None
bogdanm	85:024bf7f99721	1342	*/
bogdanm	85:024bf7f99721	1343	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	85:024bf7f99721	1344	do{ \
bogdanm	85:024bf7f99721	1345	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm	85:024bf7f99721	1346	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	85:024bf7f99721	1347	} while(0)
bogdanm	85:024bf7f99721	1348
bogdanm	85:024bf7f99721	1349	/**
bogdanm	85:024bf7f99721	1350	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	85:024bf7f99721	1351	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1352	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	85:024bf7f99721	1353	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1354	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	85:024bf7f99721	1355	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	85:024bf7f99721	1356	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	85:024bf7f99721	1357	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	85:024bf7f99721	1358	* @retval None
bogdanm	85:024bf7f99721	1359	*/
bogdanm	85:024bf7f99721	1360	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm	85:024bf7f99721	1361	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	85:024bf7f99721	1362	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	85:024bf7f99721	1363	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	85:024bf7f99721	1364	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	85:024bf7f99721	1365
bogdanm	85:024bf7f99721	1366	/**
bogdanm	92:4fc01daae5a5	1367	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1368	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1369	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	92:4fc01daae5a5	1370	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1371	* enabled)
bogdanm	92:4fc01daae5a5	1372	* @retval None
bogdanm	92:4fc01daae5a5	1373	*/
bogdanm	92:4fc01daae5a5	1374	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1375	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1376
bogdanm	92:4fc01daae5a5	1377	/**
bogdanm	92:4fc01daae5a5	1378	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1379	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1380	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	92:4fc01daae5a5	1381	* following events generate an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1382	* enabled):
bogdanm	92:4fc01daae5a5	1383	* (+) Counter overflow/underflow
bogdanm	92:4fc01daae5a5	1384	* (+) Setting the UG bit
bogdanm	92:4fc01daae5a5	1385	* (+) Update generation through the slave mode controller
bogdanm	92:4fc01daae5a5	1386	* @retval None
bogdanm	92:4fc01daae5a5	1387	*/
bogdanm	92:4fc01daae5a5	1388	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1389	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1390
bogdanm	92:4fc01daae5a5	1391	/**
bogdanm	85:024bf7f99721	1392	* @}
bogdanm	85:024bf7f99721	1393	*/
bogdanm	85:024bf7f99721	1394
bogdanm	85:024bf7f99721	1395	/* Include TIM HAL Extension module */
bogdanm	85:024bf7f99721	1396	#include "stm32f0xx_hal_tim_ex.h"
bogdanm	85:024bf7f99721	1397
bogdanm	85:024bf7f99721	1398	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1399	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
bogdanm	92:4fc01daae5a5	1400	* @{
bogdanm	92:4fc01daae5a5	1401	*/
bogdanm	85:024bf7f99721	1402
bogdanm	92:4fc01daae5a5	1403	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	92:4fc01daae5a5	1404	* @brief Time Base functions
bogdanm	92:4fc01daae5a5	1405	* @{
bogdanm	92:4fc01daae5a5	1406	*/
bogdanm	85:024bf7f99721	1407	/* Time Base functions ********************************************************/
bogdanm	85:024bf7f99721	1408	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1409	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1410	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1411	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1412	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1413	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1414	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1415	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1416	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1417	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1418	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1419	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1420	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1421	/**
bogdanm	92:4fc01daae5a5	1422	* @}
bogdanm	92:4fc01daae5a5	1423	*/
bogdanm	85:024bf7f99721	1424
bogdanm	92:4fc01daae5a5	1425	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	92:4fc01daae5a5	1426	* @brief Time Output Compare functions
bogdanm	92:4fc01daae5a5	1427	* @{
bogdanm	92:4fc01daae5a5	1428	*/
bogdanm	85:024bf7f99721	1429	/* Timer Output Compare functions **********************************************/
bogdanm	85:024bf7f99721	1430	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1431	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1432	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1433	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1434	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1435	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1436	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1437	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1438	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1439	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1440	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1441	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1442	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1443	/**
bogdanm	92:4fc01daae5a5	1444	* @}
bogdanm	92:4fc01daae5a5	1445	*/
bogdanm	85:024bf7f99721	1446
bogdanm	92:4fc01daae5a5	1447	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	92:4fc01daae5a5	1448	* @brief Time PWM functions
bogdanm	92:4fc01daae5a5	1449	* @{
bogdanm	92:4fc01daae5a5	1450	*/
bogdanm	85:024bf7f99721	1451	/* Timer PWM functions *********************************************************/
bogdanm	85:024bf7f99721	1452	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1453	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1454	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1455	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1456	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1457	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1458	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1459	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1460	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1461	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1462	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1463	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1464	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1465	/**
bogdanm	92:4fc01daae5a5	1466	* @}
bogdanm	92:4fc01daae5a5	1467	*/
bogdanm	85:024bf7f99721	1468
bogdanm	92:4fc01daae5a5	1469	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	92:4fc01daae5a5	1470	* @brief Time Input Capture functions
bogdanm	92:4fc01daae5a5	1471	* @{
bogdanm	92:4fc01daae5a5	1472	*/
bogdanm	85:024bf7f99721	1473	/* Timer Input Capture functions ***********************************************/
bogdanm	85:024bf7f99721	1474	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1475	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1476	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1477	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1478	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1479	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1480	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1481	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1482	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1483	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1484	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1485	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1486	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1487	/**
bogdanm	92:4fc01daae5a5	1488	* @}
bogdanm	92:4fc01daae5a5	1489	*/
bogdanm	85:024bf7f99721	1490
bogdanm	92:4fc01daae5a5	1491	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	92:4fc01daae5a5	1492	* @brief Time One Pulse functions
bogdanm	92:4fc01daae5a5	1493	* @{
bogdanm	92:4fc01daae5a5	1494	*/
bogdanm	85:024bf7f99721	1495	/* Timer One Pulse functions ***************************************************/
bogdanm	85:024bf7f99721	1496	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	85:024bf7f99721	1497	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1498	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1499	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1500	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1501	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1502	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1503	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1504	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1505	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1506	/**
bogdanm	92:4fc01daae5a5	1507	* @}
bogdanm	92:4fc01daae5a5	1508	*/
bogdanm	85:024bf7f99721	1509
bogdanm	92:4fc01daae5a5	1510	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	92:4fc01daae5a5	1511	* @brief Time Encoder functions
bogdanm	92:4fc01daae5a5	1512	* @{
bogdanm	92:4fc01daae5a5	1513	*/
bogdanm	85:024bf7f99721	1514	/* Timer Encoder functions *****************************************************/
bogdanm	85:024bf7f99721	1515	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	85:024bf7f99721	1516	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1517	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1518	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1519	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1520	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1521	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1522	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1523	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1524	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1525	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1526	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	85:024bf7f99721	1527	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1528	/**
bogdanm	92:4fc01daae5a5	1529	* @}
bogdanm	92:4fc01daae5a5	1530	*/
bogdanm	85:024bf7f99721	1531
bogdanm	92:4fc01daae5a5	1532	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	92:4fc01daae5a5	1533	* @brief IRQ handler management
bogdanm	92:4fc01daae5a5	1534	* @{
bogdanm	92:4fc01daae5a5	1535	*/
bogdanm	85:024bf7f99721	1536	/* Interrupt Handler functions **********************************************/
bogdanm	85:024bf7f99721	1537	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1538	/**
bogdanm	92:4fc01daae5a5	1539	* @}
bogdanm	92:4fc01daae5a5	1540	*/
bogdanm	85:024bf7f99721	1541
bogdanm	92:4fc01daae5a5	1542	/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	92:4fc01daae5a5	1543	* @brief Peripheral Control functions
bogdanm	92:4fc01daae5a5	1544	* @{
bogdanm	92:4fc01daae5a5	1545	*/
bogdanm	85:024bf7f99721	1546	/* Control functions *********************************************************/
bogdanm	85:024bf7f99721	1547	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1548	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1549	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1550	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	85:024bf7f99721	1551	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1552	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	85:024bf7f99721	1553	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	85:024bf7f99721	1554	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	92:4fc01daae5a5	1555	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	85:024bf7f99721	1556	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	85:024bf7f99721	1557	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	85:024bf7f99721	1558	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	85:024bf7f99721	1559	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	85:024bf7f99721	1560	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	85:024bf7f99721	1561	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	85:024bf7f99721	1562	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	85:024bf7f99721	1563	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1564	/**
bogdanm	92:4fc01daae5a5	1565	* @}
bogdanm	92:4fc01daae5a5	1566	*/
bogdanm	85:024bf7f99721	1567
bogdanm	92:4fc01daae5a5	1568	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	92:4fc01daae5a5	1569	* @brief TIM Callbacks functions
bogdanm	92:4fc01daae5a5	1570	* @{
bogdanm	92:4fc01daae5a5	1571	*/
bogdanm	85:024bf7f99721	1572	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	85:024bf7f99721	1573	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1574	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1575	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1576	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1577	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1578	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1579	/**
bogdanm	92:4fc01daae5a5	1580	* @}
bogdanm	92:4fc01daae5a5	1581	*/
bogdanm	85:024bf7f99721	1582
bogdanm	92:4fc01daae5a5	1583	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	92:4fc01daae5a5	1584	* @brief Peripheral State functions
bogdanm	92:4fc01daae5a5	1585	* @{
bogdanm	92:4fc01daae5a5	1586	*/
bogdanm	85:024bf7f99721	1587	/* Peripheral State functions **************************************************/
bogdanm	85:024bf7f99721	1588	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1589	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1590	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1591	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1592	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1593	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1594	/**
bogdanm	92:4fc01daae5a5	1595	* @}
bogdanm	92:4fc01daae5a5	1596	*/
bogdanm	85:024bf7f99721	1597
bogdanm	92:4fc01daae5a5	1598	/**
bogdanm	92:4fc01daae5a5	1599	* @}
bogdanm	92:4fc01daae5a5	1600	*/
bogdanm	92:4fc01daae5a5	1601
bogdanm	92:4fc01daae5a5	1602	/* Private Macros -----------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1603	/** @defgroup TIM_Private_Macros TIM Private Macros
bogdanm	92:4fc01daae5a5	1604	* @{
bogdanm	92:4fc01daae5a5	1605	*/
bogdanm	92:4fc01daae5a5	1606	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	92:4fc01daae5a5	1607	channels have been disabled */
bogdanm	92:4fc01daae5a5	1608	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	92:4fc01daae5a5	1609	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	92:4fc01daae5a5	1610	/**
bogdanm	92:4fc01daae5a5	1611	* @}
bogdanm	92:4fc01daae5a5	1612	*/
bogdanm	92:4fc01daae5a5	1613
bogdanm	92:4fc01daae5a5	1614	/* Private Functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1615	/** @addtogroup TIM_Private_Functions
bogdanm	92:4fc01daae5a5	1616	* @{
bogdanm	92:4fc01daae5a5	1617	*/
bogdanm	85:024bf7f99721	1618	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	85:024bf7f99721	1619	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	85:024bf7f99721	1620	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	85:024bf7f99721	1621	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	1622	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	1623	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	1624	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	85:024bf7f99721	1625
bogdanm	92:4fc01daae5a5	1626	/**
bogdanm	92:4fc01daae5a5	1627	* @}
bogdanm	92:4fc01daae5a5	1628	*/
bogdanm	85:024bf7f99721	1629
bogdanm	85:024bf7f99721	1630	/**
bogdanm	85:024bf7f99721	1631	* @}
bogdanm	85:024bf7f99721	1632	*/
bogdanm	85:024bf7f99721	1633
bogdanm	85:024bf7f99721	1634	/**
bogdanm	85:024bf7f99721	1635	* @}
bogdanm	92:4fc01daae5a5	1636	*/
bogdanm	92:4fc01daae5a5	1637
bogdanm	85:024bf7f99721	1638	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1639	}
bogdanm	85:024bf7f99721	1640	#endif
bogdanm	85:024bf7f99721	1641
bogdanm	85:024bf7f99721	1642	#endif /* __STM32F0xx_HAL_TIM_H */
bogdanm	85:024bf7f99721	1643
bogdanm	85:024bf7f99721	1644	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	92:4fc01daae5a5	1645

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.h@97:4298809c7c9e, 2015-04-08 (annotated)

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