Filippo Casamassima
my fork
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mbed official
TARGET_NUCLEO_F103RB/stm32f10x_rcc.h@73:1efda918f0ba, 2013-12-09 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Dec 09 18:43:03 2013 +0200
- Revision:
- 73:1efda918f0ba
- Child:
- 76:824293ae5e43
Release 73 of the mbed library
Main changes:
- added support for KL46Z and NUCLEO_F103RB
- STM32 USB device support
- various bug fixes
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 73:1efda918f0ba | 1 | /** |
| bogdanm | 73:1efda918f0ba | 2 | ****************************************************************************** |
| bogdanm | 73:1efda918f0ba | 3 | * @file stm32f10x_rcc.h |
| bogdanm | 73:1efda918f0ba | 4 | * @author MCD Application Team |
| bogdanm | 73:1efda918f0ba | 5 | * @version V3.5.0 |
| bogdanm | 73:1efda918f0ba | 6 | * @date 11-March-2011 |
| bogdanm | 73:1efda918f0ba | 7 | * @brief This file contains all the functions prototypes for the RCC firmware |
| bogdanm | 73:1efda918f0ba | 8 | * library. |
| bogdanm | 73:1efda918f0ba | 9 | ****************************************************************************** |
| bogdanm | 73:1efda918f0ba | 10 | * @attention |
| bogdanm | 73:1efda918f0ba | 11 | * |
| bogdanm | 73:1efda918f0ba | 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
| bogdanm | 73:1efda918f0ba | 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
| bogdanm | 73:1efda918f0ba | 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
| bogdanm | 73:1efda918f0ba | 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
| bogdanm | 73:1efda918f0ba | 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
| bogdanm | 73:1efda918f0ba | 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
| bogdanm | 73:1efda918f0ba | 18 | * |
| bogdanm | 73:1efda918f0ba | 19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
| bogdanm | 73:1efda918f0ba | 20 | ****************************************************************************** |
| bogdanm | 73:1efda918f0ba | 21 | */ |
| bogdanm | 73:1efda918f0ba | 22 | |
| bogdanm | 73:1efda918f0ba | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 73:1efda918f0ba | 24 | #ifndef __STM32F10x_RCC_H |
| bogdanm | 73:1efda918f0ba | 25 | #define __STM32F10x_RCC_H |
| bogdanm | 73:1efda918f0ba | 26 | |
| bogdanm | 73:1efda918f0ba | 27 | #ifdef __cplusplus |
| bogdanm | 73:1efda918f0ba | 28 | extern "C" { |
| bogdanm | 73:1efda918f0ba | 29 | #endif |
| bogdanm | 73:1efda918f0ba | 30 | |
| bogdanm | 73:1efda918f0ba | 31 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 73:1efda918f0ba | 32 | #include "stm32f10x.h" |
| bogdanm | 73:1efda918f0ba | 33 | |
| bogdanm | 73:1efda918f0ba | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver |
| bogdanm | 73:1efda918f0ba | 35 | * @{ |
| bogdanm | 73:1efda918f0ba | 36 | */ |
| bogdanm | 73:1efda918f0ba | 37 | |
| bogdanm | 73:1efda918f0ba | 38 | /** @addtogroup RCC |
| bogdanm | 73:1efda918f0ba | 39 | * @{ |
| bogdanm | 73:1efda918f0ba | 40 | */ |
| bogdanm | 73:1efda918f0ba | 41 | |
| bogdanm | 73:1efda918f0ba | 42 | /** @defgroup RCC_Exported_Types |
| bogdanm | 73:1efda918f0ba | 43 | * @{ |
| bogdanm | 73:1efda918f0ba | 44 | */ |
| bogdanm | 73:1efda918f0ba | 45 | |
| bogdanm | 73:1efda918f0ba | 46 | typedef struct |
| bogdanm | 73:1efda918f0ba | 47 | { |
| bogdanm | 73:1efda918f0ba | 48 | uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 49 | uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 50 | uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 51 | uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 52 | uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ |
| bogdanm | 73:1efda918f0ba | 53 | }RCC_ClocksTypeDef; |
| bogdanm | 73:1efda918f0ba | 54 | |
| bogdanm | 73:1efda918f0ba | 55 | /** |
| bogdanm | 73:1efda918f0ba | 56 | * @} |
| bogdanm | 73:1efda918f0ba | 57 | */ |
| bogdanm | 73:1efda918f0ba | 58 | |
| bogdanm | 73:1efda918f0ba | 59 | /** @defgroup RCC_Exported_Constants |
| bogdanm | 73:1efda918f0ba | 60 | * @{ |
| bogdanm | 73:1efda918f0ba | 61 | */ |
| bogdanm | 73:1efda918f0ba | 62 | |
| bogdanm | 73:1efda918f0ba | 63 | /** @defgroup HSE_configuration |
| bogdanm | 73:1efda918f0ba | 64 | * @{ |
| bogdanm | 73:1efda918f0ba | 65 | */ |
| bogdanm | 73:1efda918f0ba | 66 | |
| bogdanm | 73:1efda918f0ba | 67 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 68 | #define RCC_HSE_ON ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 69 | #define RCC_HSE_Bypass ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 70 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| bogdanm | 73:1efda918f0ba | 71 | ((HSE) == RCC_HSE_Bypass)) |
| bogdanm | 73:1efda918f0ba | 72 | |
| bogdanm | 73:1efda918f0ba | 73 | /** |
| bogdanm | 73:1efda918f0ba | 74 | * @} |
| bogdanm | 73:1efda918f0ba | 75 | */ |
| bogdanm | 73:1efda918f0ba | 76 | |
| bogdanm | 73:1efda918f0ba | 77 | /** @defgroup PLL_entry_clock_source |
| bogdanm | 73:1efda918f0ba | 78 | * @{ |
| bogdanm | 73:1efda918f0ba | 79 | */ |
| bogdanm | 73:1efda918f0ba | 80 | |
| bogdanm | 73:1efda918f0ba | 81 | #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 82 | |
| bogdanm | 73:1efda918f0ba | 83 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 84 | #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 85 | #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) |
| bogdanm | 73:1efda918f0ba | 86 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 87 | ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ |
| bogdanm | 73:1efda918f0ba | 88 | ((SOURCE) == RCC_PLLSource_HSE_Div2)) |
| bogdanm | 73:1efda918f0ba | 89 | #else |
| bogdanm | 73:1efda918f0ba | 90 | #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 91 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 92 | ((SOURCE) == RCC_PLLSource_PREDIV1)) |
| bogdanm | 73:1efda918f0ba | 93 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 94 | |
| bogdanm | 73:1efda918f0ba | 95 | /** |
| bogdanm | 73:1efda918f0ba | 96 | * @} |
| bogdanm | 73:1efda918f0ba | 97 | */ |
| bogdanm | 73:1efda918f0ba | 98 | |
| bogdanm | 73:1efda918f0ba | 99 | /** @defgroup PLL_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 100 | * @{ |
| bogdanm | 73:1efda918f0ba | 101 | */ |
| bogdanm | 73:1efda918f0ba | 102 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 103 | #define RCC_PLLMul_2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 104 | #define RCC_PLLMul_3 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 105 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 106 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
| bogdanm | 73:1efda918f0ba | 107 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 108 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
| bogdanm | 73:1efda918f0ba | 109 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
| bogdanm | 73:1efda918f0ba | 110 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
| bogdanm | 73:1efda918f0ba | 111 | #define RCC_PLLMul_10 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 112 | #define RCC_PLLMul_11 ((uint32_t)0x00240000) |
| bogdanm | 73:1efda918f0ba | 113 | #define RCC_PLLMul_12 ((uint32_t)0x00280000) |
| bogdanm | 73:1efda918f0ba | 114 | #define RCC_PLLMul_13 ((uint32_t)0x002C0000) |
| bogdanm | 73:1efda918f0ba | 115 | #define RCC_PLLMul_14 ((uint32_t)0x00300000) |
| bogdanm | 73:1efda918f0ba | 116 | #define RCC_PLLMul_15 ((uint32_t)0x00340000) |
| bogdanm | 73:1efda918f0ba | 117 | #define RCC_PLLMul_16 ((uint32_t)0x00380000) |
| bogdanm | 73:1efda918f0ba | 118 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ |
| bogdanm | 73:1efda918f0ba | 119 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| bogdanm | 73:1efda918f0ba | 120 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| bogdanm | 73:1efda918f0ba | 121 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| bogdanm | 73:1efda918f0ba | 122 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
| bogdanm | 73:1efda918f0ba | 123 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
| bogdanm | 73:1efda918f0ba | 124 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
| bogdanm | 73:1efda918f0ba | 125 | ((MUL) == RCC_PLLMul_16)) |
| bogdanm | 73:1efda918f0ba | 126 | |
| bogdanm | 73:1efda918f0ba | 127 | #else |
| bogdanm | 73:1efda918f0ba | 128 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 129 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
| bogdanm | 73:1efda918f0ba | 130 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 131 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
| bogdanm | 73:1efda918f0ba | 132 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
| bogdanm | 73:1efda918f0ba | 133 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
| bogdanm | 73:1efda918f0ba | 134 | #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) |
| bogdanm | 73:1efda918f0ba | 135 | |
| bogdanm | 73:1efda918f0ba | 136 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| bogdanm | 73:1efda918f0ba | 137 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| bogdanm | 73:1efda918f0ba | 138 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| bogdanm | 73:1efda918f0ba | 139 | ((MUL) == RCC_PLLMul_6_5)) |
| bogdanm | 73:1efda918f0ba | 140 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 141 | /** |
| bogdanm | 73:1efda918f0ba | 142 | * @} |
| bogdanm | 73:1efda918f0ba | 143 | */ |
| bogdanm | 73:1efda918f0ba | 144 | |
| bogdanm | 73:1efda918f0ba | 145 | /** @defgroup PREDIV1_division_factor |
| bogdanm | 73:1efda918f0ba | 146 | * @{ |
| bogdanm | 73:1efda918f0ba | 147 | */ |
| bogdanm | 73:1efda918f0ba | 148 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 149 | #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 150 | #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 151 | #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 152 | #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) |
| bogdanm | 73:1efda918f0ba | 153 | #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 154 | #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) |
| bogdanm | 73:1efda918f0ba | 155 | #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) |
| bogdanm | 73:1efda918f0ba | 156 | #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) |
| bogdanm | 73:1efda918f0ba | 157 | #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 158 | #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) |
| bogdanm | 73:1efda918f0ba | 159 | #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) |
| bogdanm | 73:1efda918f0ba | 160 | #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) |
| bogdanm | 73:1efda918f0ba | 161 | #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) |
| bogdanm | 73:1efda918f0ba | 162 | #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) |
| bogdanm | 73:1efda918f0ba | 163 | #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) |
| bogdanm | 73:1efda918f0ba | 164 | #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) |
| bogdanm | 73:1efda918f0ba | 165 | |
| bogdanm | 73:1efda918f0ba | 166 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 167 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 168 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
| bogdanm | 73:1efda918f0ba | 169 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 170 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
| bogdanm | 73:1efda918f0ba | 171 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
| bogdanm | 73:1efda918f0ba | 172 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
| bogdanm | 73:1efda918f0ba | 173 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
| bogdanm | 73:1efda918f0ba | 174 | #endif |
| bogdanm | 73:1efda918f0ba | 175 | /** |
| bogdanm | 73:1efda918f0ba | 176 | * @} |
| bogdanm | 73:1efda918f0ba | 177 | */ |
| bogdanm | 73:1efda918f0ba | 178 | |
| bogdanm | 73:1efda918f0ba | 179 | |
| bogdanm | 73:1efda918f0ba | 180 | /** @defgroup PREDIV1_clock_source |
| bogdanm | 73:1efda918f0ba | 181 | * @{ |
| bogdanm | 73:1efda918f0ba | 182 | */ |
| bogdanm | 73:1efda918f0ba | 183 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 184 | /* PREDIV1 clock source (for STM32 connectivity line devices) */ |
| bogdanm | 73:1efda918f0ba | 185 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 186 | #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 187 | |
| bogdanm | 73:1efda918f0ba | 188 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 189 | ((SOURCE) == RCC_PREDIV1_Source_PLL2)) |
| bogdanm | 73:1efda918f0ba | 190 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
| bogdanm | 73:1efda918f0ba | 191 | /* PREDIV1 clock source (for STM32 Value line devices) */ |
| bogdanm | 73:1efda918f0ba | 192 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 193 | |
| bogdanm | 73:1efda918f0ba | 194 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) |
| bogdanm | 73:1efda918f0ba | 195 | #endif |
| bogdanm | 73:1efda918f0ba | 196 | /** |
| bogdanm | 73:1efda918f0ba | 197 | * @} |
| bogdanm | 73:1efda918f0ba | 198 | */ |
| bogdanm | 73:1efda918f0ba | 199 | |
| bogdanm | 73:1efda918f0ba | 200 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 201 | /** @defgroup PREDIV2_division_factor |
| bogdanm | 73:1efda918f0ba | 202 | * @{ |
| bogdanm | 73:1efda918f0ba | 203 | */ |
| bogdanm | 73:1efda918f0ba | 204 | |
| bogdanm | 73:1efda918f0ba | 205 | #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 206 | #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 207 | #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 208 | #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) |
| bogdanm | 73:1efda918f0ba | 209 | #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 210 | #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) |
| bogdanm | 73:1efda918f0ba | 211 | #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) |
| bogdanm | 73:1efda918f0ba | 212 | #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) |
| bogdanm | 73:1efda918f0ba | 213 | #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 214 | #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) |
| bogdanm | 73:1efda918f0ba | 215 | #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) |
| bogdanm | 73:1efda918f0ba | 216 | #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) |
| bogdanm | 73:1efda918f0ba | 217 | #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) |
| bogdanm | 73:1efda918f0ba | 218 | #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) |
| bogdanm | 73:1efda918f0ba | 219 | #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) |
| bogdanm | 73:1efda918f0ba | 220 | #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) |
| bogdanm | 73:1efda918f0ba | 221 | |
| bogdanm | 73:1efda918f0ba | 222 | #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 223 | ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 224 | ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ |
| bogdanm | 73:1efda918f0ba | 225 | ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 226 | ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ |
| bogdanm | 73:1efda918f0ba | 227 | ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ |
| bogdanm | 73:1efda918f0ba | 228 | ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ |
| bogdanm | 73:1efda918f0ba | 229 | ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) |
| bogdanm | 73:1efda918f0ba | 230 | /** |
| bogdanm | 73:1efda918f0ba | 231 | * @} |
| bogdanm | 73:1efda918f0ba | 232 | */ |
| bogdanm | 73:1efda918f0ba | 233 | |
| bogdanm | 73:1efda918f0ba | 234 | |
| bogdanm | 73:1efda918f0ba | 235 | /** @defgroup PLL2_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 236 | * @{ |
| bogdanm | 73:1efda918f0ba | 237 | */ |
| bogdanm | 73:1efda918f0ba | 238 | |
| bogdanm | 73:1efda918f0ba | 239 | #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) |
| bogdanm | 73:1efda918f0ba | 240 | #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) |
| bogdanm | 73:1efda918f0ba | 241 | #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 242 | #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) |
| bogdanm | 73:1efda918f0ba | 243 | #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) |
| bogdanm | 73:1efda918f0ba | 244 | #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) |
| bogdanm | 73:1efda918f0ba | 245 | #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) |
| bogdanm | 73:1efda918f0ba | 246 | #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) |
| bogdanm | 73:1efda918f0ba | 247 | #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) |
| bogdanm | 73:1efda918f0ba | 248 | |
| bogdanm | 73:1efda918f0ba | 249 | #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ |
| bogdanm | 73:1efda918f0ba | 250 | ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ |
| bogdanm | 73:1efda918f0ba | 251 | ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ |
| bogdanm | 73:1efda918f0ba | 252 | ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ |
| bogdanm | 73:1efda918f0ba | 253 | ((MUL) == RCC_PLL2Mul_20)) |
| bogdanm | 73:1efda918f0ba | 254 | /** |
| bogdanm | 73:1efda918f0ba | 255 | * @} |
| bogdanm | 73:1efda918f0ba | 256 | */ |
| bogdanm | 73:1efda918f0ba | 257 | |
| bogdanm | 73:1efda918f0ba | 258 | |
| bogdanm | 73:1efda918f0ba | 259 | /** @defgroup PLL3_multiplication_factor |
| bogdanm | 73:1efda918f0ba | 260 | * @{ |
| bogdanm | 73:1efda918f0ba | 261 | */ |
| bogdanm | 73:1efda918f0ba | 262 | |
| bogdanm | 73:1efda918f0ba | 263 | #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) |
| bogdanm | 73:1efda918f0ba | 264 | #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) |
| bogdanm | 73:1efda918f0ba | 265 | #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 266 | #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) |
| bogdanm | 73:1efda918f0ba | 267 | #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) |
| bogdanm | 73:1efda918f0ba | 268 | #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) |
| bogdanm | 73:1efda918f0ba | 269 | #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) |
| bogdanm | 73:1efda918f0ba | 270 | #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) |
| bogdanm | 73:1efda918f0ba | 271 | #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) |
| bogdanm | 73:1efda918f0ba | 272 | |
| bogdanm | 73:1efda918f0ba | 273 | #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ |
| bogdanm | 73:1efda918f0ba | 274 | ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ |
| bogdanm | 73:1efda918f0ba | 275 | ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ |
| bogdanm | 73:1efda918f0ba | 276 | ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ |
| bogdanm | 73:1efda918f0ba | 277 | ((MUL) == RCC_PLL3Mul_20)) |
| bogdanm | 73:1efda918f0ba | 278 | /** |
| bogdanm | 73:1efda918f0ba | 279 | * @} |
| bogdanm | 73:1efda918f0ba | 280 | */ |
| bogdanm | 73:1efda918f0ba | 281 | |
| bogdanm | 73:1efda918f0ba | 282 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 283 | |
| bogdanm | 73:1efda918f0ba | 284 | |
| bogdanm | 73:1efda918f0ba | 285 | /** @defgroup System_clock_source |
| bogdanm | 73:1efda918f0ba | 286 | * @{ |
| bogdanm | 73:1efda918f0ba | 287 | */ |
| bogdanm | 73:1efda918f0ba | 288 | |
| bogdanm | 73:1efda918f0ba | 289 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 290 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 291 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 292 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 293 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 294 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| bogdanm | 73:1efda918f0ba | 295 | /** |
| bogdanm | 73:1efda918f0ba | 296 | * @} |
| bogdanm | 73:1efda918f0ba | 297 | */ |
| bogdanm | 73:1efda918f0ba | 298 | |
| bogdanm | 73:1efda918f0ba | 299 | /** @defgroup AHB_clock_source |
| bogdanm | 73:1efda918f0ba | 300 | * @{ |
| bogdanm | 73:1efda918f0ba | 301 | */ |
| bogdanm | 73:1efda918f0ba | 302 | |
| bogdanm | 73:1efda918f0ba | 303 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 304 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 305 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
| bogdanm | 73:1efda918f0ba | 306 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
| bogdanm | 73:1efda918f0ba | 307 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
| bogdanm | 73:1efda918f0ba | 308 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
| bogdanm | 73:1efda918f0ba | 309 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
| bogdanm | 73:1efda918f0ba | 310 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
| bogdanm | 73:1efda918f0ba | 311 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
| bogdanm | 73:1efda918f0ba | 312 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 313 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 314 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| bogdanm | 73:1efda918f0ba | 315 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| bogdanm | 73:1efda918f0ba | 316 | ((HCLK) == RCC_SYSCLK_Div512)) |
| bogdanm | 73:1efda918f0ba | 317 | /** |
| bogdanm | 73:1efda918f0ba | 318 | * @} |
| bogdanm | 73:1efda918f0ba | 319 | */ |
| bogdanm | 73:1efda918f0ba | 320 | |
| bogdanm | 73:1efda918f0ba | 321 | /** @defgroup APB1_APB2_clock_source |
| bogdanm | 73:1efda918f0ba | 322 | * @{ |
| bogdanm | 73:1efda918f0ba | 323 | */ |
| bogdanm | 73:1efda918f0ba | 324 | |
| bogdanm | 73:1efda918f0ba | 325 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 326 | #define RCC_HCLK_Div2 ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 327 | #define RCC_HCLK_Div4 ((uint32_t)0x00000500) |
| bogdanm | 73:1efda918f0ba | 328 | #define RCC_HCLK_Div8 ((uint32_t)0x00000600) |
| bogdanm | 73:1efda918f0ba | 329 | #define RCC_HCLK_Div16 ((uint32_t)0x00000700) |
| bogdanm | 73:1efda918f0ba | 330 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| bogdanm | 73:1efda918f0ba | 331 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| bogdanm | 73:1efda918f0ba | 332 | ((PCLK) == RCC_HCLK_Div16)) |
| bogdanm | 73:1efda918f0ba | 333 | /** |
| bogdanm | 73:1efda918f0ba | 334 | * @} |
| bogdanm | 73:1efda918f0ba | 335 | */ |
| bogdanm | 73:1efda918f0ba | 336 | |
| bogdanm | 73:1efda918f0ba | 337 | /** @defgroup RCC_Interrupt_source |
| bogdanm | 73:1efda918f0ba | 338 | * @{ |
| bogdanm | 73:1efda918f0ba | 339 | */ |
| bogdanm | 73:1efda918f0ba | 340 | |
| bogdanm | 73:1efda918f0ba | 341 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 342 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| bogdanm | 73:1efda918f0ba | 343 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 344 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| bogdanm | 73:1efda918f0ba | 345 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| bogdanm | 73:1efda918f0ba | 346 | #define RCC_IT_CSS ((uint8_t)0x80) |
| bogdanm | 73:1efda918f0ba | 347 | |
| bogdanm | 73:1efda918f0ba | 348 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 349 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 350 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 351 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 352 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) |
| bogdanm | 73:1efda918f0ba | 353 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 354 | #else |
| bogdanm | 73:1efda918f0ba | 355 | #define RCC_IT_PLL2RDY ((uint8_t)0x20) |
| bogdanm | 73:1efda918f0ba | 356 | #define RCC_IT_PLL3RDY ((uint8_t)0x40) |
| bogdanm | 73:1efda918f0ba | 357 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 358 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 359 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 360 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
| bogdanm | 73:1efda918f0ba | 361 | ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) |
| bogdanm | 73:1efda918f0ba | 362 | #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) |
| bogdanm | 73:1efda918f0ba | 363 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 364 | |
| bogdanm | 73:1efda918f0ba | 365 | |
| bogdanm | 73:1efda918f0ba | 366 | /** |
| bogdanm | 73:1efda918f0ba | 367 | * @} |
| bogdanm | 73:1efda918f0ba | 368 | */ |
| bogdanm | 73:1efda918f0ba | 369 | |
| bogdanm | 73:1efda918f0ba | 370 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 371 | /** @defgroup USB_Device_clock_source |
| bogdanm | 73:1efda918f0ba | 372 | * @{ |
| bogdanm | 73:1efda918f0ba | 373 | */ |
| bogdanm | 73:1efda918f0ba | 374 | |
| bogdanm | 73:1efda918f0ba | 375 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 376 | #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 377 | |
| bogdanm | 73:1efda918f0ba | 378 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ |
| bogdanm | 73:1efda918f0ba | 379 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) |
| bogdanm | 73:1efda918f0ba | 380 | /** |
| bogdanm | 73:1efda918f0ba | 381 | * @} |
| bogdanm | 73:1efda918f0ba | 382 | */ |
| bogdanm | 73:1efda918f0ba | 383 | #else |
| bogdanm | 73:1efda918f0ba | 384 | /** @defgroup USB_OTG_FS_clock_source |
| bogdanm | 73:1efda918f0ba | 385 | * @{ |
| bogdanm | 73:1efda918f0ba | 386 | */ |
| bogdanm | 73:1efda918f0ba | 387 | #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 388 | #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 389 | |
| bogdanm | 73:1efda918f0ba | 390 | #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ |
| bogdanm | 73:1efda918f0ba | 391 | ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) |
| bogdanm | 73:1efda918f0ba | 392 | /** |
| bogdanm | 73:1efda918f0ba | 393 | * @} |
| bogdanm | 73:1efda918f0ba | 394 | */ |
| bogdanm | 73:1efda918f0ba | 395 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 396 | |
| bogdanm | 73:1efda918f0ba | 397 | |
| bogdanm | 73:1efda918f0ba | 398 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 399 | /** @defgroup I2S2_clock_source |
| bogdanm | 73:1efda918f0ba | 400 | * @{ |
| bogdanm | 73:1efda918f0ba | 401 | */ |
| bogdanm | 73:1efda918f0ba | 402 | #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 403 | #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 404 | |
| bogdanm | 73:1efda918f0ba | 405 | #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ |
| bogdanm | 73:1efda918f0ba | 406 | ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) |
| bogdanm | 73:1efda918f0ba | 407 | /** |
| bogdanm | 73:1efda918f0ba | 408 | * @} |
| bogdanm | 73:1efda918f0ba | 409 | */ |
| bogdanm | 73:1efda918f0ba | 410 | |
| bogdanm | 73:1efda918f0ba | 411 | /** @defgroup I2S3_clock_source |
| bogdanm | 73:1efda918f0ba | 412 | * @{ |
| bogdanm | 73:1efda918f0ba | 413 | */ |
| bogdanm | 73:1efda918f0ba | 414 | #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 415 | #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 416 | |
| bogdanm | 73:1efda918f0ba | 417 | #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ |
| bogdanm | 73:1efda918f0ba | 418 | ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) |
| bogdanm | 73:1efda918f0ba | 419 | /** |
| bogdanm | 73:1efda918f0ba | 420 | * @} |
| bogdanm | 73:1efda918f0ba | 421 | */ |
| bogdanm | 73:1efda918f0ba | 422 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 423 | |
| bogdanm | 73:1efda918f0ba | 424 | |
| bogdanm | 73:1efda918f0ba | 425 | /** @defgroup ADC_clock_source |
| bogdanm | 73:1efda918f0ba | 426 | * @{ |
| bogdanm | 73:1efda918f0ba | 427 | */ |
| bogdanm | 73:1efda918f0ba | 428 | |
| bogdanm | 73:1efda918f0ba | 429 | #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) |
| bogdanm | 73:1efda918f0ba | 430 | #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 431 | #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 432 | #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) |
| bogdanm | 73:1efda918f0ba | 433 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ |
| bogdanm | 73:1efda918f0ba | 434 | ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) |
| bogdanm | 73:1efda918f0ba | 435 | /** |
| bogdanm | 73:1efda918f0ba | 436 | * @} |
| bogdanm | 73:1efda918f0ba | 437 | */ |
| bogdanm | 73:1efda918f0ba | 438 | |
| bogdanm | 73:1efda918f0ba | 439 | /** @defgroup LSE_configuration |
| bogdanm | 73:1efda918f0ba | 440 | * @{ |
| bogdanm | 73:1efda918f0ba | 441 | */ |
| bogdanm | 73:1efda918f0ba | 442 | |
| bogdanm | 73:1efda918f0ba | 443 | #define RCC_LSE_OFF ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 444 | #define RCC_LSE_ON ((uint8_t)0x01) |
| bogdanm | 73:1efda918f0ba | 445 | #define RCC_LSE_Bypass ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 446 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| bogdanm | 73:1efda918f0ba | 447 | ((LSE) == RCC_LSE_Bypass)) |
| bogdanm | 73:1efda918f0ba | 448 | /** |
| bogdanm | 73:1efda918f0ba | 449 | * @} |
| bogdanm | 73:1efda918f0ba | 450 | */ |
| bogdanm | 73:1efda918f0ba | 451 | |
| bogdanm | 73:1efda918f0ba | 452 | /** @defgroup RTC_clock_source |
| bogdanm | 73:1efda918f0ba | 453 | * @{ |
| bogdanm | 73:1efda918f0ba | 454 | */ |
| bogdanm | 73:1efda918f0ba | 455 | |
| bogdanm | 73:1efda918f0ba | 456 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 457 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
| bogdanm | 73:1efda918f0ba | 458 | #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) |
| bogdanm | 73:1efda918f0ba | 459 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| bogdanm | 73:1efda918f0ba | 460 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| bogdanm | 73:1efda918f0ba | 461 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) |
| bogdanm | 73:1efda918f0ba | 462 | /** |
| bogdanm | 73:1efda918f0ba | 463 | * @} |
| bogdanm | 73:1efda918f0ba | 464 | */ |
| bogdanm | 73:1efda918f0ba | 465 | |
| bogdanm | 73:1efda918f0ba | 466 | /** @defgroup AHB_peripheral |
| bogdanm | 73:1efda918f0ba | 467 | * @{ |
| bogdanm | 73:1efda918f0ba | 468 | */ |
| bogdanm | 73:1efda918f0ba | 469 | |
| bogdanm | 73:1efda918f0ba | 470 | #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 471 | #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 472 | #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 473 | #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 474 | #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 475 | |
| bogdanm | 73:1efda918f0ba | 476 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 477 | #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 478 | #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 479 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 480 | #else |
| bogdanm | 73:1efda918f0ba | 481 | #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) |
| bogdanm | 73:1efda918f0ba | 482 | #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 483 | #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 484 | #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 485 | |
| bogdanm | 73:1efda918f0ba | 486 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 487 | #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 488 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 489 | /** |
| bogdanm | 73:1efda918f0ba | 490 | * @} |
| bogdanm | 73:1efda918f0ba | 491 | */ |
| bogdanm | 73:1efda918f0ba | 492 | |
| bogdanm | 73:1efda918f0ba | 493 | /** @defgroup APB2_peripheral |
| bogdanm | 73:1efda918f0ba | 494 | * @{ |
| bogdanm | 73:1efda918f0ba | 495 | */ |
| bogdanm | 73:1efda918f0ba | 496 | |
| bogdanm | 73:1efda918f0ba | 497 | #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 498 | #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 499 | #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 500 | #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 501 | #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 502 | #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 503 | #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 504 | #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 505 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) |
| bogdanm | 73:1efda918f0ba | 506 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) |
| bogdanm | 73:1efda918f0ba | 507 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 508 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
| bogdanm | 73:1efda918f0ba | 509 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) |
| bogdanm | 73:1efda918f0ba | 510 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 511 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 512 | #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) |
| bogdanm | 73:1efda918f0ba | 513 | #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) |
| bogdanm | 73:1efda918f0ba | 514 | #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 515 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 516 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 517 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 518 | |
| bogdanm | 73:1efda918f0ba | 519 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 520 | /** |
| bogdanm | 73:1efda918f0ba | 521 | * @} |
| bogdanm | 73:1efda918f0ba | 522 | */ |
| bogdanm | 73:1efda918f0ba | 523 | |
| bogdanm | 73:1efda918f0ba | 524 | /** @defgroup APB1_peripheral |
| bogdanm | 73:1efda918f0ba | 525 | * @{ |
| bogdanm | 73:1efda918f0ba | 526 | */ |
| bogdanm | 73:1efda918f0ba | 527 | |
| bogdanm | 73:1efda918f0ba | 528 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
| bogdanm | 73:1efda918f0ba | 529 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
| bogdanm | 73:1efda918f0ba | 530 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
| bogdanm | 73:1efda918f0ba | 531 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
| bogdanm | 73:1efda918f0ba | 532 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
| bogdanm | 73:1efda918f0ba | 533 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
| bogdanm | 73:1efda918f0ba | 534 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
| bogdanm | 73:1efda918f0ba | 535 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
| bogdanm | 73:1efda918f0ba | 536 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
| bogdanm | 73:1efda918f0ba | 537 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
| bogdanm | 73:1efda918f0ba | 538 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
| bogdanm | 73:1efda918f0ba | 539 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
| bogdanm | 73:1efda918f0ba | 540 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
| bogdanm | 73:1efda918f0ba | 541 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
| bogdanm | 73:1efda918f0ba | 542 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
| bogdanm | 73:1efda918f0ba | 543 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
| bogdanm | 73:1efda918f0ba | 544 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
| bogdanm | 73:1efda918f0ba | 545 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
| bogdanm | 73:1efda918f0ba | 546 | #define RCC_APB1Periph_USB ((uint32_t)0x00800000) |
| bogdanm | 73:1efda918f0ba | 547 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
| bogdanm | 73:1efda918f0ba | 548 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
| bogdanm | 73:1efda918f0ba | 549 | #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) |
| bogdanm | 73:1efda918f0ba | 550 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
| bogdanm | 73:1efda918f0ba | 551 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
| bogdanm | 73:1efda918f0ba | 552 | #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) |
| bogdanm | 73:1efda918f0ba | 553 | |
| bogdanm | 73:1efda918f0ba | 554 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 73:1efda918f0ba | 555 | |
| bogdanm | 73:1efda918f0ba | 556 | /** |
| bogdanm | 73:1efda918f0ba | 557 | * @} |
| bogdanm | 73:1efda918f0ba | 558 | */ |
| bogdanm | 73:1efda918f0ba | 559 | |
| bogdanm | 73:1efda918f0ba | 560 | /** @defgroup Clock_source_to_output_on_MCO_pin |
| bogdanm | 73:1efda918f0ba | 561 | * @{ |
| bogdanm | 73:1efda918f0ba | 562 | */ |
| bogdanm | 73:1efda918f0ba | 563 | |
| bogdanm | 73:1efda918f0ba | 564 | #define RCC_MCO_NoClock ((uint8_t)0x00) |
| bogdanm | 73:1efda918f0ba | 565 | #define RCC_MCO_SYSCLK ((uint8_t)0x04) |
| bogdanm | 73:1efda918f0ba | 566 | #define RCC_MCO_HSI ((uint8_t)0x05) |
| bogdanm | 73:1efda918f0ba | 567 | #define RCC_MCO_HSE ((uint8_t)0x06) |
| bogdanm | 73:1efda918f0ba | 568 | #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) |
| bogdanm | 73:1efda918f0ba | 569 | |
| bogdanm | 73:1efda918f0ba | 570 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 571 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 572 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 573 | ((MCO) == RCC_MCO_PLLCLK_Div2)) |
| bogdanm | 73:1efda918f0ba | 574 | #else |
| bogdanm | 73:1efda918f0ba | 575 | #define RCC_MCO_PLL2CLK ((uint8_t)0x08) |
| bogdanm | 73:1efda918f0ba | 576 | #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) |
| bogdanm | 73:1efda918f0ba | 577 | #define RCC_MCO_XT1 ((uint8_t)0x0A) |
| bogdanm | 73:1efda918f0ba | 578 | #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) |
| bogdanm | 73:1efda918f0ba | 579 | |
| bogdanm | 73:1efda918f0ba | 580 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ |
| bogdanm | 73:1efda918f0ba | 581 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
| bogdanm | 73:1efda918f0ba | 582 | ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ |
| bogdanm | 73:1efda918f0ba | 583 | ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ |
| bogdanm | 73:1efda918f0ba | 584 | ((MCO) == RCC_MCO_PLL3CLK)) |
| bogdanm | 73:1efda918f0ba | 585 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 586 | |
| bogdanm | 73:1efda918f0ba | 587 | /** |
| bogdanm | 73:1efda918f0ba | 588 | * @} |
| bogdanm | 73:1efda918f0ba | 589 | */ |
| bogdanm | 73:1efda918f0ba | 590 | |
| bogdanm | 73:1efda918f0ba | 591 | /** @defgroup RCC_Flag |
| bogdanm | 73:1efda918f0ba | 592 | * @{ |
| bogdanm | 73:1efda918f0ba | 593 | */ |
| bogdanm | 73:1efda918f0ba | 594 | |
| bogdanm | 73:1efda918f0ba | 595 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
| bogdanm | 73:1efda918f0ba | 596 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
| bogdanm | 73:1efda918f0ba | 597 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
| bogdanm | 73:1efda918f0ba | 598 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
| bogdanm | 73:1efda918f0ba | 599 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
| bogdanm | 73:1efda918f0ba | 600 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
| bogdanm | 73:1efda918f0ba | 601 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
| bogdanm | 73:1efda918f0ba | 602 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
| bogdanm | 73:1efda918f0ba | 603 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
| bogdanm | 73:1efda918f0ba | 604 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
| bogdanm | 73:1efda918f0ba | 605 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
| bogdanm | 73:1efda918f0ba | 606 | |
| bogdanm | 73:1efda918f0ba | 607 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 608 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 609 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 610 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
| bogdanm | 73:1efda918f0ba | 611 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
| bogdanm | 73:1efda918f0ba | 612 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
| bogdanm | 73:1efda918f0ba | 613 | ((FLAG) == RCC_FLAG_LPWRRST)) |
| bogdanm | 73:1efda918f0ba | 614 | #else |
| bogdanm | 73:1efda918f0ba | 615 | #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) |
| bogdanm | 73:1efda918f0ba | 616 | #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) |
| bogdanm | 73:1efda918f0ba | 617 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 618 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| bogdanm | 73:1efda918f0ba | 619 | ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ |
| bogdanm | 73:1efda918f0ba | 620 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
| bogdanm | 73:1efda918f0ba | 621 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
| bogdanm | 73:1efda918f0ba | 622 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
| bogdanm | 73:1efda918f0ba | 623 | ((FLAG) == RCC_FLAG_LPWRRST)) |
| bogdanm | 73:1efda918f0ba | 624 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 625 | |
| bogdanm | 73:1efda918f0ba | 626 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| bogdanm | 73:1efda918f0ba | 627 | /** |
| bogdanm | 73:1efda918f0ba | 628 | * @} |
| bogdanm | 73:1efda918f0ba | 629 | */ |
| bogdanm | 73:1efda918f0ba | 630 | |
| bogdanm | 73:1efda918f0ba | 631 | /** |
| bogdanm | 73:1efda918f0ba | 632 | * @} |
| bogdanm | 73:1efda918f0ba | 633 | */ |
| bogdanm | 73:1efda918f0ba | 634 | |
| bogdanm | 73:1efda918f0ba | 635 | /** @defgroup RCC_Exported_Macros |
| bogdanm | 73:1efda918f0ba | 636 | * @{ |
| bogdanm | 73:1efda918f0ba | 637 | */ |
| bogdanm | 73:1efda918f0ba | 638 | |
| bogdanm | 73:1efda918f0ba | 639 | /** |
| bogdanm | 73:1efda918f0ba | 640 | * @} |
| bogdanm | 73:1efda918f0ba | 641 | */ |
| bogdanm | 73:1efda918f0ba | 642 | |
| bogdanm | 73:1efda918f0ba | 643 | /** @defgroup RCC_Exported_Functions |
| bogdanm | 73:1efda918f0ba | 644 | * @{ |
| bogdanm | 73:1efda918f0ba | 645 | */ |
| bogdanm | 73:1efda918f0ba | 646 | |
| bogdanm | 73:1efda918f0ba | 647 | void RCC_DeInit(void); |
| bogdanm | 73:1efda918f0ba | 648 | void RCC_HSEConfig(uint32_t RCC_HSE); |
| bogdanm | 73:1efda918f0ba | 649 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| bogdanm | 73:1efda918f0ba | 650 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| bogdanm | 73:1efda918f0ba | 651 | void RCC_HSICmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 652 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); |
| bogdanm | 73:1efda918f0ba | 653 | void RCC_PLLCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 654 | |
| bogdanm | 73:1efda918f0ba | 655 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
| bogdanm | 73:1efda918f0ba | 656 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); |
| bogdanm | 73:1efda918f0ba | 657 | #endif |
| bogdanm | 73:1efda918f0ba | 658 | |
| bogdanm | 73:1efda918f0ba | 659 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 660 | void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); |
| bogdanm | 73:1efda918f0ba | 661 | void RCC_PLL2Config(uint32_t RCC_PLL2Mul); |
| bogdanm | 73:1efda918f0ba | 662 | void RCC_PLL2Cmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 663 | void RCC_PLL3Config(uint32_t RCC_PLL3Mul); |
| bogdanm | 73:1efda918f0ba | 664 | void RCC_PLL3Cmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 665 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 666 | |
| bogdanm | 73:1efda918f0ba | 667 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| bogdanm | 73:1efda918f0ba | 668 | uint8_t RCC_GetSYSCLKSource(void); |
| bogdanm | 73:1efda918f0ba | 669 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| bogdanm | 73:1efda918f0ba | 670 | void RCC_PCLK1Config(uint32_t RCC_HCLK); |
| bogdanm | 73:1efda918f0ba | 671 | void RCC_PCLK2Config(uint32_t RCC_HCLK); |
| bogdanm | 73:1efda918f0ba | 672 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 673 | |
| bogdanm | 73:1efda918f0ba | 674 | #ifndef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 675 | void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); |
| bogdanm | 73:1efda918f0ba | 676 | #else |
| bogdanm | 73:1efda918f0ba | 677 | void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); |
| bogdanm | 73:1efda918f0ba | 678 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 679 | |
| bogdanm | 73:1efda918f0ba | 680 | void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); |
| bogdanm | 73:1efda918f0ba | 681 | |
| bogdanm | 73:1efda918f0ba | 682 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 683 | void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); |
| bogdanm | 73:1efda918f0ba | 684 | void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); |
| bogdanm | 73:1efda918f0ba | 685 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 686 | |
| bogdanm | 73:1efda918f0ba | 687 | void RCC_LSEConfig(uint8_t RCC_LSE); |
| bogdanm | 73:1efda918f0ba | 688 | void RCC_LSICmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 689 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| bogdanm | 73:1efda918f0ba | 690 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 691 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| bogdanm | 73:1efda918f0ba | 692 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 693 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 694 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 695 | |
| bogdanm | 73:1efda918f0ba | 696 | #ifdef STM32F10X_CL |
| bogdanm | 73:1efda918f0ba | 697 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 698 | #endif /* STM32F10X_CL */ |
| bogdanm | 73:1efda918f0ba | 699 | |
| bogdanm | 73:1efda918f0ba | 700 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 701 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 702 | void RCC_BackupResetCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 703 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| bogdanm | 73:1efda918f0ba | 704 | void RCC_MCOConfig(uint8_t RCC_MCO); |
| bogdanm | 73:1efda918f0ba | 705 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| bogdanm | 73:1efda918f0ba | 706 | void RCC_ClearFlag(void); |
| bogdanm | 73:1efda918f0ba | 707 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| bogdanm | 73:1efda918f0ba | 708 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| bogdanm | 73:1efda918f0ba | 709 | |
| bogdanm | 73:1efda918f0ba | 710 | #ifdef __cplusplus |
| bogdanm | 73:1efda918f0ba | 711 | } |
| bogdanm | 73:1efda918f0ba | 712 | #endif |
| bogdanm | 73:1efda918f0ba | 713 | |
| bogdanm | 73:1efda918f0ba | 714 | #endif /* __STM32F10x_RCC_H */ |
| bogdanm | 73:1efda918f0ba | 715 | /** |
| bogdanm | 73:1efda918f0ba | 716 | * @} |
| bogdanm | 73:1efda918f0ba | 717 | */ |
| bogdanm | 73:1efda918f0ba | 718 | |
| bogdanm | 73:1efda918f0ba | 719 | /** |
| bogdanm | 73:1efda918f0ba | 720 | * @} |
| bogdanm | 73:1efda918f0ba | 721 | */ |
| bogdanm | 73:1efda918f0ba | 722 | |
| bogdanm | 73:1efda918f0ba | 723 | /** |
| bogdanm | 73:1efda918f0ba | 724 | * @} |
| bogdanm | 73:1efda918f0ba | 725 | */ |
| bogdanm | 73:1efda918f0ba | 726 | |
| bogdanm | 73:1efda918f0ba | 727 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |