/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Wed Jun 11 15:14:05 2014 +0100
Revision:
85:024bf7f99721
Child:
92:4fc01daae5a5
Release 85 of the mbed library

Main changes:

- K64F Ethernet fixes
- Updated tests
- Fixes for various mbed targets
- Code cleanup: fixed warnings, more consistent code style
- GCC support for K64F

There is a known issue with the I2C interface on some ST targets. If you
find the I2C interface problematic on your ST board, please log a bug
against this on mbed.org.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_tim.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
bogdanm 85:024bf7f99721 5 * @version V1.0.0
bogdanm 85:024bf7f99721 6 * @date 28-May-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of TIM HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_TIM_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_TIM_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup TIM
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 58
bogdanm 85:024bf7f99721 59 /**
bogdanm 85:024bf7f99721 60 * @brief TIM Time base Configuration Structure definition
bogdanm 85:024bf7f99721 61 */
bogdanm 85:024bf7f99721 62 typedef struct
bogdanm 85:024bf7f99721 63 {
bogdanm 85:024bf7f99721 64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 85:024bf7f99721 65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 85:024bf7f99721 66
bogdanm 85:024bf7f99721 67 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 85:024bf7f99721 68 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 85:024bf7f99721 69
bogdanm 85:024bf7f99721 70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 85:024bf7f99721 71 Auto-Reload Register at the next update event.
bogdanm 85:024bf7f99721 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 85:024bf7f99721 73
bogdanm 85:024bf7f99721 74 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 85:024bf7f99721 75 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 85:024bf7f99721 76
bogdanm 85:024bf7f99721 77 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 85:024bf7f99721 78 reaches zero, an update event is generated and counting restarts
bogdanm 85:024bf7f99721 79 from the RCR value (N).
bogdanm 85:024bf7f99721 80 This means in PWM mode that (N+1) corresponds to:
bogdanm 85:024bf7f99721 81 - the number of PWM periods in edge-aligned mode
bogdanm 85:024bf7f99721 82 - the number of half PWM period in center-aligned mode
bogdanm 85:024bf7f99721 83 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm 85:024bf7f99721 84 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 85 } TIM_Base_InitTypeDef;
bogdanm 85:024bf7f99721 86
bogdanm 85:024bf7f99721 87 /**
bogdanm 85:024bf7f99721 88 * @brief TIM Output Compare Configuration Structure definition
bogdanm 85:024bf7f99721 89 */
bogdanm 85:024bf7f99721 90 typedef struct
bogdanm 85:024bf7f99721 91 {
bogdanm 85:024bf7f99721 92 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 85:024bf7f99721 93 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 85:024bf7f99721 94
bogdanm 85:024bf7f99721 95 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 85:024bf7f99721 96 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 85:024bf7f99721 97
bogdanm 85:024bf7f99721 98 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 85:024bf7f99721 99 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 85:024bf7f99721 100
bogdanm 85:024bf7f99721 101 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 85:024bf7f99721 102 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 85:024bf7f99721 103 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 104
bogdanm 85:024bf7f99721 105 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 85:024bf7f99721 106 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 85:024bf7f99721 107 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 85:024bf7f99721 108
bogdanm 85:024bf7f99721 109
bogdanm 85:024bf7f99721 110 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 85:024bf7f99721 111 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 85:024bf7f99721 112 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 113
bogdanm 85:024bf7f99721 114 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 85:024bf7f99721 115 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 85:024bf7f99721 116 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 117 } TIM_OC_InitTypeDef;
bogdanm 85:024bf7f99721 118
bogdanm 85:024bf7f99721 119 /**
bogdanm 85:024bf7f99721 120 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 85:024bf7f99721 121 */
bogdanm 85:024bf7f99721 122 typedef struct
bogdanm 85:024bf7f99721 123 {
bogdanm 85:024bf7f99721 124 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 85:024bf7f99721 125 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 85:024bf7f99721 126
bogdanm 85:024bf7f99721 127 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 85:024bf7f99721 128 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 85:024bf7f99721 129
bogdanm 85:024bf7f99721 130 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 85:024bf7f99721 131 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 85:024bf7f99721 132
bogdanm 85:024bf7f99721 133 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 85:024bf7f99721 134 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 85:024bf7f99721 135 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 136
bogdanm 85:024bf7f99721 137 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 85:024bf7f99721 138 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 85:024bf7f99721 139 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 140
bogdanm 85:024bf7f99721 141 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 85:024bf7f99721 142 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 85:024bf7f99721 143 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 85:024bf7f99721 144
bogdanm 85:024bf7f99721 145 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 85:024bf7f99721 146 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 85:024bf7f99721 147
bogdanm 85:024bf7f99721 148 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 85:024bf7f99721 149 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 85:024bf7f99721 150
bogdanm 85:024bf7f99721 151 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 85:024bf7f99721 152 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 85:024bf7f99721 153 } TIM_OnePulse_InitTypeDef;
bogdanm 85:024bf7f99721 154
bogdanm 85:024bf7f99721 155
bogdanm 85:024bf7f99721 156 /**
bogdanm 85:024bf7f99721 157 * @brief TIM Input Capture Configuration Structure definition
bogdanm 85:024bf7f99721 158 */
bogdanm 85:024bf7f99721 159 typedef struct
bogdanm 85:024bf7f99721 160 {
bogdanm 85:024bf7f99721 161 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 85:024bf7f99721 162 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 85:024bf7f99721 163
bogdanm 85:024bf7f99721 164 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 85:024bf7f99721 165 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 85:024bf7f99721 166
bogdanm 85:024bf7f99721 167 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 85:024bf7f99721 168 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 85:024bf7f99721 169
bogdanm 85:024bf7f99721 170 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 85:024bf7f99721 171 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 85:024bf7f99721 172 } TIM_IC_InitTypeDef;
bogdanm 85:024bf7f99721 173
bogdanm 85:024bf7f99721 174 /**
bogdanm 85:024bf7f99721 175 * @brief TIM Encoder Configuration Structure definition
bogdanm 85:024bf7f99721 176 */
bogdanm 85:024bf7f99721 177 typedef struct
bogdanm 85:024bf7f99721 178 {
bogdanm 85:024bf7f99721 179 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 85:024bf7f99721 180 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 85:024bf7f99721 181
bogdanm 85:024bf7f99721 182 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 85:024bf7f99721 183 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 85:024bf7f99721 184
bogdanm 85:024bf7f99721 185 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 85:024bf7f99721 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 85:024bf7f99721 187
bogdanm 85:024bf7f99721 188 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 85:024bf7f99721 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 85:024bf7f99721 190
bogdanm 85:024bf7f99721 191 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 85:024bf7f99721 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 85:024bf7f99721 193
bogdanm 85:024bf7f99721 194 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 85:024bf7f99721 195 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 85:024bf7f99721 196
bogdanm 85:024bf7f99721 197 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 85:024bf7f99721 198 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 85:024bf7f99721 199
bogdanm 85:024bf7f99721 200 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 85:024bf7f99721 201 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 85:024bf7f99721 202
bogdanm 85:024bf7f99721 203 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 85:024bf7f99721 204 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 85:024bf7f99721 205 } TIM_Encoder_InitTypeDef;
bogdanm 85:024bf7f99721 206
bogdanm 85:024bf7f99721 207
bogdanm 85:024bf7f99721 208 /**
bogdanm 85:024bf7f99721 209 * @brief Clock Configuration Handle Structure definition
bogdanm 85:024bf7f99721 210 */
bogdanm 85:024bf7f99721 211 typedef struct
bogdanm 85:024bf7f99721 212 {
bogdanm 85:024bf7f99721 213 uint32_t ClockSource; /*!< TIM clock sources
bogdanm 85:024bf7f99721 214 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 85:024bf7f99721 215 uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm 85:024bf7f99721 216 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 85:024bf7f99721 217 uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm 85:024bf7f99721 218 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 85:024bf7f99721 219 uint32_t ClockFilter; /*!< TIM clock filter
bogdanm 85:024bf7f99721 220 This parameter can be a value of @ref TIM_Clock_Filter */
bogdanm 85:024bf7f99721 221 }TIM_ClockConfigTypeDef;
bogdanm 85:024bf7f99721 222
bogdanm 85:024bf7f99721 223 /**
bogdanm 85:024bf7f99721 224 * @brief Clear Input Configuration Handle Structure definition
bogdanm 85:024bf7f99721 225 */
bogdanm 85:024bf7f99721 226 typedef struct
bogdanm 85:024bf7f99721 227 {
bogdanm 85:024bf7f99721 228 uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm 85:024bf7f99721 229 This parameter can be ENABLE or DISABLE */
bogdanm 85:024bf7f99721 230 uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm 85:024bf7f99721 231 This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm 85:024bf7f99721 232 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm 85:024bf7f99721 233 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 85:024bf7f99721 234 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm 85:024bf7f99721 235 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 85:024bf7f99721 236 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm 85:024bf7f99721 237 This parameter can be a value of @ref TIM_ClearInput_Filter */
bogdanm 85:024bf7f99721 238 }TIM_ClearInputConfigTypeDef;
bogdanm 85:024bf7f99721 239
bogdanm 85:024bf7f99721 240 /**
bogdanm 85:024bf7f99721 241 * @brief TIM Slave configuration Structure definition
bogdanm 85:024bf7f99721 242 */
bogdanm 85:024bf7f99721 243 typedef struct {
bogdanm 85:024bf7f99721 244 uint32_t SlaveMode; /*!< Slave mode selection
bogdanm 85:024bf7f99721 245 This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm 85:024bf7f99721 246 uint32_t InputTrigger; /*!< Input Trigger source
bogdanm 85:024bf7f99721 247 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 85:024bf7f99721 248 uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm 85:024bf7f99721 249 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 85:024bf7f99721 250 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm 85:024bf7f99721 251 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 85:024bf7f99721 252 uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm 85:024bf7f99721 253 This parameter can be a value of @ref TIM_Trigger_Filter */
bogdanm 85:024bf7f99721 254
bogdanm 85:024bf7f99721 255 }TIM_SlaveConfigTypeDef;
bogdanm 85:024bf7f99721 256
bogdanm 85:024bf7f99721 257 /**
bogdanm 85:024bf7f99721 258 * @brief HAL State structures definition
bogdanm 85:024bf7f99721 259 */
bogdanm 85:024bf7f99721 260 typedef enum
bogdanm 85:024bf7f99721 261 {
bogdanm 85:024bf7f99721 262 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 85:024bf7f99721 263 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 85:024bf7f99721 264 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 85:024bf7f99721 265 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 85:024bf7f99721 266 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 85:024bf7f99721 267 }HAL_TIM_StateTypeDef;
bogdanm 85:024bf7f99721 268
bogdanm 85:024bf7f99721 269 /**
bogdanm 85:024bf7f99721 270 * @brief HAL Active channel structures definition
bogdanm 85:024bf7f99721 271 */
bogdanm 85:024bf7f99721 272 typedef enum
bogdanm 85:024bf7f99721 273 {
bogdanm 85:024bf7f99721 274 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 85:024bf7f99721 275 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 85:024bf7f99721 276 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 85:024bf7f99721 277 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 85:024bf7f99721 278 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 85:024bf7f99721 279 }HAL_TIM_ActiveChannel;
bogdanm 85:024bf7f99721 280
bogdanm 85:024bf7f99721 281 /**
bogdanm 85:024bf7f99721 282 * @brief TIM Time Base Handle Structure definition
bogdanm 85:024bf7f99721 283 */
bogdanm 85:024bf7f99721 284 typedef struct
bogdanm 85:024bf7f99721 285 {
bogdanm 85:024bf7f99721 286 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 287 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 85:024bf7f99721 288 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 85:024bf7f99721 289 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 85:024bf7f99721 290 This array is accessed by a @ref DMA_Handle_index */
bogdanm 85:024bf7f99721 291 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 85:024bf7f99721 292 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 85:024bf7f99721 293 }TIM_HandleTypeDef;
bogdanm 85:024bf7f99721 294
bogdanm 85:024bf7f99721 295 /* Exported constants --------------------------------------------------------*/
bogdanm 85:024bf7f99721 296 /** @defgroup TIM_Exported_Constants
bogdanm 85:024bf7f99721 297 * @{
bogdanm 85:024bf7f99721 298 */
bogdanm 85:024bf7f99721 299
bogdanm 85:024bf7f99721 300 /** @defgroup TIM_Input_Channel_Polarity
bogdanm 85:024bf7f99721 301 * @{
bogdanm 85:024bf7f99721 302 */
bogdanm 85:024bf7f99721 303 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 85:024bf7f99721 304 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 85:024bf7f99721 305 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 85:024bf7f99721 306 /**
bogdanm 85:024bf7f99721 307 * @}
bogdanm 85:024bf7f99721 308 */
bogdanm 85:024bf7f99721 309
bogdanm 85:024bf7f99721 310 /** @defgroup TIM_ETR_Polarity
bogdanm 85:024bf7f99721 311 * @{
bogdanm 85:024bf7f99721 312 */
bogdanm 85:024bf7f99721 313 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 85:024bf7f99721 314 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 85:024bf7f99721 315 /**
bogdanm 85:024bf7f99721 316 * @}
bogdanm 85:024bf7f99721 317 */
bogdanm 85:024bf7f99721 318
bogdanm 85:024bf7f99721 319 /** @defgroup TIM_ETR_Prescaler
bogdanm 85:024bf7f99721 320 * @{
bogdanm 85:024bf7f99721 321 */
bogdanm 85:024bf7f99721 322 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 85:024bf7f99721 323 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 85:024bf7f99721 324 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 85:024bf7f99721 325 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 85:024bf7f99721 326 /**
bogdanm 85:024bf7f99721 327 * @}
bogdanm 85:024bf7f99721 328 */
bogdanm 85:024bf7f99721 329
bogdanm 85:024bf7f99721 330 /** @defgroup TIM_Counter_Mode
bogdanm 85:024bf7f99721 331 * @{
bogdanm 85:024bf7f99721 332 */
bogdanm 85:024bf7f99721 333 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 334 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 85:024bf7f99721 335 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 85:024bf7f99721 336 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 85:024bf7f99721 337 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 85:024bf7f99721 338
bogdanm 85:024bf7f99721 339 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
bogdanm 85:024bf7f99721 340 ((MODE) == TIM_COUNTERMODE_DOWN) || \
bogdanm 85:024bf7f99721 341 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
bogdanm 85:024bf7f99721 342 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
bogdanm 85:024bf7f99721 343 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm 85:024bf7f99721 344 /**
bogdanm 85:024bf7f99721 345 * @}
bogdanm 85:024bf7f99721 346 */
bogdanm 85:024bf7f99721 347
bogdanm 85:024bf7f99721 348 /** @defgroup TIM_ClockDivision
bogdanm 85:024bf7f99721 349 * @{
bogdanm 85:024bf7f99721 350 */
bogdanm 85:024bf7f99721 351 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 85:024bf7f99721 353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 85:024bf7f99721 354
bogdanm 85:024bf7f99721 355 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
bogdanm 85:024bf7f99721 356 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
bogdanm 85:024bf7f99721 357 ((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm 85:024bf7f99721 358 /**
bogdanm 85:024bf7f99721 359 * @}
bogdanm 85:024bf7f99721 360 */
bogdanm 85:024bf7f99721 361
bogdanm 85:024bf7f99721 362 /** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm 85:024bf7f99721 363 * @{
bogdanm 85:024bf7f99721 364 */
bogdanm 85:024bf7f99721 365 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 366 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm 85:024bf7f99721 367 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm 85:024bf7f99721 368 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 85:024bf7f99721 369 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 85:024bf7f99721 370 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm 85:024bf7f99721 371 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 85:024bf7f99721 372 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm 85:024bf7f99721 373
bogdanm 85:024bf7f99721 374 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
bogdanm 85:024bf7f99721 375 ((MODE) == TIM_OCMODE_PWM2))
bogdanm 85:024bf7f99721 376
bogdanm 85:024bf7f99721 377 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
bogdanm 85:024bf7f99721 378 ((MODE) == TIM_OCMODE_ACTIVE) || \
bogdanm 85:024bf7f99721 379 ((MODE) == TIM_OCMODE_INACTIVE) || \
bogdanm 85:024bf7f99721 380 ((MODE) == TIM_OCMODE_TOGGLE) || \
bogdanm 85:024bf7f99721 381 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
bogdanm 85:024bf7f99721 382 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm 85:024bf7f99721 383 /**
bogdanm 85:024bf7f99721 384 * @}
bogdanm 85:024bf7f99721 385 */
bogdanm 85:024bf7f99721 386
bogdanm 85:024bf7f99721 387 /** @defgroup TIM_Output_Compare_State
bogdanm 85:024bf7f99721 388 * @{
bogdanm 85:024bf7f99721 389 */
bogdanm 85:024bf7f99721 390 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 391 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm 85:024bf7f99721 392
bogdanm 85:024bf7f99721 393 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
bogdanm 85:024bf7f99721 394 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm 85:024bf7f99721 395 /**
bogdanm 85:024bf7f99721 396 * @}
bogdanm 85:024bf7f99721 397 */
bogdanm 85:024bf7f99721 398
bogdanm 85:024bf7f99721 399 /** @defgroup TIM_Output_Fast_State
bogdanm 85:024bf7f99721 400 * @{
bogdanm 85:024bf7f99721 401 */
bogdanm 85:024bf7f99721 402 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 403 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 85:024bf7f99721 404
bogdanm 85:024bf7f99721 405 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
bogdanm 85:024bf7f99721 406 ((STATE) == TIM_OCFAST_ENABLE))
bogdanm 85:024bf7f99721 407 /**
bogdanm 85:024bf7f99721 408 * @}
bogdanm 85:024bf7f99721 409 */
bogdanm 85:024bf7f99721 410
bogdanm 85:024bf7f99721 411 /** @defgroup TIM_Output_Compare_N_State
bogdanm 85:024bf7f99721 412 * @{
bogdanm 85:024bf7f99721 413 */
bogdanm 85:024bf7f99721 414 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 415 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm 85:024bf7f99721 416
bogdanm 85:024bf7f99721 417 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
bogdanm 85:024bf7f99721 418 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm 85:024bf7f99721 419 /**
bogdanm 85:024bf7f99721 420 * @}
bogdanm 85:024bf7f99721 421 */
bogdanm 85:024bf7f99721 422
bogdanm 85:024bf7f99721 423 /** @defgroup TIM_Output_Compare_Polarity
bogdanm 85:024bf7f99721 424 * @{
bogdanm 85:024bf7f99721 425 */
bogdanm 85:024bf7f99721 426 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 427 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 85:024bf7f99721 428
bogdanm 85:024bf7f99721 429 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
bogdanm 85:024bf7f99721 430 ((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm 85:024bf7f99721 431 /**
bogdanm 85:024bf7f99721 432 * @}
bogdanm 85:024bf7f99721 433 */
bogdanm 85:024bf7f99721 434
bogdanm 85:024bf7f99721 435 /** @defgroup TIM_Output_Compare_N_Polarity
bogdanm 85:024bf7f99721 436 * @{
bogdanm 85:024bf7f99721 437 */
bogdanm 85:024bf7f99721 438 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 439 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm 85:024bf7f99721 440
bogdanm 85:024bf7f99721 441 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
bogdanm 85:024bf7f99721 442 ((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm 85:024bf7f99721 443 /**
bogdanm 85:024bf7f99721 444 * @}
bogdanm 85:024bf7f99721 445 */
bogdanm 85:024bf7f99721 446
bogdanm 85:024bf7f99721 447 /** @defgroup TIM_Output_Compare_Idle_State
bogdanm 85:024bf7f99721 448 * @{
bogdanm 85:024bf7f99721 449 */
bogdanm 85:024bf7f99721 450 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm 85:024bf7f99721 451 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 452 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
bogdanm 85:024bf7f99721 453 ((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm 85:024bf7f99721 454 /**
bogdanm 85:024bf7f99721 455 * @}
bogdanm 85:024bf7f99721 456 */
bogdanm 85:024bf7f99721 457
bogdanm 85:024bf7f99721 458 /** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm 85:024bf7f99721 459 * @{
bogdanm 85:024bf7f99721 460 */
bogdanm 85:024bf7f99721 461 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm 85:024bf7f99721 462 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 463
bogdanm 85:024bf7f99721 464 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
bogdanm 85:024bf7f99721 465 ((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm 85:024bf7f99721 466 /**
bogdanm 85:024bf7f99721 467 * @}
bogdanm 85:024bf7f99721 468 */
bogdanm 85:024bf7f99721 469
bogdanm 85:024bf7f99721 470 /** @defgroup TIM_Channel
bogdanm 85:024bf7f99721 471 * @{
bogdanm 85:024bf7f99721 472 */
bogdanm 85:024bf7f99721 473 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 474 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 85:024bf7f99721 475 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 85:024bf7f99721 476 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 85:024bf7f99721 477 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 85:024bf7f99721 478
bogdanm 85:024bf7f99721 479 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 85:024bf7f99721 480 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 85:024bf7f99721 481 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 85:024bf7f99721 482 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 85:024bf7f99721 483 ((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm 85:024bf7f99721 484
bogdanm 85:024bf7f99721 485 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 85:024bf7f99721 486 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 85:024bf7f99721 487
bogdanm 85:024bf7f99721 488 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 85:024bf7f99721 489 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 85:024bf7f99721 490
bogdanm 85:024bf7f99721 491 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 85:024bf7f99721 492 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 85:024bf7f99721 493 ((CHANNEL) == TIM_CHANNEL_3))
bogdanm 85:024bf7f99721 494 /**
bogdanm 85:024bf7f99721 495 * @}
bogdanm 85:024bf7f99721 496 */
bogdanm 85:024bf7f99721 497
bogdanm 85:024bf7f99721 498 /** @defgroup TIM_Input_Capture_Polarity
bogdanm 85:024bf7f99721 499 * @{
bogdanm 85:024bf7f99721 500 */
bogdanm 85:024bf7f99721 501 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 85:024bf7f99721 502 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 85:024bf7f99721 503 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 85:024bf7f99721 504
bogdanm 85:024bf7f99721 505 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
bogdanm 85:024bf7f99721 506 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
bogdanm 85:024bf7f99721 507 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm 85:024bf7f99721 508 /**
bogdanm 85:024bf7f99721 509 * @}
bogdanm 85:024bf7f99721 510 */
bogdanm 85:024bf7f99721 511
bogdanm 85:024bf7f99721 512 /** @defgroup TIM_Input_Capture_Selection
bogdanm 85:024bf7f99721 513 * @{
bogdanm 85:024bf7f99721 514 */
bogdanm 85:024bf7f99721 515 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 85:024bf7f99721 516 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 85:024bf7f99721 517 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 85:024bf7f99721 518 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 85:024bf7f99721 519 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 85:024bf7f99721 520
bogdanm 85:024bf7f99721 521 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
bogdanm 85:024bf7f99721 522 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
bogdanm 85:024bf7f99721 523 ((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm 85:024bf7f99721 524 /**
bogdanm 85:024bf7f99721 525 * @}
bogdanm 85:024bf7f99721 526 */
bogdanm 85:024bf7f99721 527
bogdanm 85:024bf7f99721 528 /** @defgroup TIM_Input_Capture_Prescaler
bogdanm 85:024bf7f99721 529 * @{
bogdanm 85:024bf7f99721 530 */
bogdanm 85:024bf7f99721 531 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 85:024bf7f99721 532 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 85:024bf7f99721 533 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 85:024bf7f99721 534 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 85:024bf7f99721 535
bogdanm 85:024bf7f99721 536 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
bogdanm 85:024bf7f99721 537 ((PRESCALER) == TIM_ICPSC_DIV2) || \
bogdanm 85:024bf7f99721 538 ((PRESCALER) == TIM_ICPSC_DIV4) || \
bogdanm 85:024bf7f99721 539 ((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm 85:024bf7f99721 540 /**
bogdanm 85:024bf7f99721 541 * @}
bogdanm 85:024bf7f99721 542 */
bogdanm 85:024bf7f99721 543
bogdanm 85:024bf7f99721 544 /** @defgroup TIM_One_Pulse_Mode
bogdanm 85:024bf7f99721 545 * @{
bogdanm 85:024bf7f99721 546 */
bogdanm 85:024bf7f99721 547 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 85:024bf7f99721 548 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 549
bogdanm 85:024bf7f99721 550 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
bogdanm 85:024bf7f99721 551 ((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm 85:024bf7f99721 552 /**
bogdanm 85:024bf7f99721 553 * @}
bogdanm 85:024bf7f99721 554 */
bogdanm 85:024bf7f99721 555
bogdanm 85:024bf7f99721 556 /** @defgroup TIM_Encoder_Mode
bogdanm 85:024bf7f99721 557 * @{
bogdanm 85:024bf7f99721 558 */
bogdanm 85:024bf7f99721 559 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 85:024bf7f99721 560 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 85:024bf7f99721 561 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
bogdanm 85:024bf7f99721 562
bogdanm 85:024bf7f99721 563 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
bogdanm 85:024bf7f99721 564 ((MODE) == TIM_ENCODERMODE_TI2) || \
bogdanm 85:024bf7f99721 565 ((MODE) == TIM_ENCODERMODE_TI12))
bogdanm 85:024bf7f99721 566 /**
bogdanm 85:024bf7f99721 567 * @}
bogdanm 85:024bf7f99721 568 */
bogdanm 85:024bf7f99721 569
bogdanm 85:024bf7f99721 570 /** @defgroup TIM_Interrupt_definition
bogdanm 85:024bf7f99721 571 * @{
bogdanm 85:024bf7f99721 572 */
bogdanm 85:024bf7f99721 573 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 85:024bf7f99721 574 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 85:024bf7f99721 575 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 85:024bf7f99721 576 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 85:024bf7f99721 577 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 85:024bf7f99721 578 #define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm 85:024bf7f99721 579 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 85:024bf7f99721 580 #define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm 85:024bf7f99721 581
bogdanm 85:024bf7f99721 582 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 85:024bf7f99721 583
bogdanm 85:024bf7f99721 584 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
bogdanm 85:024bf7f99721 585 ((IT) == TIM_IT_CC1) || \
bogdanm 85:024bf7f99721 586 ((IT) == TIM_IT_CC2) || \
bogdanm 85:024bf7f99721 587 ((IT) == TIM_IT_CC3) || \
bogdanm 85:024bf7f99721 588 ((IT) == TIM_IT_CC4) || \
bogdanm 85:024bf7f99721 589 ((IT) == TIM_IT_COM) || \
bogdanm 85:024bf7f99721 590 ((IT) == TIM_IT_TRIGGER) || \
bogdanm 85:024bf7f99721 591 ((IT) == TIM_IT_BREAK))
bogdanm 85:024bf7f99721 592 /**
bogdanm 85:024bf7f99721 593 * @}
bogdanm 85:024bf7f99721 594 */
bogdanm 85:024bf7f99721 595
bogdanm 85:024bf7f99721 596 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 85:024bf7f99721 597 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 598
bogdanm 85:024bf7f99721 599 /** @defgroup TIM_DMA_sources
bogdanm 85:024bf7f99721 600 * @{
bogdanm 85:024bf7f99721 601 */
bogdanm 85:024bf7f99721 602 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 85:024bf7f99721 603 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 85:024bf7f99721 604 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 85:024bf7f99721 605 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 85:024bf7f99721 606 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 85:024bf7f99721 607 #define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm 85:024bf7f99721 608 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 85:024bf7f99721 609
bogdanm 85:024bf7f99721 610 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 85:024bf7f99721 611 /**
bogdanm 85:024bf7f99721 612 * @}
bogdanm 85:024bf7f99721 613 */
bogdanm 85:024bf7f99721 614
bogdanm 85:024bf7f99721 615 /** @defgroup TIM_Event_Source
bogdanm 85:024bf7f99721 616 * @{
bogdanm 85:024bf7f99721 617 */
bogdanm 85:024bf7f99721 618 #define TIM_EventSource_Update TIM_EGR_UG
bogdanm 85:024bf7f99721 619 #define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm 85:024bf7f99721 620 #define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm 85:024bf7f99721 621 #define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm 85:024bf7f99721 622 #define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm 85:024bf7f99721 623 #define TIM_EventSource_COM TIM_EGR_COMG
bogdanm 85:024bf7f99721 624 #define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm 85:024bf7f99721 625 #define TIM_EventSource_Break TIM_EGR_BG
bogdanm 85:024bf7f99721 626
bogdanm 85:024bf7f99721 627 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 85:024bf7f99721 628 /**
bogdanm 85:024bf7f99721 629 * @}
bogdanm 85:024bf7f99721 630 */
bogdanm 85:024bf7f99721 631
bogdanm 85:024bf7f99721 632 /** @defgroup TIM_Flag_definition
bogdanm 85:024bf7f99721 633 * @{
bogdanm 85:024bf7f99721 634 */
bogdanm 85:024bf7f99721 635 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 85:024bf7f99721 636 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 85:024bf7f99721 637 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 85:024bf7f99721 638 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 85:024bf7f99721 639 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 85:024bf7f99721 640 #define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm 85:024bf7f99721 641 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 85:024bf7f99721 642 #define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm 85:024bf7f99721 643 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 85:024bf7f99721 644 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 85:024bf7f99721 645 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 85:024bf7f99721 646 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm 85:024bf7f99721 647
bogdanm 85:024bf7f99721 648 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
bogdanm 85:024bf7f99721 649 ((FLAG) == TIM_FLAG_CC1) || \
bogdanm 85:024bf7f99721 650 ((FLAG) == TIM_FLAG_CC2) || \
bogdanm 85:024bf7f99721 651 ((FLAG) == TIM_FLAG_CC3) || \
bogdanm 85:024bf7f99721 652 ((FLAG) == TIM_FLAG_CC4) || \
bogdanm 85:024bf7f99721 653 ((FLAG) == TIM_FLAG_COM) || \
bogdanm 85:024bf7f99721 654 ((FLAG) == TIM_FLAG_TRIGGER) || \
bogdanm 85:024bf7f99721 655 ((FLAG) == TIM_FLAG_BREAK) || \
bogdanm 85:024bf7f99721 656 ((FLAG) == TIM_FLAG_CC1OF) || \
bogdanm 85:024bf7f99721 657 ((FLAG) == TIM_FLAG_CC2OF) || \
bogdanm 85:024bf7f99721 658 ((FLAG) == TIM_FLAG_CC3OF) || \
bogdanm 85:024bf7f99721 659 ((FLAG) == TIM_FLAG_CC4OF))
bogdanm 85:024bf7f99721 660 /**
bogdanm 85:024bf7f99721 661 * @}
bogdanm 85:024bf7f99721 662 */
bogdanm 85:024bf7f99721 663
bogdanm 85:024bf7f99721 664 /** @defgroup TIM_Clock_Source
bogdanm 85:024bf7f99721 665 * @{
bogdanm 85:024bf7f99721 666 */
bogdanm 85:024bf7f99721 667 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm 85:024bf7f99721 668 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm 85:024bf7f99721 669 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 670 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm 85:024bf7f99721 671 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm 85:024bf7f99721 672 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
bogdanm 85:024bf7f99721 673 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm 85:024bf7f99721 674 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
bogdanm 85:024bf7f99721 675 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
bogdanm 85:024bf7f99721 676 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 85:024bf7f99721 677
bogdanm 85:024bf7f99721 678 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
bogdanm 85:024bf7f99721 679 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
bogdanm 85:024bf7f99721 680 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
bogdanm 85:024bf7f99721 681 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
bogdanm 85:024bf7f99721 682 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
bogdanm 85:024bf7f99721 683 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
bogdanm 85:024bf7f99721 684 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
bogdanm 85:024bf7f99721 685 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
bogdanm 85:024bf7f99721 686 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
bogdanm 85:024bf7f99721 687 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm 85:024bf7f99721 688 /**
bogdanm 85:024bf7f99721 689 * @}
bogdanm 85:024bf7f99721 690 */
bogdanm 85:024bf7f99721 691
bogdanm 85:024bf7f99721 692 /** @defgroup TIM_Clock_Polarity
bogdanm 85:024bf7f99721 693 * @{
bogdanm 85:024bf7f99721 694 */
bogdanm 85:024bf7f99721 695 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 85:024bf7f99721 696 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 85:024bf7f99721 697 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 85:024bf7f99721 698 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 85:024bf7f99721 699 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 85:024bf7f99721 700
bogdanm 85:024bf7f99721 701 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
bogdanm 85:024bf7f99721 702 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
bogdanm 85:024bf7f99721 703 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
bogdanm 85:024bf7f99721 704 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
bogdanm 85:024bf7f99721 705 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm 85:024bf7f99721 706 /**
bogdanm 85:024bf7f99721 707 * @}
bogdanm 85:024bf7f99721 708 */
bogdanm 85:024bf7f99721 709
bogdanm 85:024bf7f99721 710 /** @defgroup TIM_Clock_Prescaler
bogdanm 85:024bf7f99721 711 * @{
bogdanm 85:024bf7f99721 712 */
bogdanm 85:024bf7f99721 713 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 85:024bf7f99721 714 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
bogdanm 85:024bf7f99721 715 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
bogdanm 85:024bf7f99721 716 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 85:024bf7f99721 717
bogdanm 85:024bf7f99721 718 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
bogdanm 85:024bf7f99721 719 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
bogdanm 85:024bf7f99721 720 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
bogdanm 85:024bf7f99721 721 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm 85:024bf7f99721 722 /**
bogdanm 85:024bf7f99721 723 * @}
bogdanm 85:024bf7f99721 724 */
bogdanm 85:024bf7f99721 725
bogdanm 85:024bf7f99721 726 /** @defgroup TIM_Clock_Filter
bogdanm 85:024bf7f99721 727 * @{
bogdanm 85:024bf7f99721 728 */
bogdanm 85:024bf7f99721 729 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 85:024bf7f99721 730 /**
bogdanm 85:024bf7f99721 731 * @}
bogdanm 85:024bf7f99721 732 */
bogdanm 85:024bf7f99721 733
bogdanm 85:024bf7f99721 734 /** @defgroup TIM_ClearInput_Source
bogdanm 85:024bf7f99721 735 * @{
bogdanm 85:024bf7f99721 736 */
bogdanm 85:024bf7f99721 737 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 85:024bf7f99721 738 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 739
bogdanm 85:024bf7f99721 740 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
bogdanm 85:024bf7f99721 741 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm 85:024bf7f99721 742 /**
bogdanm 85:024bf7f99721 743 * @}
bogdanm 85:024bf7f99721 744 */
bogdanm 85:024bf7f99721 745
bogdanm 85:024bf7f99721 746 /** @defgroup TIM_ClearInput_Polarity
bogdanm 85:024bf7f99721 747 * @{
bogdanm 85:024bf7f99721 748 */
bogdanm 85:024bf7f99721 749 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 85:024bf7f99721 750 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 85:024bf7f99721 751
bogdanm 85:024bf7f99721 752
bogdanm 85:024bf7f99721 753 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
bogdanm 85:024bf7f99721 754 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm 85:024bf7f99721 755 /**
bogdanm 85:024bf7f99721 756 * @}
bogdanm 85:024bf7f99721 757 */
bogdanm 85:024bf7f99721 758
bogdanm 85:024bf7f99721 759 /** @defgroup TIM_ClearInput_Prescaler
bogdanm 85:024bf7f99721 760 * @{
bogdanm 85:024bf7f99721 761 */
bogdanm 85:024bf7f99721 762 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 85:024bf7f99721 763 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 85:024bf7f99721 764 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 85:024bf7f99721 765 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 85:024bf7f99721 766
bogdanm 85:024bf7f99721 767 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
bogdanm 85:024bf7f99721 768 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
bogdanm 85:024bf7f99721 769 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
bogdanm 85:024bf7f99721 770 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm 85:024bf7f99721 771 /**
bogdanm 85:024bf7f99721 772 * @}
bogdanm 85:024bf7f99721 773 */
bogdanm 85:024bf7f99721 774
bogdanm 85:024bf7f99721 775 /** @defgroup TIM_ClearInput_Filter
bogdanm 85:024bf7f99721 776 * @{
bogdanm 85:024bf7f99721 777 */
bogdanm 85:024bf7f99721 778 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 85:024bf7f99721 779 /**
bogdanm 85:024bf7f99721 780 * @}
bogdanm 85:024bf7f99721 781 */
bogdanm 85:024bf7f99721 782
bogdanm 85:024bf7f99721 783 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm 85:024bf7f99721 784 * @{
bogdanm 85:024bf7f99721 785 */
bogdanm 85:024bf7f99721 786 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm 85:024bf7f99721 787 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 788
bogdanm 85:024bf7f99721 789 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
bogdanm 85:024bf7f99721 790 ((STATE) == TIM_OSSR_DISABLE))
bogdanm 85:024bf7f99721 791 /**
bogdanm 85:024bf7f99721 792 * @}
bogdanm 85:024bf7f99721 793 */
bogdanm 85:024bf7f99721 794
bogdanm 85:024bf7f99721 795 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm 85:024bf7f99721 796 * @{
bogdanm 85:024bf7f99721 797 */
bogdanm 85:024bf7f99721 798 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 85:024bf7f99721 799 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 800
bogdanm 85:024bf7f99721 801 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
bogdanm 85:024bf7f99721 802 ((STATE) == TIM_OSSI_DISABLE))
bogdanm 85:024bf7f99721 803 /**
bogdanm 85:024bf7f99721 804 * @}
bogdanm 85:024bf7f99721 805 */
bogdanm 85:024bf7f99721 806
bogdanm 85:024bf7f99721 807 /** @defgroup TIM_Lock_level
bogdanm 85:024bf7f99721 808 * @{
bogdanm 85:024bf7f99721 809 */
bogdanm 85:024bf7f99721 810 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 811 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 85:024bf7f99721 812 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 85:024bf7f99721 813 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 85:024bf7f99721 814
bogdanm 85:024bf7f99721 815 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
bogdanm 85:024bf7f99721 816 ((LEVEL) == TIM_LOCKLEVEL_1) || \
bogdanm 85:024bf7f99721 817 ((LEVEL) == TIM_LOCKLEVEL_2) || \
bogdanm 85:024bf7f99721 818 ((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm 85:024bf7f99721 819 /**
bogdanm 85:024bf7f99721 820 * @}
bogdanm 85:024bf7f99721 821 */
bogdanm 85:024bf7f99721 822
bogdanm 85:024bf7f99721 823 /** @defgroup TIM_Break_Input_enable_disable
bogdanm 85:024bf7f99721 824 * @{
bogdanm 85:024bf7f99721 825 */
bogdanm 85:024bf7f99721 826 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 85:024bf7f99721 827 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 828
bogdanm 85:024bf7f99721 829 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
bogdanm 85:024bf7f99721 830 ((STATE) == TIM_BREAK_DISABLE))
bogdanm 85:024bf7f99721 831 /**
bogdanm 85:024bf7f99721 832 * @}
bogdanm 85:024bf7f99721 833 */
bogdanm 85:024bf7f99721 834
bogdanm 85:024bf7f99721 835 /** @defgroup TIM_Break_Polarity
bogdanm 85:024bf7f99721 836 * @{
bogdanm 85:024bf7f99721 837 */
bogdanm 85:024bf7f99721 838 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 839 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 85:024bf7f99721 840
bogdanm 85:024bf7f99721 841 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
bogdanm 85:024bf7f99721 842 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm 85:024bf7f99721 843 /**
bogdanm 85:024bf7f99721 844 * @}
bogdanm 85:024bf7f99721 845 */
bogdanm 85:024bf7f99721 846
bogdanm 85:024bf7f99721 847 /** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm 85:024bf7f99721 848 * @{
bogdanm 85:024bf7f99721 849 */
bogdanm 85:024bf7f99721 850 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 85:024bf7f99721 851 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 852
bogdanm 85:024bf7f99721 853 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
bogdanm 85:024bf7f99721 854 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm 85:024bf7f99721 855 /**
bogdanm 85:024bf7f99721 856 * @}
bogdanm 85:024bf7f99721 857 */
bogdanm 85:024bf7f99721 858
bogdanm 85:024bf7f99721 859 /** @defgroup TIM_Master_Mode_Selection
bogdanm 85:024bf7f99721 860 * @{
bogdanm 85:024bf7f99721 861 */
bogdanm 85:024bf7f99721 862 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 863 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 85:024bf7f99721 864 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 85:024bf7f99721 865 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 866 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 85:024bf7f99721 867 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 868 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 85:024bf7f99721 869 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 870
bogdanm 85:024bf7f99721 871 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 85:024bf7f99721 872 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 85:024bf7f99721 873 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 85:024bf7f99721 874 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 85:024bf7f99721 875 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 85:024bf7f99721 876 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 85:024bf7f99721 877 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 85:024bf7f99721 878 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 85:024bf7f99721 879 /**
bogdanm 85:024bf7f99721 880 * @}
bogdanm 85:024bf7f99721 881 */
bogdanm 85:024bf7f99721 882
bogdanm 85:024bf7f99721 883 /** @defgroup TIM_Slave_Mode
bogdanm 85:024bf7f99721 884 * @{
bogdanm 85:024bf7f99721 885 */
bogdanm 85:024bf7f99721 886 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 887 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm 85:024bf7f99721 888 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm 85:024bf7f99721 889 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm 85:024bf7f99721 890 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm 85:024bf7f99721 891
bogdanm 85:024bf7f99721 892 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
bogdanm 85:024bf7f99721 893 ((MODE) == TIM_SLAVEMODE_GATED) || \
bogdanm 85:024bf7f99721 894 ((MODE) == TIM_SLAVEMODE_RESET) || \
bogdanm 85:024bf7f99721 895 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
bogdanm 85:024bf7f99721 896 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm 85:024bf7f99721 897 /**
bogdanm 85:024bf7f99721 898 * @}
bogdanm 85:024bf7f99721 899 */
bogdanm 85:024bf7f99721 900
bogdanm 85:024bf7f99721 901 /** @defgroup TIM_Master_Slave_Mode
bogdanm 85:024bf7f99721 902 * @{
bogdanm 85:024bf7f99721 903 */
bogdanm 85:024bf7f99721 904 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 85:024bf7f99721 905 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 906
bogdanm 85:024bf7f99721 907 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
bogdanm 85:024bf7f99721 908 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm 85:024bf7f99721 909 /**
bogdanm 85:024bf7f99721 910 * @}
bogdanm 85:024bf7f99721 911 */
bogdanm 85:024bf7f99721 912
bogdanm 85:024bf7f99721 913 /** @defgroup TIM_Trigger_Selection
bogdanm 85:024bf7f99721 914 * @{
bogdanm 85:024bf7f99721 915 */
bogdanm 85:024bf7f99721 916 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 917 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 85:024bf7f99721 918 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 85:024bf7f99721 919 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 85:024bf7f99721 920 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 85:024bf7f99721 921 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 85:024bf7f99721 922 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 85:024bf7f99721 923 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 85:024bf7f99721 924 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 85:024bf7f99721 925
bogdanm 85:024bf7f99721 926 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 85:024bf7f99721 927 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 85:024bf7f99721 928 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 85:024bf7f99721 929 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 85:024bf7f99721 930 ((SELECTION) == TIM_TS_TI1F_ED) || \
bogdanm 85:024bf7f99721 931 ((SELECTION) == TIM_TS_TI1FP1) || \
bogdanm 85:024bf7f99721 932 ((SELECTION) == TIM_TS_TI2FP2) || \
bogdanm 85:024bf7f99721 933 ((SELECTION) == TIM_TS_ETRF))
bogdanm 85:024bf7f99721 934
bogdanm 85:024bf7f99721 935 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 85:024bf7f99721 936 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 85:024bf7f99721 937 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 85:024bf7f99721 938 ((SELECTION) == TIM_TS_ITR3))
bogdanm 85:024bf7f99721 939
bogdanm 85:024bf7f99721 940 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 85:024bf7f99721 941 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 85:024bf7f99721 942 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 85:024bf7f99721 943 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 85:024bf7f99721 944 ((SELECTION) == TIM_TS_NONE))
bogdanm 85:024bf7f99721 945 /**
bogdanm 85:024bf7f99721 946 * @}
bogdanm 85:024bf7f99721 947 */
bogdanm 85:024bf7f99721 948
bogdanm 85:024bf7f99721 949 /** @defgroup TIM_Trigger_Polarity
bogdanm 85:024bf7f99721 950 * @{
bogdanm 85:024bf7f99721 951 */
bogdanm 85:024bf7f99721 952 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 85:024bf7f99721 953 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 85:024bf7f99721 954 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 85:024bf7f99721 955 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 85:024bf7f99721 956 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 85:024bf7f99721 957
bogdanm 85:024bf7f99721 958 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
bogdanm 85:024bf7f99721 959 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
bogdanm 85:024bf7f99721 960 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
bogdanm 85:024bf7f99721 961 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
bogdanm 85:024bf7f99721 962 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm 85:024bf7f99721 963 /**
bogdanm 85:024bf7f99721 964 * @}
bogdanm 85:024bf7f99721 965 */
bogdanm 85:024bf7f99721 966
bogdanm 85:024bf7f99721 967 /** @defgroup TIM_Trigger_Prescaler
bogdanm 85:024bf7f99721 968 * @{
bogdanm 85:024bf7f99721 969 */
bogdanm 85:024bf7f99721 970 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 85:024bf7f99721 971 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 85:024bf7f99721 972 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 85:024bf7f99721 973 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 85:024bf7f99721 974
bogdanm 85:024bf7f99721 975 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
bogdanm 85:024bf7f99721 976 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
bogdanm 85:024bf7f99721 977 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
bogdanm 85:024bf7f99721 978 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm 85:024bf7f99721 979 /**
bogdanm 85:024bf7f99721 980 * @}
bogdanm 85:024bf7f99721 981 */
bogdanm 85:024bf7f99721 982
bogdanm 85:024bf7f99721 983 /** @defgroup TIM_Trigger_Filter
bogdanm 85:024bf7f99721 984 * @{
bogdanm 85:024bf7f99721 985 */
bogdanm 85:024bf7f99721 986 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 85:024bf7f99721 987 /**
bogdanm 85:024bf7f99721 988 * @}
bogdanm 85:024bf7f99721 989 */
bogdanm 85:024bf7f99721 990
bogdanm 85:024bf7f99721 991 /** @defgroup TIM_TI1_Selection
bogdanm 85:024bf7f99721 992 * @{
bogdanm 85:024bf7f99721 993 */
bogdanm 85:024bf7f99721 994 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 995 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 85:024bf7f99721 996
bogdanm 85:024bf7f99721 997 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
bogdanm 85:024bf7f99721 998 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm 85:024bf7f99721 999 /**
bogdanm 85:024bf7f99721 1000 * @}
bogdanm 85:024bf7f99721 1001 */
bogdanm 85:024bf7f99721 1002
bogdanm 85:024bf7f99721 1003 /** @defgroup TIM_DMA_Base_address
bogdanm 85:024bf7f99721 1004 * @{
bogdanm 85:024bf7f99721 1005 */
bogdanm 85:024bf7f99721 1006 #define TIM_DMABase_CR1 (0x00000000)
bogdanm 85:024bf7f99721 1007 #define TIM_DMABase_CR2 (0x00000001)
bogdanm 85:024bf7f99721 1008 #define TIM_DMABase_SMCR (0x00000002)
bogdanm 85:024bf7f99721 1009 #define TIM_DMABase_DIER (0x00000003)
bogdanm 85:024bf7f99721 1010 #define TIM_DMABase_SR (0x00000004)
bogdanm 85:024bf7f99721 1011 #define TIM_DMABase_EGR (0x00000005)
bogdanm 85:024bf7f99721 1012 #define TIM_DMABase_CCMR1 (0x00000006)
bogdanm 85:024bf7f99721 1013 #define TIM_DMABase_CCMR2 (0x00000007)
bogdanm 85:024bf7f99721 1014 #define TIM_DMABase_CCER (0x00000008)
bogdanm 85:024bf7f99721 1015 #define TIM_DMABase_CNT (0x00000009)
bogdanm 85:024bf7f99721 1016 #define TIM_DMABase_PSC (0x0000000A)
bogdanm 85:024bf7f99721 1017 #define TIM_DMABase_ARR (0x0000000B)
bogdanm 85:024bf7f99721 1018 #define TIM_DMABase_RCR (0x0000000C)
bogdanm 85:024bf7f99721 1019 #define TIM_DMABase_CCR1 (0x0000000D)
bogdanm 85:024bf7f99721 1020 #define TIM_DMABase_CCR2 (0x0000000E)
bogdanm 85:024bf7f99721 1021 #define TIM_DMABase_CCR3 (0x0000000F)
bogdanm 85:024bf7f99721 1022 #define TIM_DMABase_CCR4 (0x00000010)
bogdanm 85:024bf7f99721 1023 #define TIM_DMABase_BDTR (0x00000011)
bogdanm 85:024bf7f99721 1024 #define TIM_DMABase_DCR (0x00000012)
bogdanm 85:024bf7f99721 1025 #define TIM_DMABase_OR (0x00000013)
bogdanm 85:024bf7f99721 1026
bogdanm 85:024bf7f99721 1027 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 85:024bf7f99721 1028 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 85:024bf7f99721 1029 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 85:024bf7f99721 1030 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 85:024bf7f99721 1031 ((BASE) == TIM_DMABase_SR) || \
bogdanm 85:024bf7f99721 1032 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 85:024bf7f99721 1033 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 85:024bf7f99721 1034 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 85:024bf7f99721 1035 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 85:024bf7f99721 1036 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 85:024bf7f99721 1037 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 85:024bf7f99721 1038 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 85:024bf7f99721 1039 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 85:024bf7f99721 1040 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 85:024bf7f99721 1041 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 85:024bf7f99721 1042 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 85:024bf7f99721 1043 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 85:024bf7f99721 1044 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 85:024bf7f99721 1045 ((BASE) == TIM_DMABase_DCR) || \
bogdanm 85:024bf7f99721 1046 ((BASE) == TIM_DMABase_OR))
bogdanm 85:024bf7f99721 1047 /**
bogdanm 85:024bf7f99721 1048 * @}
bogdanm 85:024bf7f99721 1049 */
bogdanm 85:024bf7f99721 1050
bogdanm 85:024bf7f99721 1051 /** @defgroup TIM_DMA_Burst_Length
bogdanm 85:024bf7f99721 1052 * @{
bogdanm 85:024bf7f99721 1053 */
bogdanm 85:024bf7f99721 1054 #define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm 85:024bf7f99721 1055 #define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm 85:024bf7f99721 1056 #define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm 85:024bf7f99721 1057 #define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm 85:024bf7f99721 1058 #define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm 85:024bf7f99721 1059 #define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm 85:024bf7f99721 1060 #define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm 85:024bf7f99721 1061 #define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm 85:024bf7f99721 1062 #define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm 85:024bf7f99721 1063 #define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm 85:024bf7f99721 1064 #define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm 85:024bf7f99721 1065 #define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm 85:024bf7f99721 1066 #define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm 85:024bf7f99721 1067 #define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm 85:024bf7f99721 1068 #define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm 85:024bf7f99721 1069 #define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm 85:024bf7f99721 1070 #define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm 85:024bf7f99721 1071 #define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm 85:024bf7f99721 1072
bogdanm 85:024bf7f99721 1073 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
bogdanm 85:024bf7f99721 1074 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
bogdanm 85:024bf7f99721 1075 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
bogdanm 85:024bf7f99721 1076 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
bogdanm 85:024bf7f99721 1077 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
bogdanm 85:024bf7f99721 1078 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
bogdanm 85:024bf7f99721 1079 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
bogdanm 85:024bf7f99721 1080 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
bogdanm 85:024bf7f99721 1081 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
bogdanm 85:024bf7f99721 1082 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
bogdanm 85:024bf7f99721 1083 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
bogdanm 85:024bf7f99721 1084 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
bogdanm 85:024bf7f99721 1085 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
bogdanm 85:024bf7f99721 1086 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
bogdanm 85:024bf7f99721 1087 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
bogdanm 85:024bf7f99721 1088 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
bogdanm 85:024bf7f99721 1089 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
bogdanm 85:024bf7f99721 1090 ((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm 85:024bf7f99721 1091 /**
bogdanm 85:024bf7f99721 1092 * @}
bogdanm 85:024bf7f99721 1093 */
bogdanm 85:024bf7f99721 1094
bogdanm 85:024bf7f99721 1095 /** @defgroup TIM_Input_Capture_Filer_Value
bogdanm 85:024bf7f99721 1096 * @{
bogdanm 85:024bf7f99721 1097 */
bogdanm 85:024bf7f99721 1098 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 85:024bf7f99721 1099 /**
bogdanm 85:024bf7f99721 1100 * @}
bogdanm 85:024bf7f99721 1101 */
bogdanm 85:024bf7f99721 1102
bogdanm 85:024bf7f99721 1103 /** @defgroup DMA_Handle_index
bogdanm 85:024bf7f99721 1104 * @{
bogdanm 85:024bf7f99721 1105 */
bogdanm 85:024bf7f99721 1106 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 85:024bf7f99721 1107 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 85:024bf7f99721 1108 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 85:024bf7f99721 1109 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 85:024bf7f99721 1110 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 85:024bf7f99721 1111 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
bogdanm 85:024bf7f99721 1112 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 85:024bf7f99721 1113 /**
bogdanm 85:024bf7f99721 1114 * @}
bogdanm 85:024bf7f99721 1115 */
bogdanm 85:024bf7f99721 1116
bogdanm 85:024bf7f99721 1117 /** @defgroup Channel_CC_State
bogdanm 85:024bf7f99721 1118 * @{
bogdanm 85:024bf7f99721 1119 */
bogdanm 85:024bf7f99721 1120 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 85:024bf7f99721 1121 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 1122 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm 85:024bf7f99721 1123 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 1124 /**
bogdanm 85:024bf7f99721 1125 * @}
bogdanm 85:024bf7f99721 1126 */
bogdanm 85:024bf7f99721 1127
bogdanm 85:024bf7f99721 1128 /**
bogdanm 85:024bf7f99721 1129 * @}
bogdanm 85:024bf7f99721 1130 */
bogdanm 85:024bf7f99721 1131
bogdanm 85:024bf7f99721 1132 /* Exported macros -----------------------------------------------------------*/
bogdanm 85:024bf7f99721 1133 /** @defgroup TIM_Exported_Macros
bogdanm 85:024bf7f99721 1134 * @{
bogdanm 85:024bf7f99721 1135 */
bogdanm 85:024bf7f99721 1136
bogdanm 85:024bf7f99721 1137 /** @brief Reset TIM handle state
bogdanm 85:024bf7f99721 1138 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1139 * @retval None
bogdanm 85:024bf7f99721 1140 */
bogdanm 85:024bf7f99721 1141 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 85:024bf7f99721 1142
bogdanm 85:024bf7f99721 1143 /**
bogdanm 85:024bf7f99721 1144 * @brief Enable the TIM peripheral.
bogdanm 85:024bf7f99721 1145 * @param __HANDLE__: TIM handle
bogdanm 85:024bf7f99721 1146 * @retval None
bogdanm 85:024bf7f99721 1147 */
bogdanm 85:024bf7f99721 1148 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 85:024bf7f99721 1149
bogdanm 85:024bf7f99721 1150 /**
bogdanm 85:024bf7f99721 1151 * @brief Enable the TIM main Output.
bogdanm 85:024bf7f99721 1152 * @param __HANDLE__: TIM handle
bogdanm 85:024bf7f99721 1153 * @retval None
bogdanm 85:024bf7f99721 1154 */
bogdanm 85:024bf7f99721 1155 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
bogdanm 85:024bf7f99721 1156
bogdanm 85:024bf7f99721 1157 /* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm 85:024bf7f99721 1158 channels have been disabled */
bogdanm 85:024bf7f99721 1159 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
bogdanm 85:024bf7f99721 1160 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
bogdanm 85:024bf7f99721 1161
bogdanm 85:024bf7f99721 1162 /**
bogdanm 85:024bf7f99721 1163 * @brief Disable the TIM peripheral.
bogdanm 85:024bf7f99721 1164 * @param __HANDLE__: TIM handle
bogdanm 85:024bf7f99721 1165 * @retval None
bogdanm 85:024bf7f99721 1166 */
bogdanm 85:024bf7f99721 1167 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 85:024bf7f99721 1168 do { \
bogdanm 85:024bf7f99721 1169 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 85:024bf7f99721 1170 { \
bogdanm 85:024bf7f99721 1171 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 85:024bf7f99721 1172 { \
bogdanm 85:024bf7f99721 1173 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CEN); \
bogdanm 85:024bf7f99721 1174 } \
bogdanm 85:024bf7f99721 1175 } \
bogdanm 85:024bf7f99721 1176 } while(0)
bogdanm 85:024bf7f99721 1177 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm 85:024bf7f99721 1178 channels have been disabled */
bogdanm 85:024bf7f99721 1179 /**
bogdanm 85:024bf7f99721 1180 * @brief Disable the TIM main Output.
bogdanm 85:024bf7f99721 1181 * @param __HANDLE__: TIM handle
bogdanm 85:024bf7f99721 1182 * @retval None
bogdanm 85:024bf7f99721 1183 */
bogdanm 85:024bf7f99721 1184 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm 85:024bf7f99721 1185 do { \
bogdanm 85:024bf7f99721 1186 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 85:024bf7f99721 1187 { \
bogdanm 85:024bf7f99721 1188 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 85:024bf7f99721 1189 { \
bogdanm 85:024bf7f99721 1190 (__HANDLE__)->Instance->BDTR &= (uint16_t)(~TIM_BDTR_MOE); \
bogdanm 85:024bf7f99721 1191 } \
bogdanm 85:024bf7f99721 1192 } \
bogdanm 85:024bf7f99721 1193 } while(0)
bogdanm 85:024bf7f99721 1194
bogdanm 85:024bf7f99721 1195 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 85:024bf7f99721 1196 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 85:024bf7f99721 1197 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (uint16_t)~(__INTERRUPT__))
bogdanm 85:024bf7f99721 1198 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= (uint16_t)~(__DMA__))
bogdanm 85:024bf7f99721 1199 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 85:024bf7f99721 1200 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (uint16_t)~(__FLAG__))
bogdanm 85:024bf7f99721 1201
bogdanm 85:024bf7f99721 1202 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 85:024bf7f99721 1203 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= (uint16_t)~(__INTERRUPT__))
bogdanm 85:024bf7f99721 1204
bogdanm 85:024bf7f99721 1205 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm 85:024bf7f99721 1206 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__))
bogdanm 85:024bf7f99721 1207
bogdanm 85:024bf7f99721 1208 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 85:024bf7f99721 1209 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 85:024bf7f99721 1210 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 85:024bf7f99721 1211 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 85:024bf7f99721 1212 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 85:024bf7f99721 1213
bogdanm 85:024bf7f99721 1214 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm 85:024bf7f99721 1215 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 85:024bf7f99721 1216 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 85:024bf7f99721 1217 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 85:024bf7f99721 1218 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 85:024bf7f99721 1219
bogdanm 85:024bf7f99721 1220 /**
bogdanm 85:024bf7f99721 1221 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 85:024bf7f99721 1222 * calling another time ConfigChannel function.
bogdanm 85:024bf7f99721 1223 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1224 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 85:024bf7f99721 1225 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 85:024bf7f99721 1227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 85:024bf7f99721 1228 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 85:024bf7f99721 1229 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 85:024bf7f99721 1230 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 85:024bf7f99721 1231 * @retval None
bogdanm 85:024bf7f99721 1232 */
bogdanm 85:024bf7f99721 1233 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 85:024bf7f99721 1234 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 85:024bf7f99721 1235
bogdanm 85:024bf7f99721 1236 /**
bogdanm 85:024bf7f99721 1237 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 85:024bf7f99721 1238 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1239 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 85:024bf7f99721 1240 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1241 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 85:024bf7f99721 1242 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 85:024bf7f99721 1243 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 85:024bf7f99721 1244 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 85:024bf7f99721 1245 * @retval None
bogdanm 85:024bf7f99721 1246 */
bogdanm 85:024bf7f99721 1247 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm 85:024bf7f99721 1248 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 85:024bf7f99721 1249
bogdanm 85:024bf7f99721 1250 /**
bogdanm 85:024bf7f99721 1251 * @brief Sets the TIM Counter Register value on runtime.
bogdanm 85:024bf7f99721 1252 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1253 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 85:024bf7f99721 1254 * @retval None
bogdanm 85:024bf7f99721 1255 */
bogdanm 85:024bf7f99721 1256 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 85:024bf7f99721 1257
bogdanm 85:024bf7f99721 1258 /**
bogdanm 85:024bf7f99721 1259 * @brief Gets the TIM Counter Register value on runtime.
bogdanm 85:024bf7f99721 1260 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1261 * @retval None
bogdanm 85:024bf7f99721 1262 */
bogdanm 85:024bf7f99721 1263 #define __HAL_TIM_GetCounter(__HANDLE__) \
bogdanm 85:024bf7f99721 1264 ((__HANDLE__)->Instance->CNT)
bogdanm 85:024bf7f99721 1265
bogdanm 85:024bf7f99721 1266 /**
bogdanm 85:024bf7f99721 1267 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 85:024bf7f99721 1268 * another time any Init function.
bogdanm 85:024bf7f99721 1269 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1270 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 85:024bf7f99721 1271 * @retval None
bogdanm 85:024bf7f99721 1272 */
bogdanm 85:024bf7f99721 1273 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm 85:024bf7f99721 1274 do{ \
bogdanm 85:024bf7f99721 1275 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 85:024bf7f99721 1276 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 85:024bf7f99721 1277 } while(0)
bogdanm 85:024bf7f99721 1278
bogdanm 85:024bf7f99721 1279 /**
bogdanm 85:024bf7f99721 1280 * @brief Gets the TIM Autoreload Register value on runtime
bogdanm 85:024bf7f99721 1281 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1282 * @retval None
bogdanm 85:024bf7f99721 1283 */
bogdanm 85:024bf7f99721 1284 #define __HAL_TIM_GetAutoreload(__HANDLE__) \
bogdanm 85:024bf7f99721 1285 ((__HANDLE__)->Instance->ARR)
bogdanm 85:024bf7f99721 1286
bogdanm 85:024bf7f99721 1287 /**
bogdanm 85:024bf7f99721 1288 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 85:024bf7f99721 1289 * another time any Init function.
bogdanm 85:024bf7f99721 1290 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1291 * @param __CKD__: specifies the clock division value.
bogdanm 85:024bf7f99721 1292 * This parameter can be one of the following value:
bogdanm 85:024bf7f99721 1293 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 85:024bf7f99721 1294 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 85:024bf7f99721 1295 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 85:024bf7f99721 1296 * @retval None
bogdanm 85:024bf7f99721 1297 */
bogdanm 85:024bf7f99721 1298 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm 85:024bf7f99721 1299 do{ \
bogdanm 85:024bf7f99721 1300 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 85:024bf7f99721 1301 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 85:024bf7f99721 1302 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 85:024bf7f99721 1303 } while(0)
bogdanm 85:024bf7f99721 1304
bogdanm 85:024bf7f99721 1305 /**
bogdanm 85:024bf7f99721 1306 * @brief Gets the TIM Clock Division value on runtime
bogdanm 85:024bf7f99721 1307 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1308 * @retval None
bogdanm 85:024bf7f99721 1309 */
bogdanm 85:024bf7f99721 1310 #define __HAL_TIM_GetClockDivision(__HANDLE__) \
bogdanm 85:024bf7f99721 1311 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 85:024bf7f99721 1312
bogdanm 85:024bf7f99721 1313 /**
bogdanm 85:024bf7f99721 1314 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 85:024bf7f99721 1315 * another time HAL_TIM_IC_ConfigChannel() function.
bogdanm 85:024bf7f99721 1316 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1317 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 85:024bf7f99721 1318 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1319 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 85:024bf7f99721 1320 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 85:024bf7f99721 1321 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 85:024bf7f99721 1322 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 85:024bf7f99721 1323 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 85:024bf7f99721 1324 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1325 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 85:024bf7f99721 1326 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 85:024bf7f99721 1327 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 85:024bf7f99721 1328 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 85:024bf7f99721 1329 * @retval None
bogdanm 85:024bf7f99721 1330 */
bogdanm 85:024bf7f99721 1331 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 85:024bf7f99721 1332 do{ \
bogdanm 85:024bf7f99721 1333 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm 85:024bf7f99721 1334 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 85:024bf7f99721 1335 } while(0)
bogdanm 85:024bf7f99721 1336
bogdanm 85:024bf7f99721 1337 /**
bogdanm 85:024bf7f99721 1338 * @brief Gets the TIM Input Capture prescaler on runtime
bogdanm 85:024bf7f99721 1339 * @param __HANDLE__: TIM handle.
bogdanm 85:024bf7f99721 1340 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 85:024bf7f99721 1341 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 1342 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 85:024bf7f99721 1343 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 85:024bf7f99721 1344 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 85:024bf7f99721 1345 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 85:024bf7f99721 1346 * @retval None
bogdanm 85:024bf7f99721 1347 */
bogdanm 85:024bf7f99721 1348 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm 85:024bf7f99721 1349 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 85:024bf7f99721 1350 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 85:024bf7f99721 1351 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 85:024bf7f99721 1352 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm 85:024bf7f99721 1353
bogdanm 85:024bf7f99721 1354 /**
bogdanm 85:024bf7f99721 1355 * @}
bogdanm 85:024bf7f99721 1356 */
bogdanm 85:024bf7f99721 1357
bogdanm 85:024bf7f99721 1358 /* Include TIM HAL Extension module */
bogdanm 85:024bf7f99721 1359 #include "stm32f0xx_hal_tim_ex.h"
bogdanm 85:024bf7f99721 1360
bogdanm 85:024bf7f99721 1361 /* Exported functions --------------------------------------------------------*/
bogdanm 85:024bf7f99721 1362
bogdanm 85:024bf7f99721 1363 /* Time Base functions ********************************************************/
bogdanm 85:024bf7f99721 1364 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1365 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1366 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1367 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1368 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1369 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1370 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1371 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1372 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1373 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1374 /* Non-Blocking mode: DMA */
bogdanm 85:024bf7f99721 1375 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 85:024bf7f99721 1376 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1377
bogdanm 85:024bf7f99721 1378 /* Timer Output Compare functions **********************************************/
bogdanm 85:024bf7f99721 1379 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1380 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1381 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1382 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1383 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1384 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1385 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1386 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1387 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1388 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1389 /* Non-Blocking mode: DMA */
bogdanm 85:024bf7f99721 1390 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 85:024bf7f99721 1391 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1392
bogdanm 85:024bf7f99721 1393 /* Timer PWM functions *********************************************************/
bogdanm 85:024bf7f99721 1394 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1395 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1396 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1397 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1398 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1399 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1400 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1401 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1402 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1403 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1404 /* Non-Blocking mode: DMA */
bogdanm 85:024bf7f99721 1405 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 85:024bf7f99721 1406 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1407
bogdanm 85:024bf7f99721 1408 /* Timer Input Capture functions ***********************************************/
bogdanm 85:024bf7f99721 1409 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1410 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1411 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1412 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1413 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1414 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1415 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1416 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1417 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1418 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1419 /* Non-Blocking mode: DMA */
bogdanm 85:024bf7f99721 1420 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 85:024bf7f99721 1421 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1422
bogdanm 85:024bf7f99721 1423 /* Timer One Pulse functions ***************************************************/
bogdanm 85:024bf7f99721 1424 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 85:024bf7f99721 1425 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1426 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1427 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1428 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1429 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 85:024bf7f99721 1430 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 85:024bf7f99721 1431 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1432 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 85:024bf7f99721 1433 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 85:024bf7f99721 1434
bogdanm 85:024bf7f99721 1435 /* Timer Encoder functions *****************************************************/
bogdanm 85:024bf7f99721 1436 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 85:024bf7f99721 1437 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1438
bogdanm 85:024bf7f99721 1439
bogdanm 85:024bf7f99721 1440
bogdanm 85:024bf7f99721 1441
bogdanm 85:024bf7f99721 1442
bogdanm 85:024bf7f99721 1443
bogdanm 85:024bf7f99721 1444
bogdanm 85:024bf7f99721 1445 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1446 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1447 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 1448 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1449 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1450 /* Non-Blocking mode: Interrupt */
bogdanm 85:024bf7f99721 1451 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1452 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1453 /* Non-Blocking mode: DMA */
bogdanm 85:024bf7f99721 1454 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 85:024bf7f99721 1455 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1456
bogdanm 85:024bf7f99721 1457 /* Interrupt Handler functions **********************************************/
bogdanm 85:024bf7f99721 1458 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1459
bogdanm 85:024bf7f99721 1460 /* Control functions *********************************************************/
bogdanm 85:024bf7f99721 1461 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 85:024bf7f99721 1462 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 85:024bf7f99721 1463 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 85:024bf7f99721 1464 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 85:024bf7f99721 1465 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 85:024bf7f99721 1466 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 85:024bf7f99721 1467 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 85:024bf7f99721 1468 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 85:024bf7f99721 1469 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 85:024bf7f99721 1470 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 85:024bf7f99721 1471 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 85:024bf7f99721 1472 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 85:024bf7f99721 1473 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 85:024bf7f99721 1474 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 85:024bf7f99721 1475 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 85:024bf7f99721 1476 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 85:024bf7f99721 1477
bogdanm 85:024bf7f99721 1478 /* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm 85:024bf7f99721 1479 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1480 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1481 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1482 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1483 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1484 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1485
bogdanm 85:024bf7f99721 1486 /* Peripheral State functions **************************************************/
bogdanm 85:024bf7f99721 1487 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1488 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1489 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1490 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1491 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1492 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm 85:024bf7f99721 1493
bogdanm 85:024bf7f99721 1494 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
bogdanm 85:024bf7f99721 1495 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm 85:024bf7f99721 1496 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 85:024bf7f99721 1497 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 1498 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 1499 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 1500 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm 85:024bf7f99721 1501
bogdanm 85:024bf7f99721 1502
bogdanm 85:024bf7f99721 1503
bogdanm 85:024bf7f99721 1504
bogdanm 85:024bf7f99721 1505 /**
bogdanm 85:024bf7f99721 1506 * @}
bogdanm 85:024bf7f99721 1507 */
bogdanm 85:024bf7f99721 1508
bogdanm 85:024bf7f99721 1509 /**
bogdanm 85:024bf7f99721 1510 * @}
bogdanm 85:024bf7f99721 1511 */
bogdanm 85:024bf7f99721 1512
bogdanm 85:024bf7f99721 1513 #ifdef __cplusplus
bogdanm 85:024bf7f99721 1514 }
bogdanm 85:024bf7f99721 1515 #endif
bogdanm 85:024bf7f99721 1516
bogdanm 85:024bf7f99721 1517 #endif /* __STM32F0xx_HAL_TIM_H */
bogdanm 85:024bf7f99721 1518
bogdanm 85:024bf7f99721 1519 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/