erez i / mbed

version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_port.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_PORT_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_PORT_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 PORT
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Pin Control and Interrupts
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_PORT_PCRn - Pin Control Register n
bogdanm 82:6473597d706e 33 * - HW_PORT_GPCLR - Global Pin Control Low Register
bogdanm 82:6473597d706e 34 * - HW_PORT_GPCHR - Global Pin Control High Register
bogdanm 82:6473597d706e 35 * - HW_PORT_ISFR - Interrupt Status Flag Register
bogdanm 82:6473597d706e 36 * - HW_PORT_DFER - Digital Filter Enable Register
bogdanm 82:6473597d706e 37 * - HW_PORT_DFCR - Digital Filter Clock Register
bogdanm 82:6473597d706e 38 * - HW_PORT_DFWR - Digital Filter Width Register
bogdanm 82:6473597d706e 39 *
bogdanm 82:6473597d706e 40 * - hw_port_t - Struct containing all module registers.
bogdanm 82:6473597d706e 41 */
bogdanm 82:6473597d706e 42
bogdanm 82:6473597d706e 43 //! @name Module base addresses
bogdanm 82:6473597d706e 44 //@{
bogdanm 82:6473597d706e 45 #ifndef REGS_PORT_BASE
bogdanm 82:6473597d706e 46 #define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
bogdanm 82:6473597d706e 47 #define HW_PORTA (0U) //!< Instance number for PORTA.
bogdanm 82:6473597d706e 48 #define HW_PORTB (1U) //!< Instance number for PORTB.
bogdanm 82:6473597d706e 49 #define HW_PORTC (2U) //!< Instance number for PORTC.
bogdanm 82:6473597d706e 50 #define HW_PORTD (3U) //!< Instance number for PORTD.
bogdanm 82:6473597d706e 51 #define HW_PORTE (4U) //!< Instance number for PORTE.
bogdanm 82:6473597d706e 52 #define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
bogdanm 82:6473597d706e 53 #define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
bogdanm 82:6473597d706e 54 #define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
bogdanm 82:6473597d706e 55 #define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
bogdanm 82:6473597d706e 56 #define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
bogdanm 82:6473597d706e 57
bogdanm 82:6473597d706e 58 //! @brief Table of base addresses for PORT instances.
bogdanm 82:6473597d706e 59 static const uint32_t __g_regs_PORT_base_addresses[] = {
bogdanm 82:6473597d706e 60 REGS_PORTA_BASE,
bogdanm 82:6473597d706e 61 REGS_PORTB_BASE,
bogdanm 82:6473597d706e 62 REGS_PORTC_BASE,
bogdanm 82:6473597d706e 63 REGS_PORTD_BASE,
bogdanm 82:6473597d706e 64 REGS_PORTE_BASE,
bogdanm 82:6473597d706e 65 };
bogdanm 82:6473597d706e 66
bogdanm 82:6473597d706e 67 //! @brief Get the base address of PORT by instance number.
bogdanm 82:6473597d706e 68 //! @param x PORT instance number, from 0 through 4.
bogdanm 82:6473597d706e 69 #define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
bogdanm 82:6473597d706e 70
bogdanm 82:6473597d706e 71 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 72 //! @param b Base address for an instance of PORT.
bogdanm 82:6473597d706e 73 #define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
bogdanm 82:6473597d706e 74 #endif
bogdanm 82:6473597d706e 75 //@}
bogdanm 82:6473597d706e 76
bogdanm 82:6473597d706e 77 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 78 // HW_PORT_PCRn - Pin Control Register n
bogdanm 82:6473597d706e 79 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 80
bogdanm 82:6473597d706e 81 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 82 /*!
bogdanm 82:6473597d706e 83 * @brief HW_PORT_PCRn - Pin Control Register n (RW)
bogdanm 82:6473597d706e 84 *
bogdanm 82:6473597d706e 85 * Reset value: 0x00000742U
bogdanm 82:6473597d706e 86 *
bogdanm 82:6473597d706e 87 * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
bogdanm 82:6473597d706e 88 * this device. See the GPIO Configuration section for details on the available
bogdanm 82:6473597d706e 89 * functions for each pin. Do not modify pin configuration registers associated
bogdanm 82:6473597d706e 90 * with pins not available in your selected package. All unbonded pins not
bogdanm 82:6473597d706e 91 * available in your package will default to DISABLE state for lowest power consumption.
bogdanm 82:6473597d706e 92 */
bogdanm 82:6473597d706e 93 typedef union _hw_port_pcrn
bogdanm 82:6473597d706e 94 {
bogdanm 82:6473597d706e 95 uint32_t U;
bogdanm 82:6473597d706e 96 struct _hw_port_pcrn_bitfields
bogdanm 82:6473597d706e 97 {
bogdanm 82:6473597d706e 98 uint32_t PS : 1; //!< [0] Pull Select
bogdanm 82:6473597d706e 99 uint32_t PE : 1; //!< [1] Pull Enable
bogdanm 82:6473597d706e 100 uint32_t SRE : 1; //!< [2] Slew Rate Enable
bogdanm 82:6473597d706e 101 uint32_t RESERVED0 : 1; //!< [3]
bogdanm 82:6473597d706e 102 uint32_t PFE : 1; //!< [4] Passive Filter Enable
bogdanm 82:6473597d706e 103 uint32_t ODE : 1; //!< [5] Open Drain Enable
bogdanm 82:6473597d706e 104 uint32_t DSE : 1; //!< [6] Drive Strength Enable
bogdanm 82:6473597d706e 105 uint32_t RESERVED1 : 1; //!< [7]
bogdanm 82:6473597d706e 106 uint32_t MUX : 3; //!< [10:8] Pin Mux Control
bogdanm 82:6473597d706e 107 uint32_t RESERVED2 : 4; //!< [14:11]
bogdanm 82:6473597d706e 108 uint32_t LK : 1; //!< [15] Lock Register
bogdanm 82:6473597d706e 109 uint32_t IRQC : 4; //!< [19:16] Interrupt Configuration
bogdanm 82:6473597d706e 110 uint32_t RESERVED3 : 4; //!< [23:20]
bogdanm 82:6473597d706e 111 uint32_t ISF : 1; //!< [24] Interrupt Status Flag
bogdanm 82:6473597d706e 112 uint32_t RESERVED4 : 7; //!< [31:25]
bogdanm 82:6473597d706e 113 } B;
bogdanm 82:6473597d706e 114 } hw_port_pcrn_t;
bogdanm 82:6473597d706e 115 #endif
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 /*!
bogdanm 82:6473597d706e 118 * @name Constants and macros for entire PORT_PCRn register
bogdanm 82:6473597d706e 119 */
bogdanm 82:6473597d706e 120 //@{
bogdanm 82:6473597d706e 121 #define HW_PORT_PCRn_COUNT (32U)
bogdanm 82:6473597d706e 122
bogdanm 82:6473597d706e 123 #define HW_PORT_PCRn_ADDR(x, n) (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
bogdanm 82:6473597d706e 124
bogdanm 82:6473597d706e 125 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 126 #define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
bogdanm 82:6473597d706e 127 #define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
bogdanm 82:6473597d706e 128 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
bogdanm 82:6473597d706e 129 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
bogdanm 82:6473597d706e 130 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 131 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 132 #endif
bogdanm 82:6473597d706e 133 //@}
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 /*
bogdanm 82:6473597d706e 136 * Constants & macros for individual PORT_PCRn bitfields
bogdanm 82:6473597d706e 137 */
bogdanm 82:6473597d706e 138
bogdanm 82:6473597d706e 139 /*!
bogdanm 82:6473597d706e 140 * @name Register PORT_PCRn, field PS[0] (RW)
bogdanm 82:6473597d706e 141 *
bogdanm 82:6473597d706e 142 * Pull configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 143 *
bogdanm 82:6473597d706e 144 * Values:
bogdanm 82:6473597d706e 145 * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
bogdanm 82:6473597d706e 146 * corresponding PE field is set.
bogdanm 82:6473597d706e 147 * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
bogdanm 82:6473597d706e 148 * corresponding PE field is set.
bogdanm 82:6473597d706e 149 */
bogdanm 82:6473597d706e 150 //@{
bogdanm 82:6473597d706e 151 #define BP_PORT_PCRn_PS (0U) //!< Bit position for PORT_PCRn_PS.
bogdanm 82:6473597d706e 152 #define BM_PORT_PCRn_PS (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
bogdanm 82:6473597d706e 153 #define BS_PORT_PCRn_PS (1U) //!< Bit field size in bits for PORT_PCRn_PS.
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 156 //! @brief Read current value of the PORT_PCRn_PS field.
bogdanm 82:6473597d706e 157 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
bogdanm 82:6473597d706e 158 #endif
bogdanm 82:6473597d706e 159
bogdanm 82:6473597d706e 160 //! @brief Format value for bitfield PORT_PCRn_PS.
bogdanm 82:6473597d706e 161 #define BF_PORT_PCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
bogdanm 82:6473597d706e 162
bogdanm 82:6473597d706e 163 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 164 //! @brief Set the PS field to a new value.
bogdanm 82:6473597d706e 165 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
bogdanm 82:6473597d706e 166 #endif
bogdanm 82:6473597d706e 167 //@}
bogdanm 82:6473597d706e 168
bogdanm 82:6473597d706e 169 /*!
bogdanm 82:6473597d706e 170 * @name Register PORT_PCRn, field PE[1] (RW)
bogdanm 82:6473597d706e 171 *
bogdanm 82:6473597d706e 172 * Pull configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 173 *
bogdanm 82:6473597d706e 174 * Values:
bogdanm 82:6473597d706e 175 * - 0 - Internal pullup or pulldown resistor is not enabled on the
bogdanm 82:6473597d706e 176 * corresponding pin.
bogdanm 82:6473597d706e 177 * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
bogdanm 82:6473597d706e 178 * pin, if the pin is configured as a digital input.
bogdanm 82:6473597d706e 179 */
bogdanm 82:6473597d706e 180 //@{
bogdanm 82:6473597d706e 181 #define BP_PORT_PCRn_PE (1U) //!< Bit position for PORT_PCRn_PE.
bogdanm 82:6473597d706e 182 #define BM_PORT_PCRn_PE (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
bogdanm 82:6473597d706e 183 #define BS_PORT_PCRn_PE (1U) //!< Bit field size in bits for PORT_PCRn_PE.
bogdanm 82:6473597d706e 184
bogdanm 82:6473597d706e 185 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 186 //! @brief Read current value of the PORT_PCRn_PE field.
bogdanm 82:6473597d706e 187 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
bogdanm 82:6473597d706e 188 #endif
bogdanm 82:6473597d706e 189
bogdanm 82:6473597d706e 190 //! @brief Format value for bitfield PORT_PCRn_PE.
bogdanm 82:6473597d706e 191 #define BF_PORT_PCRn_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
bogdanm 82:6473597d706e 192
bogdanm 82:6473597d706e 193 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 194 //! @brief Set the PE field to a new value.
bogdanm 82:6473597d706e 195 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
bogdanm 82:6473597d706e 196 #endif
bogdanm 82:6473597d706e 197 //@}
bogdanm 82:6473597d706e 198
bogdanm 82:6473597d706e 199 /*!
bogdanm 82:6473597d706e 200 * @name Register PORT_PCRn, field SRE[2] (RW)
bogdanm 82:6473597d706e 201 *
bogdanm 82:6473597d706e 202 * Slew rate configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 203 *
bogdanm 82:6473597d706e 204 * Values:
bogdanm 82:6473597d706e 205 * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
bogdanm 82:6473597d706e 206 * configured as a digital output.
bogdanm 82:6473597d706e 207 * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
bogdanm 82:6473597d706e 208 * configured as a digital output.
bogdanm 82:6473597d706e 209 */
bogdanm 82:6473597d706e 210 //@{
bogdanm 82:6473597d706e 211 #define BP_PORT_PCRn_SRE (2U) //!< Bit position for PORT_PCRn_SRE.
bogdanm 82:6473597d706e 212 #define BM_PORT_PCRn_SRE (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
bogdanm 82:6473597d706e 213 #define BS_PORT_PCRn_SRE (1U) //!< Bit field size in bits for PORT_PCRn_SRE.
bogdanm 82:6473597d706e 214
bogdanm 82:6473597d706e 215 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 216 //! @brief Read current value of the PORT_PCRn_SRE field.
bogdanm 82:6473597d706e 217 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
bogdanm 82:6473597d706e 218 #endif
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 //! @brief Format value for bitfield PORT_PCRn_SRE.
bogdanm 82:6473597d706e 221 #define BF_PORT_PCRn_SRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
bogdanm 82:6473597d706e 222
bogdanm 82:6473597d706e 223 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 224 //! @brief Set the SRE field to a new value.
bogdanm 82:6473597d706e 225 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
bogdanm 82:6473597d706e 226 #endif
bogdanm 82:6473597d706e 227 //@}
bogdanm 82:6473597d706e 228
bogdanm 82:6473597d706e 229 /*!
bogdanm 82:6473597d706e 230 * @name Register PORT_PCRn, field PFE[4] (RW)
bogdanm 82:6473597d706e 231 *
bogdanm 82:6473597d706e 232 * Passive filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 233 *
bogdanm 82:6473597d706e 234 * Values:
bogdanm 82:6473597d706e 235 * - 0 - Passive input filter is disabled on the corresponding pin.
bogdanm 82:6473597d706e 236 * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
bogdanm 82:6473597d706e 237 * configured as a digital input. Refer to the device data sheet for filter
bogdanm 82:6473597d706e 238 * characteristics.
bogdanm 82:6473597d706e 239 */
bogdanm 82:6473597d706e 240 //@{
bogdanm 82:6473597d706e 241 #define BP_PORT_PCRn_PFE (4U) //!< Bit position for PORT_PCRn_PFE.
bogdanm 82:6473597d706e 242 #define BM_PORT_PCRn_PFE (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
bogdanm 82:6473597d706e 243 #define BS_PORT_PCRn_PFE (1U) //!< Bit field size in bits for PORT_PCRn_PFE.
bogdanm 82:6473597d706e 244
bogdanm 82:6473597d706e 245 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 246 //! @brief Read current value of the PORT_PCRn_PFE field.
bogdanm 82:6473597d706e 247 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
bogdanm 82:6473597d706e 248 #endif
bogdanm 82:6473597d706e 249
bogdanm 82:6473597d706e 250 //! @brief Format value for bitfield PORT_PCRn_PFE.
bogdanm 82:6473597d706e 251 #define BF_PORT_PCRn_PFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 254 //! @brief Set the PFE field to a new value.
bogdanm 82:6473597d706e 255 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
bogdanm 82:6473597d706e 256 #endif
bogdanm 82:6473597d706e 257 //@}
bogdanm 82:6473597d706e 258
bogdanm 82:6473597d706e 259 /*!
bogdanm 82:6473597d706e 260 * @name Register PORT_PCRn, field ODE[5] (RW)
bogdanm 82:6473597d706e 261 *
bogdanm 82:6473597d706e 262 * Open drain configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 263 *
bogdanm 82:6473597d706e 264 * Values:
bogdanm 82:6473597d706e 265 * - 0 - Open drain output is disabled on the corresponding pin.
bogdanm 82:6473597d706e 266 * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
bogdanm 82:6473597d706e 267 * configured as a digital output.
bogdanm 82:6473597d706e 268 */
bogdanm 82:6473597d706e 269 //@{
bogdanm 82:6473597d706e 270 #define BP_PORT_PCRn_ODE (5U) //!< Bit position for PORT_PCRn_ODE.
bogdanm 82:6473597d706e 271 #define BM_PORT_PCRn_ODE (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
bogdanm 82:6473597d706e 272 #define BS_PORT_PCRn_ODE (1U) //!< Bit field size in bits for PORT_PCRn_ODE.
bogdanm 82:6473597d706e 273
bogdanm 82:6473597d706e 274 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 275 //! @brief Read current value of the PORT_PCRn_ODE field.
bogdanm 82:6473597d706e 276 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
bogdanm 82:6473597d706e 277 #endif
bogdanm 82:6473597d706e 278
bogdanm 82:6473597d706e 279 //! @brief Format value for bitfield PORT_PCRn_ODE.
bogdanm 82:6473597d706e 280 #define BF_PORT_PCRn_ODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
bogdanm 82:6473597d706e 281
bogdanm 82:6473597d706e 282 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 283 //! @brief Set the ODE field to a new value.
bogdanm 82:6473597d706e 284 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
bogdanm 82:6473597d706e 285 #endif
bogdanm 82:6473597d706e 286 //@}
bogdanm 82:6473597d706e 287
bogdanm 82:6473597d706e 288 /*!
bogdanm 82:6473597d706e 289 * @name Register PORT_PCRn, field DSE[6] (RW)
bogdanm 82:6473597d706e 290 *
bogdanm 82:6473597d706e 291 * Drive strength configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 292 *
bogdanm 82:6473597d706e 293 * Values:
bogdanm 82:6473597d706e 294 * - 0 - Low drive strength is configured on the corresponding pin, if pin is
bogdanm 82:6473597d706e 295 * configured as a digital output.
bogdanm 82:6473597d706e 296 * - 1 - High drive strength is configured on the corresponding pin, if pin is
bogdanm 82:6473597d706e 297 * configured as a digital output.
bogdanm 82:6473597d706e 298 */
bogdanm 82:6473597d706e 299 //@{
bogdanm 82:6473597d706e 300 #define BP_PORT_PCRn_DSE (6U) //!< Bit position for PORT_PCRn_DSE.
bogdanm 82:6473597d706e 301 #define BM_PORT_PCRn_DSE (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
bogdanm 82:6473597d706e 302 #define BS_PORT_PCRn_DSE (1U) //!< Bit field size in bits for PORT_PCRn_DSE.
bogdanm 82:6473597d706e 303
bogdanm 82:6473597d706e 304 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 305 //! @brief Read current value of the PORT_PCRn_DSE field.
bogdanm 82:6473597d706e 306 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
bogdanm 82:6473597d706e 307 #endif
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 //! @brief Format value for bitfield PORT_PCRn_DSE.
bogdanm 82:6473597d706e 310 #define BF_PORT_PCRn_DSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
bogdanm 82:6473597d706e 311
bogdanm 82:6473597d706e 312 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 313 //! @brief Set the DSE field to a new value.
bogdanm 82:6473597d706e 314 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
bogdanm 82:6473597d706e 315 #endif
bogdanm 82:6473597d706e 316 //@}
bogdanm 82:6473597d706e 317
bogdanm 82:6473597d706e 318 /*!
bogdanm 82:6473597d706e 319 * @name Register PORT_PCRn, field MUX[10:8] (RW)
bogdanm 82:6473597d706e 320 *
bogdanm 82:6473597d706e 321 * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
bogdanm 82:6473597d706e 322 * reserved and may result in configuring the pin for a different pin muxing
bogdanm 82:6473597d706e 323 * slot. The corresponding pin is configured in the following pin muxing slot as
bogdanm 82:6473597d706e 324 * follows:
bogdanm 82:6473597d706e 325 *
bogdanm 82:6473597d706e 326 * Values:
bogdanm 82:6473597d706e 327 * - 000 - Pin disabled (analog).
bogdanm 82:6473597d706e 328 * - 001 - Alternative 1 (GPIO).
bogdanm 82:6473597d706e 329 * - 010 - Alternative 2 (chip-specific).
bogdanm 82:6473597d706e 330 * - 011 - Alternative 3 (chip-specific).
bogdanm 82:6473597d706e 331 * - 100 - Alternative 4 (chip-specific).
bogdanm 82:6473597d706e 332 * - 101 - Alternative 5 (chip-specific).
bogdanm 82:6473597d706e 333 * - 110 - Alternative 6 (chip-specific).
bogdanm 82:6473597d706e 334 * - 111 - Alternative 7 (chip-specific).
bogdanm 82:6473597d706e 335 */
bogdanm 82:6473597d706e 336 //@{
bogdanm 82:6473597d706e 337 #define BP_PORT_PCRn_MUX (8U) //!< Bit position for PORT_PCRn_MUX.
bogdanm 82:6473597d706e 338 #define BM_PORT_PCRn_MUX (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
bogdanm 82:6473597d706e 339 #define BS_PORT_PCRn_MUX (3U) //!< Bit field size in bits for PORT_PCRn_MUX.
bogdanm 82:6473597d706e 340
bogdanm 82:6473597d706e 341 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 342 //! @brief Read current value of the PORT_PCRn_MUX field.
bogdanm 82:6473597d706e 343 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
bogdanm 82:6473597d706e 344 #endif
bogdanm 82:6473597d706e 345
bogdanm 82:6473597d706e 346 //! @brief Format value for bitfield PORT_PCRn_MUX.
bogdanm 82:6473597d706e 347 #define BF_PORT_PCRn_MUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
bogdanm 82:6473597d706e 348
bogdanm 82:6473597d706e 349 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 350 //! @brief Set the MUX field to a new value.
bogdanm 82:6473597d706e 351 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
bogdanm 82:6473597d706e 352 #endif
bogdanm 82:6473597d706e 353 //@}
bogdanm 82:6473597d706e 354
bogdanm 82:6473597d706e 355 /*!
bogdanm 82:6473597d706e 356 * @name Register PORT_PCRn, field LK[15] (RW)
bogdanm 82:6473597d706e 357 *
bogdanm 82:6473597d706e 358 * Values:
bogdanm 82:6473597d706e 359 * - 0 - Pin Control Register fields [15:0] are not locked.
bogdanm 82:6473597d706e 360 * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
bogdanm 82:6473597d706e 361 * until the next system reset.
bogdanm 82:6473597d706e 362 */
bogdanm 82:6473597d706e 363 //@{
bogdanm 82:6473597d706e 364 #define BP_PORT_PCRn_LK (15U) //!< Bit position for PORT_PCRn_LK.
bogdanm 82:6473597d706e 365 #define BM_PORT_PCRn_LK (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
bogdanm 82:6473597d706e 366 #define BS_PORT_PCRn_LK (1U) //!< Bit field size in bits for PORT_PCRn_LK.
bogdanm 82:6473597d706e 367
bogdanm 82:6473597d706e 368 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 369 //! @brief Read current value of the PORT_PCRn_LK field.
bogdanm 82:6473597d706e 370 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
bogdanm 82:6473597d706e 371 #endif
bogdanm 82:6473597d706e 372
bogdanm 82:6473597d706e 373 //! @brief Format value for bitfield PORT_PCRn_LK.
bogdanm 82:6473597d706e 374 #define BF_PORT_PCRn_LK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
bogdanm 82:6473597d706e 375
bogdanm 82:6473597d706e 376 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 377 //! @brief Set the LK field to a new value.
bogdanm 82:6473597d706e 378 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
bogdanm 82:6473597d706e 379 #endif
bogdanm 82:6473597d706e 380 //@}
bogdanm 82:6473597d706e 381
bogdanm 82:6473597d706e 382 /*!
bogdanm 82:6473597d706e 383 * @name Register PORT_PCRn, field IRQC[19:16] (RW)
bogdanm 82:6473597d706e 384 *
bogdanm 82:6473597d706e 385 * The pin interrupt configuration is valid in all digital pin muxing modes. The
bogdanm 82:6473597d706e 386 * corresponding pin is configured to generate interrupt/DMA request as follows:
bogdanm 82:6473597d706e 387 *
bogdanm 82:6473597d706e 388 * Values:
bogdanm 82:6473597d706e 389 * - 0000 - Interrupt/DMA request disabled.
bogdanm 82:6473597d706e 390 * - 0001 - DMA request on rising edge.
bogdanm 82:6473597d706e 391 * - 0010 - DMA request on falling edge.
bogdanm 82:6473597d706e 392 * - 0011 - DMA request on either edge.
bogdanm 82:6473597d706e 393 * - 1000 - Interrupt when logic 0.
bogdanm 82:6473597d706e 394 * - 1001 - Interrupt on rising-edge.
bogdanm 82:6473597d706e 395 * - 1010 - Interrupt on falling-edge.
bogdanm 82:6473597d706e 396 * - 1011 - Interrupt on either edge.
bogdanm 82:6473597d706e 397 * - 1100 - Interrupt when logic 1.
bogdanm 82:6473597d706e 398 */
bogdanm 82:6473597d706e 399 //@{
bogdanm 82:6473597d706e 400 #define BP_PORT_PCRn_IRQC (16U) //!< Bit position for PORT_PCRn_IRQC.
bogdanm 82:6473597d706e 401 #define BM_PORT_PCRn_IRQC (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
bogdanm 82:6473597d706e 402 #define BS_PORT_PCRn_IRQC (4U) //!< Bit field size in bits for PORT_PCRn_IRQC.
bogdanm 82:6473597d706e 403
bogdanm 82:6473597d706e 404 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 405 //! @brief Read current value of the PORT_PCRn_IRQC field.
bogdanm 82:6473597d706e 406 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
bogdanm 82:6473597d706e 407 #endif
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 //! @brief Format value for bitfield PORT_PCRn_IRQC.
bogdanm 82:6473597d706e 410 #define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
bogdanm 82:6473597d706e 411
bogdanm 82:6473597d706e 412 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 413 //! @brief Set the IRQC field to a new value.
bogdanm 82:6473597d706e 414 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
bogdanm 82:6473597d706e 415 #endif
bogdanm 82:6473597d706e 416 //@}
bogdanm 82:6473597d706e 417
bogdanm 82:6473597d706e 418 /*!
bogdanm 82:6473597d706e 419 * @name Register PORT_PCRn, field ISF[24] (W1C)
bogdanm 82:6473597d706e 420 *
bogdanm 82:6473597d706e 421 * The pin interrupt configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 422 *
bogdanm 82:6473597d706e 423 * Values:
bogdanm 82:6473597d706e 424 * - 0 - Configured interrupt is not detected.
bogdanm 82:6473597d706e 425 * - 1 - Configured interrupt is detected. If the pin is configured to generate
bogdanm 82:6473597d706e 426 * a DMA request, then the corresponding flag will be cleared automatically
bogdanm 82:6473597d706e 427 * at the completion of the requested DMA transfer. Otherwise, the flag
bogdanm 82:6473597d706e 428 * remains set until a logic 1 is written to the flag. If the pin is configured for
bogdanm 82:6473597d706e 429 * a level sensitive interrupt and the pin remains asserted, then the flag
bogdanm 82:6473597d706e 430 * is set again immediately after it is cleared.
bogdanm 82:6473597d706e 431 */
bogdanm 82:6473597d706e 432 //@{
bogdanm 82:6473597d706e 433 #define BP_PORT_PCRn_ISF (24U) //!< Bit position for PORT_PCRn_ISF.
bogdanm 82:6473597d706e 434 #define BM_PORT_PCRn_ISF (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
bogdanm 82:6473597d706e 435 #define BS_PORT_PCRn_ISF (1U) //!< Bit field size in bits for PORT_PCRn_ISF.
bogdanm 82:6473597d706e 436
bogdanm 82:6473597d706e 437 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 438 //! @brief Read current value of the PORT_PCRn_ISF field.
bogdanm 82:6473597d706e 439 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
bogdanm 82:6473597d706e 440 #endif
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 //! @brief Format value for bitfield PORT_PCRn_ISF.
bogdanm 82:6473597d706e 443 #define BF_PORT_PCRn_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
bogdanm 82:6473597d706e 444
bogdanm 82:6473597d706e 445 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 446 //! @brief Set the ISF field to a new value.
bogdanm 82:6473597d706e 447 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
bogdanm 82:6473597d706e 448 #endif
bogdanm 82:6473597d706e 449 //@}
bogdanm 82:6473597d706e 450
bogdanm 82:6473597d706e 451 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 452 // HW_PORT_GPCLR - Global Pin Control Low Register
bogdanm 82:6473597d706e 453 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 454
bogdanm 82:6473597d706e 455 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 456 /*!
bogdanm 82:6473597d706e 457 * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
bogdanm 82:6473597d706e 458 *
bogdanm 82:6473597d706e 459 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 460 *
bogdanm 82:6473597d706e 461 * Only 32-bit writes are supported to this register.
bogdanm 82:6473597d706e 462 */
bogdanm 82:6473597d706e 463 typedef union _hw_port_gpclr
bogdanm 82:6473597d706e 464 {
bogdanm 82:6473597d706e 465 uint32_t U;
bogdanm 82:6473597d706e 466 struct _hw_port_gpclr_bitfields
bogdanm 82:6473597d706e 467 {
bogdanm 82:6473597d706e 468 uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
bogdanm 82:6473597d706e 469 uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
bogdanm 82:6473597d706e 470 } B;
bogdanm 82:6473597d706e 471 } hw_port_gpclr_t;
bogdanm 82:6473597d706e 472 #endif
bogdanm 82:6473597d706e 473
bogdanm 82:6473597d706e 474 /*!
bogdanm 82:6473597d706e 475 * @name Constants and macros for entire PORT_GPCLR register
bogdanm 82:6473597d706e 476 */
bogdanm 82:6473597d706e 477 //@{
bogdanm 82:6473597d706e 478 #define HW_PORT_GPCLR_ADDR(x) (REGS_PORT_BASE(x) + 0x80U)
bogdanm 82:6473597d706e 479
bogdanm 82:6473597d706e 480 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 481 #define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
bogdanm 82:6473597d706e 482 #define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
bogdanm 82:6473597d706e 483 #define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
bogdanm 82:6473597d706e 484 #endif
bogdanm 82:6473597d706e 485 //@}
bogdanm 82:6473597d706e 486
bogdanm 82:6473597d706e 487 /*
bogdanm 82:6473597d706e 488 * Constants & macros for individual PORT_GPCLR bitfields
bogdanm 82:6473597d706e 489 */
bogdanm 82:6473597d706e 490
bogdanm 82:6473597d706e 491 /*!
bogdanm 82:6473597d706e 492 * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
bogdanm 82:6473597d706e 493 *
bogdanm 82:6473597d706e 494 * Write value that is written to all Pin Control Registers bits [15:0] that are
bogdanm 82:6473597d706e 495 * selected by GPWE.
bogdanm 82:6473597d706e 496 */
bogdanm 82:6473597d706e 497 //@{
bogdanm 82:6473597d706e 498 #define BP_PORT_GPCLR_GPWD (0U) //!< Bit position for PORT_GPCLR_GPWD.
bogdanm 82:6473597d706e 499 #define BM_PORT_GPCLR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
bogdanm 82:6473597d706e 500 #define BS_PORT_GPCLR_GPWD (16U) //!< Bit field size in bits for PORT_GPCLR_GPWD.
bogdanm 82:6473597d706e 501
bogdanm 82:6473597d706e 502 //! @brief Format value for bitfield PORT_GPCLR_GPWD.
bogdanm 82:6473597d706e 503 #define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 506 //! @brief Set the GPWD field to a new value.
bogdanm 82:6473597d706e 507 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
bogdanm 82:6473597d706e 508 #endif
bogdanm 82:6473597d706e 509 //@}
bogdanm 82:6473597d706e 510
bogdanm 82:6473597d706e 511 /*!
bogdanm 82:6473597d706e 512 * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
bogdanm 82:6473597d706e 513 *
bogdanm 82:6473597d706e 514 * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
bogdanm 82:6473597d706e 515 * the value in GPWD. If a selected Pin Control Register is locked then the write
bogdanm 82:6473597d706e 516 * to that register is ignored.
bogdanm 82:6473597d706e 517 *
bogdanm 82:6473597d706e 518 * Values:
bogdanm 82:6473597d706e 519 * - 0 - Corresponding Pin Control Register is not updated with the value in
bogdanm 82:6473597d706e 520 * GPWD.
bogdanm 82:6473597d706e 521 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
bogdanm 82:6473597d706e 522 */
bogdanm 82:6473597d706e 523 //@{
bogdanm 82:6473597d706e 524 #define BP_PORT_GPCLR_GPWE (16U) //!< Bit position for PORT_GPCLR_GPWE.
bogdanm 82:6473597d706e 525 #define BM_PORT_GPCLR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
bogdanm 82:6473597d706e 526 #define BS_PORT_GPCLR_GPWE (16U) //!< Bit field size in bits for PORT_GPCLR_GPWE.
bogdanm 82:6473597d706e 527
bogdanm 82:6473597d706e 528 //! @brief Format value for bitfield PORT_GPCLR_GPWE.
bogdanm 82:6473597d706e 529 #define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
bogdanm 82:6473597d706e 530
bogdanm 82:6473597d706e 531 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 532 //! @brief Set the GPWE field to a new value.
bogdanm 82:6473597d706e 533 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
bogdanm 82:6473597d706e 534 #endif
bogdanm 82:6473597d706e 535 //@}
bogdanm 82:6473597d706e 536
bogdanm 82:6473597d706e 537 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 538 // HW_PORT_GPCHR - Global Pin Control High Register
bogdanm 82:6473597d706e 539 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 542 /*!
bogdanm 82:6473597d706e 543 * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
bogdanm 82:6473597d706e 544 *
bogdanm 82:6473597d706e 545 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 546 *
bogdanm 82:6473597d706e 547 * Only 32-bit writes are supported to this register.
bogdanm 82:6473597d706e 548 */
bogdanm 82:6473597d706e 549 typedef union _hw_port_gpchr
bogdanm 82:6473597d706e 550 {
bogdanm 82:6473597d706e 551 uint32_t U;
bogdanm 82:6473597d706e 552 struct _hw_port_gpchr_bitfields
bogdanm 82:6473597d706e 553 {
bogdanm 82:6473597d706e 554 uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
bogdanm 82:6473597d706e 555 uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
bogdanm 82:6473597d706e 556 } B;
bogdanm 82:6473597d706e 557 } hw_port_gpchr_t;
bogdanm 82:6473597d706e 558 #endif
bogdanm 82:6473597d706e 559
bogdanm 82:6473597d706e 560 /*!
bogdanm 82:6473597d706e 561 * @name Constants and macros for entire PORT_GPCHR register
bogdanm 82:6473597d706e 562 */
bogdanm 82:6473597d706e 563 //@{
bogdanm 82:6473597d706e 564 #define HW_PORT_GPCHR_ADDR(x) (REGS_PORT_BASE(x) + 0x84U)
bogdanm 82:6473597d706e 565
bogdanm 82:6473597d706e 566 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 567 #define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
bogdanm 82:6473597d706e 568 #define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
bogdanm 82:6473597d706e 569 #define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
bogdanm 82:6473597d706e 570 #endif
bogdanm 82:6473597d706e 571 //@}
bogdanm 82:6473597d706e 572
bogdanm 82:6473597d706e 573 /*
bogdanm 82:6473597d706e 574 * Constants & macros for individual PORT_GPCHR bitfields
bogdanm 82:6473597d706e 575 */
bogdanm 82:6473597d706e 576
bogdanm 82:6473597d706e 577 /*!
bogdanm 82:6473597d706e 578 * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
bogdanm 82:6473597d706e 579 *
bogdanm 82:6473597d706e 580 * Write value that is written to all Pin Control Registers bits [15:0] that are
bogdanm 82:6473597d706e 581 * selected by GPWE.
bogdanm 82:6473597d706e 582 */
bogdanm 82:6473597d706e 583 //@{
bogdanm 82:6473597d706e 584 #define BP_PORT_GPCHR_GPWD (0U) //!< Bit position for PORT_GPCHR_GPWD.
bogdanm 82:6473597d706e 585 #define BM_PORT_GPCHR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
bogdanm 82:6473597d706e 586 #define BS_PORT_GPCHR_GPWD (16U) //!< Bit field size in bits for PORT_GPCHR_GPWD.
bogdanm 82:6473597d706e 587
bogdanm 82:6473597d706e 588 //! @brief Format value for bitfield PORT_GPCHR_GPWD.
bogdanm 82:6473597d706e 589 #define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
bogdanm 82:6473597d706e 590
bogdanm 82:6473597d706e 591 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 592 //! @brief Set the GPWD field to a new value.
bogdanm 82:6473597d706e 593 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
bogdanm 82:6473597d706e 594 #endif
bogdanm 82:6473597d706e 595 //@}
bogdanm 82:6473597d706e 596
bogdanm 82:6473597d706e 597 /*!
bogdanm 82:6473597d706e 598 * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
bogdanm 82:6473597d706e 599 *
bogdanm 82:6473597d706e 600 * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
bogdanm 82:6473597d706e 601 * the value in GPWD. If a selected Pin Control Register is locked then the write
bogdanm 82:6473597d706e 602 * to that register is ignored.
bogdanm 82:6473597d706e 603 *
bogdanm 82:6473597d706e 604 * Values:
bogdanm 82:6473597d706e 605 * - 0 - Corresponding Pin Control Register is not updated with the value in
bogdanm 82:6473597d706e 606 * GPWD.
bogdanm 82:6473597d706e 607 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
bogdanm 82:6473597d706e 608 */
bogdanm 82:6473597d706e 609 //@{
bogdanm 82:6473597d706e 610 #define BP_PORT_GPCHR_GPWE (16U) //!< Bit position for PORT_GPCHR_GPWE.
bogdanm 82:6473597d706e 611 #define BM_PORT_GPCHR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
bogdanm 82:6473597d706e 612 #define BS_PORT_GPCHR_GPWE (16U) //!< Bit field size in bits for PORT_GPCHR_GPWE.
bogdanm 82:6473597d706e 613
bogdanm 82:6473597d706e 614 //! @brief Format value for bitfield PORT_GPCHR_GPWE.
bogdanm 82:6473597d706e 615 #define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
bogdanm 82:6473597d706e 616
bogdanm 82:6473597d706e 617 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 618 //! @brief Set the GPWE field to a new value.
bogdanm 82:6473597d706e 619 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
bogdanm 82:6473597d706e 620 #endif
bogdanm 82:6473597d706e 621 //@}
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 624 // HW_PORT_ISFR - Interrupt Status Flag Register
bogdanm 82:6473597d706e 625 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 628 /*!
bogdanm 82:6473597d706e 629 * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
bogdanm 82:6473597d706e 630 *
bogdanm 82:6473597d706e 631 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 632 *
bogdanm 82:6473597d706e 633 * The pin interrupt configuration is valid in all digital pin muxing modes. The
bogdanm 82:6473597d706e 634 * Interrupt Status Flag for each pin is also visible in the corresponding Pin
bogdanm 82:6473597d706e 635 * Control Register, and each flag can be cleared in either location.
bogdanm 82:6473597d706e 636 */
bogdanm 82:6473597d706e 637 typedef union _hw_port_isfr
bogdanm 82:6473597d706e 638 {
bogdanm 82:6473597d706e 639 uint32_t U;
bogdanm 82:6473597d706e 640 struct _hw_port_isfr_bitfields
bogdanm 82:6473597d706e 641 {
bogdanm 82:6473597d706e 642 uint32_t ISF : 32; //!< [31:0] Interrupt Status Flag
bogdanm 82:6473597d706e 643 } B;
bogdanm 82:6473597d706e 644 } hw_port_isfr_t;
bogdanm 82:6473597d706e 645 #endif
bogdanm 82:6473597d706e 646
bogdanm 82:6473597d706e 647 /*!
bogdanm 82:6473597d706e 648 * @name Constants and macros for entire PORT_ISFR register
bogdanm 82:6473597d706e 649 */
bogdanm 82:6473597d706e 650 //@{
bogdanm 82:6473597d706e 651 #define HW_PORT_ISFR_ADDR(x) (REGS_PORT_BASE(x) + 0xA0U)
bogdanm 82:6473597d706e 652
bogdanm 82:6473597d706e 653 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 654 #define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
bogdanm 82:6473597d706e 655 #define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
bogdanm 82:6473597d706e 656 #define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
bogdanm 82:6473597d706e 657 #define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
bogdanm 82:6473597d706e 658 #define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 659 #define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 660 #endif
bogdanm 82:6473597d706e 661 //@}
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 /*
bogdanm 82:6473597d706e 664 * Constants & macros for individual PORT_ISFR bitfields
bogdanm 82:6473597d706e 665 */
bogdanm 82:6473597d706e 666
bogdanm 82:6473597d706e 667 /*!
bogdanm 82:6473597d706e 668 * @name Register PORT_ISFR, field ISF[31:0] (W1C)
bogdanm 82:6473597d706e 669 *
bogdanm 82:6473597d706e 670 * Each bit in the field indicates the detection of the configured interrupt of
bogdanm 82:6473597d706e 671 * the same number as the field.
bogdanm 82:6473597d706e 672 *
bogdanm 82:6473597d706e 673 * Values:
bogdanm 82:6473597d706e 674 * - 0 - Configured interrupt is not detected.
bogdanm 82:6473597d706e 675 * - 1 - Configured interrupt is detected. If the pin is configured to generate
bogdanm 82:6473597d706e 676 * a DMA request, then the corresponding flag will be cleared automatically
bogdanm 82:6473597d706e 677 * at the completion of the requested DMA transfer. Otherwise, the flag
bogdanm 82:6473597d706e 678 * remains set until a logic 1 is written to the flag. If the pin is configured for
bogdanm 82:6473597d706e 679 * a level sensitive interrupt and the pin remains asserted, then the flag
bogdanm 82:6473597d706e 680 * is set again immediately after it is cleared.
bogdanm 82:6473597d706e 681 */
bogdanm 82:6473597d706e 682 //@{
bogdanm 82:6473597d706e 683 #define BP_PORT_ISFR_ISF (0U) //!< Bit position for PORT_ISFR_ISF.
bogdanm 82:6473597d706e 684 #define BM_PORT_ISFR_ISF (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
bogdanm 82:6473597d706e 685 #define BS_PORT_ISFR_ISF (32U) //!< Bit field size in bits for PORT_ISFR_ISF.
bogdanm 82:6473597d706e 686
bogdanm 82:6473597d706e 687 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 688 //! @brief Read current value of the PORT_ISFR_ISF field.
bogdanm 82:6473597d706e 689 #define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
bogdanm 82:6473597d706e 690 #endif
bogdanm 82:6473597d706e 691
bogdanm 82:6473597d706e 692 //! @brief Format value for bitfield PORT_ISFR_ISF.
bogdanm 82:6473597d706e 693 #define BF_PORT_ISFR_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
bogdanm 82:6473597d706e 694
bogdanm 82:6473597d706e 695 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 696 //! @brief Set the ISF field to a new value.
bogdanm 82:6473597d706e 697 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
bogdanm 82:6473597d706e 698 #endif
bogdanm 82:6473597d706e 699 //@}
bogdanm 82:6473597d706e 700
bogdanm 82:6473597d706e 701 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 702 // HW_PORT_DFER - Digital Filter Enable Register
bogdanm 82:6473597d706e 703 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 704
bogdanm 82:6473597d706e 705 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 706 /*!
bogdanm 82:6473597d706e 707 * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
bogdanm 82:6473597d706e 708 *
bogdanm 82:6473597d706e 709 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 710 *
bogdanm 82:6473597d706e 711 * The corresponding bit is read only for pins that do not support a digital
bogdanm 82:6473597d706e 712 * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
bogdanm 82:6473597d706e 713 * the pins that support digital filter. The digital filter configuration is valid
bogdanm 82:6473597d706e 714 * in all digital pin muxing modes.
bogdanm 82:6473597d706e 715 */
bogdanm 82:6473597d706e 716 typedef union _hw_port_dfer
bogdanm 82:6473597d706e 717 {
bogdanm 82:6473597d706e 718 uint32_t U;
bogdanm 82:6473597d706e 719 struct _hw_port_dfer_bitfields
bogdanm 82:6473597d706e 720 {
bogdanm 82:6473597d706e 721 uint32_t DFE : 32; //!< [31:0] Digital Filter Enable
bogdanm 82:6473597d706e 722 } B;
bogdanm 82:6473597d706e 723 } hw_port_dfer_t;
bogdanm 82:6473597d706e 724 #endif
bogdanm 82:6473597d706e 725
bogdanm 82:6473597d706e 726 /*!
bogdanm 82:6473597d706e 727 * @name Constants and macros for entire PORT_DFER register
bogdanm 82:6473597d706e 728 */
bogdanm 82:6473597d706e 729 //@{
bogdanm 82:6473597d706e 730 #define HW_PORT_DFER_ADDR(x) (REGS_PORT_BASE(x) + 0xC0U)
bogdanm 82:6473597d706e 731
bogdanm 82:6473597d706e 732 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 733 #define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
bogdanm 82:6473597d706e 734 #define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
bogdanm 82:6473597d706e 735 #define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
bogdanm 82:6473597d706e 736 #define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
bogdanm 82:6473597d706e 737 #define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
bogdanm 82:6473597d706e 738 #define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
bogdanm 82:6473597d706e 739 #endif
bogdanm 82:6473597d706e 740 //@}
bogdanm 82:6473597d706e 741
bogdanm 82:6473597d706e 742 /*
bogdanm 82:6473597d706e 743 * Constants & macros for individual PORT_DFER bitfields
bogdanm 82:6473597d706e 744 */
bogdanm 82:6473597d706e 745
bogdanm 82:6473597d706e 746 /*!
bogdanm 82:6473597d706e 747 * @name Register PORT_DFER, field DFE[31:0] (RW)
bogdanm 82:6473597d706e 748 *
bogdanm 82:6473597d706e 749 * The digital filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 750 * The output of each digital filter is reset to zero at system reset and whenever
bogdanm 82:6473597d706e 751 * the digital filter is disabled. Each bit in the field enables the digital
bogdanm 82:6473597d706e 752 * filter of the same number as the field.
bogdanm 82:6473597d706e 753 *
bogdanm 82:6473597d706e 754 * Values:
bogdanm 82:6473597d706e 755 * - 0 - Digital filter is disabled on the corresponding pin and output of the
bogdanm 82:6473597d706e 756 * digital filter is reset to zero.
bogdanm 82:6473597d706e 757 * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
bogdanm 82:6473597d706e 758 * configured as a digital input.
bogdanm 82:6473597d706e 759 */
bogdanm 82:6473597d706e 760 //@{
bogdanm 82:6473597d706e 761 #define BP_PORT_DFER_DFE (0U) //!< Bit position for PORT_DFER_DFE.
bogdanm 82:6473597d706e 762 #define BM_PORT_DFER_DFE (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
bogdanm 82:6473597d706e 763 #define BS_PORT_DFER_DFE (32U) //!< Bit field size in bits for PORT_DFER_DFE.
bogdanm 82:6473597d706e 764
bogdanm 82:6473597d706e 765 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 766 //! @brief Read current value of the PORT_DFER_DFE field.
bogdanm 82:6473597d706e 767 #define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
bogdanm 82:6473597d706e 768 #endif
bogdanm 82:6473597d706e 769
bogdanm 82:6473597d706e 770 //! @brief Format value for bitfield PORT_DFER_DFE.
bogdanm 82:6473597d706e 771 #define BF_PORT_DFER_DFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
bogdanm 82:6473597d706e 772
bogdanm 82:6473597d706e 773 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 774 //! @brief Set the DFE field to a new value.
bogdanm 82:6473597d706e 775 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
bogdanm 82:6473597d706e 776 #endif
bogdanm 82:6473597d706e 777 //@}
bogdanm 82:6473597d706e 778
bogdanm 82:6473597d706e 779 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 780 // HW_PORT_DFCR - Digital Filter Clock Register
bogdanm 82:6473597d706e 781 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 782
bogdanm 82:6473597d706e 783 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 784 /*!
bogdanm 82:6473597d706e 785 * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
bogdanm 82:6473597d706e 786 *
bogdanm 82:6473597d706e 787 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 788 *
bogdanm 82:6473597d706e 789 * This register is read only for ports that do not support a digital filter.
bogdanm 82:6473597d706e 790 * The digital filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 791 */
bogdanm 82:6473597d706e 792 typedef union _hw_port_dfcr
bogdanm 82:6473597d706e 793 {
bogdanm 82:6473597d706e 794 uint32_t U;
bogdanm 82:6473597d706e 795 struct _hw_port_dfcr_bitfields
bogdanm 82:6473597d706e 796 {
bogdanm 82:6473597d706e 797 uint32_t CS : 1; //!< [0] Clock Source
bogdanm 82:6473597d706e 798 uint32_t RESERVED0 : 31; //!< [31:1]
bogdanm 82:6473597d706e 799 } B;
bogdanm 82:6473597d706e 800 } hw_port_dfcr_t;
bogdanm 82:6473597d706e 801 #endif
bogdanm 82:6473597d706e 802
bogdanm 82:6473597d706e 803 /*!
bogdanm 82:6473597d706e 804 * @name Constants and macros for entire PORT_DFCR register
bogdanm 82:6473597d706e 805 */
bogdanm 82:6473597d706e 806 //@{
bogdanm 82:6473597d706e 807 #define HW_PORT_DFCR_ADDR(x) (REGS_PORT_BASE(x) + 0xC4U)
bogdanm 82:6473597d706e 808
bogdanm 82:6473597d706e 809 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 810 #define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
bogdanm 82:6473597d706e 811 #define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
bogdanm 82:6473597d706e 812 #define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
bogdanm 82:6473597d706e 813 #define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
bogdanm 82:6473597d706e 814 #define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 815 #define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 816 #endif
bogdanm 82:6473597d706e 817 //@}
bogdanm 82:6473597d706e 818
bogdanm 82:6473597d706e 819 /*
bogdanm 82:6473597d706e 820 * Constants & macros for individual PORT_DFCR bitfields
bogdanm 82:6473597d706e 821 */
bogdanm 82:6473597d706e 822
bogdanm 82:6473597d706e 823 /*!
bogdanm 82:6473597d706e 824 * @name Register PORT_DFCR, field CS[0] (RW)
bogdanm 82:6473597d706e 825 *
bogdanm 82:6473597d706e 826 * The digital filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 827 * Configures the clock source for the digital input filters. Changing the filter
bogdanm 82:6473597d706e 828 * clock source must be done only when all digital filters are disabled.
bogdanm 82:6473597d706e 829 *
bogdanm 82:6473597d706e 830 * Values:
bogdanm 82:6473597d706e 831 * - 0 - Digital filters are clocked by the bus clock.
bogdanm 82:6473597d706e 832 * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
bogdanm 82:6473597d706e 833 */
bogdanm 82:6473597d706e 834 //@{
bogdanm 82:6473597d706e 835 #define BP_PORT_DFCR_CS (0U) //!< Bit position for PORT_DFCR_CS.
bogdanm 82:6473597d706e 836 #define BM_PORT_DFCR_CS (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
bogdanm 82:6473597d706e 837 #define BS_PORT_DFCR_CS (1U) //!< Bit field size in bits for PORT_DFCR_CS.
bogdanm 82:6473597d706e 838
bogdanm 82:6473597d706e 839 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 840 //! @brief Read current value of the PORT_DFCR_CS field.
bogdanm 82:6473597d706e 841 #define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
bogdanm 82:6473597d706e 842 #endif
bogdanm 82:6473597d706e 843
bogdanm 82:6473597d706e 844 //! @brief Format value for bitfield PORT_DFCR_CS.
bogdanm 82:6473597d706e 845 #define BF_PORT_DFCR_CS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
bogdanm 82:6473597d706e 846
bogdanm 82:6473597d706e 847 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 848 //! @brief Set the CS field to a new value.
bogdanm 82:6473597d706e 849 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
bogdanm 82:6473597d706e 850 #endif
bogdanm 82:6473597d706e 851 //@}
bogdanm 82:6473597d706e 852
bogdanm 82:6473597d706e 853 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 854 // HW_PORT_DFWR - Digital Filter Width Register
bogdanm 82:6473597d706e 855 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 856
bogdanm 82:6473597d706e 857 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 858 /*!
bogdanm 82:6473597d706e 859 * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
bogdanm 82:6473597d706e 860 *
bogdanm 82:6473597d706e 861 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 862 *
bogdanm 82:6473597d706e 863 * This register is read only for ports that do not support a digital filter.
bogdanm 82:6473597d706e 864 * The digital filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 865 */
bogdanm 82:6473597d706e 866 typedef union _hw_port_dfwr
bogdanm 82:6473597d706e 867 {
bogdanm 82:6473597d706e 868 uint32_t U;
bogdanm 82:6473597d706e 869 struct _hw_port_dfwr_bitfields
bogdanm 82:6473597d706e 870 {
bogdanm 82:6473597d706e 871 uint32_t FILT : 5; //!< [4:0] Filter Length
bogdanm 82:6473597d706e 872 uint32_t RESERVED0 : 27; //!< [31:5]
bogdanm 82:6473597d706e 873 } B;
bogdanm 82:6473597d706e 874 } hw_port_dfwr_t;
bogdanm 82:6473597d706e 875 #endif
bogdanm 82:6473597d706e 876
bogdanm 82:6473597d706e 877 /*!
bogdanm 82:6473597d706e 878 * @name Constants and macros for entire PORT_DFWR register
bogdanm 82:6473597d706e 879 */
bogdanm 82:6473597d706e 880 //@{
bogdanm 82:6473597d706e 881 #define HW_PORT_DFWR_ADDR(x) (REGS_PORT_BASE(x) + 0xC8U)
bogdanm 82:6473597d706e 882
bogdanm 82:6473597d706e 883 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 884 #define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
bogdanm 82:6473597d706e 885 #define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
bogdanm 82:6473597d706e 886 #define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
bogdanm 82:6473597d706e 887 #define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
bogdanm 82:6473597d706e 888 #define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 889 #define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 890 #endif
bogdanm 82:6473597d706e 891 //@}
bogdanm 82:6473597d706e 892
bogdanm 82:6473597d706e 893 /*
bogdanm 82:6473597d706e 894 * Constants & macros for individual PORT_DFWR bitfields
bogdanm 82:6473597d706e 895 */
bogdanm 82:6473597d706e 896
bogdanm 82:6473597d706e 897 /*!
bogdanm 82:6473597d706e 898 * @name Register PORT_DFWR, field FILT[4:0] (RW)
bogdanm 82:6473597d706e 899 *
bogdanm 82:6473597d706e 900 * The digital filter configuration is valid in all digital pin muxing modes.
bogdanm 82:6473597d706e 901 * Configures the maximum size of the glitches, in clock cycles, that the digital
bogdanm 82:6473597d706e 902 * filter absorbs for the enabled digital filters. Glitches that are longer than
bogdanm 82:6473597d706e 903 * this register setting will pass through the digital filter, and glitches that
bogdanm 82:6473597d706e 904 * are equal to or less than this register setting are filtered. Changing the
bogdanm 82:6473597d706e 905 * filter length must be done only after all filters are disabled.
bogdanm 82:6473597d706e 906 */
bogdanm 82:6473597d706e 907 //@{
bogdanm 82:6473597d706e 908 #define BP_PORT_DFWR_FILT (0U) //!< Bit position for PORT_DFWR_FILT.
bogdanm 82:6473597d706e 909 #define BM_PORT_DFWR_FILT (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
bogdanm 82:6473597d706e 910 #define BS_PORT_DFWR_FILT (5U) //!< Bit field size in bits for PORT_DFWR_FILT.
bogdanm 82:6473597d706e 911
bogdanm 82:6473597d706e 912 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 913 //! @brief Read current value of the PORT_DFWR_FILT field.
bogdanm 82:6473597d706e 914 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
bogdanm 82:6473597d706e 915 #endif
bogdanm 82:6473597d706e 916
bogdanm 82:6473597d706e 917 //! @brief Format value for bitfield PORT_DFWR_FILT.
bogdanm 82:6473597d706e 918 #define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
bogdanm 82:6473597d706e 919
bogdanm 82:6473597d706e 920 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 921 //! @brief Set the FILT field to a new value.
bogdanm 82:6473597d706e 922 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
bogdanm 82:6473597d706e 923 #endif
bogdanm 82:6473597d706e 924 //@}
bogdanm 82:6473597d706e 925
bogdanm 82:6473597d706e 926 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 927 // hw_port_t - module struct
bogdanm 82:6473597d706e 928 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 929 /*!
bogdanm 82:6473597d706e 930 * @brief All PORT module registers.
bogdanm 82:6473597d706e 931 */
bogdanm 82:6473597d706e 932 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 933 #pragma pack(1)
bogdanm 82:6473597d706e 934 typedef struct _hw_port
bogdanm 82:6473597d706e 935 {
bogdanm 82:6473597d706e 936 __IO hw_port_pcrn_t PCRn[32]; //!< [0x0] Pin Control Register n
bogdanm 82:6473597d706e 937 __O hw_port_gpclr_t GPCLR; //!< [0x80] Global Pin Control Low Register
bogdanm 82:6473597d706e 938 __O hw_port_gpchr_t GPCHR; //!< [0x84] Global Pin Control High Register
bogdanm 82:6473597d706e 939 uint8_t _reserved0[24];
bogdanm 82:6473597d706e 940 __IO hw_port_isfr_t ISFR; //!< [0xA0] Interrupt Status Flag Register
bogdanm 82:6473597d706e 941 uint8_t _reserved1[28];
bogdanm 82:6473597d706e 942 __IO hw_port_dfer_t DFER; //!< [0xC0] Digital Filter Enable Register
bogdanm 82:6473597d706e 943 __IO hw_port_dfcr_t DFCR; //!< [0xC4] Digital Filter Clock Register
bogdanm 82:6473597d706e 944 __IO hw_port_dfwr_t DFWR; //!< [0xC8] Digital Filter Width Register
bogdanm 82:6473597d706e 945 } hw_port_t;
bogdanm 82:6473597d706e 946 #pragma pack()
bogdanm 82:6473597d706e 947
bogdanm 82:6473597d706e 948 //! @brief Macro to access all PORT registers.
bogdanm 82:6473597d706e 949 //! @param x PORT instance number.
bogdanm 82:6473597d706e 950 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 951 //! use the '&' operator, like <code>&HW_PORT(0)</code>.
bogdanm 82:6473597d706e 952 #define HW_PORT(x) (*(hw_port_t *) REGS_PORT_BASE(x))
bogdanm 82:6473597d706e 953 #endif
bogdanm 82:6473597d706e 954
bogdanm 82:6473597d706e 955 #endif // __HW_PORT_REGISTERS_H__
bogdanm 82:6473597d706e 956 // v22/130726/0.9
bogdanm 82:6473597d706e 957 // EOF