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Dependents:   cc3000_ping_demo_try_2

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dmamux.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_DMAMUX_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_DMAMUX_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 DMAMUX
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * DMA channel multiplexor
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_DMAMUX_CHCFGn - Channel Configuration register
bogdanm 82:6473597d706e 33 *
bogdanm 82:6473597d706e 34 * - hw_dmamux_t - Struct containing all module registers.
bogdanm 82:6473597d706e 35 */
bogdanm 82:6473597d706e 36
bogdanm 82:6473597d706e 37 //! @name Module base addresses
bogdanm 82:6473597d706e 38 //@{
bogdanm 82:6473597d706e 39 #ifndef REGS_DMAMUX_BASE
bogdanm 82:6473597d706e 40 #define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
bogdanm 82:6473597d706e 41 #define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
bogdanm 82:6473597d706e 42 #define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 //! @brief Table of base addresses for DMAMUX instances.
bogdanm 82:6473597d706e 45 static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
bogdanm 82:6473597d706e 46 REGS_DMAMUX0_BASE,
bogdanm 82:6473597d706e 47 };
bogdanm 82:6473597d706e 48
bogdanm 82:6473597d706e 49 //! @brief Get the base address of DMAMUX by instance number.
bogdanm 82:6473597d706e 50 //! @param x DMAMUX instance number, from 0 through 0.
bogdanm 82:6473597d706e 51 #define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
bogdanm 82:6473597d706e 52
bogdanm 82:6473597d706e 53 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 54 //! @param b Base address for an instance of DMAMUX.
bogdanm 82:6473597d706e 55 #define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
bogdanm 82:6473597d706e 56 #endif
bogdanm 82:6473597d706e 57 //@}
bogdanm 82:6473597d706e 58
bogdanm 82:6473597d706e 59 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 60 // HW_DMAMUX_CHCFGn - Channel Configuration register
bogdanm 82:6473597d706e 61 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 62
bogdanm 82:6473597d706e 63 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 64 /*!
bogdanm 82:6473597d706e 65 * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
bogdanm 82:6473597d706e 66 *
bogdanm 82:6473597d706e 67 * Reset value: 0x00U
bogdanm 82:6473597d706e 68 *
bogdanm 82:6473597d706e 69 * Each of the DMA channels can be independently enabled/disabled and associated
bogdanm 82:6473597d706e 70 * with one of the DMA slots (peripheral slots or always-on slots) in the
bogdanm 82:6473597d706e 71 * system. Setting multiple CHCFG registers with the same source value will result in
bogdanm 82:6473597d706e 72 * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
bogdanm 82:6473597d706e 73 * Before changing the trigger or source settings, a DMA channel must be disabled
bogdanm 82:6473597d706e 74 * via CHCFGn[ENBL].
bogdanm 82:6473597d706e 75 */
bogdanm 82:6473597d706e 76 typedef union _hw_dmamux_chcfgn
bogdanm 82:6473597d706e 77 {
bogdanm 82:6473597d706e 78 uint8_t U;
bogdanm 82:6473597d706e 79 struct _hw_dmamux_chcfgn_bitfields
bogdanm 82:6473597d706e 80 {
bogdanm 82:6473597d706e 81 uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
bogdanm 82:6473597d706e 82 uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
bogdanm 82:6473597d706e 83 uint8_t ENBL : 1; //!< [7] DMA Channel Enable
bogdanm 82:6473597d706e 84 } B;
bogdanm 82:6473597d706e 85 } hw_dmamux_chcfgn_t;
bogdanm 82:6473597d706e 86 #endif
bogdanm 82:6473597d706e 87
bogdanm 82:6473597d706e 88 /*!
bogdanm 82:6473597d706e 89 * @name Constants and macros for entire DMAMUX_CHCFGn register
bogdanm 82:6473597d706e 90 */
bogdanm 82:6473597d706e 91 //@{
bogdanm 82:6473597d706e 92 #define HW_DMAMUX_CHCFGn_COUNT (16U)
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 #define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
bogdanm 82:6473597d706e 95
bogdanm 82:6473597d706e 96 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 97 #define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
bogdanm 82:6473597d706e 98 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
bogdanm 82:6473597d706e 99 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
bogdanm 82:6473597d706e 100 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
bogdanm 82:6473597d706e 101 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 102 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 103 #endif
bogdanm 82:6473597d706e 104 //@}
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 /*
bogdanm 82:6473597d706e 107 * Constants & macros for individual DMAMUX_CHCFGn bitfields
bogdanm 82:6473597d706e 108 */
bogdanm 82:6473597d706e 109
bogdanm 82:6473597d706e 110 /*!
bogdanm 82:6473597d706e 111 * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
bogdanm 82:6473597d706e 112 *
bogdanm 82:6473597d706e 113 * Specifies which DMA source, if any, is routed to a particular DMA channel.
bogdanm 82:6473597d706e 114 * See your device's chip configuration details for information about the
bogdanm 82:6473597d706e 115 * peripherals and their slot numbers.
bogdanm 82:6473597d706e 116 */
bogdanm 82:6473597d706e 117 //@{
bogdanm 82:6473597d706e 118 #define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
bogdanm 82:6473597d706e 119 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
bogdanm 82:6473597d706e 120 #define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 123 //! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
bogdanm 82:6473597d706e 124 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
bogdanm 82:6473597d706e 125 #endif
bogdanm 82:6473597d706e 126
bogdanm 82:6473597d706e 127 //! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
bogdanm 82:6473597d706e 128 #define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
bogdanm 82:6473597d706e 129
bogdanm 82:6473597d706e 130 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 131 //! @brief Set the SOURCE field to a new value.
bogdanm 82:6473597d706e 132 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
bogdanm 82:6473597d706e 133 #endif
bogdanm 82:6473597d706e 134 //@}
bogdanm 82:6473597d706e 135
bogdanm 82:6473597d706e 136 /*!
bogdanm 82:6473597d706e 137 * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
bogdanm 82:6473597d706e 138 *
bogdanm 82:6473597d706e 139 * Enables the periodic trigger capability for the triggered DMA channel.
bogdanm 82:6473597d706e 140 *
bogdanm 82:6473597d706e 141 * Values:
bogdanm 82:6473597d706e 142 * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
bogdanm 82:6473597d706e 143 * DMA Channel will simply route the specified source to the DMA channel.
bogdanm 82:6473597d706e 144 * (Normal mode)
bogdanm 82:6473597d706e 145 * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
bogdanm 82:6473597d706e 146 * DMAMUX is in Periodic Trigger mode.
bogdanm 82:6473597d706e 147 */
bogdanm 82:6473597d706e 148 //@{
bogdanm 82:6473597d706e 149 #define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
bogdanm 82:6473597d706e 150 #define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
bogdanm 82:6473597d706e 151 #define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
bogdanm 82:6473597d706e 152
bogdanm 82:6473597d706e 153 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 154 //! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
bogdanm 82:6473597d706e 155 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
bogdanm 82:6473597d706e 156 #endif
bogdanm 82:6473597d706e 157
bogdanm 82:6473597d706e 158 //! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
bogdanm 82:6473597d706e 159 #define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
bogdanm 82:6473597d706e 160
bogdanm 82:6473597d706e 161 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 162 //! @brief Set the TRIG field to a new value.
bogdanm 82:6473597d706e 163 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
bogdanm 82:6473597d706e 164 #endif
bogdanm 82:6473597d706e 165 //@}
bogdanm 82:6473597d706e 166
bogdanm 82:6473597d706e 167 /*!
bogdanm 82:6473597d706e 168 * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
bogdanm 82:6473597d706e 169 *
bogdanm 82:6473597d706e 170 * Enables the DMA channel.
bogdanm 82:6473597d706e 171 *
bogdanm 82:6473597d706e 172 * Values:
bogdanm 82:6473597d706e 173 * - 0 - DMA channel is disabled. This mode is primarily used during
bogdanm 82:6473597d706e 174 * configuration of the DMAMux. The DMA has separate channel enables/disables, which
bogdanm 82:6473597d706e 175 * should be used to disable or reconfigure a DMA channel.
bogdanm 82:6473597d706e 176 * - 1 - DMA channel is enabled
bogdanm 82:6473597d706e 177 */
bogdanm 82:6473597d706e 178 //@{
bogdanm 82:6473597d706e 179 #define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
bogdanm 82:6473597d706e 180 #define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
bogdanm 82:6473597d706e 181 #define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
bogdanm 82:6473597d706e 182
bogdanm 82:6473597d706e 183 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 184 //! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
bogdanm 82:6473597d706e 185 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
bogdanm 82:6473597d706e 186 #endif
bogdanm 82:6473597d706e 187
bogdanm 82:6473597d706e 188 //! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
bogdanm 82:6473597d706e 189 #define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
bogdanm 82:6473597d706e 190
bogdanm 82:6473597d706e 191 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 192 //! @brief Set the ENBL field to a new value.
bogdanm 82:6473597d706e 193 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
bogdanm 82:6473597d706e 194 #endif
bogdanm 82:6473597d706e 195 //@}
bogdanm 82:6473597d706e 196
bogdanm 82:6473597d706e 197 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 198 // hw_dmamux_t - module struct
bogdanm 82:6473597d706e 199 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 200 /*!
bogdanm 82:6473597d706e 201 * @brief All DMAMUX module registers.
bogdanm 82:6473597d706e 202 */
bogdanm 82:6473597d706e 203 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 204 #pragma pack(1)
bogdanm 82:6473597d706e 205 typedef struct _hw_dmamux
bogdanm 82:6473597d706e 206 {
bogdanm 82:6473597d706e 207 __IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
bogdanm 82:6473597d706e 208 } hw_dmamux_t;
bogdanm 82:6473597d706e 209 #pragma pack()
bogdanm 82:6473597d706e 210
bogdanm 82:6473597d706e 211 //! @brief Macro to access all DMAMUX registers.
bogdanm 82:6473597d706e 212 //! @param x DMAMUX instance number.
bogdanm 82:6473597d706e 213 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 214 //! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
bogdanm 82:6473597d706e 215 #define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
bogdanm 82:6473597d706e 216 #endif
bogdanm 82:6473597d706e 217
bogdanm 82:6473597d706e 218 #endif // __HW_DMAMUX_REGISTERS_H__
bogdanm 82:6473597d706e 219 // v22/130726/0.9
bogdanm 82:6473597d706e 220 // EOF