erez i / mbed

version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dac.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_DAC_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_DAC_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 DAC
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * 12-Bit Digital-to-Analog Converter
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_DAC_DATnL - DAC Data Low Register
bogdanm 82:6473597d706e 33 * - HW_DAC_DATnH - DAC Data High Register
bogdanm 82:6473597d706e 34 * - HW_DAC_SR - DAC Status Register
bogdanm 82:6473597d706e 35 * - HW_DAC_C0 - DAC Control Register
bogdanm 82:6473597d706e 36 * - HW_DAC_C1 - DAC Control Register 1
bogdanm 82:6473597d706e 37 * - HW_DAC_C2 - DAC Control Register 2
bogdanm 82:6473597d706e 38 *
bogdanm 82:6473597d706e 39 * - hw_dac_t - Struct containing all module registers.
bogdanm 82:6473597d706e 40 */
bogdanm 82:6473597d706e 41
bogdanm 82:6473597d706e 42 //! @name Module base addresses
bogdanm 82:6473597d706e 43 //@{
bogdanm 82:6473597d706e 44 #ifndef REGS_DAC_BASE
bogdanm 82:6473597d706e 45 #define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
bogdanm 82:6473597d706e 46 #define HW_DAC0 (0U) //!< Instance number for DAC0.
bogdanm 82:6473597d706e 47 #define HW_DAC1 (1U) //!< Instance number for DAC1.
bogdanm 82:6473597d706e 48 #define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
bogdanm 82:6473597d706e 49 #define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
bogdanm 82:6473597d706e 50
bogdanm 82:6473597d706e 51 //! @brief Table of base addresses for DAC instances.
bogdanm 82:6473597d706e 52 static const uint32_t __g_regs_DAC_base_addresses[] = {
bogdanm 82:6473597d706e 53 REGS_DAC0_BASE,
bogdanm 82:6473597d706e 54 REGS_DAC1_BASE,
bogdanm 82:6473597d706e 55 };
bogdanm 82:6473597d706e 56
bogdanm 82:6473597d706e 57 //! @brief Get the base address of DAC by instance number.
bogdanm 82:6473597d706e 58 //! @param x DAC instance number, from 0 through 1.
bogdanm 82:6473597d706e 59 #define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
bogdanm 82:6473597d706e 60
bogdanm 82:6473597d706e 61 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 62 //! @param b Base address for an instance of DAC.
bogdanm 82:6473597d706e 63 #define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
bogdanm 82:6473597d706e 64 #endif
bogdanm 82:6473597d706e 65 //@}
bogdanm 82:6473597d706e 66
bogdanm 82:6473597d706e 67 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 68 // HW_DAC_DATnL - DAC Data Low Register
bogdanm 82:6473597d706e 69 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 70
bogdanm 82:6473597d706e 71 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 72 /*!
bogdanm 82:6473597d706e 73 * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
bogdanm 82:6473597d706e 74 *
bogdanm 82:6473597d706e 75 * Reset value: 0x00U
bogdanm 82:6473597d706e 76 */
bogdanm 82:6473597d706e 77 typedef union _hw_dac_datnl
bogdanm 82:6473597d706e 78 {
bogdanm 82:6473597d706e 79 uint8_t U;
bogdanm 82:6473597d706e 80 struct _hw_dac_datnl_bitfields
bogdanm 82:6473597d706e 81 {
bogdanm 82:6473597d706e 82 uint8_t DATA0 : 8; //!< [7:0]
bogdanm 82:6473597d706e 83 } B;
bogdanm 82:6473597d706e 84 } hw_dac_datnl_t;
bogdanm 82:6473597d706e 85 #endif
bogdanm 82:6473597d706e 86
bogdanm 82:6473597d706e 87 /*!
bogdanm 82:6473597d706e 88 * @name Constants and macros for entire DAC_DATnL register
bogdanm 82:6473597d706e 89 */
bogdanm 82:6473597d706e 90 //@{
bogdanm 82:6473597d706e 91 #define HW_DAC_DATnL_COUNT (16U)
bogdanm 82:6473597d706e 92
bogdanm 82:6473597d706e 93 #define HW_DAC_DATnL_ADDR(x, n) (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
bogdanm 82:6473597d706e 94
bogdanm 82:6473597d706e 95 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 96 #define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
bogdanm 82:6473597d706e 97 #define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
bogdanm 82:6473597d706e 98 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
bogdanm 82:6473597d706e 99 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
bogdanm 82:6473597d706e 100 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 101 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 102 #endif
bogdanm 82:6473597d706e 103 //@}
bogdanm 82:6473597d706e 104
bogdanm 82:6473597d706e 105 /*
bogdanm 82:6473597d706e 106 * Constants & macros for individual DAC_DATnL bitfields
bogdanm 82:6473597d706e 107 */
bogdanm 82:6473597d706e 108
bogdanm 82:6473597d706e 109 /*!
bogdanm 82:6473597d706e 110 * @name Register DAC_DATnL, field DATA0[7:0] (RW)
bogdanm 82:6473597d706e 111 *
bogdanm 82:6473597d706e 112 * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
bogdanm 82:6473597d706e 113 * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
bogdanm 82:6473597d706e 114 * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
bogdanm 82:6473597d706e 115 */
bogdanm 82:6473597d706e 116 //@{
bogdanm 82:6473597d706e 117 #define BP_DAC_DATnL_DATA0 (0U) //!< Bit position for DAC_DATnL_DATA0.
bogdanm 82:6473597d706e 118 #define BM_DAC_DATnL_DATA0 (0xFFU) //!< Bit mask for DAC_DATnL_DATA0.
bogdanm 82:6473597d706e 119 #define BS_DAC_DATnL_DATA0 (8U) //!< Bit field size in bits for DAC_DATnL_DATA0.
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 122 //! @brief Read current value of the DAC_DATnL_DATA0 field.
bogdanm 82:6473597d706e 123 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
bogdanm 82:6473597d706e 124 #endif
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 //! @brief Format value for bitfield DAC_DATnL_DATA0.
bogdanm 82:6473597d706e 127 #define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
bogdanm 82:6473597d706e 128
bogdanm 82:6473597d706e 129 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 130 //! @brief Set the DATA0 field to a new value.
bogdanm 82:6473597d706e 131 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
bogdanm 82:6473597d706e 132 #endif
bogdanm 82:6473597d706e 133 //@}
bogdanm 82:6473597d706e 134 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 135 // HW_DAC_DATnH - DAC Data High Register
bogdanm 82:6473597d706e 136 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 137
bogdanm 82:6473597d706e 138 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 139 /*!
bogdanm 82:6473597d706e 140 * @brief HW_DAC_DATnH - DAC Data High Register (RW)
bogdanm 82:6473597d706e 141 *
bogdanm 82:6473597d706e 142 * Reset value: 0x00U
bogdanm 82:6473597d706e 143 */
bogdanm 82:6473597d706e 144 typedef union _hw_dac_datnh
bogdanm 82:6473597d706e 145 {
bogdanm 82:6473597d706e 146 uint8_t U;
bogdanm 82:6473597d706e 147 struct _hw_dac_datnh_bitfields
bogdanm 82:6473597d706e 148 {
bogdanm 82:6473597d706e 149 uint8_t DATA1 : 4; //!< [3:0]
bogdanm 82:6473597d706e 150 uint8_t RESERVED0 : 4; //!< [7:4]
bogdanm 82:6473597d706e 151 } B;
bogdanm 82:6473597d706e 152 } hw_dac_datnh_t;
bogdanm 82:6473597d706e 153 #endif
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 /*!
bogdanm 82:6473597d706e 156 * @name Constants and macros for entire DAC_DATnH register
bogdanm 82:6473597d706e 157 */
bogdanm 82:6473597d706e 158 //@{
bogdanm 82:6473597d706e 159 #define HW_DAC_DATnH_COUNT (16U)
bogdanm 82:6473597d706e 160
bogdanm 82:6473597d706e 161 #define HW_DAC_DATnH_ADDR(x, n) (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
bogdanm 82:6473597d706e 162
bogdanm 82:6473597d706e 163 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 164 #define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
bogdanm 82:6473597d706e 165 #define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
bogdanm 82:6473597d706e 166 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
bogdanm 82:6473597d706e 167 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
bogdanm 82:6473597d706e 168 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 169 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 170 #endif
bogdanm 82:6473597d706e 171 //@}
bogdanm 82:6473597d706e 172
bogdanm 82:6473597d706e 173 /*
bogdanm 82:6473597d706e 174 * Constants & macros for individual DAC_DATnH bitfields
bogdanm 82:6473597d706e 175 */
bogdanm 82:6473597d706e 176
bogdanm 82:6473597d706e 177 /*!
bogdanm 82:6473597d706e 178 * @name Register DAC_DATnH, field DATA1[3:0] (RW)
bogdanm 82:6473597d706e 179 *
bogdanm 82:6473597d706e 180 * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
bogdanm 82:6473597d706e 181 * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
bogdanm 82:6473597d706e 182 * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
bogdanm 82:6473597d706e 183 */
bogdanm 82:6473597d706e 184 //@{
bogdanm 82:6473597d706e 185 #define BP_DAC_DATnH_DATA1 (0U) //!< Bit position for DAC_DATnH_DATA1.
bogdanm 82:6473597d706e 186 #define BM_DAC_DATnH_DATA1 (0x0FU) //!< Bit mask for DAC_DATnH_DATA1.
bogdanm 82:6473597d706e 187 #define BS_DAC_DATnH_DATA1 (4U) //!< Bit field size in bits for DAC_DATnH_DATA1.
bogdanm 82:6473597d706e 188
bogdanm 82:6473597d706e 189 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 190 //! @brief Read current value of the DAC_DATnH_DATA1 field.
bogdanm 82:6473597d706e 191 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
bogdanm 82:6473597d706e 192 #endif
bogdanm 82:6473597d706e 193
bogdanm 82:6473597d706e 194 //! @brief Format value for bitfield DAC_DATnH_DATA1.
bogdanm 82:6473597d706e 195 #define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
bogdanm 82:6473597d706e 196
bogdanm 82:6473597d706e 197 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 198 //! @brief Set the DATA1 field to a new value.
bogdanm 82:6473597d706e 199 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
bogdanm 82:6473597d706e 200 #endif
bogdanm 82:6473597d706e 201 //@}
bogdanm 82:6473597d706e 202
bogdanm 82:6473597d706e 203 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 204 // HW_DAC_SR - DAC Status Register
bogdanm 82:6473597d706e 205 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 206
bogdanm 82:6473597d706e 207 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 208 /*!
bogdanm 82:6473597d706e 209 * @brief HW_DAC_SR - DAC Status Register (RW)
bogdanm 82:6473597d706e 210 *
bogdanm 82:6473597d706e 211 * Reset value: 0x02U
bogdanm 82:6473597d706e 212 *
bogdanm 82:6473597d706e 213 * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
bogdanm 82:6473597d706e 214 * request is done. Writing 0 to a field clears it whereas writing 1 has no
bogdanm 82:6473597d706e 215 * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
bogdanm 82:6473597d706e 216 * The flags are set only when the data buffer status is changed. Do not use
bogdanm 82:6473597d706e 217 * 32/16-bit accesses to this register.
bogdanm 82:6473597d706e 218 */
bogdanm 82:6473597d706e 219 typedef union _hw_dac_sr
bogdanm 82:6473597d706e 220 {
bogdanm 82:6473597d706e 221 uint8_t U;
bogdanm 82:6473597d706e 222 struct _hw_dac_sr_bitfields
bogdanm 82:6473597d706e 223 {
bogdanm 82:6473597d706e 224 uint8_t DACBFRPBF : 1; //!< [0] DAC Buffer Read Pointer Bottom
bogdanm 82:6473597d706e 225 //! Position Flag
bogdanm 82:6473597d706e 226 uint8_t DACBFRPTF : 1; //!< [1] DAC Buffer Read Pointer Top Position
bogdanm 82:6473597d706e 227 //! Flag
bogdanm 82:6473597d706e 228 uint8_t DACBFWMF : 1; //!< [2] DAC Buffer Watermark Flag
bogdanm 82:6473597d706e 229 uint8_t RESERVED0 : 5; //!< [7:3]
bogdanm 82:6473597d706e 230 } B;
bogdanm 82:6473597d706e 231 } hw_dac_sr_t;
bogdanm 82:6473597d706e 232 #endif
bogdanm 82:6473597d706e 233
bogdanm 82:6473597d706e 234 /*!
bogdanm 82:6473597d706e 235 * @name Constants and macros for entire DAC_SR register
bogdanm 82:6473597d706e 236 */
bogdanm 82:6473597d706e 237 //@{
bogdanm 82:6473597d706e 238 #define HW_DAC_SR_ADDR(x) (REGS_DAC_BASE(x) + 0x20U)
bogdanm 82:6473597d706e 239
bogdanm 82:6473597d706e 240 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 241 #define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
bogdanm 82:6473597d706e 242 #define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
bogdanm 82:6473597d706e 243 #define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
bogdanm 82:6473597d706e 244 #define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
bogdanm 82:6473597d706e 245 #define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 246 #define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 247 #endif
bogdanm 82:6473597d706e 248 //@}
bogdanm 82:6473597d706e 249
bogdanm 82:6473597d706e 250 /*
bogdanm 82:6473597d706e 251 * Constants & macros for individual DAC_SR bitfields
bogdanm 82:6473597d706e 252 */
bogdanm 82:6473597d706e 253
bogdanm 82:6473597d706e 254 /*!
bogdanm 82:6473597d706e 255 * @name Register DAC_SR, field DACBFRPBF[0] (RW)
bogdanm 82:6473597d706e 256 *
bogdanm 82:6473597d706e 257 * Values:
bogdanm 82:6473597d706e 258 * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
bogdanm 82:6473597d706e 259 * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
bogdanm 82:6473597d706e 260 */
bogdanm 82:6473597d706e 261 //@{
bogdanm 82:6473597d706e 262 #define BP_DAC_SR_DACBFRPBF (0U) //!< Bit position for DAC_SR_DACBFRPBF.
bogdanm 82:6473597d706e 263 #define BM_DAC_SR_DACBFRPBF (0x01U) //!< Bit mask for DAC_SR_DACBFRPBF.
bogdanm 82:6473597d706e 264 #define BS_DAC_SR_DACBFRPBF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPBF.
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 267 //! @brief Read current value of the DAC_SR_DACBFRPBF field.
bogdanm 82:6473597d706e 268 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
bogdanm 82:6473597d706e 269 #endif
bogdanm 82:6473597d706e 270
bogdanm 82:6473597d706e 271 //! @brief Format value for bitfield DAC_SR_DACBFRPBF.
bogdanm 82:6473597d706e 272 #define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
bogdanm 82:6473597d706e 273
bogdanm 82:6473597d706e 274 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 275 //! @brief Set the DACBFRPBF field to a new value.
bogdanm 82:6473597d706e 276 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
bogdanm 82:6473597d706e 277 #endif
bogdanm 82:6473597d706e 278 //@}
bogdanm 82:6473597d706e 279
bogdanm 82:6473597d706e 280 /*!
bogdanm 82:6473597d706e 281 * @name Register DAC_SR, field DACBFRPTF[1] (RW)
bogdanm 82:6473597d706e 282 *
bogdanm 82:6473597d706e 283 * Values:
bogdanm 82:6473597d706e 284 * - 0 - The DAC buffer read pointer is not zero.
bogdanm 82:6473597d706e 285 * - 1 - The DAC buffer read pointer is zero.
bogdanm 82:6473597d706e 286 */
bogdanm 82:6473597d706e 287 //@{
bogdanm 82:6473597d706e 288 #define BP_DAC_SR_DACBFRPTF (1U) //!< Bit position for DAC_SR_DACBFRPTF.
bogdanm 82:6473597d706e 289 #define BM_DAC_SR_DACBFRPTF (0x02U) //!< Bit mask for DAC_SR_DACBFRPTF.
bogdanm 82:6473597d706e 290 #define BS_DAC_SR_DACBFRPTF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPTF.
bogdanm 82:6473597d706e 291
bogdanm 82:6473597d706e 292 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 293 //! @brief Read current value of the DAC_SR_DACBFRPTF field.
bogdanm 82:6473597d706e 294 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
bogdanm 82:6473597d706e 295 #endif
bogdanm 82:6473597d706e 296
bogdanm 82:6473597d706e 297 //! @brief Format value for bitfield DAC_SR_DACBFRPTF.
bogdanm 82:6473597d706e 298 #define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
bogdanm 82:6473597d706e 299
bogdanm 82:6473597d706e 300 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 301 //! @brief Set the DACBFRPTF field to a new value.
bogdanm 82:6473597d706e 302 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
bogdanm 82:6473597d706e 303 #endif
bogdanm 82:6473597d706e 304 //@}
bogdanm 82:6473597d706e 305
bogdanm 82:6473597d706e 306 /*!
bogdanm 82:6473597d706e 307 * @name Register DAC_SR, field DACBFWMF[2] (RW)
bogdanm 82:6473597d706e 308 *
bogdanm 82:6473597d706e 309 * Values:
bogdanm 82:6473597d706e 310 * - 0 - The DAC buffer read pointer has not reached the watermark level.
bogdanm 82:6473597d706e 311 * - 1 - The DAC buffer read pointer has reached the watermark level.
bogdanm 82:6473597d706e 312 */
bogdanm 82:6473597d706e 313 //@{
bogdanm 82:6473597d706e 314 #define BP_DAC_SR_DACBFWMF (2U) //!< Bit position for DAC_SR_DACBFWMF.
bogdanm 82:6473597d706e 315 #define BM_DAC_SR_DACBFWMF (0x04U) //!< Bit mask for DAC_SR_DACBFWMF.
bogdanm 82:6473597d706e 316 #define BS_DAC_SR_DACBFWMF (1U) //!< Bit field size in bits for DAC_SR_DACBFWMF.
bogdanm 82:6473597d706e 317
bogdanm 82:6473597d706e 318 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 319 //! @brief Read current value of the DAC_SR_DACBFWMF field.
bogdanm 82:6473597d706e 320 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
bogdanm 82:6473597d706e 321 #endif
bogdanm 82:6473597d706e 322
bogdanm 82:6473597d706e 323 //! @brief Format value for bitfield DAC_SR_DACBFWMF.
bogdanm 82:6473597d706e 324 #define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
bogdanm 82:6473597d706e 325
bogdanm 82:6473597d706e 326 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 327 //! @brief Set the DACBFWMF field to a new value.
bogdanm 82:6473597d706e 328 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
bogdanm 82:6473597d706e 329 #endif
bogdanm 82:6473597d706e 330 //@}
bogdanm 82:6473597d706e 331
bogdanm 82:6473597d706e 332 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 333 // HW_DAC_C0 - DAC Control Register
bogdanm 82:6473597d706e 334 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 335
bogdanm 82:6473597d706e 336 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 337 /*!
bogdanm 82:6473597d706e 338 * @brief HW_DAC_C0 - DAC Control Register (RW)
bogdanm 82:6473597d706e 339 *
bogdanm 82:6473597d706e 340 * Reset value: 0x00U
bogdanm 82:6473597d706e 341 *
bogdanm 82:6473597d706e 342 * Do not use 32- or 16-bit accesses to this register.
bogdanm 82:6473597d706e 343 */
bogdanm 82:6473597d706e 344 typedef union _hw_dac_c0
bogdanm 82:6473597d706e 345 {
bogdanm 82:6473597d706e 346 uint8_t U;
bogdanm 82:6473597d706e 347 struct _hw_dac_c0_bitfields
bogdanm 82:6473597d706e 348 {
bogdanm 82:6473597d706e 349 uint8_t DACBBIEN : 1; //!< [0] DAC Buffer Read Pointer Bottom Flag
bogdanm 82:6473597d706e 350 //! Interrupt Enable
bogdanm 82:6473597d706e 351 uint8_t DACBTIEN : 1; //!< [1] DAC Buffer Read Pointer Top Flag
bogdanm 82:6473597d706e 352 //! Interrupt Enable
bogdanm 82:6473597d706e 353 uint8_t DACBWIEN : 1; //!< [2] DAC Buffer Watermark Interrupt Enable
bogdanm 82:6473597d706e 354 uint8_t LPEN : 1; //!< [3] DAC Low Power Control
bogdanm 82:6473597d706e 355 uint8_t DACSWTRG : 1; //!< [4] DAC Software Trigger
bogdanm 82:6473597d706e 356 uint8_t DACTRGSEL : 1; //!< [5] DAC Trigger Select
bogdanm 82:6473597d706e 357 uint8_t DACRFS : 1; //!< [6] DAC Reference Select
bogdanm 82:6473597d706e 358 uint8_t DACEN : 1; //!< [7] DAC Enable
bogdanm 82:6473597d706e 359 } B;
bogdanm 82:6473597d706e 360 } hw_dac_c0_t;
bogdanm 82:6473597d706e 361 #endif
bogdanm 82:6473597d706e 362
bogdanm 82:6473597d706e 363 /*!
bogdanm 82:6473597d706e 364 * @name Constants and macros for entire DAC_C0 register
bogdanm 82:6473597d706e 365 */
bogdanm 82:6473597d706e 366 //@{
bogdanm 82:6473597d706e 367 #define HW_DAC_C0_ADDR(x) (REGS_DAC_BASE(x) + 0x21U)
bogdanm 82:6473597d706e 368
bogdanm 82:6473597d706e 369 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 370 #define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
bogdanm 82:6473597d706e 371 #define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
bogdanm 82:6473597d706e 372 #define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
bogdanm 82:6473597d706e 373 #define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
bogdanm 82:6473597d706e 374 #define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
bogdanm 82:6473597d706e 375 #define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
bogdanm 82:6473597d706e 376 #endif
bogdanm 82:6473597d706e 377 //@}
bogdanm 82:6473597d706e 378
bogdanm 82:6473597d706e 379 /*
bogdanm 82:6473597d706e 380 * Constants & macros for individual DAC_C0 bitfields
bogdanm 82:6473597d706e 381 */
bogdanm 82:6473597d706e 382
bogdanm 82:6473597d706e 383 /*!
bogdanm 82:6473597d706e 384 * @name Register DAC_C0, field DACBBIEN[0] (RW)
bogdanm 82:6473597d706e 385 *
bogdanm 82:6473597d706e 386 * Values:
bogdanm 82:6473597d706e 387 * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
bogdanm 82:6473597d706e 388 * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
bogdanm 82:6473597d706e 389 */
bogdanm 82:6473597d706e 390 //@{
bogdanm 82:6473597d706e 391 #define BP_DAC_C0_DACBBIEN (0U) //!< Bit position for DAC_C0_DACBBIEN.
bogdanm 82:6473597d706e 392 #define BM_DAC_C0_DACBBIEN (0x01U) //!< Bit mask for DAC_C0_DACBBIEN.
bogdanm 82:6473597d706e 393 #define BS_DAC_C0_DACBBIEN (1U) //!< Bit field size in bits for DAC_C0_DACBBIEN.
bogdanm 82:6473597d706e 394
bogdanm 82:6473597d706e 395 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 396 //! @brief Read current value of the DAC_C0_DACBBIEN field.
bogdanm 82:6473597d706e 397 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
bogdanm 82:6473597d706e 398 #endif
bogdanm 82:6473597d706e 399
bogdanm 82:6473597d706e 400 //! @brief Format value for bitfield DAC_C0_DACBBIEN.
bogdanm 82:6473597d706e 401 #define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 404 //! @brief Set the DACBBIEN field to a new value.
bogdanm 82:6473597d706e 405 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
bogdanm 82:6473597d706e 406 #endif
bogdanm 82:6473597d706e 407 //@}
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 /*!
bogdanm 82:6473597d706e 410 * @name Register DAC_C0, field DACBTIEN[1] (RW)
bogdanm 82:6473597d706e 411 *
bogdanm 82:6473597d706e 412 * Values:
bogdanm 82:6473597d706e 413 * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
bogdanm 82:6473597d706e 414 * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
bogdanm 82:6473597d706e 415 */
bogdanm 82:6473597d706e 416 //@{
bogdanm 82:6473597d706e 417 #define BP_DAC_C0_DACBTIEN (1U) //!< Bit position for DAC_C0_DACBTIEN.
bogdanm 82:6473597d706e 418 #define BM_DAC_C0_DACBTIEN (0x02U) //!< Bit mask for DAC_C0_DACBTIEN.
bogdanm 82:6473597d706e 419 #define BS_DAC_C0_DACBTIEN (1U) //!< Bit field size in bits for DAC_C0_DACBTIEN.
bogdanm 82:6473597d706e 420
bogdanm 82:6473597d706e 421 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 422 //! @brief Read current value of the DAC_C0_DACBTIEN field.
bogdanm 82:6473597d706e 423 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
bogdanm 82:6473597d706e 424 #endif
bogdanm 82:6473597d706e 425
bogdanm 82:6473597d706e 426 //! @brief Format value for bitfield DAC_C0_DACBTIEN.
bogdanm 82:6473597d706e 427 #define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
bogdanm 82:6473597d706e 428
bogdanm 82:6473597d706e 429 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 430 //! @brief Set the DACBTIEN field to a new value.
bogdanm 82:6473597d706e 431 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
bogdanm 82:6473597d706e 432 #endif
bogdanm 82:6473597d706e 433 //@}
bogdanm 82:6473597d706e 434
bogdanm 82:6473597d706e 435 /*!
bogdanm 82:6473597d706e 436 * @name Register DAC_C0, field DACBWIEN[2] (RW)
bogdanm 82:6473597d706e 437 *
bogdanm 82:6473597d706e 438 * Values:
bogdanm 82:6473597d706e 439 * - 0 - The DAC buffer watermark interrupt is disabled.
bogdanm 82:6473597d706e 440 * - 1 - The DAC buffer watermark interrupt is enabled.
bogdanm 82:6473597d706e 441 */
bogdanm 82:6473597d706e 442 //@{
bogdanm 82:6473597d706e 443 #define BP_DAC_C0_DACBWIEN (2U) //!< Bit position for DAC_C0_DACBWIEN.
bogdanm 82:6473597d706e 444 #define BM_DAC_C0_DACBWIEN (0x04U) //!< Bit mask for DAC_C0_DACBWIEN.
bogdanm 82:6473597d706e 445 #define BS_DAC_C0_DACBWIEN (1U) //!< Bit field size in bits for DAC_C0_DACBWIEN.
bogdanm 82:6473597d706e 446
bogdanm 82:6473597d706e 447 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 448 //! @brief Read current value of the DAC_C0_DACBWIEN field.
bogdanm 82:6473597d706e 449 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
bogdanm 82:6473597d706e 450 #endif
bogdanm 82:6473597d706e 451
bogdanm 82:6473597d706e 452 //! @brief Format value for bitfield DAC_C0_DACBWIEN.
bogdanm 82:6473597d706e 453 #define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
bogdanm 82:6473597d706e 454
bogdanm 82:6473597d706e 455 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 456 //! @brief Set the DACBWIEN field to a new value.
bogdanm 82:6473597d706e 457 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
bogdanm 82:6473597d706e 458 #endif
bogdanm 82:6473597d706e 459 //@}
bogdanm 82:6473597d706e 460
bogdanm 82:6473597d706e 461 /*!
bogdanm 82:6473597d706e 462 * @name Register DAC_C0, field LPEN[3] (RW)
bogdanm 82:6473597d706e 463 *
bogdanm 82:6473597d706e 464 * See the 12-bit DAC electrical characteristics of the device data sheet for
bogdanm 82:6473597d706e 465 * details on the impact of the modes below.
bogdanm 82:6473597d706e 466 *
bogdanm 82:6473597d706e 467 * Values:
bogdanm 82:6473597d706e 468 * - 0 - High-Power mode
bogdanm 82:6473597d706e 469 * - 1 - Low-Power mode
bogdanm 82:6473597d706e 470 */
bogdanm 82:6473597d706e 471 //@{
bogdanm 82:6473597d706e 472 #define BP_DAC_C0_LPEN (3U) //!< Bit position for DAC_C0_LPEN.
bogdanm 82:6473597d706e 473 #define BM_DAC_C0_LPEN (0x08U) //!< Bit mask for DAC_C0_LPEN.
bogdanm 82:6473597d706e 474 #define BS_DAC_C0_LPEN (1U) //!< Bit field size in bits for DAC_C0_LPEN.
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 477 //! @brief Read current value of the DAC_C0_LPEN field.
bogdanm 82:6473597d706e 478 #define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
bogdanm 82:6473597d706e 479 #endif
bogdanm 82:6473597d706e 480
bogdanm 82:6473597d706e 481 //! @brief Format value for bitfield DAC_C0_LPEN.
bogdanm 82:6473597d706e 482 #define BF_DAC_C0_LPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
bogdanm 82:6473597d706e 483
bogdanm 82:6473597d706e 484 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 485 //! @brief Set the LPEN field to a new value.
bogdanm 82:6473597d706e 486 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
bogdanm 82:6473597d706e 487 #endif
bogdanm 82:6473597d706e 488 //@}
bogdanm 82:6473597d706e 489
bogdanm 82:6473597d706e 490 /*!
bogdanm 82:6473597d706e 491 * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
bogdanm 82:6473597d706e 492 *
bogdanm 82:6473597d706e 493 * Active high. This is a write-only field, which always reads 0. If DAC
bogdanm 82:6473597d706e 494 * software trigger is selected and buffer is enabled, writing 1 to this field will
bogdanm 82:6473597d706e 495 * advance the buffer read pointer once.
bogdanm 82:6473597d706e 496 *
bogdanm 82:6473597d706e 497 * Values:
bogdanm 82:6473597d706e 498 * - 0 - The DAC soft trigger is not valid.
bogdanm 82:6473597d706e 499 * - 1 - The DAC soft trigger is valid.
bogdanm 82:6473597d706e 500 */
bogdanm 82:6473597d706e 501 //@{
bogdanm 82:6473597d706e 502 #define BP_DAC_C0_DACSWTRG (4U) //!< Bit position for DAC_C0_DACSWTRG.
bogdanm 82:6473597d706e 503 #define BM_DAC_C0_DACSWTRG (0x10U) //!< Bit mask for DAC_C0_DACSWTRG.
bogdanm 82:6473597d706e 504 #define BS_DAC_C0_DACSWTRG (1U) //!< Bit field size in bits for DAC_C0_DACSWTRG.
bogdanm 82:6473597d706e 505
bogdanm 82:6473597d706e 506 //! @brief Format value for bitfield DAC_C0_DACSWTRG.
bogdanm 82:6473597d706e 507 #define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 510 //! @brief Set the DACSWTRG field to a new value.
bogdanm 82:6473597d706e 511 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
bogdanm 82:6473597d706e 512 #endif
bogdanm 82:6473597d706e 513 //@}
bogdanm 82:6473597d706e 514
bogdanm 82:6473597d706e 515 /*!
bogdanm 82:6473597d706e 516 * @name Register DAC_C0, field DACTRGSEL[5] (RW)
bogdanm 82:6473597d706e 517 *
bogdanm 82:6473597d706e 518 * Values:
bogdanm 82:6473597d706e 519 * - 0 - The DAC hardware trigger is selected.
bogdanm 82:6473597d706e 520 * - 1 - The DAC software trigger is selected.
bogdanm 82:6473597d706e 521 */
bogdanm 82:6473597d706e 522 //@{
bogdanm 82:6473597d706e 523 #define BP_DAC_C0_DACTRGSEL (5U) //!< Bit position for DAC_C0_DACTRGSEL.
bogdanm 82:6473597d706e 524 #define BM_DAC_C0_DACTRGSEL (0x20U) //!< Bit mask for DAC_C0_DACTRGSEL.
bogdanm 82:6473597d706e 525 #define BS_DAC_C0_DACTRGSEL (1U) //!< Bit field size in bits for DAC_C0_DACTRGSEL.
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Read current value of the DAC_C0_DACTRGSEL field.
bogdanm 82:6473597d706e 529 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 //! @brief Format value for bitfield DAC_C0_DACTRGSEL.
bogdanm 82:6473597d706e 533 #define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
bogdanm 82:6473597d706e 534
bogdanm 82:6473597d706e 535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 536 //! @brief Set the DACTRGSEL field to a new value.
bogdanm 82:6473597d706e 537 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
bogdanm 82:6473597d706e 538 #endif
bogdanm 82:6473597d706e 539 //@}
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 /*!
bogdanm 82:6473597d706e 542 * @name Register DAC_C0, field DACRFS[6] (RW)
bogdanm 82:6473597d706e 543 *
bogdanm 82:6473597d706e 544 * Values:
bogdanm 82:6473597d706e 545 * - 0 - The DAC selects DACREF_1 as the reference voltage.
bogdanm 82:6473597d706e 546 * - 1 - The DAC selects DACREF_2 as the reference voltage.
bogdanm 82:6473597d706e 547 */
bogdanm 82:6473597d706e 548 //@{
bogdanm 82:6473597d706e 549 #define BP_DAC_C0_DACRFS (6U) //!< Bit position for DAC_C0_DACRFS.
bogdanm 82:6473597d706e 550 #define BM_DAC_C0_DACRFS (0x40U) //!< Bit mask for DAC_C0_DACRFS.
bogdanm 82:6473597d706e 551 #define BS_DAC_C0_DACRFS (1U) //!< Bit field size in bits for DAC_C0_DACRFS.
bogdanm 82:6473597d706e 552
bogdanm 82:6473597d706e 553 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 554 //! @brief Read current value of the DAC_C0_DACRFS field.
bogdanm 82:6473597d706e 555 #define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
bogdanm 82:6473597d706e 556 #endif
bogdanm 82:6473597d706e 557
bogdanm 82:6473597d706e 558 //! @brief Format value for bitfield DAC_C0_DACRFS.
bogdanm 82:6473597d706e 559 #define BF_DAC_C0_DACRFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
bogdanm 82:6473597d706e 560
bogdanm 82:6473597d706e 561 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 562 //! @brief Set the DACRFS field to a new value.
bogdanm 82:6473597d706e 563 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
bogdanm 82:6473597d706e 564 #endif
bogdanm 82:6473597d706e 565 //@}
bogdanm 82:6473597d706e 566
bogdanm 82:6473597d706e 567 /*!
bogdanm 82:6473597d706e 568 * @name Register DAC_C0, field DACEN[7] (RW)
bogdanm 82:6473597d706e 569 *
bogdanm 82:6473597d706e 570 * Starts the Programmable Reference Generator operation.
bogdanm 82:6473597d706e 571 *
bogdanm 82:6473597d706e 572 * Values:
bogdanm 82:6473597d706e 573 * - 0 - The DAC system is disabled.
bogdanm 82:6473597d706e 574 * - 1 - The DAC system is enabled.
bogdanm 82:6473597d706e 575 */
bogdanm 82:6473597d706e 576 //@{
bogdanm 82:6473597d706e 577 #define BP_DAC_C0_DACEN (7U) //!< Bit position for DAC_C0_DACEN.
bogdanm 82:6473597d706e 578 #define BM_DAC_C0_DACEN (0x80U) //!< Bit mask for DAC_C0_DACEN.
bogdanm 82:6473597d706e 579 #define BS_DAC_C0_DACEN (1U) //!< Bit field size in bits for DAC_C0_DACEN.
bogdanm 82:6473597d706e 580
bogdanm 82:6473597d706e 581 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 582 //! @brief Read current value of the DAC_C0_DACEN field.
bogdanm 82:6473597d706e 583 #define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
bogdanm 82:6473597d706e 584 #endif
bogdanm 82:6473597d706e 585
bogdanm 82:6473597d706e 586 //! @brief Format value for bitfield DAC_C0_DACEN.
bogdanm 82:6473597d706e 587 #define BF_DAC_C0_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
bogdanm 82:6473597d706e 588
bogdanm 82:6473597d706e 589 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 590 //! @brief Set the DACEN field to a new value.
bogdanm 82:6473597d706e 591 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
bogdanm 82:6473597d706e 592 #endif
bogdanm 82:6473597d706e 593 //@}
bogdanm 82:6473597d706e 594
bogdanm 82:6473597d706e 595 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 596 // HW_DAC_C1 - DAC Control Register 1
bogdanm 82:6473597d706e 597 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 598
bogdanm 82:6473597d706e 599 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 600 /*!
bogdanm 82:6473597d706e 601 * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
bogdanm 82:6473597d706e 602 *
bogdanm 82:6473597d706e 603 * Reset value: 0x00U
bogdanm 82:6473597d706e 604 *
bogdanm 82:6473597d706e 605 * Do not use 32- or 16-bit accesses to this register.
bogdanm 82:6473597d706e 606 */
bogdanm 82:6473597d706e 607 typedef union _hw_dac_c1
bogdanm 82:6473597d706e 608 {
bogdanm 82:6473597d706e 609 uint8_t U;
bogdanm 82:6473597d706e 610 struct _hw_dac_c1_bitfields
bogdanm 82:6473597d706e 611 {
bogdanm 82:6473597d706e 612 uint8_t DACBFEN : 1; //!< [0] DAC Buffer Enable
bogdanm 82:6473597d706e 613 uint8_t DACBFMD : 2; //!< [2:1] DAC Buffer Work Mode Select
bogdanm 82:6473597d706e 614 uint8_t DACBFWM : 2; //!< [4:3] DAC Buffer Watermark Select
bogdanm 82:6473597d706e 615 uint8_t RESERVED0 : 2; //!< [6:5]
bogdanm 82:6473597d706e 616 uint8_t DMAEN : 1; //!< [7] DMA Enable Select
bogdanm 82:6473597d706e 617 } B;
bogdanm 82:6473597d706e 618 } hw_dac_c1_t;
bogdanm 82:6473597d706e 619 #endif
bogdanm 82:6473597d706e 620
bogdanm 82:6473597d706e 621 /*!
bogdanm 82:6473597d706e 622 * @name Constants and macros for entire DAC_C1 register
bogdanm 82:6473597d706e 623 */
bogdanm 82:6473597d706e 624 //@{
bogdanm 82:6473597d706e 625 #define HW_DAC_C1_ADDR(x) (REGS_DAC_BASE(x) + 0x22U)
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 628 #define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
bogdanm 82:6473597d706e 629 #define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
bogdanm 82:6473597d706e 630 #define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
bogdanm 82:6473597d706e 631 #define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
bogdanm 82:6473597d706e 632 #define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
bogdanm 82:6473597d706e 633 #define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
bogdanm 82:6473597d706e 634 #endif
bogdanm 82:6473597d706e 635 //@}
bogdanm 82:6473597d706e 636
bogdanm 82:6473597d706e 637 /*
bogdanm 82:6473597d706e 638 * Constants & macros for individual DAC_C1 bitfields
bogdanm 82:6473597d706e 639 */
bogdanm 82:6473597d706e 640
bogdanm 82:6473597d706e 641 /*!
bogdanm 82:6473597d706e 642 * @name Register DAC_C1, field DACBFEN[0] (RW)
bogdanm 82:6473597d706e 643 *
bogdanm 82:6473597d706e 644 * Values:
bogdanm 82:6473597d706e 645 * - 0 - Buffer read pointer is disabled. The converted data is always the first
bogdanm 82:6473597d706e 646 * word of the buffer.
bogdanm 82:6473597d706e 647 * - 1 - Buffer read pointer is enabled. The converted data is the word that the
bogdanm 82:6473597d706e 648 * read pointer points to. It means converted data can be from any word of
bogdanm 82:6473597d706e 649 * the buffer.
bogdanm 82:6473597d706e 650 */
bogdanm 82:6473597d706e 651 //@{
bogdanm 82:6473597d706e 652 #define BP_DAC_C1_DACBFEN (0U) //!< Bit position for DAC_C1_DACBFEN.
bogdanm 82:6473597d706e 653 #define BM_DAC_C1_DACBFEN (0x01U) //!< Bit mask for DAC_C1_DACBFEN.
bogdanm 82:6473597d706e 654 #define BS_DAC_C1_DACBFEN (1U) //!< Bit field size in bits for DAC_C1_DACBFEN.
bogdanm 82:6473597d706e 655
bogdanm 82:6473597d706e 656 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 657 //! @brief Read current value of the DAC_C1_DACBFEN field.
bogdanm 82:6473597d706e 658 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
bogdanm 82:6473597d706e 659 #endif
bogdanm 82:6473597d706e 660
bogdanm 82:6473597d706e 661 //! @brief Format value for bitfield DAC_C1_DACBFEN.
bogdanm 82:6473597d706e 662 #define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
bogdanm 82:6473597d706e 663
bogdanm 82:6473597d706e 664 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 665 //! @brief Set the DACBFEN field to a new value.
bogdanm 82:6473597d706e 666 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
bogdanm 82:6473597d706e 667 #endif
bogdanm 82:6473597d706e 668 //@}
bogdanm 82:6473597d706e 669
bogdanm 82:6473597d706e 670 /*!
bogdanm 82:6473597d706e 671 * @name Register DAC_C1, field DACBFMD[2:1] (RW)
bogdanm 82:6473597d706e 672 *
bogdanm 82:6473597d706e 673 * Values:
bogdanm 82:6473597d706e 674 * - 00 - Normal mode
bogdanm 82:6473597d706e 675 * - 01 - Swing mode
bogdanm 82:6473597d706e 676 * - 10 - One-Time Scan mode
bogdanm 82:6473597d706e 677 * - 11 - Reserved
bogdanm 82:6473597d706e 678 */
bogdanm 82:6473597d706e 679 //@{
bogdanm 82:6473597d706e 680 #define BP_DAC_C1_DACBFMD (1U) //!< Bit position for DAC_C1_DACBFMD.
bogdanm 82:6473597d706e 681 #define BM_DAC_C1_DACBFMD (0x06U) //!< Bit mask for DAC_C1_DACBFMD.
bogdanm 82:6473597d706e 682 #define BS_DAC_C1_DACBFMD (2U) //!< Bit field size in bits for DAC_C1_DACBFMD.
bogdanm 82:6473597d706e 683
bogdanm 82:6473597d706e 684 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 685 //! @brief Read current value of the DAC_C1_DACBFMD field.
bogdanm 82:6473597d706e 686 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
bogdanm 82:6473597d706e 687 #endif
bogdanm 82:6473597d706e 688
bogdanm 82:6473597d706e 689 //! @brief Format value for bitfield DAC_C1_DACBFMD.
bogdanm 82:6473597d706e 690 #define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
bogdanm 82:6473597d706e 691
bogdanm 82:6473597d706e 692 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 693 //! @brief Set the DACBFMD field to a new value.
bogdanm 82:6473597d706e 694 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
bogdanm 82:6473597d706e 695 #endif
bogdanm 82:6473597d706e 696 //@}
bogdanm 82:6473597d706e 697
bogdanm 82:6473597d706e 698 /*!
bogdanm 82:6473597d706e 699 * @name Register DAC_C1, field DACBFWM[4:3] (RW)
bogdanm 82:6473597d706e 700 *
bogdanm 82:6473597d706e 701 * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
bogdanm 82:6473597d706e 702 * the word defined by this field, which is 1-4 words away from the upper limit
bogdanm 82:6473597d706e 703 * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
bogdanm 82:6473597d706e 704 * watermark interrupt.
bogdanm 82:6473597d706e 705 *
bogdanm 82:6473597d706e 706 * Values:
bogdanm 82:6473597d706e 707 * - 00 - 1 word
bogdanm 82:6473597d706e 708 * - 01 - 2 words
bogdanm 82:6473597d706e 709 * - 10 - 3 words
bogdanm 82:6473597d706e 710 * - 11 - 4 words
bogdanm 82:6473597d706e 711 */
bogdanm 82:6473597d706e 712 //@{
bogdanm 82:6473597d706e 713 #define BP_DAC_C1_DACBFWM (3U) //!< Bit position for DAC_C1_DACBFWM.
bogdanm 82:6473597d706e 714 #define BM_DAC_C1_DACBFWM (0x18U) //!< Bit mask for DAC_C1_DACBFWM.
bogdanm 82:6473597d706e 715 #define BS_DAC_C1_DACBFWM (2U) //!< Bit field size in bits for DAC_C1_DACBFWM.
bogdanm 82:6473597d706e 716
bogdanm 82:6473597d706e 717 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 718 //! @brief Read current value of the DAC_C1_DACBFWM field.
bogdanm 82:6473597d706e 719 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
bogdanm 82:6473597d706e 720 #endif
bogdanm 82:6473597d706e 721
bogdanm 82:6473597d706e 722 //! @brief Format value for bitfield DAC_C1_DACBFWM.
bogdanm 82:6473597d706e 723 #define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
bogdanm 82:6473597d706e 724
bogdanm 82:6473597d706e 725 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 726 //! @brief Set the DACBFWM field to a new value.
bogdanm 82:6473597d706e 727 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
bogdanm 82:6473597d706e 728 #endif
bogdanm 82:6473597d706e 729 //@}
bogdanm 82:6473597d706e 730
bogdanm 82:6473597d706e 731 /*!
bogdanm 82:6473597d706e 732 * @name Register DAC_C1, field DMAEN[7] (RW)
bogdanm 82:6473597d706e 733 *
bogdanm 82:6473597d706e 734 * Values:
bogdanm 82:6473597d706e 735 * - 0 - DMA is disabled.
bogdanm 82:6473597d706e 736 * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
bogdanm 82:6473597d706e 737 * by original interrupts. The interrupts will not be presented on this
bogdanm 82:6473597d706e 738 * module at the same time.
bogdanm 82:6473597d706e 739 */
bogdanm 82:6473597d706e 740 //@{
bogdanm 82:6473597d706e 741 #define BP_DAC_C1_DMAEN (7U) //!< Bit position for DAC_C1_DMAEN.
bogdanm 82:6473597d706e 742 #define BM_DAC_C1_DMAEN (0x80U) //!< Bit mask for DAC_C1_DMAEN.
bogdanm 82:6473597d706e 743 #define BS_DAC_C1_DMAEN (1U) //!< Bit field size in bits for DAC_C1_DMAEN.
bogdanm 82:6473597d706e 744
bogdanm 82:6473597d706e 745 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 746 //! @brief Read current value of the DAC_C1_DMAEN field.
bogdanm 82:6473597d706e 747 #define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
bogdanm 82:6473597d706e 748 #endif
bogdanm 82:6473597d706e 749
bogdanm 82:6473597d706e 750 //! @brief Format value for bitfield DAC_C1_DMAEN.
bogdanm 82:6473597d706e 751 #define BF_DAC_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
bogdanm 82:6473597d706e 752
bogdanm 82:6473597d706e 753 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 754 //! @brief Set the DMAEN field to a new value.
bogdanm 82:6473597d706e 755 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
bogdanm 82:6473597d706e 756 #endif
bogdanm 82:6473597d706e 757 //@}
bogdanm 82:6473597d706e 758
bogdanm 82:6473597d706e 759 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 760 // HW_DAC_C2 - DAC Control Register 2
bogdanm 82:6473597d706e 761 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 762
bogdanm 82:6473597d706e 763 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 764 /*!
bogdanm 82:6473597d706e 765 * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
bogdanm 82:6473597d706e 766 *
bogdanm 82:6473597d706e 767 * Reset value: 0x0FU
bogdanm 82:6473597d706e 768 */
bogdanm 82:6473597d706e 769 typedef union _hw_dac_c2
bogdanm 82:6473597d706e 770 {
bogdanm 82:6473597d706e 771 uint8_t U;
bogdanm 82:6473597d706e 772 struct _hw_dac_c2_bitfields
bogdanm 82:6473597d706e 773 {
bogdanm 82:6473597d706e 774 uint8_t DACBFUP : 4; //!< [3:0] DAC Buffer Upper Limit
bogdanm 82:6473597d706e 775 uint8_t DACBFRP : 4; //!< [7:4] DAC Buffer Read Pointer
bogdanm 82:6473597d706e 776 } B;
bogdanm 82:6473597d706e 777 } hw_dac_c2_t;
bogdanm 82:6473597d706e 778 #endif
bogdanm 82:6473597d706e 779
bogdanm 82:6473597d706e 780 /*!
bogdanm 82:6473597d706e 781 * @name Constants and macros for entire DAC_C2 register
bogdanm 82:6473597d706e 782 */
bogdanm 82:6473597d706e 783 //@{
bogdanm 82:6473597d706e 784 #define HW_DAC_C2_ADDR(x) (REGS_DAC_BASE(x) + 0x23U)
bogdanm 82:6473597d706e 785
bogdanm 82:6473597d706e 786 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 787 #define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
bogdanm 82:6473597d706e 788 #define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
bogdanm 82:6473597d706e 789 #define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
bogdanm 82:6473597d706e 790 #define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
bogdanm 82:6473597d706e 791 #define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
bogdanm 82:6473597d706e 792 #define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
bogdanm 82:6473597d706e 793 #endif
bogdanm 82:6473597d706e 794 //@}
bogdanm 82:6473597d706e 795
bogdanm 82:6473597d706e 796 /*
bogdanm 82:6473597d706e 797 * Constants & macros for individual DAC_C2 bitfields
bogdanm 82:6473597d706e 798 */
bogdanm 82:6473597d706e 799
bogdanm 82:6473597d706e 800 /*!
bogdanm 82:6473597d706e 801 * @name Register DAC_C2, field DACBFUP[3:0] (RW)
bogdanm 82:6473597d706e 802 *
bogdanm 82:6473597d706e 803 * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
bogdanm 82:6473597d706e 804 * exceed it.
bogdanm 82:6473597d706e 805 */
bogdanm 82:6473597d706e 806 //@{
bogdanm 82:6473597d706e 807 #define BP_DAC_C2_DACBFUP (0U) //!< Bit position for DAC_C2_DACBFUP.
bogdanm 82:6473597d706e 808 #define BM_DAC_C2_DACBFUP (0x0FU) //!< Bit mask for DAC_C2_DACBFUP.
bogdanm 82:6473597d706e 809 #define BS_DAC_C2_DACBFUP (4U) //!< Bit field size in bits for DAC_C2_DACBFUP.
bogdanm 82:6473597d706e 810
bogdanm 82:6473597d706e 811 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 812 //! @brief Read current value of the DAC_C2_DACBFUP field.
bogdanm 82:6473597d706e 813 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
bogdanm 82:6473597d706e 814 #endif
bogdanm 82:6473597d706e 815
bogdanm 82:6473597d706e 816 //! @brief Format value for bitfield DAC_C2_DACBFUP.
bogdanm 82:6473597d706e 817 #define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
bogdanm 82:6473597d706e 818
bogdanm 82:6473597d706e 819 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 820 //! @brief Set the DACBFUP field to a new value.
bogdanm 82:6473597d706e 821 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
bogdanm 82:6473597d706e 822 #endif
bogdanm 82:6473597d706e 823 //@}
bogdanm 82:6473597d706e 824
bogdanm 82:6473597d706e 825 /*!
bogdanm 82:6473597d706e 826 * @name Register DAC_C2, field DACBFRP[7:4] (RW)
bogdanm 82:6473597d706e 827 *
bogdanm 82:6473597d706e 828 * Keeps the current value of the buffer read pointer.
bogdanm 82:6473597d706e 829 */
bogdanm 82:6473597d706e 830 //@{
bogdanm 82:6473597d706e 831 #define BP_DAC_C2_DACBFRP (4U) //!< Bit position for DAC_C2_DACBFRP.
bogdanm 82:6473597d706e 832 #define BM_DAC_C2_DACBFRP (0xF0U) //!< Bit mask for DAC_C2_DACBFRP.
bogdanm 82:6473597d706e 833 #define BS_DAC_C2_DACBFRP (4U) //!< Bit field size in bits for DAC_C2_DACBFRP.
bogdanm 82:6473597d706e 834
bogdanm 82:6473597d706e 835 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 836 //! @brief Read current value of the DAC_C2_DACBFRP field.
bogdanm 82:6473597d706e 837 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
bogdanm 82:6473597d706e 838 #endif
bogdanm 82:6473597d706e 839
bogdanm 82:6473597d706e 840 //! @brief Format value for bitfield DAC_C2_DACBFRP.
bogdanm 82:6473597d706e 841 #define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
bogdanm 82:6473597d706e 842
bogdanm 82:6473597d706e 843 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 844 //! @brief Set the DACBFRP field to a new value.
bogdanm 82:6473597d706e 845 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
bogdanm 82:6473597d706e 846 #endif
bogdanm 82:6473597d706e 847 //@}
bogdanm 82:6473597d706e 848
bogdanm 82:6473597d706e 849 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 850 // hw_dac_t - module struct
bogdanm 82:6473597d706e 851 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 852 /*!
bogdanm 82:6473597d706e 853 * @brief All DAC module registers.
bogdanm 82:6473597d706e 854 */
bogdanm 82:6473597d706e 855 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 856 #pragma pack(1)
bogdanm 82:6473597d706e 857 typedef struct _hw_dac
bogdanm 82:6473597d706e 858 {
bogdanm 82:6473597d706e 859 struct {
bogdanm 82:6473597d706e 860 __IO hw_dac_datnl_t DATnL; //!< [0x0] DAC Data Low Register
bogdanm 82:6473597d706e 861 __IO hw_dac_datnh_t DATnH; //!< [0x1] DAC Data High Register
bogdanm 82:6473597d706e 862 } DAT[16];
bogdanm 82:6473597d706e 863 __IO hw_dac_sr_t SR; //!< [0x20] DAC Status Register
bogdanm 82:6473597d706e 864 __IO hw_dac_c0_t C0; //!< [0x21] DAC Control Register
bogdanm 82:6473597d706e 865 __IO hw_dac_c1_t C1; //!< [0x22] DAC Control Register 1
bogdanm 82:6473597d706e 866 __IO hw_dac_c2_t C2; //!< [0x23] DAC Control Register 2
bogdanm 82:6473597d706e 867 } hw_dac_t;
bogdanm 82:6473597d706e 868 #pragma pack()
bogdanm 82:6473597d706e 869
bogdanm 82:6473597d706e 870 //! @brief Macro to access all DAC registers.
bogdanm 82:6473597d706e 871 //! @param x DAC instance number.
bogdanm 82:6473597d706e 872 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 873 //! use the '&' operator, like <code>&HW_DAC(0)</code>.
bogdanm 82:6473597d706e 874 #define HW_DAC(x) (*(hw_dac_t *) REGS_DAC_BASE(x))
bogdanm 82:6473597d706e 875 #endif
bogdanm 82:6473597d706e 876
bogdanm 82:6473597d706e 877 #endif // __HW_DAC_REGISTERS_H__
bogdanm 82:6473597d706e 878 // v22/130726/0.9
bogdanm 82:6473597d706e 879 // EOF