version_2.0

Dependents:   cc3000_ping_demo_try_2

Fork of mbed by mbed official

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
81:7d30d6019079
Child:
85:024bf7f99721
version_2.0

Who changed what in which revision?

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emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_rcc_ex.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
bogdanm 81:7d30d6019079 5 * @version V1.0.0
bogdanm 81:7d30d6019079 6 * @date 18-February-2014
emilmont 77:869cf507173a 7 * @brief Header file of RCC HAL Extension module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_RCC_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup RCCEx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 59 /**
emilmont 77:869cf507173a 60 * @brief PLLI2S Clock structure definition
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62 typedef struct
emilmont 77:869cf507173a 63 {
emilmont 77:869cf507173a 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
emilmont 77:869cf507173a 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont 77:869cf507173a 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 67
emilmont 77:869cf507173a 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
emilmont 77:869cf507173a 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7
emilmont 77:869cf507173a 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
emilmont 77:869cf507173a 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15
emilmont 77:869cf507173a 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont 77:869cf507173a 75 }RCC_PLLI2SInitTypeDef;
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 /**
emilmont 77:869cf507173a 78 * @brief PLLSAI Clock structure definition
emilmont 77:869cf507173a 79 */
emilmont 77:869cf507173a 80 typedef struct
emilmont 77:869cf507173a 81 {
emilmont 77:869cf507173a 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
emilmont 77:869cf507173a 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont 77:869cf507173a 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
emilmont 77:869cf507173a 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15
emilmont 77:869cf507173a 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 89
emilmont 77:869cf507173a 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
emilmont 77:869cf507173a 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7
emilmont 77:869cf507173a 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 }RCC_PLLSAIInitTypeDef;
emilmont 77:869cf507173a 95 /**
emilmont 77:869cf507173a 96 * @brief RCC extended clocks structure definition
emilmont 77:869cf507173a 97 */
emilmont 77:869cf507173a 98 typedef struct
emilmont 77:869cf507173a 99 {
emilmont 77:869cf507173a 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont 77:869cf507173a 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
emilmont 77:869cf507173a 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters
emilmont 77:869cf507173a 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock
emilmont 77:869cf507173a 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont 77:869cf507173a 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont 77:869cf507173a 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont 77:869cf507173a 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
emilmont 77:869cf507173a 116
emilmont 77:869cf507173a 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
emilmont 77:869cf507173a 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
emilmont 77:869cf507173a 119
emilmont 77:869cf507173a 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
emilmont 77:869cf507173a 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
emilmont 77:869cf507173a 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 }RCC_PeriphCLKInitTypeDef;
emilmont 77:869cf507173a 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 128
emilmont 77:869cf507173a 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
emilmont 77:869cf507173a 130 /**
emilmont 77:869cf507173a 131 * @brief PLLI2S Clock structure definition
emilmont 77:869cf507173a 132 */
emilmont 77:869cf507173a 133 typedef struct
emilmont 77:869cf507173a 134 {
emilmont 77:869cf507173a 135 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
emilmont 77:869cf507173a 136 This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont 77:869cf507173a 137 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 138
emilmont 77:869cf507173a 139 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
emilmont 77:869cf507173a 140 This parameter must be a number between Min_Data = 2 and Max_Data = 7
emilmont 77:869cf507173a 141 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 142
emilmont 77:869cf507173a 143 }RCC_PLLI2SInitTypeDef;
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 /**
emilmont 77:869cf507173a 147 * @brief RCC extended clocks structure definition
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149 typedef struct
emilmont 77:869cf507173a 150 {
emilmont 77:869cf507173a 151 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont 77:869cf507173a 152 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
emilmont 77:869cf507173a 155 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 156
bogdanm 81:7d30d6019079 157 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
emilmont 77:869cf507173a 158 This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont 77:869cf507173a 159
emilmont 77:869cf507173a 160 }RCC_PeriphCLKInitTypeDef;
emilmont 77:869cf507173a 161 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
emilmont 77:869cf507173a 162 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 163 /** @defgroup RCCEx_Exported_Constants
emilmont 77:869cf507173a 164 * @{
emilmont 77:869cf507173a 165 */
emilmont 77:869cf507173a 166
emilmont 77:869cf507173a 167 /** @defgroup RCCEx_Periph_Clock_Selection
emilmont 77:869cf507173a 168 * @{
emilmont 77:869cf507173a 169 */
emilmont 77:869cf507173a 170 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 171 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont 77:869cf507173a 172 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
emilmont 77:869cf507173a 173 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
emilmont 77:869cf507173a 174 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
emilmont 77:869cf507173a 175 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
emilmont 77:869cf507173a 176 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
emilmont 77:869cf507173a 177 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
emilmont 77:869cf507173a 178 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 179
emilmont 77:869cf507173a 180 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
emilmont 77:869cf507173a 181 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont 77:869cf507173a 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
emilmont 77:869cf507173a 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
emilmont 77:869cf507173a 184 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 /**
emilmont 77:869cf507173a 187 * @}
emilmont 77:869cf507173a 188 */
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 /** @defgroup RCCEx_BitAddress_AliasRegion
emilmont 77:869cf507173a 191 * @brief RCC registers bit address in the alias region
emilmont 77:869cf507173a 192 * @{
emilmont 77:869cf507173a 193 */
emilmont 77:869cf507173a 194 /* --- CR Register ---*/
emilmont 77:869cf507173a 195 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 196 /* Alias word address of PLLSAION bit */
emilmont 77:869cf507173a 197 #define PLLSAION_BitNumber 0x1C
emilmont 77:869cf507173a 198 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
emilmont 77:869cf507173a 199
emilmont 77:869cf507173a 200 /* --- DCKCFGR Register ---*/
emilmont 77:869cf507173a 201 /* Alias word address of TIMPRE bit */
emilmont 77:869cf507173a 202 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
emilmont 77:869cf507173a 203 #define TIMPRE_BitNumber 0x18
emilmont 77:869cf507173a 204 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
emilmont 77:869cf507173a 205 /**
emilmont 77:869cf507173a 206 * @}
emilmont 77:869cf507173a 207 */
emilmont 77:869cf507173a 208
emilmont 77:869cf507173a 209 /** @defgroup RCCEx_PLLI2S_Clock_Source
emilmont 77:869cf507173a 210 * @{
emilmont 77:869cf507173a 211 */
emilmont 77:869cf507173a 212 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
emilmont 77:869cf507173a 213 /**
emilmont 77:869cf507173a 214 * @}
emilmont 77:869cf507173a 215 */
emilmont 77:869cf507173a 216
emilmont 77:869cf507173a 217 /** @defgroup RCCEx_PLLSAI_Clock_Source
emilmont 77:869cf507173a 218 * @{
emilmont 77:869cf507173a 219 */
emilmont 77:869cf507173a 220 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
emilmont 77:869cf507173a 221 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
emilmont 77:869cf507173a 222 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
emilmont 77:869cf507173a 223 /**
emilmont 77:869cf507173a 224 * @}
emilmont 77:869cf507173a 225 */
emilmont 77:869cf507173a 226
emilmont 77:869cf507173a 227 /** @defgroup RCCEx_PLLSAI_DIVQ
emilmont 77:869cf507173a 228 * @{
emilmont 77:869cf507173a 229 */
emilmont 77:869cf507173a 230 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
emilmont 77:869cf507173a 231 /**
emilmont 77:869cf507173a 232 * @}
emilmont 77:869cf507173a 233 */
emilmont 77:869cf507173a 234
emilmont 77:869cf507173a 235 /** @defgroup RCCEx_PLLI2S_DIVQ
emilmont 77:869cf507173a 236 * @{
emilmont 77:869cf507173a 237 */
emilmont 77:869cf507173a 238 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
emilmont 77:869cf507173a 239
emilmont 77:869cf507173a 240 /**
emilmont 77:869cf507173a 241 * @}
emilmont 77:869cf507173a 242 */
emilmont 77:869cf507173a 243
emilmont 77:869cf507173a 244 /** @defgroup RCCEx_PLLSAI_DIVR
emilmont 77:869cf507173a 245 * @{
emilmont 77:869cf507173a 246 */
emilmont 77:869cf507173a 247 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 248 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 249 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 250 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 251 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
emilmont 77:869cf507173a 252 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
emilmont 77:869cf507173a 253 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
emilmont 77:869cf507173a 254 ((VALUE) == RCC_PLLSAIDIVR_16))
emilmont 77:869cf507173a 255
emilmont 77:869cf507173a 256 /**
emilmont 77:869cf507173a 257 * @}
emilmont 77:869cf507173a 258 */
emilmont 77:869cf507173a 259
emilmont 77:869cf507173a 260 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
emilmont 77:869cf507173a 261 * @{
emilmont 77:869cf507173a 262 */
emilmont 77:869cf507173a 263 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 264 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
emilmont 77:869cf507173a 265 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
emilmont 77:869cf507173a 266 /**
emilmont 77:869cf507173a 267 * @}
emilmont 77:869cf507173a 268 */
emilmont 77:869cf507173a 269
emilmont 77:869cf507173a 270 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
emilmont 77:869cf507173a 271 * @{
emilmont 77:869cf507173a 272 */
emilmont 77:869cf507173a 273 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 274 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
emilmont 77:869cf507173a 275 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
emilmont 77:869cf507173a 276 /**
emilmont 77:869cf507173a 277 * @}
emilmont 77:869cf507173a 278 */
emilmont 77:869cf507173a 279
emilmont 77:869cf507173a 280 /** @defgroup RCCEx_TIM_PRescaler_Selection
emilmont 77:869cf507173a 281 * @{
emilmont 77:869cf507173a 282 */
emilmont 77:869cf507173a 283 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
emilmont 77:869cf507173a 284 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
emilmont 77:869cf507173a 285 /**
emilmont 77:869cf507173a 286 * @}
emilmont 77:869cf507173a 287 */
emilmont 77:869cf507173a 288 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 289 /**
emilmont 77:869cf507173a 290 * @}
emilmont 77:869cf507173a 291 */
emilmont 77:869cf507173a 292
emilmont 77:869cf507173a 293 /**
emilmont 77:869cf507173a 294 * @}
emilmont 77:869cf507173a 295 */
emilmont 77:869cf507173a 296
emilmont 77:869cf507173a 297 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 298
emilmont 77:869cf507173a 299 /** @brief Enables or disables the AHB1 peripheral clock.
emilmont 77:869cf507173a 300 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 301 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 302 * using it.
emilmont 77:869cf507173a 303 */
emilmont 77:869cf507173a 304
emilmont 77:869cf507173a 305 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 306 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
emilmont 77:869cf507173a 307 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
emilmont 77:869cf507173a 308 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
emilmont 77:869cf507173a 309 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
emilmont 77:869cf507173a 310 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
emilmont 77:869cf507173a 311 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
emilmont 77:869cf507173a 312 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
emilmont 77:869cf507173a 313 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
emilmont 77:869cf507173a 314 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
emilmont 77:869cf507173a 315
emilmont 77:869cf507173a 316 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
emilmont 77:869cf507173a 317 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
emilmont 77:869cf507173a 318 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
emilmont 77:869cf507173a 319 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
emilmont 77:869cf507173a 320 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
emilmont 77:869cf507173a 321 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
emilmont 77:869cf507173a 322 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
emilmont 77:869cf507173a 323 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
emilmont 77:869cf507173a 324 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
emilmont 77:869cf507173a 325 #endif /* !(STM32F401xC && STM32F401xE) */
emilmont 77:869cf507173a 326
emilmont 77:869cf507173a 327 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 328 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
emilmont 77:869cf507173a 329 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
emilmont 77:869cf507173a 330 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
emilmont 77:869cf507173a 331
emilmont 77:869cf507173a 332 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
emilmont 77:869cf507173a 333 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
emilmont 77:869cf507173a 334 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
emilmont 77:869cf507173a 335 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
emilmont 77:869cf507173a 336
emilmont 77:869cf507173a 337 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 338 /**
emilmont 77:869cf507173a 339 * @brief Enable ETHERNET clock.
emilmont 77:869cf507173a 340 */
emilmont 77:869cf507173a 341 #define __ETH_CLK_ENABLE() do { \
emilmont 77:869cf507173a 342 __ETHMAC_CLK_ENABLE(); \
emilmont 77:869cf507173a 343 __ETHMACTX_CLK_ENABLE(); \
emilmont 77:869cf507173a 344 __ETHMACRX_CLK_ENABLE(); \
emilmont 77:869cf507173a 345 } while(0)
emilmont 77:869cf507173a 346
emilmont 77:869cf507173a 347 /**
emilmont 77:869cf507173a 348 * @brief Disable ETHERNET clock.
emilmont 77:869cf507173a 349 */
emilmont 77:869cf507173a 350 #define __ETH_CLK_DISABLE() do { \
emilmont 77:869cf507173a 351 __ETHMACTX_CLK_DISABLE(); \
emilmont 77:869cf507173a 352 __ETHMACRX_CLK_DISABLE(); \
emilmont 77:869cf507173a 353 __ETHMAC_CLK_DISABLE(); \
emilmont 77:869cf507173a 354 } while(0)
emilmont 77:869cf507173a 355 #endif /* !(STM32F401xC && STM32F401xE) */
emilmont 77:869cf507173a 356
emilmont 77:869cf507173a 357 /** @brief Enable or disable the AHB2 peripheral clock.
emilmont 77:869cf507173a 358 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 359 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 360 * using it.
emilmont 77:869cf507173a 361 */
emilmont 77:869cf507173a 362 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 363 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
emilmont 77:869cf507173a 364 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
emilmont 77:869cf507173a 365 #endif /* !(STM32F401xC && STM32F401xE) */
emilmont 77:869cf507173a 366
emilmont 77:869cf507173a 367 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 368 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
emilmont 77:869cf507173a 369 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
emilmont 77:869cf507173a 370
emilmont 77:869cf507173a 371 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
emilmont 77:869cf507173a 372 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
emilmont 77:869cf507173a 373
emilmont 77:869cf507173a 374 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
emilmont 77:869cf507173a 375
emilmont 77:869cf507173a 376 /** @brief Enables or disables the AHB3 peripheral clock.
emilmont 77:869cf507173a 377 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 378 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 379 * using it.
emilmont 77:869cf507173a 380 */
emilmont 77:869cf507173a 381 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 382 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
emilmont 77:869cf507173a 383 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
emilmont 77:869cf507173a 384 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 385
emilmont 77:869cf507173a 386 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 387 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
emilmont 77:869cf507173a 388 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
emilmont 77:869cf507173a 389 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
emilmont 77:869cf507173a 390
emilmont 77:869cf507173a 391
emilmont 77:869cf507173a 392 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont 77:869cf507173a 393 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 394 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 395 * using it.
emilmont 77:869cf507173a 396 */
emilmont 77:869cf507173a 397 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 398 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
emilmont 77:869cf507173a 399 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
emilmont 77:869cf507173a 400 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
emilmont 77:869cf507173a 401 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
emilmont 77:869cf507173a 402 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
emilmont 77:869cf507173a 403 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
emilmont 77:869cf507173a 404 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
emilmont 77:869cf507173a 405 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
emilmont 77:869cf507173a 406 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
emilmont 77:869cf507173a 407 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
emilmont 77:869cf507173a 408 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
emilmont 77:869cf507173a 409 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
emilmont 77:869cf507173a 410
emilmont 77:869cf507173a 411 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
emilmont 77:869cf507173a 412 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
emilmont 77:869cf507173a 413 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
emilmont 77:869cf507173a 414 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
emilmont 77:869cf507173a 415 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
emilmont 77:869cf507173a 416 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
emilmont 77:869cf507173a 417 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
emilmont 77:869cf507173a 418 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
emilmont 77:869cf507173a 419 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
emilmont 77:869cf507173a 420 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
emilmont 77:869cf507173a 421 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
emilmont 77:869cf507173a 422 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
emilmont 77:869cf507173a 423 #endif /* !(STM32F401xC && STM32F401xE) */
emilmont 77:869cf507173a 424
emilmont 77:869cf507173a 425 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 426 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
emilmont 77:869cf507173a 427 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
emilmont 77:869cf507173a 428
emilmont 77:869cf507173a 429 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
emilmont 77:869cf507173a 430 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
emilmont 77:869cf507173a 431 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
emilmont 77:869cf507173a 432
emilmont 77:869cf507173a 433 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont 77:869cf507173a 434 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 435 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 436 * using it.
emilmont 77:869cf507173a 437 */
emilmont 77:869cf507173a 438 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
emilmont 77:869cf507173a 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
emilmont 77:869cf507173a 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
emilmont 77:869cf507173a 442
emilmont 77:869cf507173a 443 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
emilmont 77:869cf507173a 444 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
emilmont 77:869cf507173a 445 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
emilmont 77:869cf507173a 446 #endif /* !(STM32F401xC && STM32F401xE) */
emilmont 77:869cf507173a 447
emilmont 77:869cf507173a 448 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 449 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
emilmont 77:869cf507173a 450 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
emilmont 77:869cf507173a 451 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
emilmont 77:869cf507173a 452 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
emilmont 77:869cf507173a 453
emilmont 77:869cf507173a 454 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
emilmont 77:869cf507173a 455 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
emilmont 77:869cf507173a 456 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
emilmont 77:869cf507173a 457 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
emilmont 77:869cf507173a 458 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 459
emilmont 77:869cf507173a 460 /** @brief Force or release AHB1 peripheral reset.
emilmont 77:869cf507173a 461 */
emilmont 77:869cf507173a 462 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 463 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
emilmont 77:869cf507173a 464 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
emilmont 77:869cf507173a 465 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
emilmont 77:869cf507173a 466 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
emilmont 77:869cf507173a 467 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
emilmont 77:869cf507173a 468
emilmont 77:869cf507173a 469 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
emilmont 77:869cf507173a 470 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
emilmont 77:869cf507173a 471 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
emilmont 77:869cf507173a 472 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
emilmont 77:869cf507173a 473 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
emilmont 77:869cf507173a 474 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 475
emilmont 77:869cf507173a 476 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 477 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
emilmont 77:869cf507173a 478 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
emilmont 77:869cf507173a 479 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
emilmont 77:869cf507173a 480
emilmont 77:869cf507173a 481 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
emilmont 77:869cf507173a 482 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
emilmont 77:869cf507173a 483 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
emilmont 77:869cf507173a 484 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486 /** @brief Force or release AHB2 peripheral reset.
emilmont 77:869cf507173a 487 */
emilmont 77:869cf507173a 488 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 489 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
emilmont 77:869cf507173a 490 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
emilmont 77:869cf507173a 491 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 492
emilmont 77:869cf507173a 493 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 494 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
emilmont 77:869cf507173a 495 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
emilmont 77:869cf507173a 496
emilmont 77:869cf507173a 497 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
emilmont 77:869cf507173a 498 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
emilmont 77:869cf507173a 499
emilmont 77:869cf507173a 500 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
emilmont 77:869cf507173a 501
emilmont 77:869cf507173a 502 /** @brief Force or release AHB3 peripheral reset
emilmont 77:869cf507173a 503 */
emilmont 77:869cf507173a 504 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 505 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
emilmont 77:869cf507173a 506 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
emilmont 77:869cf507173a 507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 508
emilmont 77:869cf507173a 509 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 510 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
emilmont 77:869cf507173a 511 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
emilmont 77:869cf507173a 512 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 513
emilmont 77:869cf507173a 514 /** @brief Force or release APB1 peripheral reset.
emilmont 77:869cf507173a 515 */
emilmont 77:869cf507173a 516 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 517 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
emilmont 77:869cf507173a 518 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
emilmont 77:869cf507173a 519 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
emilmont 77:869cf507173a 520 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
emilmont 77:869cf507173a 521 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
emilmont 77:869cf507173a 522 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
emilmont 77:869cf507173a 523 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
emilmont 77:869cf507173a 524 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
emilmont 77:869cf507173a 525 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
emilmont 77:869cf507173a 526 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
emilmont 77:869cf507173a 527 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
emilmont 77:869cf507173a 528
emilmont 77:869cf507173a 529 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
emilmont 77:869cf507173a 530 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
emilmont 77:869cf507173a 531 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
emilmont 77:869cf507173a 532 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
emilmont 77:869cf507173a 533 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
emilmont 77:869cf507173a 534 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
emilmont 77:869cf507173a 535 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
emilmont 77:869cf507173a 536 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
emilmont 77:869cf507173a 537 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
emilmont 77:869cf507173a 538 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
emilmont 77:869cf507173a 539 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
emilmont 77:869cf507173a 540 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 541
emilmont 77:869cf507173a 542 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 543 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
emilmont 77:869cf507173a 544 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
emilmont 77:869cf507173a 545
emilmont 77:869cf507173a 546 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
emilmont 77:869cf507173a 547 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
emilmont 77:869cf507173a 548 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 549
emilmont 77:869cf507173a 550 /** @brief Force or release APB2 peripheral reset.
emilmont 77:869cf507173a 551 */
emilmont 77:869cf507173a 552 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 553 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
emilmont 77:869cf507173a 554 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
emilmont 77:869cf507173a 555 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 556
emilmont 77:869cf507173a 557 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 558 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
emilmont 77:869cf507173a 559 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
emilmont 77:869cf507173a 560 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
emilmont 77:869cf507173a 561 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
emilmont 77:869cf507173a 562
emilmont 77:869cf507173a 563 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
emilmont 77:869cf507173a 564 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
emilmont 77:869cf507173a 565 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
emilmont 77:869cf507173a 566 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
emilmont 77:869cf507173a 567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 568
emilmont 77:869cf507173a 569
emilmont 77:869cf507173a 570 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 572 * power consumption.
emilmont 77:869cf507173a 573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 574 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 575 */
emilmont 77:869cf507173a 576 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 577 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
emilmont 77:869cf507173a 578 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
emilmont 77:869cf507173a 579 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
emilmont 77:869cf507173a 580 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
emilmont 77:869cf507173a 581 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
emilmont 77:869cf507173a 582 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
emilmont 77:869cf507173a 583 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
emilmont 77:869cf507173a 584 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
emilmont 77:869cf507173a 585 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
emilmont 77:869cf507173a 586 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont 77:869cf507173a 587
emilmont 77:869cf507173a 588 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
emilmont 77:869cf507173a 589 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
emilmont 77:869cf507173a 590 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
emilmont 77:869cf507173a 591 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
emilmont 77:869cf507173a 592 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
emilmont 77:869cf507173a 593 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
emilmont 77:869cf507173a 594 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
emilmont 77:869cf507173a 595 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
emilmont 77:869cf507173a 596 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
emilmont 77:869cf507173a 597 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont 77:869cf507173a 598 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 599
emilmont 77:869cf507173a 600 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 601 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
emilmont 77:869cf507173a 602 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
emilmont 77:869cf507173a 603 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
emilmont 77:869cf507173a 604 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
emilmont 77:869cf507173a 605
emilmont 77:869cf507173a 606 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
emilmont 77:869cf507173a 607 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
emilmont 77:869cf507173a 608 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
emilmont 77:869cf507173a 609 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 610
emilmont 77:869cf507173a 611 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 612 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 613 * power consumption.
emilmont 77:869cf507173a 614 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 615 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 616 */
emilmont 77:869cf507173a 617 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 618 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
emilmont 77:869cf507173a 619 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
emilmont 77:869cf507173a 620 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 621
emilmont 77:869cf507173a 622 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 623 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
emilmont 77:869cf507173a 624 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
emilmont 77:869cf507173a 625
emilmont 77:869cf507173a 626 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
emilmont 77:869cf507173a 627 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
emilmont 77:869cf507173a 628
emilmont 77:869cf507173a 629 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
emilmont 77:869cf507173a 630
emilmont 77:869cf507173a 631 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 633 * power consumption.
emilmont 77:869cf507173a 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 636 */
emilmont 77:869cf507173a 637 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 638 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
emilmont 77:869cf507173a 639 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
emilmont 77:869cf507173a 640 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 641
emilmont 77:869cf507173a 642 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 643 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
emilmont 77:869cf507173a 644 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
emilmont 77:869cf507173a 645 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 646
emilmont 77:869cf507173a 647 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 648 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 649 * power consumption.
emilmont 77:869cf507173a 650 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 651 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 652 */
emilmont 77:869cf507173a 653 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 654 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
emilmont 77:869cf507173a 655 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
emilmont 77:869cf507173a 656 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
emilmont 77:869cf507173a 657 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
emilmont 77:869cf507173a 658 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
emilmont 77:869cf507173a 659 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
emilmont 77:869cf507173a 660 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
emilmont 77:869cf507173a 661 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
emilmont 77:869cf507173a 662 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
emilmont 77:869cf507173a 663 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
emilmont 77:869cf507173a 664 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
emilmont 77:869cf507173a 665
emilmont 77:869cf507173a 666 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
emilmont 77:869cf507173a 667 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
emilmont 77:869cf507173a 668 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
emilmont 77:869cf507173a 669 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
emilmont 77:869cf507173a 670 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
emilmont 77:869cf507173a 671 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
emilmont 77:869cf507173a 672 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
emilmont 77:869cf507173a 673 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
emilmont 77:869cf507173a 674 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
emilmont 77:869cf507173a 675 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
emilmont 77:869cf507173a 676 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
emilmont 77:869cf507173a 677 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 678
emilmont 77:869cf507173a 679 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 680 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
emilmont 77:869cf507173a 681 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
emilmont 77:869cf507173a 682
emilmont 77:869cf507173a 683 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
emilmont 77:869cf507173a 684 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
emilmont 77:869cf507173a 685 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 686
emilmont 77:869cf507173a 687 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 688 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 689 * power consumption.
emilmont 77:869cf507173a 690 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 691 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 692 */
emilmont 77:869cf507173a 693 #if !defined(STM32F401xC) && !defined(STM32F401xE)
emilmont 77:869cf507173a 694 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
emilmont 77:869cf507173a 695 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
emilmont 77:869cf507173a 696 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
emilmont 77:869cf507173a 697
emilmont 77:869cf507173a 698 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
emilmont 77:869cf507173a 699 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
emilmont 77:869cf507173a 700 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
emilmont 77:869cf507173a 701 #endif /* !STM32F401xC && STM32F401xE */
emilmont 77:869cf507173a 702
emilmont 77:869cf507173a 703 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 704 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
emilmont 77:869cf507173a 705 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
emilmont 77:869cf507173a 706 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
emilmont 77:869cf507173a 707 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
emilmont 77:869cf507173a 708
emilmont 77:869cf507173a 709 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
emilmont 77:869cf507173a 710 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
emilmont 77:869cf507173a 711 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
emilmont 77:869cf507173a 712 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
emilmont 77:869cf507173a 713 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 714
emilmont 77:869cf507173a 715 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 716
emilmont 77:869cf507173a 717 /** @brief Macro to configure the Timers clocks prescalers
emilmont 77:869cf507173a 718 * @note This feature is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 719 * @param __PRESC__ : specifies the Timers clocks prescalers selection
emilmont 77:869cf507173a 720 * This parameter can be one of the following values:
emilmont 77:869cf507173a 721 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
emilmont 77:869cf507173a 722 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
emilmont 77:869cf507173a 723 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
emilmont 77:869cf507173a 724 * division by 4 or more.
emilmont 77:869cf507173a 725 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
emilmont 77:869cf507173a 726 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
emilmont 77:869cf507173a 727 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
emilmont 77:869cf507173a 728 * to division by 8 or more.
emilmont 77:869cf507173a 729 */
emilmont 77:869cf507173a 730 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
emilmont 77:869cf507173a 731
emilmont 77:869cf507173a 732 /** @brief Macros to Enable or Disable the PLLISAI.
emilmont 77:869cf507173a 733 * @note The PLLSAI is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 734 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 735 */
emilmont 77:869cf507173a 736 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
emilmont 77:869cf507173a 737 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
emilmont 77:869cf507173a 738
emilmont 77:869cf507173a 739 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
emilmont 77:869cf507173a 740 * @note The PLLSAI is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 741 * @note This function must be used only when the PLLSAI is disabled.
emilmont 77:869cf507173a 742 * @note PLLSAI clock source is common with the main PLL (configured in
emilmont 77:869cf507173a 743 * RCC_PLLConfig function )
emilmont 77:869cf507173a 744 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
emilmont 77:869cf507173a 745 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 746 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
emilmont 77:869cf507173a 747 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
emilmont 77:869cf507173a 748 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
emilmont 77:869cf507173a 749 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 750 * @param __PLLSAIR__: specifies the division factor for LTDC clock
emilmont 77:869cf507173a 751 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 752 */
emilmont 77:869cf507173a 753 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
emilmont 77:869cf507173a 754
emilmont 77:869cf507173a 755 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
emilmont 77:869cf507173a 756 * @note This macro must be used only when the PLLI2S is disabled.
emilmont 77:869cf507173a 757 * @note PLLI2S clock source is common with the main PLL (configured in
emilmont 77:869cf507173a 758 * HAL_RCC_ClockConfig() API)
emilmont 77:869cf507173a 759 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
emilmont 77:869cf507173a 760 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 761 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
emilmont 77:869cf507173a 762 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
emilmont 77:869cf507173a 763 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
emilmont 77:869cf507173a 764 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 765 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
emilmont 77:869cf507173a 766 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
emilmont 77:869cf507173a 767 * @param __PLLI2SR__: specifies the division factor for I2S clock
emilmont 77:869cf507173a 768 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 769 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
emilmont 77:869cf507173a 770 * on the I2S clock frequency.
emilmont 77:869cf507173a 771 */
emilmont 77:869cf507173a 772 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
emilmont 77:869cf507173a 773
emilmont 77:869cf507173a 774 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
emilmont 77:869cf507173a 775 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 776 * @note This function must be called before enabling the PLLI2S.
emilmont 77:869cf507173a 777 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
emilmont 77:869cf507173a 778 * This parameter must be a number between 1 and 32.
emilmont 77:869cf507173a 779 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
emilmont 77:869cf507173a 780 */
emilmont 77:869cf507173a 781 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
emilmont 77:869cf507173a 782
emilmont 77:869cf507173a 783 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
emilmont 77:869cf507173a 784 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 785 * @note This function must be called before enabling the PLLSAI.
emilmont 77:869cf507173a 786 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
emilmont 77:869cf507173a 787 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
emilmont 77:869cf507173a 788 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
emilmont 77:869cf507173a 789 */
emilmont 77:869cf507173a 790 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
emilmont 77:869cf507173a 791
emilmont 77:869cf507173a 792 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
emilmont 77:869cf507173a 793 *
emilmont 77:869cf507173a 794 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 795 * @note This function must be called before enabling the PLLSAI.
emilmont 77:869cf507173a 796 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
emilmont 77:869cf507173a 797 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
emilmont 77:869cf507173a 798 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
emilmont 77:869cf507173a 799 */
emilmont 77:869cf507173a 800 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
emilmont 77:869cf507173a 801
emilmont 77:869cf507173a 802 /** @brief Macro to configure SAI1BlockA clock source selection.
emilmont 77:869cf507173a 803 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 804 * @note This function must be called before enabling PLLSAI, PLLI2S and
emilmont 77:869cf507173a 805 * the SAI clock.
emilmont 77:869cf507173a 806 * @param __SOURCE__: specifies the SAI Block A clock source.
emilmont 77:869cf507173a 807 * This parameter can be one of the following values:
emilmont 77:869cf507173a 808 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
emilmont 77:869cf507173a 809 * as SAI1 Block A clock.
emilmont 77:869cf507173a 810 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
emilmont 77:869cf507173a 811 * as SAI1 Block A clock.
emilmont 77:869cf507173a 812 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
emilmont 77:869cf507173a 813 * used as SAI1 Block A clock.
emilmont 77:869cf507173a 814 */
emilmont 77:869cf507173a 815 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
emilmont 77:869cf507173a 816
emilmont 77:869cf507173a 817 /** @brief Macro to configure SAI1BlockB clock source selection.
emilmont 77:869cf507173a 818 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 819 * @note This function must be called before enabling PLLSAI, PLLI2S and
emilmont 77:869cf507173a 820 * the SAI clock.
emilmont 77:869cf507173a 821 * @param __SOURCE__: specifies the SAI Block B clock source.
emilmont 77:869cf507173a 822 * This parameter can be one of the following values:
emilmont 77:869cf507173a 823 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
emilmont 77:869cf507173a 824 * as SAI1 Block B clock.
emilmont 77:869cf507173a 825 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
emilmont 77:869cf507173a 826 * as SAI1 Block B clock.
emilmont 77:869cf507173a 827 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
emilmont 77:869cf507173a 828 * used as SAI1 Block B clock.
emilmont 77:869cf507173a 829 */
emilmont 77:869cf507173a 830 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
emilmont 77:869cf507173a 831
emilmont 77:869cf507173a 832 /** @brief Enable PLLSAI_RDY interrupt.
emilmont 77:869cf507173a 833 */
emilmont 77:869cf507173a 834 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 835
emilmont 77:869cf507173a 836 /** @brief Disable PLLSAI_RDY interrupt.
emilmont 77:869cf507173a 837 */
emilmont 77:869cf507173a 838 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 839
emilmont 77:869cf507173a 840 /** @brief Clear the PLLSAI RDY interrupt pending bits.
emilmont 77:869cf507173a 841 */
emilmont 77:869cf507173a 842 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
emilmont 77:869cf507173a 843
emilmont 77:869cf507173a 844 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
emilmont 77:869cf507173a 845 * @retval The new state (TRUE or FALSE).
emilmont 77:869cf507173a 846 */
emilmont 77:869cf507173a 847 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 848
emilmont 77:869cf507173a 849 /** @brief Check PLLSAI RDY flag is set or not.
emilmont 77:869cf507173a 850 * @retval The new state (TRUE or FALSE).
emilmont 77:869cf507173a 851 */
emilmont 77:869cf507173a 852 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
emilmont 77:869cf507173a 853
emilmont 77:869cf507173a 854 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 855
emilmont 77:869cf507173a 856 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 857 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont 77:869cf507173a 858 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont 77:869cf507173a 859
emilmont 77:869cf507173a 860 /**
emilmont 77:869cf507173a 861 * @}
emilmont 77:869cf507173a 862 */
emilmont 77:869cf507173a 863
emilmont 77:869cf507173a 864 /**
emilmont 77:869cf507173a 865 * @}
emilmont 77:869cf507173a 866 */
emilmont 77:869cf507173a 867
emilmont 77:869cf507173a 868 #ifdef __cplusplus
emilmont 77:869cf507173a 869 }
emilmont 77:869cf507173a 870 #endif
emilmont 77:869cf507173a 871
emilmont 77:869cf507173a 872 #endif /* __STM32F4xx_HAL_RCC_EX_H */
emilmont 77:869cf507173a 873
emilmont 77:869cf507173a 874 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/