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version_2.0

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:: bogdanm
Date:: Wed Jun 11 15:14:05 2014 +0100
Revision:: 85:024bf7f99721

Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.0.0
bogdanm	85:024bf7f99721	6	* @date 28-May-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_RCC_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup RCC
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	58
bogdanm	85:024bf7f99721	59	/**
bogdanm	85:024bf7f99721	60	* @brief RCC PLL configuration structure definition
bogdanm	85:024bf7f99721	61	*/
bogdanm	85:024bf7f99721	62	typedef struct
bogdanm	85:024bf7f99721	63	{
bogdanm	85:024bf7f99721	64	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
bogdanm	85:024bf7f99721	65	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	85:024bf7f99721	66
bogdanm	85:024bf7f99721	67	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm	85:024bf7f99721	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	85:024bf7f99721	69
bogdanm	85:024bf7f99721	70	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
bogdanm	85:024bf7f99721	71	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
bogdanm	85:024bf7f99721	72
bogdanm	85:024bf7f99721	73	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm	85:024bf7f99721	74	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
bogdanm	85:024bf7f99721	75
bogdanm	85:024bf7f99721	76	}RCC_PLLInitTypeDef;
bogdanm	85:024bf7f99721	77
bogdanm	85:024bf7f99721	78	/**
bogdanm	85:024bf7f99721	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	85:024bf7f99721	80	*/
bogdanm	85:024bf7f99721	81	typedef struct
bogdanm	85:024bf7f99721	82	{
bogdanm	85:024bf7f99721	83	uint32_t OscillatorType; /*!< The Oscillators to be configured.
bogdanm	85:024bf7f99721	84	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	85:024bf7f99721	85
bogdanm	85:024bf7f99721	86	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	85:024bf7f99721	87	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	85:024bf7f99721	88
bogdanm	85:024bf7f99721	89	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	85:024bf7f99721	90	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	85:024bf7f99721	91
bogdanm	85:024bf7f99721	92	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	85:024bf7f99721	93	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	85:024bf7f99721	94
bogdanm	85:024bf7f99721	95	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	85:024bf7f99721	97
bogdanm	85:024bf7f99721	98	uint32_t HSI14State; /*!< The new state of the HSI14.
bogdanm	85:024bf7f99721	99	This parameter can be a value of @ref RCC_HSI14_Config */
bogdanm	85:024bf7f99721	100
bogdanm	85:024bf7f99721	101	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	85:024bf7f99721	103
bogdanm	85:024bf7f99721	104	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x and STM32F0x2 devices).
bogdanm	85:024bf7f99721	105	This parameter can be a value of @ref RCCEx_HSI48_Config */
bogdanm	85:024bf7f99721	106
bogdanm	85:024bf7f99721	107	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	85:024bf7f99721	108	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	85:024bf7f99721	109
bogdanm	85:024bf7f99721	110	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	85:024bf7f99721	111
bogdanm	85:024bf7f99721	112	}RCC_OscInitTypeDef;
bogdanm	85:024bf7f99721	113
bogdanm	85:024bf7f99721	114	/**
bogdanm	85:024bf7f99721	115	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	85:024bf7f99721	116	*/
bogdanm	85:024bf7f99721	117	typedef struct
bogdanm	85:024bf7f99721	118	{
bogdanm	85:024bf7f99721	119	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	85:024bf7f99721	120	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	85:024bf7f99721	121
bogdanm	85:024bf7f99721	122	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	85:024bf7f99721	123	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	85:024bf7f99721	124
bogdanm	85:024bf7f99721	125	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	85:024bf7f99721	126	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	85:024bf7f99721	127
bogdanm	85:024bf7f99721	128	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	85:024bf7f99721	129	This parameter can be a value of @ref RCC_APB1_Clock_Source */
bogdanm	85:024bf7f99721	130
bogdanm	85:024bf7f99721	131	}RCC_ClkInitTypeDef;
bogdanm	85:024bf7f99721	132
bogdanm	85:024bf7f99721	133	/* Exported constants --------------------------------------------------------*/
bogdanm	85:024bf7f99721	134	/** @defgroup RCC_Exported_Constants
bogdanm	85:024bf7f99721	135	* @{
bogdanm	85:024bf7f99721	136	*/
bogdanm	85:024bf7f99721	137
bogdanm	85:024bf7f99721	138	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	85:024bf7f99721	139	/* --- CR Register ---*/
bogdanm	85:024bf7f99721	140	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	85:024bf7f99721	141	/* --- CFGR Register ---*/
bogdanm	85:024bf7f99721	142	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
bogdanm	85:024bf7f99721	143	/* --- CIR Register ---*/
bogdanm	85:024bf7f99721	144	#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	85:024bf7f99721	145	/* --- BDCR Register ---*/
bogdanm	85:024bf7f99721	146	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
bogdanm	85:024bf7f99721	147	/* --- CSR Register ---*/
bogdanm	85:024bf7f99721	148	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
bogdanm	85:024bf7f99721	149	/* --- CR2 Register ---*/
bogdanm	85:024bf7f99721	150	#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
bogdanm	85:024bf7f99721	151
bogdanm	85:024bf7f99721	152	/* CR register byte 2 (Bits[23:16]) base address */
bogdanm	85:024bf7f99721	153	#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
bogdanm	85:024bf7f99721	154
bogdanm	85:024bf7f99721	155	/* CIR register byte 1 (Bits[15:8]) base address */
bogdanm	85:024bf7f99721	156	#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
bogdanm	85:024bf7f99721	157
bogdanm	85:024bf7f99721	158	/* CIR register byte 2 (Bits[23:16]) base address */
bogdanm	85:024bf7f99721	159	#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
bogdanm	85:024bf7f99721	160
bogdanm	85:024bf7f99721	161	/* CSR register byte 1 (Bits[15:8]) base address */
bogdanm	85:024bf7f99721	162	#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
bogdanm	85:024bf7f99721	163
bogdanm	85:024bf7f99721	164	/* BDCR register byte 0 (Bits[7:0] base address */
bogdanm	85:024bf7f99721	165	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm	85:024bf7f99721	166
bogdanm	85:024bf7f99721	167	/* LSE state change timeout */
bogdanm	85:024bf7f99721	168	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	85:024bf7f99721	169
bogdanm	85:024bf7f99721	170	/* Disable Backup domain write protection state change timeout */
bogdanm	85:024bf7f99721	171	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	172
bogdanm	85:024bf7f99721	173	#define RCC_CFGR_PLLMUL_BITNUMBER 18
bogdanm	85:024bf7f99721	174	#define RCC_CFGR2_PREDIV_BITNUMBER 0
bogdanm	85:024bf7f99721	175
bogdanm	85:024bf7f99721	176	/** @defgroup RCC_Oscillator_Type
bogdanm	85:024bf7f99721	177	* @{
bogdanm	85:024bf7f99721	178	*/
bogdanm	85:024bf7f99721	179	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	180	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	181	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	182	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	183	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	184	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	185	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	186
bogdanm	85:024bf7f99721	187	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	85:024bf7f99721	188	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	85:024bf7f99721	189	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	85:024bf7f99721	190	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	85:024bf7f99721	191	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
bogdanm	85:024bf7f99721	192	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
bogdanm	85:024bf7f99721	193	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
bogdanm	85:024bf7f99721	194	/**
bogdanm	85:024bf7f99721	195	* @}
bogdanm	85:024bf7f99721	196	*/
bogdanm	85:024bf7f99721	197
bogdanm	85:024bf7f99721	198	/** @defgroup RCC_HSE_Config
bogdanm	85:024bf7f99721	199	* @{
bogdanm	85:024bf7f99721	200	*/
bogdanm	85:024bf7f99721	201	#define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	202	#define RCC_HSE_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	203	#define RCC_HSE_BYPASS ((uint8_t)0x05)
bogdanm	85:024bf7f99721	204
bogdanm	85:024bf7f99721	205	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
bogdanm	85:024bf7f99721	206	((HSE) == RCC_HSE_BYPASS))
bogdanm	85:024bf7f99721	207	/**
bogdanm	85:024bf7f99721	208	* @}
bogdanm	85:024bf7f99721	209	*/
bogdanm	85:024bf7f99721	210
bogdanm	85:024bf7f99721	211	/** @defgroup RCC_LSE_Config
bogdanm	85:024bf7f99721	212	* @{
bogdanm	85:024bf7f99721	213	*/
bogdanm	85:024bf7f99721	214	#define RCC_LSE_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	215	#define RCC_LSE_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	216	#define RCC_LSE_BYPASS ((uint8_t)0x05)
bogdanm	85:024bf7f99721	217
bogdanm	85:024bf7f99721	218	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
bogdanm	85:024bf7f99721	219	((LSE) == RCC_LSE_BYPASS))
bogdanm	85:024bf7f99721	220	/**
bogdanm	85:024bf7f99721	221	* @}
bogdanm	85:024bf7f99721	222	*/
bogdanm	85:024bf7f99721	223
bogdanm	85:024bf7f99721	224	/** @defgroup RCC_HSI_Config
bogdanm	85:024bf7f99721	225	* @{
bogdanm	85:024bf7f99721	226	*/
bogdanm	85:024bf7f99721	227	#define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	228	#define RCC_HSI_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	229
bogdanm	85:024bf7f99721	230	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
bogdanm	85:024bf7f99721	231
bogdanm	85:024bf7f99721	232	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	85:024bf7f99721	233	/**
bogdanm	85:024bf7f99721	234	* @}
bogdanm	85:024bf7f99721	235	*/
bogdanm	85:024bf7f99721	236
bogdanm	85:024bf7f99721	237	/** @defgroup RCC_HSI14_Config
bogdanm	85:024bf7f99721	238	* @{
bogdanm	85:024bf7f99721	239	*/
bogdanm	85:024bf7f99721	240	#define RCC_HSI14_OFF ((uint32_t)0x00)
bogdanm	85:024bf7f99721	241	#define RCC_HSI14_ON RCC_CR2_HSI14ON
bogdanm	85:024bf7f99721	242	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
bogdanm	85:024bf7f99721	243
bogdanm	85:024bf7f99721	244	#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) \|\| ((HSI14) == RCC_HSI14_ON) \|\| ((HSI14) == RCC_HSI14_ADC_CONTROL))
bogdanm	85:024bf7f99721	245
bogdanm	85:024bf7f99721	246	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
bogdanm	85:024bf7f99721	247	/**
bogdanm	85:024bf7f99721	248	* @}
bogdanm	85:024bf7f99721	249	*/
bogdanm	85:024bf7f99721	250
bogdanm	85:024bf7f99721	251	/** @defgroup RCC_LSI_Config
bogdanm	85:024bf7f99721	252	* @{
bogdanm	85:024bf7f99721	253	*/
bogdanm	85:024bf7f99721	254	#define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	255	#define RCC_LSI_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	256
bogdanm	85:024bf7f99721	257	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
bogdanm	85:024bf7f99721	258	/**
bogdanm	85:024bf7f99721	259	* @}
bogdanm	85:024bf7f99721	260	*/
bogdanm	85:024bf7f99721	261
bogdanm	85:024bf7f99721	262	/** @defgroup RCC_PLL_Config
bogdanm	85:024bf7f99721	263	* @{
bogdanm	85:024bf7f99721	264	*/
bogdanm	85:024bf7f99721	265	#define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm	85:024bf7f99721	266	#define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm	85:024bf7f99721	267	#define RCC_PLL_ON ((uint8_t)0x02)
bogdanm	85:024bf7f99721	268
bogdanm	85:024bf7f99721	269	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
bogdanm	85:024bf7f99721	270	/**
bogdanm	85:024bf7f99721	271	* @}
bogdanm	85:024bf7f99721	272	*/
bogdanm	85:024bf7f99721	273
bogdanm	85:024bf7f99721	274	/** @defgroup RCC_PLL_Prediv_Factor
bogdanm	85:024bf7f99721	275	* @{
bogdanm	85:024bf7f99721	276	*/
bogdanm	85:024bf7f99721	277	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm	85:024bf7f99721	278	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm	85:024bf7f99721	279	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm	85:024bf7f99721	280	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm	85:024bf7f99721	281	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm	85:024bf7f99721	282	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm	85:024bf7f99721	283	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm	85:024bf7f99721	284	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm	85:024bf7f99721	285	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm	85:024bf7f99721	286	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm	85:024bf7f99721	287	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm	85:024bf7f99721	288	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm	85:024bf7f99721	289	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm	85:024bf7f99721	290	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm	85:024bf7f99721	291	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm	85:024bf7f99721	292	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm	85:024bf7f99721	293
bogdanm	85:024bf7f99721	294	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
bogdanm	85:024bf7f99721	295	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
bogdanm	85:024bf7f99721	296	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
bogdanm	85:024bf7f99721	297	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
bogdanm	85:024bf7f99721	298	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
bogdanm	85:024bf7f99721	299	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
bogdanm	85:024bf7f99721	300	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
bogdanm	85:024bf7f99721	301	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
bogdanm	85:024bf7f99721	302	/**
bogdanm	85:024bf7f99721	303	* @}
bogdanm	85:024bf7f99721	304	*/
bogdanm	85:024bf7f99721	305
bogdanm	85:024bf7f99721	306	/** @defgroup RCC_PLL_Multiplication_Factor
bogdanm	85:024bf7f99721	307	* @{
bogdanm	85:024bf7f99721	308	*/
bogdanm	85:024bf7f99721	309	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm	85:024bf7f99721	310	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm	85:024bf7f99721	311	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm	85:024bf7f99721	312	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm	85:024bf7f99721	313	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm	85:024bf7f99721	314	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm	85:024bf7f99721	315	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm	85:024bf7f99721	316	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm	85:024bf7f99721	317	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm	85:024bf7f99721	318	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm	85:024bf7f99721	319	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm	85:024bf7f99721	320	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm	85:024bf7f99721	321	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm	85:024bf7f99721	322	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm	85:024bf7f99721	323	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm	85:024bf7f99721	324
bogdanm	85:024bf7f99721	325	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) \|\| ((MUL) == RCC_PLL_MUL3) \|\| \
bogdanm	85:024bf7f99721	326	((MUL) == RCC_PLL_MUL4) \|\| ((MUL) == RCC_PLL_MUL5) \|\| \
bogdanm	85:024bf7f99721	327	((MUL) == RCC_PLL_MUL6) \|\| ((MUL) == RCC_PLL_MUL7) \|\| \
bogdanm	85:024bf7f99721	328	((MUL) == RCC_PLL_MUL8) \|\| ((MUL) == RCC_PLL_MUL9) \|\| \
bogdanm	85:024bf7f99721	329	((MUL) == RCC_PLL_MUL10) \|\| ((MUL) == RCC_PLL_MUL11) \|\| \
bogdanm	85:024bf7f99721	330	((MUL) == RCC_PLL_MUL12) \|\| ((MUL) == RCC_PLL_MUL13) \|\| \
bogdanm	85:024bf7f99721	331	((MUL) == RCC_PLL_MUL14) \|\| ((MUL) == RCC_PLL_MUL15) \|\| \
bogdanm	85:024bf7f99721	332	((MUL) == RCC_PLL_MUL16))
bogdanm	85:024bf7f99721	333	/**
bogdanm	85:024bf7f99721	334	* @}
bogdanm	85:024bf7f99721	335	*/
bogdanm	85:024bf7f99721	336
bogdanm	85:024bf7f99721	337	/** @defgroup RCC_PLL_Clock_Source
bogdanm	85:024bf7f99721	338	* @{
bogdanm	85:024bf7f99721	339	*/
bogdanm	85:024bf7f99721	340	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
bogdanm	85:024bf7f99721	341	/**
bogdanm	85:024bf7f99721	342	* @}
bogdanm	85:024bf7f99721	343	*/
bogdanm	85:024bf7f99721	344
bogdanm	85:024bf7f99721	345	/** @defgroup RCC_System_Clock_Type
bogdanm	85:024bf7f99721	346	* @{
bogdanm	85:024bf7f99721	347	*/
bogdanm	85:024bf7f99721	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	351
bogdanm	85:024bf7f99721	352	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	353	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
bogdanm	85:024bf7f99721	354	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
bogdanm	85:024bf7f99721	355	/**
bogdanm	85:024bf7f99721	356	* @}
bogdanm	85:024bf7f99721	357	*/
bogdanm	85:024bf7f99721	358
bogdanm	85:024bf7f99721	359	/** @defgroup RCC_System_Clock_Source
bogdanm	85:024bf7f99721	360	* @{
bogdanm	85:024bf7f99721	361	*/
bogdanm	85:024bf7f99721	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm	85:024bf7f99721	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm	85:024bf7f99721	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm	85:024bf7f99721	365	/**
bogdanm	85:024bf7f99721	366	* @}
bogdanm	85:024bf7f99721	367	*/
bogdanm	85:024bf7f99721	368
bogdanm	85:024bf7f99721	369	/** @defgroup RCC_System_Clock_Source_Status
bogdanm	85:024bf7f99721	370	* @{
bogdanm	85:024bf7f99721	371	*/
bogdanm	85:024bf7f99721	372	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm	85:024bf7f99721	373	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm	85:024bf7f99721	374	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm	85:024bf7f99721	375	/**
bogdanm	85:024bf7f99721	376	* @}
bogdanm	85:024bf7f99721	377	*/
bogdanm	85:024bf7f99721	378
bogdanm	85:024bf7f99721	379	/** @defgroup RCC_AHB_Clock_Source
bogdanm	85:024bf7f99721	380	* @{
bogdanm	85:024bf7f99721	381	*/
bogdanm	85:024bf7f99721	382	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm	85:024bf7f99721	383	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm	85:024bf7f99721	384	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm	85:024bf7f99721	385	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm	85:024bf7f99721	386	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm	85:024bf7f99721	387	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm	85:024bf7f99721	388	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm	85:024bf7f99721	389	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm	85:024bf7f99721	390	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm	85:024bf7f99721	391
bogdanm	85:024bf7f99721	392	#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) \|\| ((DIV) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	393	((DIV) == RCC_SYSCLK_DIV4) \|\| ((DIV) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	85:024bf7f99721	394	((DIV) == RCC_SYSCLK_DIV16) \|\| ((DIV) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	85:024bf7f99721	395	((DIV) == RCC_SYSCLK_DIV128) \|\| ((DIV) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	85:024bf7f99721	396	((DIV) == RCC_SYSCLK_DIV512))
bogdanm	85:024bf7f99721	397	/**
bogdanm	85:024bf7f99721	398	* @}
bogdanm	85:024bf7f99721	399	*/
bogdanm	85:024bf7f99721	400
bogdanm	85:024bf7f99721	401	/** @defgroup RCC_APB1_Clock_Source
bogdanm	85:024bf7f99721	402	* @{
bogdanm	85:024bf7f99721	403	*/
bogdanm	85:024bf7f99721	404	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
bogdanm	85:024bf7f99721	405	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
bogdanm	85:024bf7f99721	406	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
bogdanm	85:024bf7f99721	407	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
bogdanm	85:024bf7f99721	408	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
bogdanm	85:024bf7f99721	409
bogdanm	85:024bf7f99721	410	#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) \|\| ((DIV) == RCC_HCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	411	((DIV) == RCC_HCLK_DIV4) \|\| ((DIV) == RCC_HCLK_DIV8) \|\| \
bogdanm	85:024bf7f99721	412	((DIV) == RCC_HCLK_DIV16))
bogdanm	85:024bf7f99721	413	/**
bogdanm	85:024bf7f99721	414	* @}
bogdanm	85:024bf7f99721	415	*/
bogdanm	85:024bf7f99721	416
bogdanm	85:024bf7f99721	417	/** @defgroup RCC_RTC_Clock_Source
bogdanm	85:024bf7f99721	418	* @{
bogdanm	85:024bf7f99721	419	*/
bogdanm	85:024bf7f99721	420	#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
bogdanm	85:024bf7f99721	421	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
bogdanm	85:024bf7f99721	422	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
bogdanm	85:024bf7f99721	423	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
bogdanm	85:024bf7f99721	424
bogdanm	85:024bf7f99721	425	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	426	((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	427	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	428	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm	85:024bf7f99721	429	/**
bogdanm	85:024bf7f99721	430	* @}
bogdanm	85:024bf7f99721	431	*/
bogdanm	85:024bf7f99721	432
bogdanm	85:024bf7f99721	433
bogdanm	85:024bf7f99721	434	/** @defgroup RCC_USART1_Clock_Source
bogdanm	85:024bf7f99721	435	* @{
bogdanm	85:024bf7f99721	436	*/
bogdanm	85:024bf7f99721	437	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm	85:024bf7f99721	438	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	85:024bf7f99721	439	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	85:024bf7f99721	440	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	85:024bf7f99721	441
bogdanm	85:024bf7f99721	442	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
bogdanm	85:024bf7f99721	443	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	444	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	445	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	85:024bf7f99721	446	/**
bogdanm	85:024bf7f99721	447	* @}
bogdanm	85:024bf7f99721	448	*/
bogdanm	85:024bf7f99721	449
bogdanm	85:024bf7f99721	450	/** @defgroup RCC_I2C1_Clock_Source
bogdanm	85:024bf7f99721	451	* @{
bogdanm	85:024bf7f99721	452	*/
bogdanm	85:024bf7f99721	453	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm	85:024bf7f99721	454	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm	85:024bf7f99721	455
bogdanm	85:024bf7f99721	456	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	457	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
bogdanm	85:024bf7f99721	458	/**
bogdanm	85:024bf7f99721	459	* @}
bogdanm	85:024bf7f99721	460	*/
bogdanm	85:024bf7f99721	461
bogdanm	85:024bf7f99721	462	/** @defgroup RCC_MCOx_Index
bogdanm	85:024bf7f99721	463	* @{
bogdanm	85:024bf7f99721	464	*/
bogdanm	85:024bf7f99721	465	#define RCC_MCO ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	466
bogdanm	85:024bf7f99721	467	#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
bogdanm	85:024bf7f99721	468	/**
bogdanm	85:024bf7f99721	469	* @}
bogdanm	85:024bf7f99721	470	*/
bogdanm	85:024bf7f99721	471
bogdanm	85:024bf7f99721	472	/** @defgroup RCC_MCO_Clock_Source
bogdanm	85:024bf7f99721	473	* @{
bogdanm	85:024bf7f99721	474	*/
bogdanm	85:024bf7f99721	475	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm	85:024bf7f99721	476	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	85:024bf7f99721	477	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	85:024bf7f99721	478	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	85:024bf7f99721	479	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	85:024bf7f99721	480	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	85:024bf7f99721	481	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm	85:024bf7f99721	482	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
bogdanm	85:024bf7f99721	483	/**
bogdanm	85:024bf7f99721	484	* @}
bogdanm	85:024bf7f99721	485	*/
bogdanm	85:024bf7f99721	486
bogdanm	85:024bf7f99721	487	/** @defgroup RCC_Interrupt
bogdanm	85:024bf7f99721	488	* @{
bogdanm	85:024bf7f99721	489	*/
bogdanm	85:024bf7f99721	490	#define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm	85:024bf7f99721	491	#define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm	85:024bf7f99721	492	#define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm	85:024bf7f99721	493	#define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm	85:024bf7f99721	494	#define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm	85:024bf7f99721	495	#define RCC_IT_HSI14 ((uint8_t)0x20)
bogdanm	85:024bf7f99721	496	#define RCC_IT_CSS ((uint8_t)0x80)
bogdanm	85:024bf7f99721	497	/**
bogdanm	85:024bf7f99721	498	* @}
bogdanm	85:024bf7f99721	499	*/
bogdanm	85:024bf7f99721	500
bogdanm	85:024bf7f99721	501	/** @defgroup RCC_Flag
bogdanm	85:024bf7f99721	502	* Elements values convention: 0XXYYYYYb
bogdanm	85:024bf7f99721	503	* - YYYYY : Flag position in the register
bogdanm	85:024bf7f99721	504	* - XX : Register index
bogdanm	85:024bf7f99721	505	* - 00: CR register
bogdanm	85:024bf7f99721	506	* - 01: CR2 register
bogdanm	85:024bf7f99721	507	* - 10: BDCR register
bogdanm	85:024bf7f99721	508	* - 11: CSR register
bogdanm	85:024bf7f99721	509	* @{
bogdanm	85:024bf7f99721	510	*/
bogdanm	85:024bf7f99721	511	#define CR_REG_INDEX 0
bogdanm	85:024bf7f99721	512	#define CR2_REG_INDEX 1
bogdanm	85:024bf7f99721	513	#define BDCR_REG_INDEX 2
bogdanm	85:024bf7f99721	514	#define CSR_REG_INDEX 3
bogdanm	85:024bf7f99721	515
bogdanm	85:024bf7f99721	516	/* Flags in the CR register */
bogdanm	85:024bf7f99721	517	#define RCC_CR_HSIRDY_BitNumber 1
bogdanm	85:024bf7f99721	518	#define RCC_CR_HSERDY_BitNumber 17
bogdanm	85:024bf7f99721	519	#define RCC_CR_PLLRDY_BitNumber 25
bogdanm	85:024bf7f99721	520
bogdanm	85:024bf7f99721	521	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
bogdanm	85:024bf7f99721	522	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
bogdanm	85:024bf7f99721	523	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
bogdanm	85:024bf7f99721	524
bogdanm	85:024bf7f99721	525	/* Flags in the CR2 register */
bogdanm	85:024bf7f99721	526	#define RCC_CR2_HSI14RDY_BitNumber 1
bogdanm	85:024bf7f99721	527
bogdanm	85:024bf7f99721	528	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
bogdanm	85:024bf7f99721	529
bogdanm	85:024bf7f99721	530	/* Flags in the BDCR register */
bogdanm	85:024bf7f99721	531	#define RCC_BDCR_LSERDY_BitNumber 1
bogdanm	85:024bf7f99721	532
bogdanm	85:024bf7f99721	533	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
bogdanm	85:024bf7f99721	534
bogdanm	85:024bf7f99721	535	/* Flags in the CSR register */
bogdanm	85:024bf7f99721	536	#define RCC_CSR_LSIRDY_BitNumber 1
bogdanm	85:024bf7f99721	537	#define RCC_CSR_V18PWRRSTF_BitNumber 23
bogdanm	85:024bf7f99721	538	#define RCC_CSR_RMVF_BitNumber 24
bogdanm	85:024bf7f99721	539	#define RCC_CSR_OBLRSTF_BitNumber 25
bogdanm	85:024bf7f99721	540	#define RCC_CSR_PINRSTF_BitNumber 26
bogdanm	85:024bf7f99721	541	#define RCC_CSR_PORRSTF_BitNumber 27
bogdanm	85:024bf7f99721	542	#define RCC_CSR_SFTRSTF_BitNumber 28
bogdanm	85:024bf7f99721	543	#define RCC_CSR_IWDGRSTF_BitNumber 29
bogdanm	85:024bf7f99721	544	#define RCC_CSR_WWDGRSTF_BitNumber 30
bogdanm	85:024bf7f99721	545	#define RCC_CSR_LPWRRSTF_BitNumber 31
bogdanm	85:024bf7f99721	546
bogdanm	85:024bf7f99721	547	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	85:024bf7f99721	548	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
bogdanm	85:024bf7f99721	549	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
bogdanm	85:024bf7f99721	550	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
bogdanm	85:024bf7f99721	551	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
bogdanm	85:024bf7f99721	552	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
bogdanm	85:024bf7f99721	553	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
bogdanm	85:024bf7f99721	554	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
bogdanm	85:024bf7f99721	555	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
bogdanm	85:024bf7f99721	556	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
bogdanm	85:024bf7f99721	557	/**
bogdanm	85:024bf7f99721	558	* @}
bogdanm	85:024bf7f99721	559	*/
bogdanm	85:024bf7f99721	560
bogdanm	85:024bf7f99721	561	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm	85:024bf7f99721	562
bogdanm	85:024bf7f99721	563	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm	85:024bf7f99721	564	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	565	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	566	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	85:024bf7f99721	567	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	568	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	569	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	85:024bf7f99721	570	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	85:024bf7f99721	571
bogdanm	85:024bf7f99721	572	/**
bogdanm	85:024bf7f99721	573	* @}
bogdanm	85:024bf7f99721	574	*/
bogdanm	85:024bf7f99721	575	/* Exported macro ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	576	/** @defgroup RCC_Exported_Macros
bogdanm	85:024bf7f99721	577	* @{
bogdanm	85:024bf7f99721	578	*/
bogdanm	85:024bf7f99721	579
bogdanm	85:024bf7f99721	580	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	85:024bf7f99721	581	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	582	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	583	* using it.
bogdanm	85:024bf7f99721	584	*/
bogdanm	85:024bf7f99721	585	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
bogdanm	85:024bf7f99721	586	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
bogdanm	85:024bf7f99721	587	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
bogdanm	85:024bf7f99721	588	#define __GPIOF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOFEN))
bogdanm	85:024bf7f99721	589	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
bogdanm	85:024bf7f99721	590	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
bogdanm	85:024bf7f99721	591	#define __SRAM_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_SRAMEN))
bogdanm	85:024bf7f99721	592	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
bogdanm	85:024bf7f99721	593
bogdanm	85:024bf7f99721	594	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
bogdanm	85:024bf7f99721	595	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
bogdanm	85:024bf7f99721	596	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
bogdanm	85:024bf7f99721	597	#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
bogdanm	85:024bf7f99721	598	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm	85:024bf7f99721	599	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm	85:024bf7f99721	600	#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm	85:024bf7f99721	601	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	85:024bf7f99721	602
bogdanm	85:024bf7f99721	603	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	604	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	605	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	606	* using it.
bogdanm	85:024bf7f99721	607	*/
bogdanm	85:024bf7f99721	608	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	85:024bf7f99721	609	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
bogdanm	85:024bf7f99721	610	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	85:024bf7f99721	611	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	85:024bf7f99721	612	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
bogdanm	85:024bf7f99721	613
bogdanm	85:024bf7f99721	614	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	85:024bf7f99721	615	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	85:024bf7f99721	616	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	85:024bf7f99721	617	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	85:024bf7f99721	618	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	85:024bf7f99721	619
bogdanm	85:024bf7f99721	620	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	621	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	622	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	623	* using it.
bogdanm	85:024bf7f99721	624	*/
bogdanm	85:024bf7f99721	625	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
bogdanm	85:024bf7f99721	626	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	85:024bf7f99721	627	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
bogdanm	85:024bf7f99721	628	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	85:024bf7f99721	629	#define __TIM16_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM16EN))
bogdanm	85:024bf7f99721	630	#define __TIM17_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM17EN))
bogdanm	85:024bf7f99721	631	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	85:024bf7f99721	632	#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
bogdanm	85:024bf7f99721	633
bogdanm	85:024bf7f99721	634	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm	85:024bf7f99721	635	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	85:024bf7f99721	636	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	85:024bf7f99721	637	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	85:024bf7f99721	638	#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
bogdanm	85:024bf7f99721	639	#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
bogdanm	85:024bf7f99721	640	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	85:024bf7f99721	641	#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
bogdanm	85:024bf7f99721	642
bogdanm	85:024bf7f99721	643	/** @brief Force or release AHB peripheral reset.
bogdanm	85:024bf7f99721	644	*/
bogdanm	85:024bf7f99721	645	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm	85:024bf7f99721	646	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
bogdanm	85:024bf7f99721	647	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
bogdanm	85:024bf7f99721	648	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
bogdanm	85:024bf7f99721	649	#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
bogdanm	85:024bf7f99721	650
bogdanm	85:024bf7f99721	651	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm	85:024bf7f99721	652	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
bogdanm	85:024bf7f99721	653	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
bogdanm	85:024bf7f99721	654	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
bogdanm	85:024bf7f99721	655	#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm	85:024bf7f99721	656
bogdanm	85:024bf7f99721	657	/** @brief Force or release APB1 peripheral reset.
bogdanm	85:024bf7f99721	658	*/
bogdanm	85:024bf7f99721	659	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	85:024bf7f99721	660	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	85:024bf7f99721	661	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	85:024bf7f99721	662	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	85:024bf7f99721	663	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	85:024bf7f99721	664	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	85:024bf7f99721	665
bogdanm	85:024bf7f99721	666	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	85:024bf7f99721	667	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	85:024bf7f99721	668	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	85:024bf7f99721	669	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	85:024bf7f99721	670	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	85:024bf7f99721	671	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	85:024bf7f99721	672
bogdanm	85:024bf7f99721	673	/** @brief Force or release APB2 peripheral reset.
bogdanm	85:024bf7f99721	674	*/
bogdanm	85:024bf7f99721	675	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	85:024bf7f99721	676	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	85:024bf7f99721	677	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	85:024bf7f99721	678	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	85:024bf7f99721	679	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	85:024bf7f99721	680	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	85:024bf7f99721	681	#define __TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
bogdanm	85:024bf7f99721	682	#define __TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
bogdanm	85:024bf7f99721	683	#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
bogdanm	85:024bf7f99721	684
bogdanm	85:024bf7f99721	685	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	85:024bf7f99721	686	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm	85:024bf7f99721	687	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm	85:024bf7f99721	688	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	85:024bf7f99721	689	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	85:024bf7f99721	690	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	85:024bf7f99721	691	#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
bogdanm	85:024bf7f99721	692	#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
bogdanm	85:024bf7f99721	693	#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
bogdanm	85:024bf7f99721	694
bogdanm	85:024bf7f99721	695	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	85:024bf7f99721	696	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	697	* It is used (enabled by hardware) as system clock source after startup
bogdanm	85:024bf7f99721	698	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	85:024bf7f99721	699	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	85:024bf7f99721	700	* Security System CSS is enabled).
bogdanm	85:024bf7f99721	701	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	702	* you have to select another source of the system clock then stop the HSI.
bogdanm	85:024bf7f99721	703	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	85:024bf7f99721	704	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	85:024bf7f99721	705	* system clock source.
bogdanm	85:024bf7f99721	706	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	85:024bf7f99721	707	* clock cycles.
bogdanm	85:024bf7f99721	708	*/
bogdanm	85:024bf7f99721	709	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	85:024bf7f99721	710	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	85:024bf7f99721	711
bogdanm	85:024bf7f99721	712
bogdanm	85:024bf7f99721	713	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	85:024bf7f99721	714	* @note The calibration is used to compensate for the variations in voltage
bogdanm	85:024bf7f99721	715	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	85:024bf7f99721	716	* @param __HSICalibrationValue__: specifies the calibration trimming value
bogdanm	85:024bf7f99721	717	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	718	* This parameter must be a number between 0 and 0x1F.
bogdanm	85:024bf7f99721	719	*/
bogdanm	85:024bf7f99721	720	#define RCC_CR_HSITRIM_BitNumber 3
bogdanm	85:024bf7f99721	721	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
bogdanm	85:024bf7f99721	722	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
bogdanm	85:024bf7f99721	723
bogdanm	85:024bf7f99721	724	/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	85:024bf7f99721	725	* @note After enabling the LSI, the application software should wait on
bogdanm	85:024bf7f99721	726	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	85:024bf7f99721	727	* be used to clock the IWDG and/or the RTC.
bogdanm	85:024bf7f99721	728	* @note LSI can not be disabled if the IWDG is running.
bogdanm	85:024bf7f99721	729	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	85:024bf7f99721	730	* clock cycles.
bogdanm	85:024bf7f99721	731	*/
bogdanm	85:024bf7f99721	732	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	85:024bf7f99721	733	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	85:024bf7f99721	734
bogdanm	85:024bf7f99721	735	/**
bogdanm	85:024bf7f99721	736	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	85:024bf7f99721	737	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	85:024bf7f99721	738	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	85:024bf7f99721	739	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	85:024bf7f99721	740	* @note HSE state can not be changed if it is used directly or through the
bogdanm	85:024bf7f99721	741	* PLL as system clock. In this case, you have to select another source
bogdanm	85:024bf7f99721	742	* of the system clock then change the HSE state (ex. disable it).
bogdanm	85:024bf7f99721	743	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	744	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm	85:024bf7f99721	745	* was previously enabled you have to enable it again after calling this
bogdanm	85:024bf7f99721	746	* function.
bogdanm	85:024bf7f99721	747	* @param __STATE__: specifies the new state of the HSE.
bogdanm	85:024bf7f99721	748	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	749	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	85:024bf7f99721	750	* 6 HSE oscillator clock cycles.
bogdanm	85:024bf7f99721	751	* @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm	85:024bf7f99721	752	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm	85:024bf7f99721	753	*/
bogdanm	85:024bf7f99721	754	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t )RCC_CR_BYTE2_ADDRESS = (__STATE__))
bogdanm	85:024bf7f99721	755
bogdanm	85:024bf7f99721	756	/**
bogdanm	85:024bf7f99721	757	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm	85:024bf7f99721	758	* @note Predivision factor can not be changed if PLL is used as system clock
bogdanm	85:024bf7f99721	759	* In this case, you have to select another source of the system clock, disable the PLL and
bogdanm	85:024bf7f99721	760	* then change the HSE predivision factor.
bogdanm	85:024bf7f99721	761	* @param __HSEPredivValue__: specifies the division value applied to HSE.
bogdanm	85:024bf7f99721	762	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm	85:024bf7f99721	763	*/
bogdanm	85:024bf7f99721	764	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
bogdanm	85:024bf7f99721	765	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
bogdanm	85:024bf7f99721	766
bogdanm	85:024bf7f99721	767	/**
bogdanm	85:024bf7f99721	768	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	85:024bf7f99721	769	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	85:024bf7f99721	770	* this domain after reset, you have to enable write access using
bogdanm	85:024bf7f99721	771	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	85:024bf7f99721	772	* (to be done once after reset).
bogdanm	85:024bf7f99721	773	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	85:024bf7f99721	774	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	85:024bf7f99721	775	* is stable and can be used to clock the RTC.
bogdanm	85:024bf7f99721	776	* @param __STATE__: specifies the new state of the LSE.
bogdanm	85:024bf7f99721	777	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	778	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	85:024bf7f99721	779	* 6 LSE oscillator clock cycles.
bogdanm	85:024bf7f99721	780	* @arg RCC_LSE_ON: turn ON the LSE oscillator
bogdanm	85:024bf7f99721	781	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
bogdanm	85:024bf7f99721	782	*/
bogdanm	85:024bf7f99721	783	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	85:024bf7f99721	784	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON\|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
bogdanm	85:024bf7f99721	785
bogdanm	85:024bf7f99721	786	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
bogdanm	85:024bf7f99721	787	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	788	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	789	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	790	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
bogdanm	85:024bf7f99721	791	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
bogdanm	85:024bf7f99721	792	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	793	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
bogdanm	85:024bf7f99721	794	* clock cycles.
bogdanm	85:024bf7f99721	795	*/
bogdanm	85:024bf7f99721	796	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	85:024bf7f99721	797	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm	85:024bf7f99721	798
bogdanm	85:024bf7f99721	799	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
bogdanm	85:024bf7f99721	800	*/
bogdanm	85:024bf7f99721	801	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	85:024bf7f99721	802	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm	85:024bf7f99721	803
bogdanm	85:024bf7f99721	804
bogdanm	85:024bf7f99721	805	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
bogdanm	85:024bf7f99721	806	* @note The calibration is used to compensate for the variations in voltage
bogdanm	85:024bf7f99721	807	* and temperature that influence the frequency of the internal HSI14 RC.
bogdanm	85:024bf7f99721	808	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
bogdanm	85:024bf7f99721	809	* (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm	85:024bf7f99721	810	* This parameter must be a number between 0 and 0x1F.
bogdanm	85:024bf7f99721	811	*/
bogdanm	85:024bf7f99721	812	#define RCC_CR2_HSI14TRIM_BitNumber 3
bogdanm	85:024bf7f99721	813	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
bogdanm	85:024bf7f99721	814	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
bogdanm	85:024bf7f99721	815
bogdanm	85:024bf7f99721	816	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	85:024bf7f99721	817	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	85:024bf7f99721	818	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	819	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	85:024bf7f99721	820	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	85:024bf7f99721	821	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	85:024bf7f99721	822	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	85:024bf7f99721	823	*/
bogdanm	85:024bf7f99721	824	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	85:024bf7f99721	825	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm	85:024bf7f99721	826
bogdanm	85:024bf7f99721	827	/** @brief Macro to get the USART1 clock source.
bogdanm	85:024bf7f99721	828	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	829	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
bogdanm	85:024bf7f99721	830	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	85:024bf7f99721	831	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	85:024bf7f99721	832	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	85:024bf7f99721	833	*/
bogdanm	85:024bf7f99721	834	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm	85:024bf7f99721	835
bogdanm	85:024bf7f99721	836	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	85:024bf7f99721	837	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	85:024bf7f99721	838	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	839	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	85:024bf7f99721	840	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	85:024bf7f99721	841	*/
bogdanm	85:024bf7f99721	842	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	85:024bf7f99721	843	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm	85:024bf7f99721	844
bogdanm	85:024bf7f99721	845	/** @brief Macro to get the I2C1 clock source.
bogdanm	85:024bf7f99721	846	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	847	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	85:024bf7f99721	848	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	85:024bf7f99721	849	*/
bogdanm	85:024bf7f99721	850	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm	85:024bf7f99721	851
bogdanm	85:024bf7f99721	852	/** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm	85:024bf7f99721	853	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	85:024bf7f99721	854	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	855	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	85:024bf7f99721	856	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	85:024bf7f99721	857	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	85:024bf7f99721	858	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	85:024bf7f99721	859	*/
bogdanm	85:024bf7f99721	860	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	85:024bf7f99721	861	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
bogdanm	85:024bf7f99721	862
bogdanm	85:024bf7f99721	863	/** @brief Macro to get the USART2 clock source.
bogdanm	85:024bf7f99721	864	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	865	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	85:024bf7f99721	866	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	85:024bf7f99721	867	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	85:024bf7f99721	868	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	85:024bf7f99721	869	*/
bogdanm	85:024bf7f99721	870	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
bogdanm	85:024bf7f99721	871
bogdanm	85:024bf7f99721	872	/** @brief Macros to enable or disable the the RTC clock.
bogdanm	85:024bf7f99721	873	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	85:024bf7f99721	874	*/
bogdanm	85:024bf7f99721	875	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	85:024bf7f99721	876	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm	85:024bf7f99721	877
bogdanm	85:024bf7f99721	878	/** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm	85:024bf7f99721	879	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	85:024bf7f99721	880	* access is denied to this domain after reset, you have to enable write
bogdanm	85:024bf7f99721	881	* access using the Power Backup Access macro before to configure
bogdanm	85:024bf7f99721	882	* the RTC clock source (to be done once after reset).
bogdanm	85:024bf7f99721	883	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	85:024bf7f99721	884	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm	85:024bf7f99721	885	* a Power On Reset (POR).
bogdanm	85:024bf7f99721	886	* @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm	85:024bf7f99721	887	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	888	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm	85:024bf7f99721	889	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	85:024bf7f99721	890	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	85:024bf7f99721	891	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm	85:024bf7f99721	892	*
bogdanm	85:024bf7f99721	893	* @note If the LSE is used as RTC clock source, the RTC continues to
bogdanm	85:024bf7f99721	894	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	85:024bf7f99721	895	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm	85:024bf7f99721	896	* the RTC cannot be used in STOP and STANDBY modes.
bogdanm	85:024bf7f99721	897	* @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm	85:024bf7f99721	898	* equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm	85:024bf7f99721	899	*/
bogdanm	85:024bf7f99721	900	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
bogdanm	85:024bf7f99721	901	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
bogdanm	85:024bf7f99721	902
bogdanm	85:024bf7f99721	903	/** @brief Macro to get the RTC clock source.
bogdanm	85:024bf7f99721	904	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	905	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm	85:024bf7f99721	906	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	85:024bf7f99721	907	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	85:024bf7f99721	908	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
bogdanm	85:024bf7f99721	909	*/
bogdanm	85:024bf7f99721	910	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
bogdanm	85:024bf7f99721	911
bogdanm	85:024bf7f99721	912	/** @brief Macro to force or release the Backup domain reset.
bogdanm	85:024bf7f99721	913	* @note These macros reset the RTC peripheral (including the backup registers)
bogdanm	85:024bf7f99721	914	* and the RTC clock source selection in RCC_CSR register.
bogdanm	85:024bf7f99721	915	* @note The BKPSRAM is not affected by this reset.
bogdanm	85:024bf7f99721	916	*/
bogdanm	85:024bf7f99721	917	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	85:024bf7f99721	918	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
bogdanm	85:024bf7f99721	919
bogdanm	85:024bf7f99721	920	/** @brief Macro to enable or disable the PLL.
bogdanm	85:024bf7f99721	921	* @note After enabling the PLL, the application software should wait on
bogdanm	85:024bf7f99721	922	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	85:024bf7f99721	923	* be used as system clock source.
bogdanm	85:024bf7f99721	924	* @note The PLL can not be disabled if it is used as system clock source
bogdanm	85:024bf7f99721	925	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	926	*/
bogdanm	85:024bf7f99721	927	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	85:024bf7f99721	928	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	85:024bf7f99721	929
bogdanm	85:024bf7f99721	930	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
bogdanm	85:024bf7f99721	931	* @note This macro must be used only when the PLL is disabled.
bogdanm	85:024bf7f99721	932	*
bogdanm	85:024bf7f99721	933	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	85:024bf7f99721	934	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	935	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	85:024bf7f99721	936	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	85:024bf7f99721	937	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
bogdanm	85:024bf7f99721	938	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
bogdanm	85:024bf7f99721	939	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
bogdanm	85:024bf7f99721	940	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm	85:024bf7f99721	941	*
bogdanm	85:024bf7f99721	942	*/
bogdanm	85:024bf7f99721	943	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
bogdanm	85:024bf7f99721	944	do { \
bogdanm	85:024bf7f99721	945	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
bogdanm	85:024bf7f99721	946	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
bogdanm	85:024bf7f99721	947	} while(0)
bogdanm	85:024bf7f99721	948
bogdanm	85:024bf7f99721	949
bogdanm	85:024bf7f99721	950	/** @brief Macro to get the clock source used as system clock.
bogdanm	85:024bf7f99721	951	* @retval The clock source used as system clock.
bogdanm	85:024bf7f99721	952	* The returned value can be one of the following value:
bogdanm	85:024bf7f99721	953	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm	85:024bf7f99721	954	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm	85:024bf7f99721	955	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm	85:024bf7f99721	956	*/
bogdanm	85:024bf7f99721	957	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
bogdanm	85:024bf7f99721	958
bogdanm	85:024bf7f99721	959	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	85:024bf7f99721	960	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	85:024bf7f99721	961	* of the following:
bogdanm	85:024bf7f99721	962	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	85:024bf7f99721	963	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	85:024bf7f99721	964	*/
bogdanm	85:024bf7f99721	965	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
bogdanm	85:024bf7f99721	966
bogdanm	85:024bf7f99721	967	/**
bogdanm	85:024bf7f99721	968	* @}
bogdanm	85:024bf7f99721	969	*/
bogdanm	85:024bf7f99721	970
bogdanm	85:024bf7f99721	971	/** @defgroup RCC_Flags_Interrupts_Management
bogdanm	85:024bf7f99721	972	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	85:024bf7f99721	973	* @{
bogdanm	85:024bf7f99721	974	*/
bogdanm	85:024bf7f99721	975
bogdanm	85:024bf7f99721	976	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
bogdanm	85:024bf7f99721	977	* the selected interrupts.).
bogdanm	85:024bf7f99721	978	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	85:024bf7f99721	979	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	980	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
bogdanm	85:024bf7f99721	981	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
bogdanm	85:024bf7f99721	982	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
bogdanm	85:024bf7f99721	983	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
bogdanm	85:024bf7f99721	984	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
bogdanm	85:024bf7f99721	985	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	85:024bf7f99721	986	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	987	*/
bogdanm	85:024bf7f99721	988	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	989
bogdanm	85:024bf7f99721	990	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
bogdanm	85:024bf7f99721	991	* the selected interrupts.).
bogdanm	85:024bf7f99721	992	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	85:024bf7f99721	993	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	994	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
bogdanm	85:024bf7f99721	995	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
bogdanm	85:024bf7f99721	996	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
bogdanm	85:024bf7f99721	997	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
bogdanm	85:024bf7f99721	998	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
bogdanm	85:024bf7f99721	999	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
bogdanm	85:024bf7f99721	1000	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1001	*/
bogdanm	85:024bf7f99721	1002	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	1003
bogdanm	85:024bf7f99721	1004	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
bogdanm	85:024bf7f99721	1005	* bits to clear the selected interrupt pending bits.
bogdanm	85:024bf7f99721	1006	* @param __IT__: specifies the interrupt pending bit to clear.
bogdanm	85:024bf7f99721	1007	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1008	* @arg RCC_IT_LSIRDY: LSI ready interrupt clear
bogdanm	85:024bf7f99721	1009	* @arg RCC_IT_LSERDY: LSE ready interrupt clear
bogdanm	85:024bf7f99721	1010	* @arg RCC_IT_HSIRDY: HSI ready interrupt clear
bogdanm	85:024bf7f99721	1011	* @arg RCC_IT_HSERDY: HSE ready interrupt clear
bogdanm	85:024bf7f99721	1012	* @arg RCC_IT_PLLRDY: PLL ready interrupt clear
bogdanm	85:024bf7f99721	1013	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
bogdanm	85:024bf7f99721	1014	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1015	* @arg RCC_IT_CSS: Clock Security System interrupt clear
bogdanm	85:024bf7f99721	1016	*/
bogdanm	85:024bf7f99721	1017	#define __HAL_RCC_CLEAR_IT(__IT__) ((__IO uint8_t )RCC_CIR_BYTE2_ADDRESS = (__IT__))
bogdanm	85:024bf7f99721	1018
bogdanm	85:024bf7f99721	1019	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	85:024bf7f99721	1020	* @param __IT__: specifies the RCC interrupt source to check.
bogdanm	85:024bf7f99721	1021	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1022	* @arg RCC_IT_LSIRDY: LSI ready interrupt flag
bogdanm	85:024bf7f99721	1023	* @arg RCC_IT_LSERDY: LSE ready interrupt flag
bogdanm	85:024bf7f99721	1024	* @arg RCC_IT_HSIRDY: HSI ready interrupt flag
bogdanm	85:024bf7f99721	1025	* @arg RCC_IT_HSERDY: HSE ready interrupt flag
bogdanm	85:024bf7f99721	1026	* @arg RCC_IT_PLLRDY: PLL ready interrupt flag
bogdanm	85:024bf7f99721	1027	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
bogdanm	85:024bf7f99721	1028	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1029	* @arg RCC_IT_CSS: Clock Security System interrupt flag
bogdanm	85:024bf7f99721	1030	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1031	*/
bogdanm	85:024bf7f99721	1032	#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
bogdanm	85:024bf7f99721	1033
bogdanm	85:024bf7f99721	1034	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm	85:024bf7f99721	1035	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	85:024bf7f99721	1036	*/
bogdanm	85:024bf7f99721	1037	#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
bogdanm	85:024bf7f99721	1038
bogdanm	85:024bf7f99721	1039	/** @brief Check RCC flag is set or not.
bogdanm	85:024bf7f99721	1040	* @param __FLAG__: specifies the flag to check.
bogdanm	85:024bf7f99721	1041	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1042	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm	85:024bf7f99721	1043	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm	85:024bf7f99721	1044	* @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm	85:024bf7f99721	1045	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
bogdanm	85:024bf7f99721	1046	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
bogdanm	85:024bf7f99721	1047	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm	85:024bf7f99721	1048	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm	85:024bf7f99721	1049	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
bogdanm	85:024bf7f99721	1050	* @arg RCC_FLAG_PINRST: Pin reset
bogdanm	85:024bf7f99721	1051	* @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm	85:024bf7f99721	1052	* @arg RCC_FLAG_SFTRST: Software reset
bogdanm	85:024bf7f99721	1053	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm	85:024bf7f99721	1054	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm	85:024bf7f99721	1055	* @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm	85:024bf7f99721	1056	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1057	*/
bogdanm	85:024bf7f99721	1058	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	85:024bf7f99721	1059	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
bogdanm	85:024bf7f99721	1060	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
bogdanm	85:024bf7f99721	1061	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm	85:024bf7f99721	1062	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	85:024bf7f99721	1063
bogdanm	85:024bf7f99721	1064
bogdanm	85:024bf7f99721	1065
bogdanm	85:024bf7f99721	1066	/**
bogdanm	85:024bf7f99721	1067	* @}
bogdanm	85:024bf7f99721	1068	*/
bogdanm	85:024bf7f99721	1069
bogdanm	85:024bf7f99721	1070	/* Include RCC HAL Extension module */
bogdanm	85:024bf7f99721	1071	#include "stm32f0xx_hal_rcc_ex.h"
bogdanm	85:024bf7f99721	1072
bogdanm	85:024bf7f99721	1073	/* Exported functions --------------------------------------------------------*/
bogdanm	85:024bf7f99721	1074
bogdanm	85:024bf7f99721	1075	/* Initialization and de-initialization functions ***************************/
bogdanm	85:024bf7f99721	1076	void HAL_RCC_DeInit(void);
bogdanm	85:024bf7f99721	1077	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	85:024bf7f99721	1078	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	85:024bf7f99721	1079
bogdanm	85:024bf7f99721	1080	/* Peripheral Control functions *********************************************/
bogdanm	85:024bf7f99721	1081	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	85:024bf7f99721	1082	void HAL_RCC_EnableCSS(void);
bogdanm	85:024bf7f99721	1083	void HAL_RCC_DisableCSS(void);
bogdanm	85:024bf7f99721	1084	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	85:024bf7f99721	1085	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	85:024bf7f99721	1086	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	85:024bf7f99721	1087	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	85:024bf7f99721	1088	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	85:024bf7f99721	1089
bogdanm	85:024bf7f99721	1090	/* CSS NMI IRQ handler */
bogdanm	85:024bf7f99721	1091	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	85:024bf7f99721	1092
bogdanm	85:024bf7f99721	1093	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	85:024bf7f99721	1094	void HAL_RCC_CCSCallback(void);
bogdanm	85:024bf7f99721	1095
bogdanm	85:024bf7f99721	1096	/**
bogdanm	85:024bf7f99721	1097	* @}
bogdanm	85:024bf7f99721	1098	*/
bogdanm	85:024bf7f99721	1099
bogdanm	85:024bf7f99721	1100	/**
bogdanm	85:024bf7f99721	1101	* @}
bogdanm	85:024bf7f99721	1102	*/
bogdanm	85:024bf7f99721	1103
bogdanm	85:024bf7f99721	1104	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1105	}
bogdanm	85:024bf7f99721	1106	#endif
bogdanm	85:024bf7f99721	1107
bogdanm	85:024bf7f99721	1108	#endif /* __STM32F0xx_HAL_RCC_H */
bogdanm	85:024bf7f99721	1109
bogdanm	85:024bf7f99721	1110	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jun 2014
Imports:	10
Forks:	0
Commits:	87
Dependents:	1
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@85:024bf7f99721, 2014-06-11 (annotated)

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