Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_NUCLEO_F042K6/stm32f042x6.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
109:9296ab0bfc11 
.

Who changed what in which revision?

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Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f042x6.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V2.2.2
Kojto 109:9296ab0bfc11 6 * @date 26-June-2015
Kojto 109:9296ab0bfc11 7 * @brief CMSIS STM32F042x4/STM32F042x6 Devices Peripheral Access Layer Header File.
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 * This file contains:
Kojto 109:9296ab0bfc11 10 * - Data structures and the address mapping for all peripherals
Kojto 109:9296ab0bfc11 11 * - Peripheral's registers declarations and bits definition
Kojto 109:9296ab0bfc11 12 * - Macros to access peripheral’s registers hardware
Kojto 109:9296ab0bfc11 13 *
Kojto 109:9296ab0bfc11 14 ******************************************************************************
Kojto 109:9296ab0bfc11 15 * @attention
Kojto 109:9296ab0bfc11 16 *
Kojto 109:9296ab0bfc11 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 18 *
Kojto 109:9296ab0bfc11 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 20 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 22 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 24 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 25 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 27 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 28 * without specific prior written permission.
Kojto 109:9296ab0bfc11 29 *
Kojto 109:9296ab0bfc11 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 40 *
Kojto 109:9296ab0bfc11 41 ******************************************************************************
Kojto 109:9296ab0bfc11 42 */
Kojto 109:9296ab0bfc11 43
Kojto 109:9296ab0bfc11 44 /** @addtogroup CMSIS_Device
Kojto 109:9296ab0bfc11 45 * @{
Kojto 109:9296ab0bfc11 46 */
Kojto 109:9296ab0bfc11 47
Kojto 109:9296ab0bfc11 48 /** @addtogroup stm32f042x6
Kojto 109:9296ab0bfc11 49 * @{
Kojto 109:9296ab0bfc11 50 */
Kojto 109:9296ab0bfc11 51
Kojto 109:9296ab0bfc11 52 #ifndef __STM32F042x6_H
Kojto 109:9296ab0bfc11 53 #define __STM32F042x6_H
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 56 extern "C" {
Kojto 109:9296ab0bfc11 57 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62 /**
Kojto 109:9296ab0bfc11 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 109:9296ab0bfc11 64 */
Kojto 109:9296ab0bfc11 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 109:9296ab0bfc11 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 109:9296ab0bfc11 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 109:9296ab0bfc11 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 109:9296ab0bfc11 69
Kojto 109:9296ab0bfc11 70 /**
Kojto 109:9296ab0bfc11 71 * @}
Kojto 109:9296ab0bfc11 72 */
Kojto 109:9296ab0bfc11 73
Kojto 109:9296ab0bfc11 74 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 109:9296ab0bfc11 75 * @{
Kojto 109:9296ab0bfc11 76 */
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78 /**
Kojto 109:9296ab0bfc11 79 * @brief STM32F042x4/STM32F042x6 device Interrupt Number Definition
Kojto 109:9296ab0bfc11 80 */
Kojto 109:9296ab0bfc11 81 typedef enum
Kojto 109:9296ab0bfc11 82 {
Kojto 109:9296ab0bfc11 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 109:9296ab0bfc11 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 109:9296ab0bfc11 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 109:9296ab0bfc11 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 109:9296ab0bfc11 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 109:9296ab0bfc11 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 109:9296ab0bfc11 89
Kojto 109:9296ab0bfc11 90 /****** STM32F042x4/STM32F042x6 specific Interrupt Numbers **************************************************/
Kojto 109:9296ab0bfc11 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 109:9296ab0bfc11 92 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
Kojto 109:9296ab0bfc11 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 109:9296ab0bfc11 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 109:9296ab0bfc11 95 RCC_CRS_IRQn = 4, /*!< RCC & CRS Global Interrupts */
Kojto 109:9296ab0bfc11 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Kojto 109:9296ab0bfc11 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Kojto 109:9296ab0bfc11 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Kojto 109:9296ab0bfc11 99 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
Kojto 109:9296ab0bfc11 100 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 109:9296ab0bfc11 101 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
Kojto 109:9296ab0bfc11 102 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
Kojto 109:9296ab0bfc11 103 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
Kojto 109:9296ab0bfc11 104 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
Kojto 109:9296ab0bfc11 105 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 109:9296ab0bfc11 106 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
Kojto 109:9296ab0bfc11 107 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 109:9296ab0bfc11 108 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 109:9296ab0bfc11 109 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 109:9296ab0bfc11 110 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 109:9296ab0bfc11 111 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 109:9296ab0bfc11 112 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 109:9296ab0bfc11 113 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Kojto 109:9296ab0bfc11 114 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Kojto 109:9296ab0bfc11 115 USART2_IRQn = 28, /*!< USART2 global Interrupt */
Kojto 109:9296ab0bfc11 116 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
Kojto 109:9296ab0bfc11 117 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
Kojto 109:9296ab0bfc11 118 } IRQn_Type;
Kojto 109:9296ab0bfc11 119
Kojto 109:9296ab0bfc11 120 /**
Kojto 109:9296ab0bfc11 121 * @}
Kojto 109:9296ab0bfc11 122 */
Kojto 109:9296ab0bfc11 123
Kojto 109:9296ab0bfc11 124 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 109:9296ab0bfc11 125 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 109:9296ab0bfc11 126 #include <stdint.h>
Kojto 109:9296ab0bfc11 127
Kojto 109:9296ab0bfc11 128 /** @addtogroup Peripheral_registers_structures
Kojto 109:9296ab0bfc11 129 * @{
Kojto 109:9296ab0bfc11 130 */
Kojto 109:9296ab0bfc11 131
Kojto 109:9296ab0bfc11 132 /**
Kojto 109:9296ab0bfc11 133 * @brief Analog to Digital Converter
Kojto 109:9296ab0bfc11 134 */
Kojto 109:9296ab0bfc11 135
Kojto 109:9296ab0bfc11 136 typedef struct
Kojto 109:9296ab0bfc11 137 {
Kojto 109:9296ab0bfc11 138 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Kojto 109:9296ab0bfc11 139 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Kojto 109:9296ab0bfc11 140 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Kojto 109:9296ab0bfc11 141 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Kojto 109:9296ab0bfc11 142 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Kojto 109:9296ab0bfc11 143 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Kojto 109:9296ab0bfc11 144 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 145 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 109:9296ab0bfc11 146 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Kojto 109:9296ab0bfc11 147 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 109:9296ab0bfc11 148 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Kojto 109:9296ab0bfc11 149 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 109:9296ab0bfc11 150 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Kojto 109:9296ab0bfc11 151 }ADC_TypeDef;
Kojto 109:9296ab0bfc11 152
Kojto 109:9296ab0bfc11 153 typedef struct
Kojto 109:9296ab0bfc11 154 {
Kojto 109:9296ab0bfc11 155 __IO uint32_t CCR;
Kojto 109:9296ab0bfc11 156 }ADC_Common_TypeDef;
Kojto 109:9296ab0bfc11 157
Kojto 109:9296ab0bfc11 158 /**
Kojto 109:9296ab0bfc11 159 * @brief Controller Area Network TxMailBox
Kojto 109:9296ab0bfc11 160 */
Kojto 109:9296ab0bfc11 161 typedef struct
Kojto 109:9296ab0bfc11 162 {
Kojto 109:9296ab0bfc11 163 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 109:9296ab0bfc11 164 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 109:9296ab0bfc11 165 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 109:9296ab0bfc11 166 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 109:9296ab0bfc11 167 }CAN_TxMailBox_TypeDef;
Kojto 109:9296ab0bfc11 168
Kojto 109:9296ab0bfc11 169 /**
Kojto 109:9296ab0bfc11 170 * @brief Controller Area Network FIFOMailBox
Kojto 109:9296ab0bfc11 171 */
Kojto 109:9296ab0bfc11 172 typedef struct
Kojto 109:9296ab0bfc11 173 {
Kojto 109:9296ab0bfc11 174 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 109:9296ab0bfc11 175 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 109:9296ab0bfc11 176 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 109:9296ab0bfc11 177 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 109:9296ab0bfc11 178 }CAN_FIFOMailBox_TypeDef;
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 /**
Kojto 109:9296ab0bfc11 181 * @brief Controller Area Network FilterRegister
Kojto 109:9296ab0bfc11 182 */
Kojto 109:9296ab0bfc11 183 typedef struct
Kojto 109:9296ab0bfc11 184 {
Kojto 109:9296ab0bfc11 185 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 109:9296ab0bfc11 186 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 109:9296ab0bfc11 187 }CAN_FilterRegister_TypeDef;
Kojto 109:9296ab0bfc11 188
Kojto 109:9296ab0bfc11 189 /**
Kojto 109:9296ab0bfc11 190 * @brief Controller Area Network
Kojto 109:9296ab0bfc11 191 */
Kojto 109:9296ab0bfc11 192 typedef struct
Kojto 109:9296ab0bfc11 193 {
Kojto 109:9296ab0bfc11 194 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 195 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 196 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 197 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 198 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 199 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 200 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 201 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 202 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 109:9296ab0bfc11 203 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 109:9296ab0bfc11 204 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 109:9296ab0bfc11 205 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 109:9296ab0bfc11 206 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 109:9296ab0bfc11 207 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 109:9296ab0bfc11 208 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 109:9296ab0bfc11 209 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 109:9296ab0bfc11 210 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 109:9296ab0bfc11 211 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 109:9296ab0bfc11 212 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 109:9296ab0bfc11 213 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 109:9296ab0bfc11 214 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 109:9296ab0bfc11 215 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 109:9296ab0bfc11 216 }CAN_TypeDef;
Kojto 109:9296ab0bfc11 217
Kojto 109:9296ab0bfc11 218 /**
Kojto 109:9296ab0bfc11 219 * @brief HDMI-CEC
Kojto 109:9296ab0bfc11 220 */
Kojto 109:9296ab0bfc11 221
Kojto 109:9296ab0bfc11 222 typedef struct
Kojto 109:9296ab0bfc11 223 {
Kojto 109:9296ab0bfc11 224 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 109:9296ab0bfc11 225 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 109:9296ab0bfc11 226 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 109:9296ab0bfc11 227 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 109:9296ab0bfc11 228 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 109:9296ab0bfc11 229 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 109:9296ab0bfc11 230 }CEC_TypeDef;
Kojto 109:9296ab0bfc11 231
Kojto 109:9296ab0bfc11 232 /**
Kojto 109:9296ab0bfc11 233 * @brief CRC calculation unit
Kojto 109:9296ab0bfc11 234 */
Kojto 109:9296ab0bfc11 235
Kojto 109:9296ab0bfc11 236 typedef struct
Kojto 109:9296ab0bfc11 237 {
Kojto 109:9296ab0bfc11 238 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 239 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 240 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 109:9296ab0bfc11 241 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 109:9296ab0bfc11 242 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 243 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 109:9296ab0bfc11 244 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 245 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 246 }CRC_TypeDef;
Kojto 109:9296ab0bfc11 247
Kojto 109:9296ab0bfc11 248 /**
Kojto 109:9296ab0bfc11 249 * @brief Clock Recovery System
Kojto 109:9296ab0bfc11 250 */
Kojto 109:9296ab0bfc11 251 typedef struct
Kojto 109:9296ab0bfc11 252 {
Kojto 109:9296ab0bfc11 253 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 254 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 255 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 256 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 257 }CRS_TypeDef;
Kojto 109:9296ab0bfc11 258
Kojto 109:9296ab0bfc11 259 /**
Kojto 109:9296ab0bfc11 260 * @brief Debug MCU
Kojto 109:9296ab0bfc11 261 */
Kojto 109:9296ab0bfc11 262
Kojto 109:9296ab0bfc11 263 typedef struct
Kojto 109:9296ab0bfc11 264 {
Kojto 109:9296ab0bfc11 265 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 266 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 267 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 268 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 269 }DBGMCU_TypeDef;
Kojto 109:9296ab0bfc11 270
Kojto 109:9296ab0bfc11 271 /**
Kojto 109:9296ab0bfc11 272 * @brief DMA Controller
Kojto 109:9296ab0bfc11 273 */
Kojto 109:9296ab0bfc11 274
Kojto 109:9296ab0bfc11 275 typedef struct
Kojto 109:9296ab0bfc11 276 {
Kojto 109:9296ab0bfc11 277 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 109:9296ab0bfc11 278 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 109:9296ab0bfc11 279 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 109:9296ab0bfc11 280 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 109:9296ab0bfc11 281 }DMA_Channel_TypeDef;
Kojto 109:9296ab0bfc11 282
Kojto 109:9296ab0bfc11 283 typedef struct
Kojto 109:9296ab0bfc11 284 {
Kojto 109:9296ab0bfc11 285 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 286 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 287 }DMA_TypeDef;
Kojto 109:9296ab0bfc11 288
Kojto 109:9296ab0bfc11 289 /**
Kojto 109:9296ab0bfc11 290 * @brief External Interrupt/Event Controller
Kojto 109:9296ab0bfc11 291 */
Kojto 109:9296ab0bfc11 292
Kojto 109:9296ab0bfc11 293 typedef struct
Kojto 109:9296ab0bfc11 294 {
Kojto 109:9296ab0bfc11 295 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 296 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 297 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 109:9296ab0bfc11 298 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 299 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 300 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 301 }EXTI_TypeDef;
Kojto 109:9296ab0bfc11 302
Kojto 109:9296ab0bfc11 303 /**
Kojto 109:9296ab0bfc11 304 * @brief FLASH Registers
Kojto 109:9296ab0bfc11 305 */
Kojto 109:9296ab0bfc11 306 typedef struct
Kojto 109:9296ab0bfc11 307 {
Kojto 109:9296ab0bfc11 308 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 309 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 310 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 311 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 312 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 313 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 314 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 315 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 316 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 317 }FLASH_TypeDef;
Kojto 109:9296ab0bfc11 318
Kojto 109:9296ab0bfc11 319
Kojto 109:9296ab0bfc11 320 /**
Kojto 109:9296ab0bfc11 321 * @brief Option Bytes Registers
Kojto 109:9296ab0bfc11 322 */
Kojto 109:9296ab0bfc11 323 typedef struct
Kojto 109:9296ab0bfc11 324 {
Kojto 109:9296ab0bfc11 325 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 326 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 109:9296ab0bfc11 327 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 109:9296ab0bfc11 328 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 109:9296ab0bfc11 329 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 330 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 109:9296ab0bfc11 331 }OB_TypeDef;
Kojto 109:9296ab0bfc11 332
Kojto 109:9296ab0bfc11 333 /**
Kojto 109:9296ab0bfc11 334 * @brief General Purpose I/O
Kojto 109:9296ab0bfc11 335 */
Kojto 109:9296ab0bfc11 336
Kojto 109:9296ab0bfc11 337 typedef struct
Kojto 109:9296ab0bfc11 338 {
Kojto 109:9296ab0bfc11 339 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 340 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 341 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 342 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 343 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 344 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 345 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 109:9296ab0bfc11 346 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 347 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 109:9296ab0bfc11 348 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 349 }GPIO_TypeDef;
Kojto 109:9296ab0bfc11 350
Kojto 109:9296ab0bfc11 351 /**
Kojto 109:9296ab0bfc11 352 * @brief SysTem Configuration
Kojto 109:9296ab0bfc11 353 */
Kojto 109:9296ab0bfc11 354
Kojto 109:9296ab0bfc11 355 typedef struct
Kojto 109:9296ab0bfc11 356 {
Kojto 109:9296ab0bfc11 357 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 358 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 109:9296ab0bfc11 359 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 109:9296ab0bfc11 360 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 361 }SYSCFG_TypeDef;
Kojto 109:9296ab0bfc11 362
Kojto 109:9296ab0bfc11 363 /**
Kojto 109:9296ab0bfc11 364 * @brief Inter-integrated Circuit Interface
Kojto 109:9296ab0bfc11 365 */
Kojto 109:9296ab0bfc11 366
Kojto 109:9296ab0bfc11 367 typedef struct
Kojto 109:9296ab0bfc11 368 {
Kojto 109:9296ab0bfc11 369 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 370 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 371 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 372 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 373 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 374 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 375 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 376 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 377 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 378 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 379 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 380 }I2C_TypeDef;
Kojto 109:9296ab0bfc11 381
Kojto 109:9296ab0bfc11 382 /**
Kojto 109:9296ab0bfc11 383 * @brief Independent WATCHDOG
Kojto 109:9296ab0bfc11 384 */
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 typedef struct
Kojto 109:9296ab0bfc11 387 {
Kojto 109:9296ab0bfc11 388 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 389 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 390 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 391 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 392 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 393 }IWDG_TypeDef;
Kojto 109:9296ab0bfc11 394
Kojto 109:9296ab0bfc11 395 /**
Kojto 109:9296ab0bfc11 396 * @brief Power Control
Kojto 109:9296ab0bfc11 397 */
Kojto 109:9296ab0bfc11 398
Kojto 109:9296ab0bfc11 399 typedef struct
Kojto 109:9296ab0bfc11 400 {
Kojto 109:9296ab0bfc11 401 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 402 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 403 }PWR_TypeDef;
Kojto 109:9296ab0bfc11 404
Kojto 109:9296ab0bfc11 405 /**
Kojto 109:9296ab0bfc11 406 * @brief Reset and Clock Control
Kojto 109:9296ab0bfc11 407 */
Kojto 109:9296ab0bfc11 408
Kojto 109:9296ab0bfc11 409 typedef struct
Kojto 109:9296ab0bfc11 410 {
Kojto 109:9296ab0bfc11 411 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 412 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 413 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 414 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 415 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 416 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 417 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 418 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 419 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 420 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 421 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 422 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 423 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 424 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 425 }RCC_TypeDef;
Kojto 109:9296ab0bfc11 426
Kojto 109:9296ab0bfc11 427 /**
Kojto 109:9296ab0bfc11 428 * @brief Real-Time Clock
Kojto 109:9296ab0bfc11 429 */
Kojto 109:9296ab0bfc11 430 typedef struct
Kojto 109:9296ab0bfc11 431 {
Kojto 109:9296ab0bfc11 432 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 433 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 434 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 435 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 436 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 437 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 438 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 439 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 440 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 441 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 442 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 443 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 444 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 445 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 446 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 447 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 448 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 449 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 450 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 451 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 452 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 453 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 109:9296ab0bfc11 454 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 109:9296ab0bfc11 455 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 109:9296ab0bfc11 456 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 109:9296ab0bfc11 457 }RTC_TypeDef;
Kojto 109:9296ab0bfc11 458
Kojto 109:9296ab0bfc11 459 /**
Kojto 109:9296ab0bfc11 460 * @brief Serial Peripheral Interface
Kojto 109:9296ab0bfc11 461 */
Kojto 109:9296ab0bfc11 462
Kojto 109:9296ab0bfc11 463 typedef struct
Kojto 109:9296ab0bfc11 464 {
Kojto 109:9296ab0bfc11 465 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 109:9296ab0bfc11 466 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 467 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 468 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 469 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 109:9296ab0bfc11 470 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 109:9296ab0bfc11 471 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 109:9296ab0bfc11 472 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 473 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 474 }SPI_TypeDef;
Kojto 109:9296ab0bfc11 475
Kojto 109:9296ab0bfc11 476 /**
Kojto 109:9296ab0bfc11 477 * @brief TIM
Kojto 109:9296ab0bfc11 478 */
Kojto 109:9296ab0bfc11 479 typedef struct
Kojto 109:9296ab0bfc11 480 {
Kojto 109:9296ab0bfc11 481 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 482 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 483 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 484 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 485 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 486 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 487 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 488 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 489 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 490 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 491 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 492 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 493 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 494 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 495 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 496 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 497 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 498 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 499 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 500 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 501 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 502 }TIM_TypeDef;
Kojto 109:9296ab0bfc11 503
Kojto 109:9296ab0bfc11 504 /**
Kojto 109:9296ab0bfc11 505 * @brief Touch Sensing Controller (TSC)
Kojto 109:9296ab0bfc11 506 */
Kojto 109:9296ab0bfc11 507 typedef struct
Kojto 109:9296ab0bfc11 508 {
Kojto 109:9296ab0bfc11 509 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 510 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 511 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 512 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 513 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 514 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 515 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 516 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 517 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 518 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 519 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 520 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 521 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 522 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Kojto 109:9296ab0bfc11 523 }TSC_TypeDef;
Kojto 109:9296ab0bfc11 524
Kojto 109:9296ab0bfc11 525 /**
Kojto 109:9296ab0bfc11 526 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 109:9296ab0bfc11 527 */
Kojto 109:9296ab0bfc11 528
Kojto 109:9296ab0bfc11 529 typedef struct
Kojto 109:9296ab0bfc11 530 {
Kojto 109:9296ab0bfc11 531 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 532 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 533 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 534 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 535 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 536 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 537 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 538 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 539 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 540 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 541 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 109:9296ab0bfc11 542 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 543 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 109:9296ab0bfc11 544 }USART_TypeDef;
Kojto 109:9296ab0bfc11 545
Kojto 109:9296ab0bfc11 546 /**
Kojto 109:9296ab0bfc11 547 * @brief Universal Serial Bus Full Speed Device
Kojto 109:9296ab0bfc11 548 */
Kojto 109:9296ab0bfc11 549
Kojto 109:9296ab0bfc11 550 typedef struct
Kojto 109:9296ab0bfc11 551 {
Kojto 109:9296ab0bfc11 552 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 553 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 109:9296ab0bfc11 554 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 555 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 109:9296ab0bfc11 556 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 557 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 109:9296ab0bfc11 558 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 559 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 109:9296ab0bfc11 560 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 561 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 109:9296ab0bfc11 562 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 563 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 109:9296ab0bfc11 564 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 565 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 109:9296ab0bfc11 566 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 567 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 109:9296ab0bfc11 568 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 569 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 109:9296ab0bfc11 570 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 571 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 109:9296ab0bfc11 572 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 573 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 109:9296ab0bfc11 574 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 575 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 109:9296ab0bfc11 576 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 577 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 109:9296ab0bfc11 578 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
Kojto 109:9296ab0bfc11 579 __IO uint16_t RESERVEDD; /*!< Reserved */
Kojto 109:9296ab0bfc11 580 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
Kojto 109:9296ab0bfc11 581 __IO uint16_t RESERVEDE; /*!< Reserved */
Kojto 109:9296ab0bfc11 582 }USB_TypeDef;
Kojto 109:9296ab0bfc11 583
Kojto 109:9296ab0bfc11 584 /**
Kojto 109:9296ab0bfc11 585 * @brief Window WATCHDOG
Kojto 109:9296ab0bfc11 586 */
Kojto 109:9296ab0bfc11 587 typedef struct
Kojto 109:9296ab0bfc11 588 {
Kojto 109:9296ab0bfc11 589 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 590 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 591 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 592 }WWDG_TypeDef;
Kojto 109:9296ab0bfc11 593
Kojto 109:9296ab0bfc11 594 /**
Kojto 109:9296ab0bfc11 595 * @}
Kojto 109:9296ab0bfc11 596 */
Kojto 109:9296ab0bfc11 597
Kojto 109:9296ab0bfc11 598 /** @addtogroup Peripheral_memory_map
Kojto 109:9296ab0bfc11 599 * @{
Kojto 109:9296ab0bfc11 600 */
Kojto 109:9296ab0bfc11 601
Kojto 109:9296ab0bfc11 602 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Kojto 109:9296ab0bfc11 603 #define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
Kojto 109:9296ab0bfc11 604 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Kojto 109:9296ab0bfc11 605 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 109:9296ab0bfc11 606
Kojto 109:9296ab0bfc11 607 /*!< Peripheral memory map */
Kojto 109:9296ab0bfc11 608 #define APBPERIPH_BASE PERIPH_BASE
Kojto 109:9296ab0bfc11 609 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 109:9296ab0bfc11 610 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 109:9296ab0bfc11 611
Kojto 109:9296ab0bfc11 612 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 613 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 614 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 109:9296ab0bfc11 615 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 109:9296ab0bfc11 616 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 109:9296ab0bfc11 617 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 618 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 109:9296ab0bfc11 619 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 109:9296ab0bfc11 620 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 109:9296ab0bfc11 621 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
Kojto 109:9296ab0bfc11 622 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
Kojto 109:9296ab0bfc11 623 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
Kojto 109:9296ab0bfc11 624 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
Kojto 109:9296ab0bfc11 625 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 109:9296ab0bfc11 626 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
Kojto 109:9296ab0bfc11 627
Kojto 109:9296ab0bfc11 628 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 109:9296ab0bfc11 629 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 109:9296ab0bfc11 630 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 109:9296ab0bfc11 631 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 109:9296ab0bfc11 632 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 109:9296ab0bfc11 633 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 109:9296ab0bfc11 634 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 109:9296ab0bfc11 635 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 109:9296ab0bfc11 636 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 109:9296ab0bfc11 637 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 109:9296ab0bfc11 638
Kojto 109:9296ab0bfc11 639 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 640 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 109:9296ab0bfc11 641 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 109:9296ab0bfc11 642 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 109:9296ab0bfc11 643 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 109:9296ab0bfc11 644 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 109:9296ab0bfc11 645 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Kojto 109:9296ab0bfc11 646 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Kojto 109:9296ab0bfc11 647
Kojto 109:9296ab0bfc11 648 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 109:9296ab0bfc11 649 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 109:9296ab0bfc11 650 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
Kojto 109:9296ab0bfc11 651 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 652 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
Kojto 109:9296ab0bfc11 653
Kojto 109:9296ab0bfc11 654 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 655 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 656 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 109:9296ab0bfc11 657 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 109:9296ab0bfc11 658
Kojto 109:9296ab0bfc11 659 /**
Kojto 109:9296ab0bfc11 660 * @}
Kojto 109:9296ab0bfc11 661 */
Kojto 109:9296ab0bfc11 662
Kojto 109:9296ab0bfc11 663 /** @addtogroup Peripheral_declaration
Kojto 109:9296ab0bfc11 664 * @{
Kojto 109:9296ab0bfc11 665 */
Kojto 109:9296ab0bfc11 666
Kojto 109:9296ab0bfc11 667 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 109:9296ab0bfc11 668 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 109:9296ab0bfc11 669 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 109:9296ab0bfc11 670 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 109:9296ab0bfc11 671 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 109:9296ab0bfc11 672 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 109:9296ab0bfc11 673 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 109:9296ab0bfc11 674 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 109:9296ab0bfc11 675 #define CAN ((CAN_TypeDef *) CAN_BASE)
Kojto 109:9296ab0bfc11 676 #define CRS ((CRS_TypeDef *) CRS_BASE)
Kojto 109:9296ab0bfc11 677 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 109:9296ab0bfc11 678 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 109:9296ab0bfc11 679 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 109:9296ab0bfc11 680 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 109:9296ab0bfc11 681 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 109:9296ab0bfc11 682 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 109:9296ab0bfc11 683 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 109:9296ab0bfc11 684 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 109:9296ab0bfc11 685 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 109:9296ab0bfc11 686 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 109:9296ab0bfc11 687 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 109:9296ab0bfc11 688 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 109:9296ab0bfc11 689 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 109:9296ab0bfc11 690 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 109:9296ab0bfc11 691 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 109:9296ab0bfc11 692 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 109:9296ab0bfc11 693 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 109:9296ab0bfc11 694 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 109:9296ab0bfc11 695 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 109:9296ab0bfc11 696 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 109:9296ab0bfc11 697 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 109:9296ab0bfc11 698 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 109:9296ab0bfc11 699 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 109:9296ab0bfc11 700 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 109:9296ab0bfc11 701 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 109:9296ab0bfc11 702 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 109:9296ab0bfc11 703 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 109:9296ab0bfc11 704 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 109:9296ab0bfc11 705 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 109:9296ab0bfc11 706 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 109:9296ab0bfc11 707 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 109:9296ab0bfc11 708 /**
Kojto 109:9296ab0bfc11 709 * @}
Kojto 109:9296ab0bfc11 710 */
Kojto 109:9296ab0bfc11 711
Kojto 109:9296ab0bfc11 712 /** @addtogroup Exported_constants
Kojto 109:9296ab0bfc11 713 * @{
Kojto 109:9296ab0bfc11 714 */
Kojto 109:9296ab0bfc11 715
Kojto 109:9296ab0bfc11 716 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 109:9296ab0bfc11 717 * @{
Kojto 109:9296ab0bfc11 718 */
Kojto 109:9296ab0bfc11 719
Kojto 109:9296ab0bfc11 720 /******************************************************************************/
Kojto 109:9296ab0bfc11 721 /* Peripheral Registers Bits Definition */
Kojto 109:9296ab0bfc11 722 /******************************************************************************/
Kojto 109:9296ab0bfc11 723 /******************************************************************************/
Kojto 109:9296ab0bfc11 724 /* */
Kojto 109:9296ab0bfc11 725 /* Analog to Digital Converter (ADC) */
Kojto 109:9296ab0bfc11 726 /* */
Kojto 109:9296ab0bfc11 727 /******************************************************************************/
Kojto 109:9296ab0bfc11 728 /******************** Bits definition for ADC_ISR register ******************/
Kojto 109:9296ab0bfc11 729 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
Kojto 109:9296ab0bfc11 730 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
Kojto 109:9296ab0bfc11 731 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
Kojto 109:9296ab0bfc11 732 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
Kojto 109:9296ab0bfc11 733 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
Kojto 109:9296ab0bfc11 734 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
Kojto 109:9296ab0bfc11 735
Kojto 109:9296ab0bfc11 736 /* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 737 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto 109:9296ab0bfc11 738
Kojto 109:9296ab0bfc11 739 /******************** Bits definition for ADC_IER register ******************/
Kojto 109:9296ab0bfc11 740 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
Kojto 109:9296ab0bfc11 741 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
Kojto 109:9296ab0bfc11 742 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
Kojto 109:9296ab0bfc11 743 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
Kojto 109:9296ab0bfc11 744 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
Kojto 109:9296ab0bfc11 745 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
Kojto 109:9296ab0bfc11 746
Kojto 109:9296ab0bfc11 747 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 748 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto 109:9296ab0bfc11 749
Kojto 109:9296ab0bfc11 750 /******************** Bits definition for ADC_CR register *******************/
Kojto 109:9296ab0bfc11 751 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
Kojto 109:9296ab0bfc11 752 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
Kojto 109:9296ab0bfc11 753 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
Kojto 109:9296ab0bfc11 754 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
Kojto 109:9296ab0bfc11 755 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
Kojto 109:9296ab0bfc11 756
Kojto 109:9296ab0bfc11 757 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 109:9296ab0bfc11 758 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 109:9296ab0bfc11 759 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 760 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 761 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 762 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 763 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 764 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Kojto 109:9296ab0bfc11 765 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
Kojto 109:9296ab0bfc11 766 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
Kojto 109:9296ab0bfc11 767 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
Kojto 109:9296ab0bfc11 768 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
Kojto 109:9296ab0bfc11 769 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
Kojto 109:9296ab0bfc11 770 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
Kojto 109:9296ab0bfc11 771 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Kojto 109:9296ab0bfc11 772 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 773 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 774 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 109:9296ab0bfc11 775 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 776 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 777 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 778 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
Kojto 109:9296ab0bfc11 779 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
Kojto 109:9296ab0bfc11 780 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 781 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 782 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
Kojto 109:9296ab0bfc11 783 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
Kojto 109:9296ab0bfc11 784 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
Kojto 109:9296ab0bfc11 785
Kojto 109:9296ab0bfc11 786 /* Old WAIT bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 787 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto 109:9296ab0bfc11 788
Kojto 109:9296ab0bfc11 789 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 109:9296ab0bfc11 790 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
Kojto 109:9296ab0bfc11 791 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
Kojto 109:9296ab0bfc11 792 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
Kojto 109:9296ab0bfc11 793
Kojto 109:9296ab0bfc11 794 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 795 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
Kojto 109:9296ab0bfc11 796 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
Kojto 109:9296ab0bfc11 797
Kojto 109:9296ab0bfc11 798 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 109:9296ab0bfc11 799 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 109:9296ab0bfc11 800 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 801 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 802 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 803
Kojto 109:9296ab0bfc11 804 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 805 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 109:9296ab0bfc11 806 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
Kojto 109:9296ab0bfc11 807 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
Kojto 109:9296ab0bfc11 808 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
Kojto 109:9296ab0bfc11 809
Kojto 109:9296ab0bfc11 810 /******************* Bit definition for ADC_TR register ********************/
Kojto 109:9296ab0bfc11 811 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
Kojto 109:9296ab0bfc11 812 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Kojto 109:9296ab0bfc11 813
Kojto 109:9296ab0bfc11 814 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 815 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
Kojto 109:9296ab0bfc11 816 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
Kojto 109:9296ab0bfc11 817
Kojto 109:9296ab0bfc11 818 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 109:9296ab0bfc11 819 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
Kojto 109:9296ab0bfc11 820 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
Kojto 109:9296ab0bfc11 821 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
Kojto 109:9296ab0bfc11 822 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
Kojto 109:9296ab0bfc11 823 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
Kojto 109:9296ab0bfc11 824 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
Kojto 109:9296ab0bfc11 825 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
Kojto 109:9296ab0bfc11 826 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
Kojto 109:9296ab0bfc11 827 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
Kojto 109:9296ab0bfc11 828 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
Kojto 109:9296ab0bfc11 829 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
Kojto 109:9296ab0bfc11 830 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
Kojto 109:9296ab0bfc11 831 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
Kojto 109:9296ab0bfc11 832 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
Kojto 109:9296ab0bfc11 833 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
Kojto 109:9296ab0bfc11 834 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
Kojto 109:9296ab0bfc11 835 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
Kojto 109:9296ab0bfc11 836 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
Kojto 109:9296ab0bfc11 837 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
Kojto 109:9296ab0bfc11 838
Kojto 109:9296ab0bfc11 839 /******************** Bit definition for ADC_DR register ********************/
Kojto 109:9296ab0bfc11 840 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Kojto 109:9296ab0bfc11 841
Kojto 109:9296ab0bfc11 842 /******************* Bit definition for ADC_CCR register ********************/
Kojto 109:9296ab0bfc11 843 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
Kojto 109:9296ab0bfc11 844 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
Kojto 109:9296ab0bfc11 845 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
Kojto 109:9296ab0bfc11 846
Kojto 109:9296ab0bfc11 847 /******************************************************************************/
Kojto 109:9296ab0bfc11 848 /* */
Kojto 109:9296ab0bfc11 849 /* Controller Area Network (CAN ) */
Kojto 109:9296ab0bfc11 850 /* */
Kojto 109:9296ab0bfc11 851 /******************************************************************************/
Kojto 109:9296ab0bfc11 852 /*!<CAN control and status registers */
Kojto 109:9296ab0bfc11 853 /******************* Bit definition for CAN_MCR register ********************/
Kojto 109:9296ab0bfc11 854 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 109:9296ab0bfc11 855 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 109:9296ab0bfc11 856 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 109:9296ab0bfc11 857 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 109:9296ab0bfc11 858 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 109:9296ab0bfc11 859 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 109:9296ab0bfc11 860 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 109:9296ab0bfc11 861 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 109:9296ab0bfc11 862 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 109:9296ab0bfc11 863
Kojto 109:9296ab0bfc11 864 /******************* Bit definition for CAN_MSR register ********************/
Kojto 109:9296ab0bfc11 865 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
Kojto 109:9296ab0bfc11 866 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
Kojto 109:9296ab0bfc11 867 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
Kojto 109:9296ab0bfc11 868 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
Kojto 109:9296ab0bfc11 869 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
Kojto 109:9296ab0bfc11 870 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
Kojto 109:9296ab0bfc11 871 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
Kojto 109:9296ab0bfc11 872 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
Kojto 109:9296ab0bfc11 873 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
Kojto 109:9296ab0bfc11 874
Kojto 109:9296ab0bfc11 875 /******************* Bit definition for CAN_TSR register ********************/
Kojto 109:9296ab0bfc11 876 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 109:9296ab0bfc11 877 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 109:9296ab0bfc11 878 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 109:9296ab0bfc11 879 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 109:9296ab0bfc11 880 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 109:9296ab0bfc11 881 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 109:9296ab0bfc11 882 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 109:9296ab0bfc11 883 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 109:9296ab0bfc11 884 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 109:9296ab0bfc11 885 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 109:9296ab0bfc11 886 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 109:9296ab0bfc11 887 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 109:9296ab0bfc11 888 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 109:9296ab0bfc11 889 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 109:9296ab0bfc11 890 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 109:9296ab0bfc11 891 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 109:9296ab0bfc11 892
Kojto 109:9296ab0bfc11 893 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 109:9296ab0bfc11 894 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 109:9296ab0bfc11 895 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 109:9296ab0bfc11 896 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 109:9296ab0bfc11 897
Kojto 109:9296ab0bfc11 898 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 109:9296ab0bfc11 899 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 109:9296ab0bfc11 900 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 109:9296ab0bfc11 901 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 109:9296ab0bfc11 902
Kojto 109:9296ab0bfc11 903 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 109:9296ab0bfc11 904 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
Kojto 109:9296ab0bfc11 905 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
Kojto 109:9296ab0bfc11 906 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
Kojto 109:9296ab0bfc11 907 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
Kojto 109:9296ab0bfc11 908
Kojto 109:9296ab0bfc11 909 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 109:9296ab0bfc11 910 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
Kojto 109:9296ab0bfc11 911 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
Kojto 109:9296ab0bfc11 912 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
Kojto 109:9296ab0bfc11 913 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
Kojto 109:9296ab0bfc11 914
Kojto 109:9296ab0bfc11 915 /******************** Bit definition for CAN_IER register *******************/
Kojto 109:9296ab0bfc11 916 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 917 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 109:9296ab0bfc11 918 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 109:9296ab0bfc11 919 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 109:9296ab0bfc11 920 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 109:9296ab0bfc11 921 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 109:9296ab0bfc11 922 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 109:9296ab0bfc11 923 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 109:9296ab0bfc11 924 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 109:9296ab0bfc11 925 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 109:9296ab0bfc11 926 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 109:9296ab0bfc11 927 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 109:9296ab0bfc11 928 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 109:9296ab0bfc11 929 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 109:9296ab0bfc11 930
Kojto 109:9296ab0bfc11 931 /******************** Bit definition for CAN_ESR register *******************/
Kojto 109:9296ab0bfc11 932 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 109:9296ab0bfc11 933 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 109:9296ab0bfc11 934 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 109:9296ab0bfc11 935
Kojto 109:9296ab0bfc11 936 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 109:9296ab0bfc11 937 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 938 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 939 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 940
Kojto 109:9296ab0bfc11 941 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 109:9296ab0bfc11 942 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 109:9296ab0bfc11 943
Kojto 109:9296ab0bfc11 944 /******************* Bit definition for CAN_BTR register ********************/
Kojto 109:9296ab0bfc11 945 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 109:9296ab0bfc11 946 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 109:9296ab0bfc11 947 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
Kojto 109:9296ab0bfc11 948 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
Kojto 109:9296ab0bfc11 949 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
Kojto 109:9296ab0bfc11 950 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
Kojto 109:9296ab0bfc11 951 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 109:9296ab0bfc11 952 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
Kojto 109:9296ab0bfc11 953 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
Kojto 109:9296ab0bfc11 954 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
Kojto 109:9296ab0bfc11 955 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 109:9296ab0bfc11 956 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
Kojto 109:9296ab0bfc11 957 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
Kojto 109:9296ab0bfc11 958 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 109:9296ab0bfc11 959 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 109:9296ab0bfc11 960
Kojto 109:9296ab0bfc11 961 /*!<Mailbox registers */
Kojto 109:9296ab0bfc11 962 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 109:9296ab0bfc11 963 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 964 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 965 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 966 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 967 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 968
Kojto 109:9296ab0bfc11 969 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 109:9296ab0bfc11 970 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 971 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 972 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 973
Kojto 109:9296ab0bfc11 974 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 109:9296ab0bfc11 975 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 976 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 977 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 978 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 979
Kojto 109:9296ab0bfc11 980 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 109:9296ab0bfc11 981 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 982 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 983 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 984 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 985
Kojto 109:9296ab0bfc11 986 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 109:9296ab0bfc11 987 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 988 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 989 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 990 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 991 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 992
Kojto 109:9296ab0bfc11 993 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 109:9296ab0bfc11 994 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 995 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 996 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 997
Kojto 109:9296ab0bfc11 998 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 109:9296ab0bfc11 999 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1000 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1001 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1002 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1003
Kojto 109:9296ab0bfc11 1004 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 109:9296ab0bfc11 1005 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1006 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1007 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1008 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1009
Kojto 109:9296ab0bfc11 1010 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 109:9296ab0bfc11 1011 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 1012 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1013 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1014 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 109:9296ab0bfc11 1015 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1016
Kojto 109:9296ab0bfc11 1017 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 109:9296ab0bfc11 1018 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1019 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 1020 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1021
Kojto 109:9296ab0bfc11 1022 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 109:9296ab0bfc11 1023 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1024 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1025 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1026 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1027
Kojto 109:9296ab0bfc11 1028 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 109:9296ab0bfc11 1029 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1030 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1031 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1032 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1033
Kojto 109:9296ab0bfc11 1034 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 109:9296ab0bfc11 1035 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1036 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1037 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 1038 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1039
Kojto 109:9296ab0bfc11 1040 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 109:9296ab0bfc11 1041 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1042 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 109:9296ab0bfc11 1043 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1044
Kojto 109:9296ab0bfc11 1045 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 109:9296ab0bfc11 1046 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1047 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1048 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1049 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1050
Kojto 109:9296ab0bfc11 1051 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 109:9296ab0bfc11 1052 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1053 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1054 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1055 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1056
Kojto 109:9296ab0bfc11 1057 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 109:9296ab0bfc11 1058 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1059 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1060 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 109:9296ab0bfc11 1061 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1062
Kojto 109:9296ab0bfc11 1063 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 109:9296ab0bfc11 1064 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1065 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 109:9296ab0bfc11 1066 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1067
Kojto 109:9296ab0bfc11 1068 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 109:9296ab0bfc11 1069 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1070 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1071 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1072 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1073
Kojto 109:9296ab0bfc11 1074 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 109:9296ab0bfc11 1075 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1076 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1077 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1078 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1079
Kojto 109:9296ab0bfc11 1080 /*!<CAN filter registers */
Kojto 109:9296ab0bfc11 1081 /******************* Bit definition for CAN_FMR register ********************/
Kojto 109:9296ab0bfc11 1082 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
Kojto 109:9296ab0bfc11 1083 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
Kojto 109:9296ab0bfc11 1084
Kojto 109:9296ab0bfc11 1085 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 109:9296ab0bfc11 1086 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
Kojto 109:9296ab0bfc11 1087 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Kojto 109:9296ab0bfc11 1088 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Kojto 109:9296ab0bfc11 1089 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Kojto 109:9296ab0bfc11 1090 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Kojto 109:9296ab0bfc11 1091 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Kojto 109:9296ab0bfc11 1092 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Kojto 109:9296ab0bfc11 1093 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Kojto 109:9296ab0bfc11 1094 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Kojto 109:9296ab0bfc11 1095 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Kojto 109:9296ab0bfc11 1096 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Kojto 109:9296ab0bfc11 1097 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Kojto 109:9296ab0bfc11 1098 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Kojto 109:9296ab0bfc11 1099 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Kojto 109:9296ab0bfc11 1100 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Kojto 109:9296ab0bfc11 1101 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
Kojto 109:9296ab0bfc11 1102 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
Kojto 109:9296ab0bfc11 1103 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
Kojto 109:9296ab0bfc11 1104 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
Kojto 109:9296ab0bfc11 1105 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
Kojto 109:9296ab0bfc11 1106 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
Kojto 109:9296ab0bfc11 1107 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
Kojto 109:9296ab0bfc11 1108 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
Kojto 109:9296ab0bfc11 1109 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
Kojto 109:9296ab0bfc11 1110 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
Kojto 109:9296ab0bfc11 1111 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
Kojto 109:9296ab0bfc11 1112 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
Kojto 109:9296ab0bfc11 1113 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
Kojto 109:9296ab0bfc11 1114 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
Kojto 109:9296ab0bfc11 1115
Kojto 109:9296ab0bfc11 1116 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 109:9296ab0bfc11 1117 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
Kojto 109:9296ab0bfc11 1118 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 109:9296ab0bfc11 1119 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 109:9296ab0bfc11 1120 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 109:9296ab0bfc11 1121 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 109:9296ab0bfc11 1122 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 109:9296ab0bfc11 1123 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 109:9296ab0bfc11 1124 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 109:9296ab0bfc11 1125 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 109:9296ab0bfc11 1126 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 109:9296ab0bfc11 1127 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 109:9296ab0bfc11 1128 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 109:9296ab0bfc11 1129 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 109:9296ab0bfc11 1130 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 109:9296ab0bfc11 1131 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 109:9296ab0bfc11 1132 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
Kojto 109:9296ab0bfc11 1133 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
Kojto 109:9296ab0bfc11 1134 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
Kojto 109:9296ab0bfc11 1135 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
Kojto 109:9296ab0bfc11 1136 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
Kojto 109:9296ab0bfc11 1137 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
Kojto 109:9296ab0bfc11 1138 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
Kojto 109:9296ab0bfc11 1139 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
Kojto 109:9296ab0bfc11 1140 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
Kojto 109:9296ab0bfc11 1141 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
Kojto 109:9296ab0bfc11 1142 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
Kojto 109:9296ab0bfc11 1143 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
Kojto 109:9296ab0bfc11 1144 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
Kojto 109:9296ab0bfc11 1145 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
Kojto 109:9296ab0bfc11 1146
Kojto 109:9296ab0bfc11 1147 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 109:9296ab0bfc11 1148 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
Kojto 109:9296ab0bfc11 1149 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
Kojto 109:9296ab0bfc11 1150 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
Kojto 109:9296ab0bfc11 1151 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
Kojto 109:9296ab0bfc11 1152 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
Kojto 109:9296ab0bfc11 1153 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
Kojto 109:9296ab0bfc11 1154 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
Kojto 109:9296ab0bfc11 1155 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
Kojto 109:9296ab0bfc11 1156 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
Kojto 109:9296ab0bfc11 1157 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
Kojto 109:9296ab0bfc11 1158 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
Kojto 109:9296ab0bfc11 1159 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
Kojto 109:9296ab0bfc11 1160 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
Kojto 109:9296ab0bfc11 1161 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
Kojto 109:9296ab0bfc11 1162 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
Kojto 109:9296ab0bfc11 1163 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
Kojto 109:9296ab0bfc11 1164 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
Kojto 109:9296ab0bfc11 1165 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
Kojto 109:9296ab0bfc11 1166 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
Kojto 109:9296ab0bfc11 1167 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
Kojto 109:9296ab0bfc11 1168 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
Kojto 109:9296ab0bfc11 1169 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
Kojto 109:9296ab0bfc11 1170 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
Kojto 109:9296ab0bfc11 1171 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
Kojto 109:9296ab0bfc11 1172 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
Kojto 109:9296ab0bfc11 1173 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
Kojto 109:9296ab0bfc11 1174 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
Kojto 109:9296ab0bfc11 1175 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
Kojto 109:9296ab0bfc11 1176 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
Kojto 109:9296ab0bfc11 1177
Kojto 109:9296ab0bfc11 1178 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 109:9296ab0bfc11 1179 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
Kojto 109:9296ab0bfc11 1180 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
Kojto 109:9296ab0bfc11 1181 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
Kojto 109:9296ab0bfc11 1182 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
Kojto 109:9296ab0bfc11 1183 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
Kojto 109:9296ab0bfc11 1184 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
Kojto 109:9296ab0bfc11 1185 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
Kojto 109:9296ab0bfc11 1186 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
Kojto 109:9296ab0bfc11 1187 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
Kojto 109:9296ab0bfc11 1188 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
Kojto 109:9296ab0bfc11 1189 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
Kojto 109:9296ab0bfc11 1190 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
Kojto 109:9296ab0bfc11 1191 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
Kojto 109:9296ab0bfc11 1192 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
Kojto 109:9296ab0bfc11 1193 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
Kojto 109:9296ab0bfc11 1194 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
Kojto 109:9296ab0bfc11 1195 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
Kojto 109:9296ab0bfc11 1196 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
Kojto 109:9296ab0bfc11 1197 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
Kojto 109:9296ab0bfc11 1198 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
Kojto 109:9296ab0bfc11 1199 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
Kojto 109:9296ab0bfc11 1200 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
Kojto 109:9296ab0bfc11 1201 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
Kojto 109:9296ab0bfc11 1202 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
Kojto 109:9296ab0bfc11 1203 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
Kojto 109:9296ab0bfc11 1204 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
Kojto 109:9296ab0bfc11 1205 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
Kojto 109:9296ab0bfc11 1206 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
Kojto 109:9296ab0bfc11 1207 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
Kojto 109:9296ab0bfc11 1208
Kojto 109:9296ab0bfc11 1209 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 109:9296ab0bfc11 1210 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1211 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1212 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1213 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1214 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1215 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1216 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1217 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1218 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1219 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1220 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1221 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1222 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1223 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1224 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1225 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1226 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1227 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1228 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1229 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1230 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1231 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1232 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1233 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1234 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1235 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1236 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1237 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1238 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1239 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1240 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1241 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1242
Kojto 109:9296ab0bfc11 1243 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 109:9296ab0bfc11 1244 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1245 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1246 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1247 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1248 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1249 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1250 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1251 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1252 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1253 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1254 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1255 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1256 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1257 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1258 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1259 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1260 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1261 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1262 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1263 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1264 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1265 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1266 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1267 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1268 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1269 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1270 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1271 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1272 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1273 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1274 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1275 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1276
Kojto 109:9296ab0bfc11 1277 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 109:9296ab0bfc11 1278 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1279 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1280 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1281 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1282 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1283 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1284 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1285 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1286 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1287 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1288 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1289 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1290 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1291 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1292 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1293 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1294 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1295 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1296 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1297 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1298 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1299 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1300 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1301 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1302 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1303 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1304 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1305 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1306 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1307 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1308 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1309 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1310
Kojto 109:9296ab0bfc11 1311 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 109:9296ab0bfc11 1312 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1313 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1314 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1315 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1316 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1317 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1318 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1319 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1320 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1321 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1322 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1323 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1324 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1325 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1326 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1327 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1328 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1329 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1330 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1331 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1332 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1333 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1334 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1335 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1336 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1337 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1338 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1339 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1340 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1341 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1342 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1343 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1344
Kojto 109:9296ab0bfc11 1345 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 109:9296ab0bfc11 1346 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1347 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1348 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1349 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1350 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1351 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1352 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1353 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1354 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1355 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1356 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1357 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1358 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1359 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1360 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1361 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1362 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1363 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1364 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1365 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1366 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1367 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1368 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1369 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1370 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1371 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1372 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1373 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1374 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1375 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1376 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1377 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1378
Kojto 109:9296ab0bfc11 1379 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 109:9296ab0bfc11 1380 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1381 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1382 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1383 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1384 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1385 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1386 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1387 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1388 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1389 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1390 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1391 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1392 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1393 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1394 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1395 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1396 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1397 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1398 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1399 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1400 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1401 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1402 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1403 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1404 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1405 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1406 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1407 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1408 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1409 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1410 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1411 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1412
Kojto 109:9296ab0bfc11 1413 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 109:9296ab0bfc11 1414 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1415 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1416 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1417 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1418 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1419 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1420 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1421 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1422 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1423 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1424 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1425 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1426 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1427 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1428 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1429 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1430 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1431 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1432 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1433 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1434 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1435 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1436 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1437 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1438 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1439 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1440 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1441 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1442 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1443 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1444 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1445 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1446
Kojto 109:9296ab0bfc11 1447 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 109:9296ab0bfc11 1448 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1449 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1450 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1451 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1452 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1453 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1454 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1455 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1456 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1457 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1458 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1459 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1460 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1461 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1462 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1463 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1464 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1465 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1466 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1467 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1468 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1469 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1470 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1471 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1472 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1473 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1474 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1475 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1476 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1477 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1478 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1479 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1480
Kojto 109:9296ab0bfc11 1481 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 109:9296ab0bfc11 1482 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1483 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1484 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1485 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1486 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1487 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1488 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1489 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1490 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1491 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1492 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1493 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1494 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1495 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1496 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1497 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1498 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1499 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1500 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1501 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1502 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1503 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1504 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1505 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1506 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1507 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1508 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1509 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1510 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1511 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1512 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1513 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1514
Kojto 109:9296ab0bfc11 1515 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 109:9296ab0bfc11 1516 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1517 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1518 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1519 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1520 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1521 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1522 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1523 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1524 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1525 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1526 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1527 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1528 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1529 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1530 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1531 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1532 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1533 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1534 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1535 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1536 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1537 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1538 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1539 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1540 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1541 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1542 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1543 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1544 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1545 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1546 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1547 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1548
Kojto 109:9296ab0bfc11 1549 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 109:9296ab0bfc11 1550 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1551 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1552 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1553 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1554 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1555 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1556 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1557 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1558 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1559 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1560 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1561 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1562 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1563 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1564 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1565 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1566 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1567 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1568 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1569 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1570 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1571 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1572 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1573 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1574 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1575 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1576 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1577 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1578 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1579 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1580 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1581 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1582
Kojto 109:9296ab0bfc11 1583 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 109:9296ab0bfc11 1584 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1585 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1586 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1587 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1588 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1589 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1590 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1591 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1592 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1593 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1594 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1595 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1596 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1597 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1598 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1599 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1600 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1601 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1602 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1603 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1604 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1605 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1606 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1607 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1608 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1609 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1610 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1611 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1612 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1613 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1614 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1615 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1616
Kojto 109:9296ab0bfc11 1617 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 109:9296ab0bfc11 1618 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1619 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1620 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1621 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1622 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1623 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1624 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1625 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1626 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1627 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1628 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1629 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1630 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1631 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1632 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1633 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1634 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1635 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1636 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1637 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1638 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1639 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1640 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1641 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1642 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1643 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1644 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1645 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1646 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1647 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1648 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1649 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1650
Kojto 109:9296ab0bfc11 1651 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 109:9296ab0bfc11 1652 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1653 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1654 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1655 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1656 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1657 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1658 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1659 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1660 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1661 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1662 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1663 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1664 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1665 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1666 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1667 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1668 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1669 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1670 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1671 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1672 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1673 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1674 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1675 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1676 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1677 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1678 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1679 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1680 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1681 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1682 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1683 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1684
Kojto 109:9296ab0bfc11 1685 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 109:9296ab0bfc11 1686 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1687 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1688 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1689 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1690 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1691 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1692 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1693 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1694 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1695 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1696 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1697 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1698 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1699 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1700 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1701 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1702 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1703 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1704 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1705 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1706 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1707 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1708 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1709 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1710 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1711 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1712 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1713 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1714 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1715 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1716 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1717 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1718
Kojto 109:9296ab0bfc11 1719 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 109:9296ab0bfc11 1720 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1721 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1722 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1723 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1724 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1725 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1726 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1727 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1728 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1729 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1730 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1731 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1732 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1733 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1734 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1735 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1736 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1737 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1738 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1739 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1740 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1741 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1742 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1743 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1744 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1745 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1746 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1747 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1748 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1749 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1750 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1751 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1752
Kojto 109:9296ab0bfc11 1753 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 109:9296ab0bfc11 1754 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1755 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1756 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1757 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1758 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1759 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1760 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1761 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1762 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1763 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1764 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1765 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1766 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1767 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1768 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1769 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1770 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1771 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1772 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1773 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1774 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1775 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1776 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1777 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1778 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1779 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1780 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1781 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1782 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1783 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1784 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1785 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1786
Kojto 109:9296ab0bfc11 1787 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 109:9296ab0bfc11 1788 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1789 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1790 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1791 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1792 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1793 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1794 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1795 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1796 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1797 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1798 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1799 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1800 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1801 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1802 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1803 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1804 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1805 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1806 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1807 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1808 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1809 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1810 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1811 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1812 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1813 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1814 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1815 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1816 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1817 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1818 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1819 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1820
Kojto 109:9296ab0bfc11 1821 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 109:9296ab0bfc11 1822 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1823 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1824 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1825 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1826 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1827 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1828 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1829 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1830 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1831 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1832 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1833 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1834 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1835 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1836 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1837 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1838 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1839 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1840 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1841 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1842 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1843 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1844 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1845 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1846 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1847 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1848 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1849 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1850 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1851 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1852 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1853 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1854
Kojto 109:9296ab0bfc11 1855 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 109:9296ab0bfc11 1856 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1857 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1858 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1859 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1860 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1861 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1862 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1863 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1864 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1865 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1866 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1867 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1868 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1869 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1870 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1871 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1872 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1873 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1874 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1875 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1876 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1877 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1878 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1879 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1880 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1881 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1882 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1883 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1884 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1885 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1886 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1887 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1888
Kojto 109:9296ab0bfc11 1889 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 109:9296ab0bfc11 1890 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1891 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1892 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1893 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1894 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1895 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1896 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1897 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1898 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1899 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1900 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1901 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1902 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1903 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1904 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1905 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1906 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1907 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1908 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1909 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1910 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1911 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1912 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1913 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1914 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1915 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1916 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1917 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1918 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1919 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1920 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1921 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1922
Kojto 109:9296ab0bfc11 1923 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 109:9296ab0bfc11 1924 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1925 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1926 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1927 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1928 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1929 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1930 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1931 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1932 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1933 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1934 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1935 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1936 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1937 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1938 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1939 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1940 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1941 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1942 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1943 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1944 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1945 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1946 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1947 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1948 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1949 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1950 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1951 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1952 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1953 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1954 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1955 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1956
Kojto 109:9296ab0bfc11 1957 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 109:9296ab0bfc11 1958 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1959 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1960 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1961 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1962 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1963 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1964 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1965 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 1966 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 1967 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 1968 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 1969 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 1970 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 1971 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 1972 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 1973 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 1974 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 1975 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 1976 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 1977 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 1978 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 1979 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 1980 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 1981 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 1982 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 1983 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 1984 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 1985 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 1986 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 1987 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 1988 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 1989 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 1990
Kojto 109:9296ab0bfc11 1991 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 109:9296ab0bfc11 1992 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 1993 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 1994 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 1995 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 1996 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 1997 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 1998 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 1999 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2000 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2001 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2002 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2003 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2004 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2005 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2006 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2007 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2008 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2009 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2010 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2011 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2012 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2013 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2014 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2015 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2016 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2017 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2018 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2019 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2020 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2021 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2022 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2023 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2024
Kojto 109:9296ab0bfc11 2025 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 109:9296ab0bfc11 2026 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2027 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2028 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2029 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2030 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2031 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2032 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2033 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2034 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2035 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2036 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2037 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2038 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2039 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2040 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2041 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2042 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2043 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2044 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2045 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2046 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2047 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2048 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2049 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2050 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2051 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2052 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2053 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2054 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2055 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2056 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2057 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2058
Kojto 109:9296ab0bfc11 2059 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 109:9296ab0bfc11 2060 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2061 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2062 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2063 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2064 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2065 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2066 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2067 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2068 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2069 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2070 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2071 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2072 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2073 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2074 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2075 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2076 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2077 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2078 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2079 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2080 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2081 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2082 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2083 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2084 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2085 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2086 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2087 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2088 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2089 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2090 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2091 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2092
Kojto 109:9296ab0bfc11 2093 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 109:9296ab0bfc11 2094 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2095 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2096 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2097 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2098 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2099 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2100 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2101 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2102 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2103 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2104 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2105 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2106 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2107 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2108 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2109 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2110 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2111 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2112 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2113 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2114 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2115 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2116 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2117 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2118 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2119 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2120 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2121 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2122 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2123 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2124 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2125 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2126
Kojto 109:9296ab0bfc11 2127 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 109:9296ab0bfc11 2128 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2129 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2130 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2131 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2132 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2133 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2134 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2135 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2136 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2137 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2138 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2139 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2140 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2141 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2142 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2143 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2144 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2145 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2146 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2147 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2148 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2149 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2150 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2151 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2152 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2153 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2154 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2155 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2156 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2157 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2158 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2159 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2160
Kojto 109:9296ab0bfc11 2161 /******************************************************************************/
Kojto 109:9296ab0bfc11 2162 /* */
Kojto 109:9296ab0bfc11 2163 /* HDMI-CEC (CEC) */
Kojto 109:9296ab0bfc11 2164 /* */
Kojto 109:9296ab0bfc11 2165 /******************************************************************************/
Kojto 109:9296ab0bfc11 2166
Kojto 109:9296ab0bfc11 2167 /******************* Bit definition for CEC_CR register *********************/
Kojto 109:9296ab0bfc11 2168 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
Kojto 109:9296ab0bfc11 2169 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
Kojto 109:9296ab0bfc11 2170 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
Kojto 109:9296ab0bfc11 2171
Kojto 109:9296ab0bfc11 2172 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 109:9296ab0bfc11 2173 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
Kojto 109:9296ab0bfc11 2174 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
Kojto 109:9296ab0bfc11 2175 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
Kojto 109:9296ab0bfc11 2176 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
Kojto 109:9296ab0bfc11 2177 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
Kojto 109:9296ab0bfc11 2178 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
Kojto 109:9296ab0bfc11 2179 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
Kojto 109:9296ab0bfc11 2180 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
Kojto 109:9296ab0bfc11 2181 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
Kojto 109:9296ab0bfc11 2182
Kojto 109:9296ab0bfc11 2183 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 109:9296ab0bfc11 2184 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
Kojto 109:9296ab0bfc11 2185
Kojto 109:9296ab0bfc11 2186 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 109:9296ab0bfc11 2187 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
Kojto 109:9296ab0bfc11 2188
Kojto 109:9296ab0bfc11 2189 /******************* Bit definition for CEC_ISR register ********************/
Kojto 109:9296ab0bfc11 2190 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
Kojto 109:9296ab0bfc11 2191 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
Kojto 109:9296ab0bfc11 2192 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
Kojto 109:9296ab0bfc11 2193 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
Kojto 109:9296ab0bfc11 2194 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
Kojto 109:9296ab0bfc11 2195 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
Kojto 109:9296ab0bfc11 2196 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
Kojto 109:9296ab0bfc11 2197 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
Kojto 109:9296ab0bfc11 2198 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
Kojto 109:9296ab0bfc11 2199 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
Kojto 109:9296ab0bfc11 2200 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
Kojto 109:9296ab0bfc11 2201 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
Kojto 109:9296ab0bfc11 2202 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
Kojto 109:9296ab0bfc11 2203
Kojto 109:9296ab0bfc11 2204 /******************* Bit definition for CEC_IER register ********************/
Kojto 109:9296ab0bfc11 2205 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
Kojto 109:9296ab0bfc11 2206 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
Kojto 109:9296ab0bfc11 2207 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
Kojto 109:9296ab0bfc11 2208 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 109:9296ab0bfc11 2209 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
Kojto 109:9296ab0bfc11 2210 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 109:9296ab0bfc11 2211 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 109:9296ab0bfc11 2212 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
Kojto 109:9296ab0bfc11 2213 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
Kojto 109:9296ab0bfc11 2214 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
Kojto 109:9296ab0bfc11 2215 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 109:9296ab0bfc11 2216 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
Kojto 109:9296ab0bfc11 2217 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 109:9296ab0bfc11 2218
Kojto 109:9296ab0bfc11 2219 /******************************************************************************/
Kojto 109:9296ab0bfc11 2220 /* */
Kojto 109:9296ab0bfc11 2221 /* CRC calculation unit (CRC) */
Kojto 109:9296ab0bfc11 2222 /* */
Kojto 109:9296ab0bfc11 2223 /******************************************************************************/
Kojto 109:9296ab0bfc11 2224 /******************* Bit definition for CRC_DR register *********************/
Kojto 109:9296ab0bfc11 2225 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 109:9296ab0bfc11 2226
Kojto 109:9296ab0bfc11 2227 /******************* Bit definition for CRC_IDR register ********************/
Kojto 109:9296ab0bfc11 2228 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 109:9296ab0bfc11 2229
Kojto 109:9296ab0bfc11 2230 /******************** Bit definition for CRC_CR register ********************/
Kojto 109:9296ab0bfc11 2231 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 109:9296ab0bfc11 2232 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 109:9296ab0bfc11 2233 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
Kojto 109:9296ab0bfc11 2234 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
Kojto 109:9296ab0bfc11 2235 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 109:9296ab0bfc11 2236
Kojto 109:9296ab0bfc11 2237 /******************* Bit definition for CRC_INIT register *******************/
Kojto 109:9296ab0bfc11 2238 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 109:9296ab0bfc11 2239
Kojto 109:9296ab0bfc11 2240 /******************************************************************************/
Kojto 109:9296ab0bfc11 2241 /* */
Kojto 109:9296ab0bfc11 2242 /* CRS Clock Recovery System */
Kojto 109:9296ab0bfc11 2243 /******************************************************************************/
Kojto 109:9296ab0bfc11 2244
Kojto 109:9296ab0bfc11 2245 /******************* Bit definition for CRS_CR register *********************/
Kojto 109:9296ab0bfc11 2246 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
Kojto 109:9296ab0bfc11 2247 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
Kojto 109:9296ab0bfc11 2248 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
Kojto 109:9296ab0bfc11 2249 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
Kojto 109:9296ab0bfc11 2250 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
Kojto 109:9296ab0bfc11 2251 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
Kojto 109:9296ab0bfc11 2252 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
Kojto 109:9296ab0bfc11 2253 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
Kojto 109:9296ab0bfc11 2254
Kojto 109:9296ab0bfc11 2255 /******************* Bit definition for CRS_CFGR register *********************/
Kojto 109:9296ab0bfc11 2256 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
Kojto 109:9296ab0bfc11 2257 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
Kojto 109:9296ab0bfc11 2258
Kojto 109:9296ab0bfc11 2259 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
Kojto 109:9296ab0bfc11 2260 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
Kojto 109:9296ab0bfc11 2261 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
Kojto 109:9296ab0bfc11 2262 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
Kojto 109:9296ab0bfc11 2263
Kojto 109:9296ab0bfc11 2264 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
Kojto 109:9296ab0bfc11 2265 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
Kojto 109:9296ab0bfc11 2266 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
Kojto 109:9296ab0bfc11 2267
Kojto 109:9296ab0bfc11 2268 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
Kojto 109:9296ab0bfc11 2269
Kojto 109:9296ab0bfc11 2270 /******************* Bit definition for CRS_ISR register *********************/
Kojto 109:9296ab0bfc11 2271 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
Kojto 109:9296ab0bfc11 2272 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
Kojto 109:9296ab0bfc11 2273 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
Kojto 109:9296ab0bfc11 2274 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
Kojto 109:9296ab0bfc11 2275 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
Kojto 109:9296ab0bfc11 2276 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
Kojto 109:9296ab0bfc11 2277 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
Kojto 109:9296ab0bfc11 2278 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
Kojto 109:9296ab0bfc11 2279 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
Kojto 109:9296ab0bfc11 2280
Kojto 109:9296ab0bfc11 2281 /******************* Bit definition for CRS_ICR register *********************/
Kojto 109:9296ab0bfc11 2282 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
Kojto 109:9296ab0bfc11 2283 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
Kojto 109:9296ab0bfc11 2284 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
Kojto 109:9296ab0bfc11 2285 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
Kojto 109:9296ab0bfc11 2286
Kojto 109:9296ab0bfc11 2287 /******************************************************************************/
Kojto 109:9296ab0bfc11 2288 /* */
Kojto 109:9296ab0bfc11 2289 /* Debug MCU (DBGMCU) */
Kojto 109:9296ab0bfc11 2290 /* */
Kojto 109:9296ab0bfc11 2291 /******************************************************************************/
Kojto 109:9296ab0bfc11 2292
Kojto 109:9296ab0bfc11 2293 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 109:9296ab0bfc11 2294 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Kojto 109:9296ab0bfc11 2295
Kojto 109:9296ab0bfc11 2296 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 109:9296ab0bfc11 2297 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2298 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2299 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2300 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 2301 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 2302 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Kojto 109:9296ab0bfc11 2303 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Kojto 109:9296ab0bfc11 2304 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Kojto 109:9296ab0bfc11 2305 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Kojto 109:9296ab0bfc11 2306 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Kojto 109:9296ab0bfc11 2307 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Kojto 109:9296ab0bfc11 2308 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Kojto 109:9296ab0bfc11 2309 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Kojto 109:9296ab0bfc11 2310 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Kojto 109:9296ab0bfc11 2311 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Kojto 109:9296ab0bfc11 2312 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Kojto 109:9296ab0bfc11 2313
Kojto 109:9296ab0bfc11 2314 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 109:9296ab0bfc11 2315 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Kojto 109:9296ab0bfc11 2316 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Kojto 109:9296ab0bfc11 2317
Kojto 109:9296ab0bfc11 2318 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 109:9296ab0bfc11 2319 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2320 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2321 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2322 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
Kojto 109:9296ab0bfc11 2323 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 109:9296ab0bfc11 2324 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 109:9296ab0bfc11 2325 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 109:9296ab0bfc11 2326 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
Kojto 109:9296ab0bfc11 2327
Kojto 109:9296ab0bfc11 2328 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 109:9296ab0bfc11 2329 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2330 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2331 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 2332
Kojto 109:9296ab0bfc11 2333 /******************************************************************************/
Kojto 109:9296ab0bfc11 2334 /* */
Kojto 109:9296ab0bfc11 2335 /* DMA Controller (DMA) */
Kojto 109:9296ab0bfc11 2336 /* */
Kojto 109:9296ab0bfc11 2337 /******************************************************************************/
Kojto 109:9296ab0bfc11 2338 /******************* Bit definition for DMA_ISR register ********************/
Kojto 109:9296ab0bfc11 2339 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 109:9296ab0bfc11 2340 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2341 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 109:9296ab0bfc11 2342 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 109:9296ab0bfc11 2343 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 109:9296ab0bfc11 2344 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2345 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 109:9296ab0bfc11 2346 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 109:9296ab0bfc11 2347 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 109:9296ab0bfc11 2348 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2349 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 109:9296ab0bfc11 2350 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 109:9296ab0bfc11 2351 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 109:9296ab0bfc11 2352 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2353 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 109:9296ab0bfc11 2354 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 109:9296ab0bfc11 2355 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 109:9296ab0bfc11 2356 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2357 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 109:9296ab0bfc11 2358 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 109:9296ab0bfc11 2359 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
Kojto 109:9296ab0bfc11 2360 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2361 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
Kojto 109:9296ab0bfc11 2362 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
Kojto 109:9296ab0bfc11 2363 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
Kojto 109:9296ab0bfc11 2364 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
Kojto 109:9296ab0bfc11 2365 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
Kojto 109:9296ab0bfc11 2366 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
Kojto 109:9296ab0bfc11 2367
Kojto 109:9296ab0bfc11 2368 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 109:9296ab0bfc11 2369 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 109:9296ab0bfc11 2370 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2371 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 109:9296ab0bfc11 2372 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 109:9296ab0bfc11 2373 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 109:9296ab0bfc11 2374 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2375 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 109:9296ab0bfc11 2376 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 109:9296ab0bfc11 2377 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 109:9296ab0bfc11 2378 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2379 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 109:9296ab0bfc11 2380 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 109:9296ab0bfc11 2381 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 109:9296ab0bfc11 2382 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2383 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 109:9296ab0bfc11 2384 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 109:9296ab0bfc11 2385 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 109:9296ab0bfc11 2386 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2387 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 109:9296ab0bfc11 2388 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 109:9296ab0bfc11 2389 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
Kojto 109:9296ab0bfc11 2390 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2391 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
Kojto 109:9296ab0bfc11 2392 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
Kojto 109:9296ab0bfc11 2393 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
Kojto 109:9296ab0bfc11 2394 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
Kojto 109:9296ab0bfc11 2395 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
Kojto 109:9296ab0bfc11 2396 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
Kojto 109:9296ab0bfc11 2397
Kojto 109:9296ab0bfc11 2398 /******************* Bit definition for DMA_CCR register ********************/
Kojto 109:9296ab0bfc11 2399 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 109:9296ab0bfc11 2400 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 2401 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 109:9296ab0bfc11 2402 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 109:9296ab0bfc11 2403 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 109:9296ab0bfc11 2404 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 109:9296ab0bfc11 2405 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 109:9296ab0bfc11 2406 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 109:9296ab0bfc11 2407
Kojto 109:9296ab0bfc11 2408 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 109:9296ab0bfc11 2409 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2410 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2411
Kojto 109:9296ab0bfc11 2412 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 109:9296ab0bfc11 2413 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2414 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2415
Kojto 109:9296ab0bfc11 2416 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 109:9296ab0bfc11 2417 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2418 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2419
Kojto 109:9296ab0bfc11 2420 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 109:9296ab0bfc11 2421
Kojto 109:9296ab0bfc11 2422 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 109:9296ab0bfc11 2423 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 109:9296ab0bfc11 2424
Kojto 109:9296ab0bfc11 2425 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 109:9296ab0bfc11 2426 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 109:9296ab0bfc11 2427
Kojto 109:9296ab0bfc11 2428 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 109:9296ab0bfc11 2429 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 109:9296ab0bfc11 2430
Kojto 109:9296ab0bfc11 2431 /******************************************************************************/
Kojto 109:9296ab0bfc11 2432 /* */
Kojto 109:9296ab0bfc11 2433 /* External Interrupt/Event Controller (EXTI) */
Kojto 109:9296ab0bfc11 2434 /* */
Kojto 109:9296ab0bfc11 2435 /******************************************************************************/
Kojto 109:9296ab0bfc11 2436 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 109:9296ab0bfc11 2437 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 109:9296ab0bfc11 2438 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 109:9296ab0bfc11 2439 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 109:9296ab0bfc11 2440 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 109:9296ab0bfc11 2441 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 109:9296ab0bfc11 2442 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 109:9296ab0bfc11 2443 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 109:9296ab0bfc11 2444 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 109:9296ab0bfc11 2445 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 109:9296ab0bfc11 2446 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 109:9296ab0bfc11 2447 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 109:9296ab0bfc11 2448 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 109:9296ab0bfc11 2449 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 109:9296ab0bfc11 2450 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 109:9296ab0bfc11 2451 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 109:9296ab0bfc11 2452 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 109:9296ab0bfc11 2453 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 109:9296ab0bfc11 2454 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 109:9296ab0bfc11 2455 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 109:9296ab0bfc11 2456 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 109:9296ab0bfc11 2457 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 109:9296ab0bfc11 2458 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 109:9296ab0bfc11 2459 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
Kojto 109:9296ab0bfc11 2460 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
Kojto 109:9296ab0bfc11 2461 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
Kojto 109:9296ab0bfc11 2462
Kojto 109:9296ab0bfc11 2463 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 109:9296ab0bfc11 2464 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 109:9296ab0bfc11 2465 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 109:9296ab0bfc11 2466 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 109:9296ab0bfc11 2467 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 109:9296ab0bfc11 2468 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 109:9296ab0bfc11 2469 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 109:9296ab0bfc11 2470 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 109:9296ab0bfc11 2471 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 109:9296ab0bfc11 2472 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 109:9296ab0bfc11 2473 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 109:9296ab0bfc11 2474 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 109:9296ab0bfc11 2475 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 109:9296ab0bfc11 2476 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 109:9296ab0bfc11 2477 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 109:9296ab0bfc11 2478 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 109:9296ab0bfc11 2479 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 109:9296ab0bfc11 2480 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 109:9296ab0bfc11 2481 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 109:9296ab0bfc11 2482 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 109:9296ab0bfc11 2483 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 109:9296ab0bfc11 2484 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 109:9296ab0bfc11 2485 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 109:9296ab0bfc11 2486 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
Kojto 109:9296ab0bfc11 2487 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
Kojto 109:9296ab0bfc11 2488
Kojto 109:9296ab0bfc11 2489 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 109:9296ab0bfc11 2490 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 2491 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 2492 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 2493 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 2494 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 2495 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 2496 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 2497 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 2498 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 2499 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 2500 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 2501 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 2502 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 2503 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 2504 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 2505 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 2506 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 2507 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 2508 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 2509
Kojto 109:9296ab0bfc11 2510 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 109:9296ab0bfc11 2511 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 2512 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 2513 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 2514 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 2515 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 2516 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 2517 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 2518 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 2519 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 2520 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 2521 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 2522 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 2523 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 2524 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 2525 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 2526 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 2527 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 2528 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 2529 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 2530
Kojto 109:9296ab0bfc11 2531 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 109:9296ab0bfc11 2532 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 109:9296ab0bfc11 2533 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 109:9296ab0bfc11 2534 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 109:9296ab0bfc11 2535 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 109:9296ab0bfc11 2536 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 109:9296ab0bfc11 2537 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 109:9296ab0bfc11 2538 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 109:9296ab0bfc11 2539 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 109:9296ab0bfc11 2540 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 109:9296ab0bfc11 2541 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 109:9296ab0bfc11 2542 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 109:9296ab0bfc11 2543 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 109:9296ab0bfc11 2544 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 109:9296ab0bfc11 2545 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 109:9296ab0bfc11 2546 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 109:9296ab0bfc11 2547 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 109:9296ab0bfc11 2548 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 109:9296ab0bfc11 2549 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 109:9296ab0bfc11 2550 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 109:9296ab0bfc11 2551
Kojto 109:9296ab0bfc11 2552 /****************** Bit definition for EXTI_PR register *********************/
Kojto 109:9296ab0bfc11 2553 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
Kojto 109:9296ab0bfc11 2554 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
Kojto 109:9296ab0bfc11 2555 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
Kojto 109:9296ab0bfc11 2556 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
Kojto 109:9296ab0bfc11 2557 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
Kojto 109:9296ab0bfc11 2558 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
Kojto 109:9296ab0bfc11 2559 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
Kojto 109:9296ab0bfc11 2560 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
Kojto 109:9296ab0bfc11 2561 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
Kojto 109:9296ab0bfc11 2562 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
Kojto 109:9296ab0bfc11 2563 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
Kojto 109:9296ab0bfc11 2564 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
Kojto 109:9296ab0bfc11 2565 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
Kojto 109:9296ab0bfc11 2566 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
Kojto 109:9296ab0bfc11 2567 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
Kojto 109:9296ab0bfc11 2568 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
Kojto 109:9296ab0bfc11 2569 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
Kojto 109:9296ab0bfc11 2570 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
Kojto 109:9296ab0bfc11 2571 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
Kojto 109:9296ab0bfc11 2572
Kojto 109:9296ab0bfc11 2573 /******************************************************************************/
Kojto 109:9296ab0bfc11 2574 /* */
Kojto 109:9296ab0bfc11 2575 /* FLASH and Option Bytes Registers */
Kojto 109:9296ab0bfc11 2576 /* */
Kojto 109:9296ab0bfc11 2577 /******************************************************************************/
Kojto 109:9296ab0bfc11 2578
Kojto 109:9296ab0bfc11 2579 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 109:9296ab0bfc11 2580 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
Kojto 109:9296ab0bfc11 2581
Kojto 109:9296ab0bfc11 2582 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 109:9296ab0bfc11 2583 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 109:9296ab0bfc11 2584
Kojto 109:9296ab0bfc11 2585 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 109:9296ab0bfc11 2586 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 109:9296ab0bfc11 2587
Kojto 109:9296ab0bfc11 2588 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 109:9296ab0bfc11 2589 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 109:9296ab0bfc11 2590
Kojto 109:9296ab0bfc11 2591 /****************** FLASH Keys **********************************************/
Kojto 109:9296ab0bfc11 2592 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
Kojto 109:9296ab0bfc11 2593 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 109:9296ab0bfc11 2594 to unlock the write access to the FPEC. */
Kojto 109:9296ab0bfc11 2595
Kojto 109:9296ab0bfc11 2596 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
Kojto 109:9296ab0bfc11 2597 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 109:9296ab0bfc11 2598 unlock the write access to the option byte block */
Kojto 109:9296ab0bfc11 2599
Kojto 109:9296ab0bfc11 2600 /****************** Bit definition for FLASH_SR register *******************/
Kojto 109:9296ab0bfc11 2601 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 109:9296ab0bfc11 2602 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 109:9296ab0bfc11 2603 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 109:9296ab0bfc11 2604 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 109:9296ab0bfc11 2605 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 109:9296ab0bfc11 2606
Kojto 109:9296ab0bfc11 2607 /******************* Bit definition for FLASH_CR register *******************/
Kojto 109:9296ab0bfc11 2608 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 109:9296ab0bfc11 2609 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 109:9296ab0bfc11 2610 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 109:9296ab0bfc11 2611 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 109:9296ab0bfc11 2612 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 109:9296ab0bfc11 2613 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 109:9296ab0bfc11 2614 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 109:9296ab0bfc11 2615 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 109:9296ab0bfc11 2616 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 2617 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 109:9296ab0bfc11 2618 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
Kojto 109:9296ab0bfc11 2619
Kojto 109:9296ab0bfc11 2620 /******************* Bit definition for FLASH_AR register *******************/
Kojto 109:9296ab0bfc11 2621 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 109:9296ab0bfc11 2622
Kojto 109:9296ab0bfc11 2623 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 109:9296ab0bfc11 2624 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 109:9296ab0bfc11 2625 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Kojto 109:9296ab0bfc11 2626 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
Kojto 109:9296ab0bfc11 2627
Kojto 109:9296ab0bfc11 2628 #define FLASH_OBR_USER ((uint32_t)0x0000FF00) /*!< User Option Bytes */
Kojto 109:9296ab0bfc11 2629 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Kojto 109:9296ab0bfc11 2630 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Kojto 109:9296ab0bfc11 2631 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Kojto 109:9296ab0bfc11 2632 #define FLASH_OBR_nBOOT0 ((uint32_t)0x00001000) /*!< nBOOT0 */
Kojto 109:9296ab0bfc11 2633 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Kojto 109:9296ab0bfc11 2634 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
Kojto 109:9296ab0bfc11 2635 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
Kojto 109:9296ab0bfc11 2636 #define FLASH_OBR_BOOT_SEL ((uint32_t)0x00008000) /*!< BOOT selection */
Kojto 109:9296ab0bfc11 2637
Kojto 109:9296ab0bfc11 2638 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 2639 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 109:9296ab0bfc11 2640
Kojto 109:9296ab0bfc11 2641 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 2642 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 109:9296ab0bfc11 2643
Kojto 109:9296ab0bfc11 2644 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 109:9296ab0bfc11 2645 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
Kojto 109:9296ab0bfc11 2646
Kojto 109:9296ab0bfc11 2647 /*----------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 2648
Kojto 109:9296ab0bfc11 2649 /****************** Bit definition for OB_RDP register **********************/
Kojto 109:9296ab0bfc11 2650 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 109:9296ab0bfc11 2651 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 109:9296ab0bfc11 2652
Kojto 109:9296ab0bfc11 2653 /****************** Bit definition for OB_USER register *********************/
Kojto 109:9296ab0bfc11 2654 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 109:9296ab0bfc11 2655 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 109:9296ab0bfc11 2656
Kojto 109:9296ab0bfc11 2657 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 109:9296ab0bfc11 2658 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 2659 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 2660
Kojto 109:9296ab0bfc11 2661 /******************************************************************************/
Kojto 109:9296ab0bfc11 2662 /* */
Kojto 109:9296ab0bfc11 2663 /* General Purpose IOs (GPIO) */
Kojto 109:9296ab0bfc11 2664 /* */
Kojto 109:9296ab0bfc11 2665 /******************************************************************************/
Kojto 109:9296ab0bfc11 2666 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 109:9296ab0bfc11 2667 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 2668 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2669 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2670 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 2671 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2672 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2673 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 2674 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2675 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2676 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 2677 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2678 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2679 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 2680 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2681 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2682 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 2683 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2684 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2685 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 2686 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2687 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2688 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 2689 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2690 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2691 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 2692 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2693 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2694 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 2695 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2696 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2697 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 2698 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2699 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2700 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 2701 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2702 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 2703 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 2704 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2705 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2706 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 2707 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2708 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2709 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 2710 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 2711 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 2712 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 2713 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 2714 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 2715
Kojto 109:9296ab0bfc11 2716 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 109:9296ab0bfc11 2717 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2718 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2719 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2720 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2721 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2722 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2723 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2724 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2725 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2726 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2727 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2728 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2729 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2730 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2731 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2732 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2733
Kojto 109:9296ab0bfc11 2734 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 109:9296ab0bfc11 2735 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 2736 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2737 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2738 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 2739 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2740 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2741 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 2742 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2743 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2744 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 2745 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2746 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2747 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 2748 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2749 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2750 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 2751 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2752 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2753 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 2754 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2755 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2756 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 2757 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2758 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2759 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 2760 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2761 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2762 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 2763 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2764 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2765 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 2766 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2767 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2768 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 2769 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2770 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 2771 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 2772 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2773 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2774 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 2775 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2776 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2777 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 2778 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 2779 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 2780 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 2781 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 2782 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 2783
Kojto 109:9296ab0bfc11 2784 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 109:9296ab0bfc11 2785 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 109:9296ab0bfc11 2786 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 109:9296ab0bfc11 2787 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 109:9296ab0bfc11 2788 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 109:9296ab0bfc11 2789 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 109:9296ab0bfc11 2790 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 109:9296ab0bfc11 2791 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 109:9296ab0bfc11 2792 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 109:9296ab0bfc11 2793 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 109:9296ab0bfc11 2794 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 109:9296ab0bfc11 2795 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 109:9296ab0bfc11 2796 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 109:9296ab0bfc11 2797 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 109:9296ab0bfc11 2798 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 109:9296ab0bfc11 2799 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 109:9296ab0bfc11 2800 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 109:9296ab0bfc11 2801 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 109:9296ab0bfc11 2802 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 109:9296ab0bfc11 2803 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 109:9296ab0bfc11 2804 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 109:9296ab0bfc11 2805 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 109:9296ab0bfc11 2806 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 109:9296ab0bfc11 2807 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 109:9296ab0bfc11 2808 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 109:9296ab0bfc11 2809 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 109:9296ab0bfc11 2810 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 109:9296ab0bfc11 2811 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 109:9296ab0bfc11 2812 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 109:9296ab0bfc11 2813 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 109:9296ab0bfc11 2814 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 109:9296ab0bfc11 2815 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 109:9296ab0bfc11 2816 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 109:9296ab0bfc11 2817 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 109:9296ab0bfc11 2818 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 109:9296ab0bfc11 2819 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 109:9296ab0bfc11 2820 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 109:9296ab0bfc11 2821 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 109:9296ab0bfc11 2822 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 109:9296ab0bfc11 2823 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 109:9296ab0bfc11 2824 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 109:9296ab0bfc11 2825 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 109:9296ab0bfc11 2826 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 109:9296ab0bfc11 2827 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 109:9296ab0bfc11 2828 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 109:9296ab0bfc11 2829 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 109:9296ab0bfc11 2830 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 109:9296ab0bfc11 2831 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 109:9296ab0bfc11 2832 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 109:9296ab0bfc11 2833
Kojto 109:9296ab0bfc11 2834 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 109:9296ab0bfc11 2835 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 2836 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2837 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2838 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 2839 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2840 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2841 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 2842 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2843 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2844 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 2845 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2846 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2847 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 2848 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2849 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2850 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 2851 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2852 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2853 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 2854 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2855 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2856 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 2857 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2858 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2859 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 2860 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2861 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2862 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 2863 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2864 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2865 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 2866 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2867 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2868 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 2869 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2870 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 2871 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 2872 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2873 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2874 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 2875 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2876 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2877 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 2878 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 2879 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 2880 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 2881 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 2882 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 2883
Kojto 109:9296ab0bfc11 2884 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 109:9296ab0bfc11 2885 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2886 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2887 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2888 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2889 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2890 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2891 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2892 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2893 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2894 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2895 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2896 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2897 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2898 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2899 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2900 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2901
Kojto 109:9296ab0bfc11 2902 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 109:9296ab0bfc11 2903 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2904 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2905 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2906 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2907 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2908 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2909 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2910 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2911 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2912 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2913 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2914 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2915 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2916 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2917 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2918 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2919
Kojto 109:9296ab0bfc11 2920 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 109:9296ab0bfc11 2921 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2922 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2923 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2924 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2925 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2926 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2927 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2928 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2929 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2930 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2931 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2932 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2933 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2934 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2935 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2936 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2937 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2938 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2939 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2940 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2941 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2942 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2943 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2944 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 2945 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2946 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2947 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2948 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2949 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 2950 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 2951 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 2952 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 2953
Kojto 109:9296ab0bfc11 2954 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 109:9296ab0bfc11 2955 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2956 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2957 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2958 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2959 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2960 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2961 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2962 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2963 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2964 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2965 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2966 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2967 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2968 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2969 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2970 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2971 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2972
Kojto 109:9296ab0bfc11 2973 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 109:9296ab0bfc11 2974 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 2975 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 2976 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 2977 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 2978 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 2979 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 2980 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 2981 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 2982
Kojto 109:9296ab0bfc11 2983 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 109:9296ab0bfc11 2984 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 2985 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 2986 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 2987 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 2988 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 2989 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 2990 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 2991 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 2992
Kojto 109:9296ab0bfc11 2993 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 109:9296ab0bfc11 2994 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2995 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2996 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2997 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2998 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2999 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3000 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3001 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3002 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3003 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3004 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3005 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3006 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3007 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3008 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3009 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3010
Kojto 109:9296ab0bfc11 3011 /******************************************************************************/
Kojto 109:9296ab0bfc11 3012 /* */
Kojto 109:9296ab0bfc11 3013 /* Inter-integrated Circuit Interface (I2C) */
Kojto 109:9296ab0bfc11 3014 /* */
Kojto 109:9296ab0bfc11 3015 /******************************************************************************/
Kojto 109:9296ab0bfc11 3016
Kojto 109:9296ab0bfc11 3017 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 109:9296ab0bfc11 3018 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 109:9296ab0bfc11 3019 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 109:9296ab0bfc11 3020 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 109:9296ab0bfc11 3021 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 109:9296ab0bfc11 3022 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 109:9296ab0bfc11 3023 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 109:9296ab0bfc11 3024 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 3025 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 109:9296ab0bfc11 3026 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 109:9296ab0bfc11 3027 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 109:9296ab0bfc11 3028 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 109:9296ab0bfc11 3029 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 109:9296ab0bfc11 3030 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 109:9296ab0bfc11 3031 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 109:9296ab0bfc11 3032 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 109:9296ab0bfc11 3033 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 109:9296ab0bfc11 3034 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 109:9296ab0bfc11 3035 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 109:9296ab0bfc11 3036 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 109:9296ab0bfc11 3037 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 109:9296ab0bfc11 3038 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 109:9296ab0bfc11 3039
Kojto 109:9296ab0bfc11 3040 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 109:9296ab0bfc11 3041 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 109:9296ab0bfc11 3042 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 109:9296ab0bfc11 3043 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 109:9296ab0bfc11 3044 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 109:9296ab0bfc11 3045 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 109:9296ab0bfc11 3046 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 109:9296ab0bfc11 3047 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 109:9296ab0bfc11 3048 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 109:9296ab0bfc11 3049 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 109:9296ab0bfc11 3050 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 109:9296ab0bfc11 3051 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 109:9296ab0bfc11 3052
Kojto 109:9296ab0bfc11 3053 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 109:9296ab0bfc11 3054 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 109:9296ab0bfc11 3055 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 109:9296ab0bfc11 3056 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 109:9296ab0bfc11 3057
Kojto 109:9296ab0bfc11 3058 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 109:9296ab0bfc11 3059 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 109:9296ab0bfc11 3060 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 109:9296ab0bfc11 3061 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 109:9296ab0bfc11 3062
Kojto 109:9296ab0bfc11 3063 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 109:9296ab0bfc11 3064 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 109:9296ab0bfc11 3065 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 109:9296ab0bfc11 3066 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 109:9296ab0bfc11 3067 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 109:9296ab0bfc11 3068 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 109:9296ab0bfc11 3069
Kojto 109:9296ab0bfc11 3070 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 109:9296ab0bfc11 3071 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 109:9296ab0bfc11 3072 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 109:9296ab0bfc11 3073 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 109:9296ab0bfc11 3074 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Kojto 109:9296ab0bfc11 3075 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 109:9296ab0bfc11 3076
Kojto 109:9296ab0bfc11 3077 /****************** Bit definition for I2C_ISR register ********************/
Kojto 109:9296ab0bfc11 3078 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 109:9296ab0bfc11 3079 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 109:9296ab0bfc11 3080 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 109:9296ab0bfc11 3081 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Kojto 109:9296ab0bfc11 3082 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 109:9296ab0bfc11 3083 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 109:9296ab0bfc11 3084 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 109:9296ab0bfc11 3085 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 109:9296ab0bfc11 3086 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 109:9296ab0bfc11 3087 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 109:9296ab0bfc11 3088 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 109:9296ab0bfc11 3089 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 109:9296ab0bfc11 3090 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 109:9296ab0bfc11 3091 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 109:9296ab0bfc11 3092 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 109:9296ab0bfc11 3093 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 109:9296ab0bfc11 3094 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 109:9296ab0bfc11 3095
Kojto 109:9296ab0bfc11 3096 /****************** Bit definition for I2C_ICR register ********************/
Kojto 109:9296ab0bfc11 3097 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 109:9296ab0bfc11 3098 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 109:9296ab0bfc11 3099 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 109:9296ab0bfc11 3100 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 109:9296ab0bfc11 3101 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 109:9296ab0bfc11 3102 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 109:9296ab0bfc11 3103 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 109:9296ab0bfc11 3104 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 109:9296ab0bfc11 3105 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 109:9296ab0bfc11 3106
Kojto 109:9296ab0bfc11 3107 /****************** Bit definition for I2C_PECR register *******************/
Kojto 109:9296ab0bfc11 3108 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 109:9296ab0bfc11 3109
Kojto 109:9296ab0bfc11 3110 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 109:9296ab0bfc11 3111 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 109:9296ab0bfc11 3112
Kojto 109:9296ab0bfc11 3113 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 109:9296ab0bfc11 3114 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 109:9296ab0bfc11 3115
Kojto 109:9296ab0bfc11 3116 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3117 /* */
Kojto 109:9296ab0bfc11 3118 /* Independent WATCHDOG (IWDG) */
Kojto 109:9296ab0bfc11 3119 /* */
Kojto 109:9296ab0bfc11 3120 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3121 /******************* Bit definition for IWDG_KR register *******************/
Kojto 109:9296ab0bfc11 3122 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
Kojto 109:9296ab0bfc11 3123
Kojto 109:9296ab0bfc11 3124 /******************* Bit definition for IWDG_PR register *******************/
Kojto 109:9296ab0bfc11 3125 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
Kojto 109:9296ab0bfc11 3126 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3127 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3128 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3129
Kojto 109:9296ab0bfc11 3130 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 109:9296ab0bfc11 3131 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
Kojto 109:9296ab0bfc11 3132
Kojto 109:9296ab0bfc11 3133 /******************* Bit definition for IWDG_SR register *******************/
Kojto 109:9296ab0bfc11 3134 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Kojto 109:9296ab0bfc11 3135 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Kojto 109:9296ab0bfc11 3136 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Kojto 109:9296ab0bfc11 3137
Kojto 109:9296ab0bfc11 3138 /******************* Bit definition for IWDG_KR register *******************/
Kojto 109:9296ab0bfc11 3139 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Kojto 109:9296ab0bfc11 3140
Kojto 109:9296ab0bfc11 3141 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3142 /* */
Kojto 109:9296ab0bfc11 3143 /* Power Control (PWR) */
Kojto 109:9296ab0bfc11 3144 /* */
Kojto 109:9296ab0bfc11 3145 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3146
Kojto 109:9296ab0bfc11 3147 /******************** Bit definition for PWR_CR register *******************/
Kojto 109:9296ab0bfc11 3148 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Kojto 109:9296ab0bfc11 3149 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 109:9296ab0bfc11 3150 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 109:9296ab0bfc11 3151 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 109:9296ab0bfc11 3152 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 109:9296ab0bfc11 3153
Kojto 109:9296ab0bfc11 3154 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 109:9296ab0bfc11 3155 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3156 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3157 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3158
Kojto 109:9296ab0bfc11 3159 /*!< PVD level configuration */
Kojto 109:9296ab0bfc11 3160 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 109:9296ab0bfc11 3161 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 109:9296ab0bfc11 3162 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 109:9296ab0bfc11 3163 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 109:9296ab0bfc11 3164 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 109:9296ab0bfc11 3165 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 109:9296ab0bfc11 3166 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 109:9296ab0bfc11 3167 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 109:9296ab0bfc11 3168
Kojto 109:9296ab0bfc11 3169 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 109:9296ab0bfc11 3170
Kojto 109:9296ab0bfc11 3171 /******************* Bit definition for PWR_CSR register *******************/
Kojto 109:9296ab0bfc11 3172 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 109:9296ab0bfc11 3173 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 109:9296ab0bfc11 3174 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 109:9296ab0bfc11 3175 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 109:9296ab0bfc11 3176
Kojto 109:9296ab0bfc11 3177 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 109:9296ab0bfc11 3178 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Kojto 109:9296ab0bfc11 3179 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
Kojto 109:9296ab0bfc11 3180 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
Kojto 109:9296ab0bfc11 3181 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
Kojto 109:9296ab0bfc11 3182 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
Kojto 109:9296ab0bfc11 3183 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
Kojto 109:9296ab0bfc11 3184 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
Kojto 109:9296ab0bfc11 3185
Kojto 109:9296ab0bfc11 3186 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3187 /* */
Kojto 109:9296ab0bfc11 3188 /* Reset and Clock Control */
Kojto 109:9296ab0bfc11 3189 /* */
Kojto 109:9296ab0bfc11 3190 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3191
Kojto 109:9296ab0bfc11 3192 /******************** Bit definition for RCC_CR register *******************/
Kojto 109:9296ab0bfc11 3193 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Kojto 109:9296ab0bfc11 3194 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Kojto 109:9296ab0bfc11 3195
Kojto 109:9296ab0bfc11 3196 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Kojto 109:9296ab0bfc11 3197 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 3198 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 3199 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 3200 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 3201 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 3202
Kojto 109:9296ab0bfc11 3203 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Kojto 109:9296ab0bfc11 3204 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 3205 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 3206 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 3207 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 3208 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 3209 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 3210 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 3211 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 109:9296ab0bfc11 3212
Kojto 109:9296ab0bfc11 3213 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Kojto 109:9296ab0bfc11 3214 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Kojto 109:9296ab0bfc11 3215 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Kojto 109:9296ab0bfc11 3216 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Kojto 109:9296ab0bfc11 3217 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Kojto 109:9296ab0bfc11 3218 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Kojto 109:9296ab0bfc11 3219
Kojto 109:9296ab0bfc11 3220 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 109:9296ab0bfc11 3221 /*!< SW configuration */
Kojto 109:9296ab0bfc11 3222 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 109:9296ab0bfc11 3223 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3224 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3225
Kojto 109:9296ab0bfc11 3226 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 109:9296ab0bfc11 3227 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 109:9296ab0bfc11 3228 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 109:9296ab0bfc11 3229 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
Kojto 109:9296ab0bfc11 3230
Kojto 109:9296ab0bfc11 3231 /*!< SWS configuration */
Kojto 109:9296ab0bfc11 3232 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 109:9296ab0bfc11 3233 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3234 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3235
Kojto 109:9296ab0bfc11 3236 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 109:9296ab0bfc11 3237 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 109:9296ab0bfc11 3238 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 109:9296ab0bfc11 3239 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
Kojto 109:9296ab0bfc11 3240
Kojto 109:9296ab0bfc11 3241 /*!< HPRE configuration */
Kojto 109:9296ab0bfc11 3242 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 109:9296ab0bfc11 3243 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3244 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3245 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3246 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3247
Kojto 109:9296ab0bfc11 3248 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 109:9296ab0bfc11 3249 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 109:9296ab0bfc11 3250 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 109:9296ab0bfc11 3251 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 109:9296ab0bfc11 3252 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 109:9296ab0bfc11 3253 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 109:9296ab0bfc11 3254 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 109:9296ab0bfc11 3255 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 109:9296ab0bfc11 3256 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 109:9296ab0bfc11 3257
Kojto 109:9296ab0bfc11 3258 /*!< PPRE configuration */
Kojto 109:9296ab0bfc11 3259 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
Kojto 109:9296ab0bfc11 3260 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3261 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3262 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3263
Kojto 109:9296ab0bfc11 3264 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 109:9296ab0bfc11 3265 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 109:9296ab0bfc11 3266 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 109:9296ab0bfc11 3267 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 109:9296ab0bfc11 3268 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 109:9296ab0bfc11 3269
Kojto 109:9296ab0bfc11 3270 /*!< ADCPPRE configuration */
Kojto 109:9296ab0bfc11 3271 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
Kojto 109:9296ab0bfc11 3272
Kojto 109:9296ab0bfc11 3273 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
Kojto 109:9296ab0bfc11 3274 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
Kojto 109:9296ab0bfc11 3275
Kojto 109:9296ab0bfc11 3276 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
Kojto 109:9296ab0bfc11 3277 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 3278 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 3279 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 3280 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 3281
Kojto 109:9296ab0bfc11 3282 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 109:9296ab0bfc11 3283 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 109:9296ab0bfc11 3284 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 109:9296ab0bfc11 3285
Kojto 109:9296ab0bfc11 3286 /*!< PLLMUL configuration */
Kojto 109:9296ab0bfc11 3287 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 109:9296ab0bfc11 3288 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3289 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3290 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3291 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3292
Kojto 109:9296ab0bfc11 3293 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 109:9296ab0bfc11 3294 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 109:9296ab0bfc11 3295 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 109:9296ab0bfc11 3296 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 109:9296ab0bfc11 3297 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 109:9296ab0bfc11 3298 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 109:9296ab0bfc11 3299 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 109:9296ab0bfc11 3300 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 109:9296ab0bfc11 3301 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 109:9296ab0bfc11 3302 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 109:9296ab0bfc11 3303 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 109:9296ab0bfc11 3304 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 109:9296ab0bfc11 3305 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 109:9296ab0bfc11 3306 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 109:9296ab0bfc11 3307 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 109:9296ab0bfc11 3308
Kojto 109:9296ab0bfc11 3309 /*!< USB configuration */
Kojto 109:9296ab0bfc11 3310 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
Kojto 109:9296ab0bfc11 3311
Kojto 109:9296ab0bfc11 3312 /*!< MCO configuration */
Kojto 109:9296ab0bfc11 3313 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 109:9296ab0bfc11 3314 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3315 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3316 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3317 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3318
Kojto 109:9296ab0bfc11 3319 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 3320 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
Kojto 109:9296ab0bfc11 3321 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 3322 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 3323 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 109:9296ab0bfc11 3324 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 3325 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 3326 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 109:9296ab0bfc11 3327 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
Kojto 109:9296ab0bfc11 3328
Kojto 109:9296ab0bfc11 3329 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Kojto 109:9296ab0bfc11 3330 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Kojto 109:9296ab0bfc11 3331 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Kojto 109:9296ab0bfc11 3332 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Kojto 109:9296ab0bfc11 3333 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Kojto 109:9296ab0bfc11 3334 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Kojto 109:9296ab0bfc11 3335 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Kojto 109:9296ab0bfc11 3336 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Kojto 109:9296ab0bfc11 3337 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Kojto 109:9296ab0bfc11 3338
Kojto 109:9296ab0bfc11 3339 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Kojto 109:9296ab0bfc11 3340
Kojto 109:9296ab0bfc11 3341 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 109:9296ab0bfc11 3342 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3343 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3344 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3345 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3346 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3347 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3348 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
Kojto 109:9296ab0bfc11 3349 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 109:9296ab0bfc11 3350 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3351 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3352 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3353 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3354 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3355 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3356 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 3357 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3358 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3359 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3360 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3361 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3362 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3363 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 3364 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 109:9296ab0bfc11 3365
Kojto 109:9296ab0bfc11 3366 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 109:9296ab0bfc11 3367 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
Kojto 109:9296ab0bfc11 3368 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
Kojto 109:9296ab0bfc11 3369 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
Kojto 109:9296ab0bfc11 3370 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
Kojto 109:9296ab0bfc11 3371 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
Kojto 109:9296ab0bfc11 3372 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
Kojto 109:9296ab0bfc11 3373 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
Kojto 109:9296ab0bfc11 3374 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
Kojto 109:9296ab0bfc11 3375
Kojto 109:9296ab0bfc11 3376 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 3377 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 109:9296ab0bfc11 3378
Kojto 109:9296ab0bfc11 3379 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 109:9296ab0bfc11 3380 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
Kojto 109:9296ab0bfc11 3381 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
Kojto 109:9296ab0bfc11 3382 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
Kojto 109:9296ab0bfc11 3383 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
Kojto 109:9296ab0bfc11 3384 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
Kojto 109:9296ab0bfc11 3385 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
Kojto 109:9296ab0bfc11 3386 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
Kojto 109:9296ab0bfc11 3387 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
Kojto 109:9296ab0bfc11 3388 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
Kojto 109:9296ab0bfc11 3389 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
Kojto 109:9296ab0bfc11 3390 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
Kojto 109:9296ab0bfc11 3391 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
Kojto 109:9296ab0bfc11 3392 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
Kojto 109:9296ab0bfc11 3393 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
Kojto 109:9296ab0bfc11 3394 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
Kojto 109:9296ab0bfc11 3395 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
Kojto 109:9296ab0bfc11 3396
Kojto 109:9296ab0bfc11 3397 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 109:9296ab0bfc11 3398 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 109:9296ab0bfc11 3399 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 109:9296ab0bfc11 3400 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 109:9296ab0bfc11 3401 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 109:9296ab0bfc11 3402 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Kojto 109:9296ab0bfc11 3403 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Kojto 109:9296ab0bfc11 3404 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Kojto 109:9296ab0bfc11 3405 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Kojto 109:9296ab0bfc11 3406 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
Kojto 109:9296ab0bfc11 3407
Kojto 109:9296ab0bfc11 3408 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 3409 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 109:9296ab0bfc11 3410 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Kojto 109:9296ab0bfc11 3411
Kojto 109:9296ab0bfc11 3412 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 109:9296ab0bfc11 3413 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
Kojto 109:9296ab0bfc11 3414 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
Kojto 109:9296ab0bfc11 3415 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Kojto 109:9296ab0bfc11 3416 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Kojto 109:9296ab0bfc11 3417 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 109:9296ab0bfc11 3418 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Kojto 109:9296ab0bfc11 3419 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Kojto 109:9296ab0bfc11 3420 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
Kojto 109:9296ab0bfc11 3421
Kojto 109:9296ab0bfc11 3422 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 3423 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 109:9296ab0bfc11 3424 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 109:9296ab0bfc11 3425
Kojto 109:9296ab0bfc11 3426 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 109:9296ab0bfc11 3427 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
Kojto 109:9296ab0bfc11 3428 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 109:9296ab0bfc11 3429 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
Kojto 109:9296ab0bfc11 3430 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 109:9296ab0bfc11 3431 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
Kojto 109:9296ab0bfc11 3432 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
Kojto 109:9296ab0bfc11 3433 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
Kojto 109:9296ab0bfc11 3434 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
Kojto 109:9296ab0bfc11 3435 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
Kojto 109:9296ab0bfc11 3436 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
Kojto 109:9296ab0bfc11 3437 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
Kojto 109:9296ab0bfc11 3438 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
Kojto 109:9296ab0bfc11 3439 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
Kojto 109:9296ab0bfc11 3440 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Kojto 109:9296ab0bfc11 3441 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
Kojto 109:9296ab0bfc11 3442 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
Kojto 109:9296ab0bfc11 3443
Kojto 109:9296ab0bfc11 3444 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 109:9296ab0bfc11 3445 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 3446 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 3447 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 109:9296ab0bfc11 3448
Kojto 109:9296ab0bfc11 3449 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 109:9296ab0bfc11 3450 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3451 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3452
Kojto 109:9296ab0bfc11 3453 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 109:9296ab0bfc11 3454 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3455 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3456
Kojto 109:9296ab0bfc11 3457 /*!< RTC configuration */
Kojto 109:9296ab0bfc11 3458 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 3459 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 3460 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 3461 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 109:9296ab0bfc11 3462
Kojto 109:9296ab0bfc11 3463 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 109:9296ab0bfc11 3464 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 109:9296ab0bfc11 3465
Kojto 109:9296ab0bfc11 3466 /******************* Bit definition for RCC_CSR register *******************/
Kojto 109:9296ab0bfc11 3467 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 3468 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 3469 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
Kojto 109:9296ab0bfc11 3470 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 109:9296ab0bfc11 3471 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Kojto 109:9296ab0bfc11 3472 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 109:9296ab0bfc11 3473 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 109:9296ab0bfc11 3474 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 109:9296ab0bfc11 3475 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 109:9296ab0bfc11 3476 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 109:9296ab0bfc11 3477 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 109:9296ab0bfc11 3478
Kojto 109:9296ab0bfc11 3479 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 3480 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 109:9296ab0bfc11 3481
Kojto 109:9296ab0bfc11 3482 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 109:9296ab0bfc11 3483 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
Kojto 109:9296ab0bfc11 3484 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
Kojto 109:9296ab0bfc11 3485 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
Kojto 109:9296ab0bfc11 3486 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
Kojto 109:9296ab0bfc11 3487 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
Kojto 109:9296ab0bfc11 3488
Kojto 109:9296ab0bfc11 3489 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 3490 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
Kojto 109:9296ab0bfc11 3491
Kojto 109:9296ab0bfc11 3492 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 109:9296ab0bfc11 3493 /*!< PREDIV configuration */
Kojto 109:9296ab0bfc11 3494 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Kojto 109:9296ab0bfc11 3495 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3496 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3497 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3498 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3499
Kojto 109:9296ab0bfc11 3500 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Kojto 109:9296ab0bfc11 3501 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Kojto 109:9296ab0bfc11 3502 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Kojto 109:9296ab0bfc11 3503 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Kojto 109:9296ab0bfc11 3504 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Kojto 109:9296ab0bfc11 3505 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Kojto 109:9296ab0bfc11 3506 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Kojto 109:9296ab0bfc11 3507 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Kojto 109:9296ab0bfc11 3508 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Kojto 109:9296ab0bfc11 3509 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Kojto 109:9296ab0bfc11 3510 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Kojto 109:9296ab0bfc11 3511 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Kojto 109:9296ab0bfc11 3512 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Kojto 109:9296ab0bfc11 3513 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Kojto 109:9296ab0bfc11 3514 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Kojto 109:9296ab0bfc11 3515 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Kojto 109:9296ab0bfc11 3516
Kojto 109:9296ab0bfc11 3517 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 109:9296ab0bfc11 3518 /*!< USART1 Clock source selection */
Kojto 109:9296ab0bfc11 3519 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Kojto 109:9296ab0bfc11 3520 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3521 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3522
Kojto 109:9296ab0bfc11 3523 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 3524 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Kojto 109:9296ab0bfc11 3525 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 3526 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 3527
Kojto 109:9296ab0bfc11 3528 /*!< I2C1 Clock source selection */
Kojto 109:9296ab0bfc11 3529 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Kojto 109:9296ab0bfc11 3530
Kojto 109:9296ab0bfc11 3531 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 109:9296ab0bfc11 3532 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Kojto 109:9296ab0bfc11 3533
Kojto 109:9296ab0bfc11 3534 /*!< CEC Clock source selection */
Kojto 109:9296ab0bfc11 3535 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
Kojto 109:9296ab0bfc11 3536
Kojto 109:9296ab0bfc11 3537 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
Kojto 109:9296ab0bfc11 3538 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
Kojto 109:9296ab0bfc11 3539
Kojto 109:9296ab0bfc11 3540 /*!< USB Clock source selection */
Kojto 109:9296ab0bfc11 3541 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
Kojto 109:9296ab0bfc11 3542
Kojto 109:9296ab0bfc11 3543 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
Kojto 109:9296ab0bfc11 3544 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
Kojto 109:9296ab0bfc11 3545
Kojto 109:9296ab0bfc11 3546 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 109:9296ab0bfc11 3547 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
Kojto 109:9296ab0bfc11 3548 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
Kojto 109:9296ab0bfc11 3549 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
Kojto 109:9296ab0bfc11 3550 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
Kojto 109:9296ab0bfc11 3551 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
Kojto 109:9296ab0bfc11 3552 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
Kojto 109:9296ab0bfc11 3553 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
Kojto 109:9296ab0bfc11 3554 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
Kojto 109:9296ab0bfc11 3555
Kojto 109:9296ab0bfc11 3556 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3557 /* */
Kojto 109:9296ab0bfc11 3558 /* Real-Time Clock (RTC) */
Kojto 109:9296ab0bfc11 3559 /* */
Kojto 109:9296ab0bfc11 3560 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3561 /******************** Bits definition for RTC_TR register ******************/
Kojto 109:9296ab0bfc11 3562 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3563 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3564 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3565 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3566 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3567 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3568 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3569 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3570 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3571 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 3572 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3573 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3574 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3575 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3576 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3577 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3578 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3579 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3580 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 3581 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3582 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3583 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3584 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3585 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3586 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3587 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3588 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3589
Kojto 109:9296ab0bfc11 3590 /******************** Bits definition for RTC_DR register ******************/
Kojto 109:9296ab0bfc11 3591 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 3592 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3593 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3594 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3595 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3596 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3597 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3598 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3599 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3600 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3601 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 3602 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3603 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3604 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3605 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3606 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3607 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3608 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3609 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3610 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3611 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 3612 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3613 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3614 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3615 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3616 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3617 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3618 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3619
Kojto 109:9296ab0bfc11 3620 /******************** Bits definition for RTC_CR register ******************/
Kojto 109:9296ab0bfc11 3621 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3622 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 109:9296ab0bfc11 3623 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3624 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3625 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3626 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3627 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3628 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3629 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3630 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3631 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3632 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3633 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3634 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3635 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3636 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3637 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3638
Kojto 109:9296ab0bfc11 3639 /******************** Bits definition for RTC_ISR register *****************/
Kojto 109:9296ab0bfc11 3640 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3641 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3642 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3643 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3644 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3645 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3646 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3647 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3648 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3649 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3650 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3651 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3652
Kojto 109:9296ab0bfc11 3653 /******************** Bits definition for RTC_PRER register ****************/
Kojto 109:9296ab0bfc11 3654 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 109:9296ab0bfc11 3655 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 3656
Kojto 109:9296ab0bfc11 3657 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 109:9296ab0bfc11 3658 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3659 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 3660 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 3661 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 3662 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 3663 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 3664 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3665 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3666 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3667 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3668 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3669 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3670 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3671 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3672 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3673 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3674 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3675 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3676 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3677 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3678 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3679 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 3680 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3681 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3682 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3683 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3684 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3685 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3686 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3687 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3688 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3689 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 3690 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3691 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3692 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3693 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3694 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3695 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3696 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3697 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3698
Kojto 109:9296ab0bfc11 3699 /******************** Bits definition for RTC_WPR register *****************/
Kojto 109:9296ab0bfc11 3700 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 109:9296ab0bfc11 3701
Kojto 109:9296ab0bfc11 3702 /******************** Bits definition for RTC_SSR register *****************/
Kojto 109:9296ab0bfc11 3703 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 3704
Kojto 109:9296ab0bfc11 3705 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 109:9296ab0bfc11 3706 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 3707 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3708
Kojto 109:9296ab0bfc11 3709 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 109:9296ab0bfc11 3710 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3711 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3712 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3713 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3714 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3715 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3716 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3717 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3718 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3719 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 3720 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3721 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3722 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3723 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3724 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3725 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3726 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3727 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3728 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 3729 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3730 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3731 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3732 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3733 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3734 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3735 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3736 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3737
Kojto 109:9296ab0bfc11 3738 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 109:9296ab0bfc11 3739 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 3740 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3741 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3742 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3743 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3744 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3745 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3746 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3747 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3748 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3749 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 3750 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3751 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3752 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3753 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3754 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3755 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3756 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3757
Kojto 109:9296ab0bfc11 3758 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 109:9296ab0bfc11 3759 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 3760
Kojto 109:9296ab0bfc11 3761 /******************** Bits definition for RTC_CALR register ****************/
Kojto 109:9296ab0bfc11 3762 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3763 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3764 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3765 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 109:9296ab0bfc11 3766 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3767 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3768 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3769 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3770 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3771 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3772 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3773 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3774 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3775
Kojto 109:9296ab0bfc11 3776 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 109:9296ab0bfc11 3777 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3778 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3779 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 109:9296ab0bfc11 3780 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3781 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3782 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 109:9296ab0bfc11 3783 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3784 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3785 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 109:9296ab0bfc11 3786 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3787 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3788 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3789 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3790 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3791 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3792 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3793 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3794 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3795
Kojto 109:9296ab0bfc11 3796 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 109:9296ab0bfc11 3797 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 3798 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3799 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3800 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3801 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3802 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 3803
Kojto 109:9296ab0bfc11 3804 /******************** Bits definition for RTC_BKP0R register ***************/
Kojto 109:9296ab0bfc11 3805 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 3806
Kojto 109:9296ab0bfc11 3807 /******************** Bits definition for RTC_BKP1R register ***************/
Kojto 109:9296ab0bfc11 3808 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 3809
Kojto 109:9296ab0bfc11 3810 /******************** Bits definition for RTC_BKP2R register ***************/
Kojto 109:9296ab0bfc11 3811 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 3812
Kojto 109:9296ab0bfc11 3813 /******************** Bits definition for RTC_BKP3R register ***************/
Kojto 109:9296ab0bfc11 3814 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 3815
Kojto 109:9296ab0bfc11 3816 /******************** Bits definition for RTC_BKP4R register ***************/
Kojto 109:9296ab0bfc11 3817 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 3818
Kojto 109:9296ab0bfc11 3819 /******************** Number of backup registers ******************************/
Kojto 109:9296ab0bfc11 3820 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
Kojto 109:9296ab0bfc11 3821
Kojto 109:9296ab0bfc11 3822 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3823 /* */
Kojto 109:9296ab0bfc11 3824 /* Serial Peripheral Interface (SPI) */
Kojto 109:9296ab0bfc11 3825 /* */
Kojto 109:9296ab0bfc11 3826 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3827 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 109:9296ab0bfc11 3828 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 3829 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 3830 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 109:9296ab0bfc11 3831 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 109:9296ab0bfc11 3832 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3833 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3834 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3835 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 109:9296ab0bfc11 3836 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 109:9296ab0bfc11 3837 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 109:9296ab0bfc11 3838 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 109:9296ab0bfc11 3839 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 109:9296ab0bfc11 3840 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 109:9296ab0bfc11 3841 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 109:9296ab0bfc11 3842 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 109:9296ab0bfc11 3843 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 109:9296ab0bfc11 3844 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 109:9296ab0bfc11 3845
Kojto 109:9296ab0bfc11 3846 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 109:9296ab0bfc11 3847 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 3848 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 3849 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 109:9296ab0bfc11 3850 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 109:9296ab0bfc11 3851 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 109:9296ab0bfc11 3852 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 3853 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 3854 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 3855 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 109:9296ab0bfc11 3856 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3857 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3858 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3859 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3860 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 109:9296ab0bfc11 3861 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 109:9296ab0bfc11 3862 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 109:9296ab0bfc11 3863
Kojto 109:9296ab0bfc11 3864 /******************** Bit definition for SPI_SR register *******************/
Kojto 109:9296ab0bfc11 3865 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 109:9296ab0bfc11 3866 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 109:9296ab0bfc11 3867 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 109:9296ab0bfc11 3868 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 109:9296ab0bfc11 3869 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 109:9296ab0bfc11 3870 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 109:9296ab0bfc11 3871 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 109:9296ab0bfc11 3872 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 109:9296ab0bfc11 3873 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 109:9296ab0bfc11 3874 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 109:9296ab0bfc11 3875 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3876 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3877 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 109:9296ab0bfc11 3878 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3879 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3880
Kojto 109:9296ab0bfc11 3881 /******************** Bit definition for SPI_DR register *******************/
Kojto 109:9296ab0bfc11 3882 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
Kojto 109:9296ab0bfc11 3883
Kojto 109:9296ab0bfc11 3884 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 109:9296ab0bfc11 3885 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
Kojto 109:9296ab0bfc11 3886
Kojto 109:9296ab0bfc11 3887 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 109:9296ab0bfc11 3888 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
Kojto 109:9296ab0bfc11 3889
Kojto 109:9296ab0bfc11 3890 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 109:9296ab0bfc11 3891 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
Kojto 109:9296ab0bfc11 3892
Kojto 109:9296ab0bfc11 3893 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 109:9296ab0bfc11 3894 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 109:9296ab0bfc11 3895 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 109:9296ab0bfc11 3896 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 3897 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 3898 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 109:9296ab0bfc11 3899 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 109:9296ab0bfc11 3900 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 3901 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 3902 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 109:9296ab0bfc11 3903 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 109:9296ab0bfc11 3904 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 3905 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 3906 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 109:9296ab0bfc11 3907 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 109:9296ab0bfc11 3908
Kojto 109:9296ab0bfc11 3909 /****************** Bit definition for SPI_I2SPR register ******************/
Kojto 109:9296ab0bfc11 3910 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 109:9296ab0bfc11 3911 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 109:9296ab0bfc11 3912 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 109:9296ab0bfc11 3913
Kojto 109:9296ab0bfc11 3914 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3915 /* */
Kojto 109:9296ab0bfc11 3916 /* System Configuration (SYSCFG) */
Kojto 109:9296ab0bfc11 3917 /* */
Kojto 109:9296ab0bfc11 3918 /*****************************************************************************/
Kojto 109:9296ab0bfc11 3919 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 109:9296ab0bfc11 3920 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Kojto 109:9296ab0bfc11 3921 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
Kojto 109:9296ab0bfc11 3922 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
Kojto 109:9296ab0bfc11 3923
Kojto 109:9296ab0bfc11 3924 #define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages */
Kojto 109:9296ab0bfc11 3925
Kojto 109:9296ab0bfc11 3926 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
Kojto 109:9296ab0bfc11 3927 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
Kojto 109:9296ab0bfc11 3928 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
Kojto 109:9296ab0bfc11 3929 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
Kojto 109:9296ab0bfc11 3930 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
Kojto 109:9296ab0bfc11 3931 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
Kojto 109:9296ab0bfc11 3932
Kojto 109:9296ab0bfc11 3933 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Kojto 109:9296ab0bfc11 3934 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Kojto 109:9296ab0bfc11 3935 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Kojto 109:9296ab0bfc11 3936 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Kojto 109:9296ab0bfc11 3937 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Kojto 109:9296ab0bfc11 3938 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
Kojto 109:9296ab0bfc11 3939 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
Kojto 109:9296ab0bfc11 3940 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
Kojto 109:9296ab0bfc11 3941
Kojto 109:9296ab0bfc11 3942 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 109:9296ab0bfc11 3943 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
Kojto 109:9296ab0bfc11 3944 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
Kojto 109:9296ab0bfc11 3945 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
Kojto 109:9296ab0bfc11 3946 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
Kojto 109:9296ab0bfc11 3947
Kojto 109:9296ab0bfc11 3948 /**
Kojto 109:9296ab0bfc11 3949 * @brief EXTI0 configuration
Kojto 109:9296ab0bfc11 3950 */
Kojto 109:9296ab0bfc11 3951 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
Kojto 109:9296ab0bfc11 3952 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
Kojto 109:9296ab0bfc11 3953 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
Kojto 109:9296ab0bfc11 3954 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
Kojto 109:9296ab0bfc11 3955 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
Kojto 109:9296ab0bfc11 3956 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
Kojto 109:9296ab0bfc11 3957
Kojto 109:9296ab0bfc11 3958 /**
Kojto 109:9296ab0bfc11 3959 * @brief EXTI1 configuration
Kojto 109:9296ab0bfc11 3960 */
Kojto 109:9296ab0bfc11 3961 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
Kojto 109:9296ab0bfc11 3962 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
Kojto 109:9296ab0bfc11 3963 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
Kojto 109:9296ab0bfc11 3964 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
Kojto 109:9296ab0bfc11 3965 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
Kojto 109:9296ab0bfc11 3966 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
Kojto 109:9296ab0bfc11 3967
Kojto 109:9296ab0bfc11 3968 /**
Kojto 109:9296ab0bfc11 3969 * @brief EXTI2 configuration
Kojto 109:9296ab0bfc11 3970 */
Kojto 109:9296ab0bfc11 3971 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
Kojto 109:9296ab0bfc11 3972 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
Kojto 109:9296ab0bfc11 3973 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
Kojto 109:9296ab0bfc11 3974 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
Kojto 109:9296ab0bfc11 3975 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
Kojto 109:9296ab0bfc11 3976 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
Kojto 109:9296ab0bfc11 3977
Kojto 109:9296ab0bfc11 3978 /**
Kojto 109:9296ab0bfc11 3979 * @brief EXTI3 configuration
Kojto 109:9296ab0bfc11 3980 */
Kojto 109:9296ab0bfc11 3981 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
Kojto 109:9296ab0bfc11 3982 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
Kojto 109:9296ab0bfc11 3983 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
Kojto 109:9296ab0bfc11 3984 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
Kojto 109:9296ab0bfc11 3985 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
Kojto 109:9296ab0bfc11 3986 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
Kojto 109:9296ab0bfc11 3987
Kojto 109:9296ab0bfc11 3988 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 109:9296ab0bfc11 3989 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
Kojto 109:9296ab0bfc11 3990 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
Kojto 109:9296ab0bfc11 3991 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
Kojto 109:9296ab0bfc11 3992 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
Kojto 109:9296ab0bfc11 3993
Kojto 109:9296ab0bfc11 3994 /**
Kojto 109:9296ab0bfc11 3995 * @brief EXTI4 configuration
Kojto 109:9296ab0bfc11 3996 */
Kojto 109:9296ab0bfc11 3997 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
Kojto 109:9296ab0bfc11 3998 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
Kojto 109:9296ab0bfc11 3999 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
Kojto 109:9296ab0bfc11 4000 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
Kojto 109:9296ab0bfc11 4001 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
Kojto 109:9296ab0bfc11 4002 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
Kojto 109:9296ab0bfc11 4003
Kojto 109:9296ab0bfc11 4004 /**
Kojto 109:9296ab0bfc11 4005 * @brief EXTI5 configuration
Kojto 109:9296ab0bfc11 4006 */
Kojto 109:9296ab0bfc11 4007 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
Kojto 109:9296ab0bfc11 4008 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
Kojto 109:9296ab0bfc11 4009 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
Kojto 109:9296ab0bfc11 4010 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
Kojto 109:9296ab0bfc11 4011 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
Kojto 109:9296ab0bfc11 4012 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
Kojto 109:9296ab0bfc11 4013
Kojto 109:9296ab0bfc11 4014 /**
Kojto 109:9296ab0bfc11 4015 * @brief EXTI6 configuration
Kojto 109:9296ab0bfc11 4016 */
Kojto 109:9296ab0bfc11 4017 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
Kojto 109:9296ab0bfc11 4018 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
Kojto 109:9296ab0bfc11 4019 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
Kojto 109:9296ab0bfc11 4020 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
Kojto 109:9296ab0bfc11 4021 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
Kojto 109:9296ab0bfc11 4022 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
Kojto 109:9296ab0bfc11 4023
Kojto 109:9296ab0bfc11 4024 /**
Kojto 109:9296ab0bfc11 4025 * @brief EXTI7 configuration
Kojto 109:9296ab0bfc11 4026 */
Kojto 109:9296ab0bfc11 4027 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
Kojto 109:9296ab0bfc11 4028 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
Kojto 109:9296ab0bfc11 4029 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
Kojto 109:9296ab0bfc11 4030 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
Kojto 109:9296ab0bfc11 4031 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
Kojto 109:9296ab0bfc11 4032 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
Kojto 109:9296ab0bfc11 4033
Kojto 109:9296ab0bfc11 4034 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 109:9296ab0bfc11 4035 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
Kojto 109:9296ab0bfc11 4036 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
Kojto 109:9296ab0bfc11 4037 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
Kojto 109:9296ab0bfc11 4038 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
Kojto 109:9296ab0bfc11 4039
Kojto 109:9296ab0bfc11 4040 /**
Kojto 109:9296ab0bfc11 4041 * @brief EXTI8 configuration
Kojto 109:9296ab0bfc11 4042 */
Kojto 109:9296ab0bfc11 4043 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
Kojto 109:9296ab0bfc11 4044 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
Kojto 109:9296ab0bfc11 4045 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
Kojto 109:9296ab0bfc11 4046 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
Kojto 109:9296ab0bfc11 4047 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
Kojto 109:9296ab0bfc11 4048
Kojto 109:9296ab0bfc11 4049 /**
Kojto 109:9296ab0bfc11 4050 * @brief EXTI9 configuration
Kojto 109:9296ab0bfc11 4051 */
Kojto 109:9296ab0bfc11 4052 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
Kojto 109:9296ab0bfc11 4053 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
Kojto 109:9296ab0bfc11 4054 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
Kojto 109:9296ab0bfc11 4055 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
Kojto 109:9296ab0bfc11 4056 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
Kojto 109:9296ab0bfc11 4057 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
Kojto 109:9296ab0bfc11 4058
Kojto 109:9296ab0bfc11 4059 /**
Kojto 109:9296ab0bfc11 4060 * @brief EXTI10 configuration
Kojto 109:9296ab0bfc11 4061 */
Kojto 109:9296ab0bfc11 4062 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
Kojto 109:9296ab0bfc11 4063 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
Kojto 109:9296ab0bfc11 4064 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
Kojto 109:9296ab0bfc11 4065 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
Kojto 109:9296ab0bfc11 4066 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
Kojto 109:9296ab0bfc11 4067 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
Kojto 109:9296ab0bfc11 4068
Kojto 109:9296ab0bfc11 4069 /**
Kojto 109:9296ab0bfc11 4070 * @brief EXTI11 configuration
Kojto 109:9296ab0bfc11 4071 */
Kojto 109:9296ab0bfc11 4072 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
Kojto 109:9296ab0bfc11 4073 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
Kojto 109:9296ab0bfc11 4074 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
Kojto 109:9296ab0bfc11 4075 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
Kojto 109:9296ab0bfc11 4076 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
Kojto 109:9296ab0bfc11 4077
Kojto 109:9296ab0bfc11 4078 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 109:9296ab0bfc11 4079 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
Kojto 109:9296ab0bfc11 4080 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
Kojto 109:9296ab0bfc11 4081 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
Kojto 109:9296ab0bfc11 4082 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
Kojto 109:9296ab0bfc11 4083
Kojto 109:9296ab0bfc11 4084 /**
Kojto 109:9296ab0bfc11 4085 * @brief EXTI12 configuration
Kojto 109:9296ab0bfc11 4086 */
Kojto 109:9296ab0bfc11 4087 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
Kojto 109:9296ab0bfc11 4088 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
Kojto 109:9296ab0bfc11 4089 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
Kojto 109:9296ab0bfc11 4090 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
Kojto 109:9296ab0bfc11 4091 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
Kojto 109:9296ab0bfc11 4092
Kojto 109:9296ab0bfc11 4093 /**
Kojto 109:9296ab0bfc11 4094 * @brief EXTI13 configuration
Kojto 109:9296ab0bfc11 4095 */
Kojto 109:9296ab0bfc11 4096 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
Kojto 109:9296ab0bfc11 4097 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
Kojto 109:9296ab0bfc11 4098 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
Kojto 109:9296ab0bfc11 4099 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
Kojto 109:9296ab0bfc11 4100 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
Kojto 109:9296ab0bfc11 4101
Kojto 109:9296ab0bfc11 4102 /**
Kojto 109:9296ab0bfc11 4103 * @brief EXTI14 configuration
Kojto 109:9296ab0bfc11 4104 */
Kojto 109:9296ab0bfc11 4105 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
Kojto 109:9296ab0bfc11 4106 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
Kojto 109:9296ab0bfc11 4107 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
Kojto 109:9296ab0bfc11 4108 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
Kojto 109:9296ab0bfc11 4109 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
Kojto 109:9296ab0bfc11 4110
Kojto 109:9296ab0bfc11 4111 /**
Kojto 109:9296ab0bfc11 4112 * @brief EXTI15 configuration
Kojto 109:9296ab0bfc11 4113 */
Kojto 109:9296ab0bfc11 4114 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
Kojto 109:9296ab0bfc11 4115 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
Kojto 109:9296ab0bfc11 4116 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
Kojto 109:9296ab0bfc11 4117 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
Kojto 109:9296ab0bfc11 4118 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
Kojto 109:9296ab0bfc11 4119
Kojto 109:9296ab0bfc11 4120 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 109:9296ab0bfc11 4121 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 109:9296ab0bfc11 4122 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 109:9296ab0bfc11 4123 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
Kojto 109:9296ab0bfc11 4124 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Kojto 109:9296ab0bfc11 4125 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 109:9296ab0bfc11 4126
Kojto 109:9296ab0bfc11 4127 /*****************************************************************************/
Kojto 109:9296ab0bfc11 4128 /* */
Kojto 109:9296ab0bfc11 4129 /* Timers (TIM) */
Kojto 109:9296ab0bfc11 4130 /* */
Kojto 109:9296ab0bfc11 4131 /*****************************************************************************/
Kojto 109:9296ab0bfc11 4132 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 109:9296ab0bfc11 4133 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 109:9296ab0bfc11 4134 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 109:9296ab0bfc11 4135 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 109:9296ab0bfc11 4136 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 109:9296ab0bfc11 4137 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 109:9296ab0bfc11 4138
Kojto 109:9296ab0bfc11 4139 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 109:9296ab0bfc11 4140 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4141 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4142
Kojto 109:9296ab0bfc11 4143 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 109:9296ab0bfc11 4144
Kojto 109:9296ab0bfc11 4145 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 109:9296ab0bfc11 4146 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4147 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4148
Kojto 109:9296ab0bfc11 4149 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 109:9296ab0bfc11 4150 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 109:9296ab0bfc11 4151 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 109:9296ab0bfc11 4152 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 109:9296ab0bfc11 4153
Kojto 109:9296ab0bfc11 4154 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 109:9296ab0bfc11 4155 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4156 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4157 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4158
Kojto 109:9296ab0bfc11 4159 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 109:9296ab0bfc11 4160 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 109:9296ab0bfc11 4161 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 109:9296ab0bfc11 4162 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 109:9296ab0bfc11 4163 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 109:9296ab0bfc11 4164 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 109:9296ab0bfc11 4165 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 109:9296ab0bfc11 4166 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 109:9296ab0bfc11 4167
Kojto 109:9296ab0bfc11 4168 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 109:9296ab0bfc11 4169 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 109:9296ab0bfc11 4170 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4171 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4172 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4173
Kojto 109:9296ab0bfc11 4174 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 109:9296ab0bfc11 4175
Kojto 109:9296ab0bfc11 4176 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 109:9296ab0bfc11 4177 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4178 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4179 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4180
Kojto 109:9296ab0bfc11 4181 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 109:9296ab0bfc11 4182
Kojto 109:9296ab0bfc11 4183 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 109:9296ab0bfc11 4184 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4185 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4186 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4187 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4188
Kojto 109:9296ab0bfc11 4189 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 109:9296ab0bfc11 4190 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4191 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4192
Kojto 109:9296ab0bfc11 4193 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 109:9296ab0bfc11 4194 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 109:9296ab0bfc11 4195
Kojto 109:9296ab0bfc11 4196 /******************* Bit definition for TIM_DIER register ******************/
Kojto 109:9296ab0bfc11 4197 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 109:9296ab0bfc11 4198 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 109:9296ab0bfc11 4199 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 109:9296ab0bfc11 4200 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 109:9296ab0bfc11 4201 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 109:9296ab0bfc11 4202 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 109:9296ab0bfc11 4203 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 109:9296ab0bfc11 4204 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 109:9296ab0bfc11 4205 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 109:9296ab0bfc11 4206 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 109:9296ab0bfc11 4207 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 109:9296ab0bfc11 4208 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 109:9296ab0bfc11 4209 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 109:9296ab0bfc11 4210 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 109:9296ab0bfc11 4211 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 109:9296ab0bfc11 4212
Kojto 109:9296ab0bfc11 4213 /******************** Bit definition for TIM_SR register *******************/
Kojto 109:9296ab0bfc11 4214 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 109:9296ab0bfc11 4215 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 109:9296ab0bfc11 4216 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 109:9296ab0bfc11 4217 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 109:9296ab0bfc11 4218 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 109:9296ab0bfc11 4219 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 109:9296ab0bfc11 4220 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 109:9296ab0bfc11 4221 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 109:9296ab0bfc11 4222 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 109:9296ab0bfc11 4223 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 109:9296ab0bfc11 4224 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 109:9296ab0bfc11 4225 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 109:9296ab0bfc11 4226
Kojto 109:9296ab0bfc11 4227 /******************* Bit definition for TIM_EGR register *******************/
Kojto 109:9296ab0bfc11 4228 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 109:9296ab0bfc11 4229 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 109:9296ab0bfc11 4230 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 109:9296ab0bfc11 4231 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 109:9296ab0bfc11 4232 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 109:9296ab0bfc11 4233 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 109:9296ab0bfc11 4234 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 109:9296ab0bfc11 4235 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 109:9296ab0bfc11 4236
Kojto 109:9296ab0bfc11 4237 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 109:9296ab0bfc11 4238 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 109:9296ab0bfc11 4239 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4240 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4241
Kojto 109:9296ab0bfc11 4242 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 109:9296ab0bfc11 4243 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 109:9296ab0bfc11 4244
Kojto 109:9296ab0bfc11 4245 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 109:9296ab0bfc11 4246 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4247 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4248 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4249
Kojto 109:9296ab0bfc11 4250 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 109:9296ab0bfc11 4251
Kojto 109:9296ab0bfc11 4252 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 109:9296ab0bfc11 4253 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4254 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4255
Kojto 109:9296ab0bfc11 4256 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 109:9296ab0bfc11 4257 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 109:9296ab0bfc11 4258
Kojto 109:9296ab0bfc11 4259 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 109:9296ab0bfc11 4260 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4261 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4262 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4263
Kojto 109:9296ab0bfc11 4264 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 109:9296ab0bfc11 4265
Kojto 109:9296ab0bfc11 4266 /*---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 4267
Kojto 109:9296ab0bfc11 4268 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 109:9296ab0bfc11 4269 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4270 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4271
Kojto 109:9296ab0bfc11 4272 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 109:9296ab0bfc11 4273 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4274 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4275 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4276 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4277
Kojto 109:9296ab0bfc11 4278 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 109:9296ab0bfc11 4279 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4280 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4281
Kojto 109:9296ab0bfc11 4282 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 109:9296ab0bfc11 4283 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4284 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4285 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4286 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4287
Kojto 109:9296ab0bfc11 4288 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 109:9296ab0bfc11 4289 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 109:9296ab0bfc11 4290 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4291 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4292
Kojto 109:9296ab0bfc11 4293 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 109:9296ab0bfc11 4294 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 109:9296ab0bfc11 4295
Kojto 109:9296ab0bfc11 4296 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 109:9296ab0bfc11 4297 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4298 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4299 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4300
Kojto 109:9296ab0bfc11 4301 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 109:9296ab0bfc11 4302
Kojto 109:9296ab0bfc11 4303 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 109:9296ab0bfc11 4304 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4305 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4306
Kojto 109:9296ab0bfc11 4307 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 109:9296ab0bfc11 4308 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 109:9296ab0bfc11 4309
Kojto 109:9296ab0bfc11 4310 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 109:9296ab0bfc11 4311 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4312 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4313 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4314
Kojto 109:9296ab0bfc11 4315 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 109:9296ab0bfc11 4316
Kojto 109:9296ab0bfc11 4317 /*---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 4318
Kojto 109:9296ab0bfc11 4319 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 109:9296ab0bfc11 4320 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4321 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4322
Kojto 109:9296ab0bfc11 4323 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 109:9296ab0bfc11 4324 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4325 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4326 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4327 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4328
Kojto 109:9296ab0bfc11 4329 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 109:9296ab0bfc11 4330 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4331 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4332
Kojto 109:9296ab0bfc11 4333 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 109:9296ab0bfc11 4334 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4335 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4336 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4337 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4338
Kojto 109:9296ab0bfc11 4339 /******************* Bit definition for TIM_CCER register ******************/
Kojto 109:9296ab0bfc11 4340 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 109:9296ab0bfc11 4341 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 109:9296ab0bfc11 4342 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 109:9296ab0bfc11 4343 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 109:9296ab0bfc11 4344 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 109:9296ab0bfc11 4345 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 109:9296ab0bfc11 4346 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 109:9296ab0bfc11 4347 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 109:9296ab0bfc11 4348 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 109:9296ab0bfc11 4349 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 109:9296ab0bfc11 4350 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 109:9296ab0bfc11 4351 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 109:9296ab0bfc11 4352 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 109:9296ab0bfc11 4353 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 109:9296ab0bfc11 4354 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 109:9296ab0bfc11 4355
Kojto 109:9296ab0bfc11 4356 /******************* Bit definition for TIM_CNT register *******************/
Kojto 109:9296ab0bfc11 4357 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 109:9296ab0bfc11 4358
Kojto 109:9296ab0bfc11 4359 /******************* Bit definition for TIM_PSC register *******************/
Kojto 109:9296ab0bfc11 4360 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 109:9296ab0bfc11 4361
Kojto 109:9296ab0bfc11 4362 /******************* Bit definition for TIM_ARR register *******************/
Kojto 109:9296ab0bfc11 4363 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 109:9296ab0bfc11 4364
Kojto 109:9296ab0bfc11 4365 /******************* Bit definition for TIM_RCR register *******************/
Kojto 109:9296ab0bfc11 4366 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 109:9296ab0bfc11 4367
Kojto 109:9296ab0bfc11 4368 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 109:9296ab0bfc11 4369 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 109:9296ab0bfc11 4370
Kojto 109:9296ab0bfc11 4371 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 109:9296ab0bfc11 4372 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 109:9296ab0bfc11 4373
Kojto 109:9296ab0bfc11 4374 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 109:9296ab0bfc11 4375 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 109:9296ab0bfc11 4376
Kojto 109:9296ab0bfc11 4377 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 109:9296ab0bfc11 4378 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 109:9296ab0bfc11 4379
Kojto 109:9296ab0bfc11 4380 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 109:9296ab0bfc11 4381 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 109:9296ab0bfc11 4382 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4383 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4384 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4385 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4386 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4387 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 4388 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 4389 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 109:9296ab0bfc11 4390
Kojto 109:9296ab0bfc11 4391 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 109:9296ab0bfc11 4392 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4393 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4394
Kojto 109:9296ab0bfc11 4395 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 109:9296ab0bfc11 4396 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 109:9296ab0bfc11 4397 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 109:9296ab0bfc11 4398 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 109:9296ab0bfc11 4399 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 109:9296ab0bfc11 4400 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 109:9296ab0bfc11 4401
Kojto 109:9296ab0bfc11 4402 /******************* Bit definition for TIM_DCR register *******************/
Kojto 109:9296ab0bfc11 4403 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 109:9296ab0bfc11 4404 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4405 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4406 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4407 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4408 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4409
Kojto 109:9296ab0bfc11 4410 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 109:9296ab0bfc11 4411 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4412 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4413 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4414 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4415 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4416
Kojto 109:9296ab0bfc11 4417 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 109:9296ab0bfc11 4418 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 109:9296ab0bfc11 4419
Kojto 109:9296ab0bfc11 4420 /******************* Bit definition for TIM14_OR register ********************/
Kojto 109:9296ab0bfc11 4421 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 109:9296ab0bfc11 4422 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4423 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4424
Kojto 109:9296ab0bfc11 4425 /******************************************************************************/
Kojto 109:9296ab0bfc11 4426 /* */
Kojto 109:9296ab0bfc11 4427 /* Touch Sensing Controller (TSC) */
Kojto 109:9296ab0bfc11 4428 /* */
Kojto 109:9296ab0bfc11 4429 /******************************************************************************/
Kojto 109:9296ab0bfc11 4430 /******************* Bit definition for TSC_CR register *********************/
Kojto 109:9296ab0bfc11 4431 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
Kojto 109:9296ab0bfc11 4432 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
Kojto 109:9296ab0bfc11 4433 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
Kojto 109:9296ab0bfc11 4434 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
Kojto 109:9296ab0bfc11 4435 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
Kojto 109:9296ab0bfc11 4436
Kojto 109:9296ab0bfc11 4437 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
Kojto 109:9296ab0bfc11 4438 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4439 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4440 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4441
Kojto 109:9296ab0bfc11 4442 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 109:9296ab0bfc11 4443 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4444 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4445 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4446
Kojto 109:9296ab0bfc11 4447 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
Kojto 109:9296ab0bfc11 4448 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
Kojto 109:9296ab0bfc11 4449
Kojto 109:9296ab0bfc11 4450 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 109:9296ab0bfc11 4451 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4452 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4453 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4454 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4455 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4456 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 4457 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 4458
Kojto 109:9296ab0bfc11 4459 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 109:9296ab0bfc11 4460 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4461 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4462 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4463 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4464
Kojto 109:9296ab0bfc11 4465 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 109:9296ab0bfc11 4466 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4467 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4468 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4469 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4470
Kojto 109:9296ab0bfc11 4471 /******************* Bit definition for TSC_IER register ********************/
Kojto 109:9296ab0bfc11 4472 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
Kojto 109:9296ab0bfc11 4473 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
Kojto 109:9296ab0bfc11 4474
Kojto 109:9296ab0bfc11 4475 /******************* Bit definition for TSC_ICR register ********************/
Kojto 109:9296ab0bfc11 4476 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
Kojto 109:9296ab0bfc11 4477 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
Kojto 109:9296ab0bfc11 4478
Kojto 109:9296ab0bfc11 4479 /******************* Bit definition for TSC_ISR register ********************/
Kojto 109:9296ab0bfc11 4480 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
Kojto 109:9296ab0bfc11 4481 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
Kojto 109:9296ab0bfc11 4482
Kojto 109:9296ab0bfc11 4483 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 109:9296ab0bfc11 4484 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4485 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4486 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4487 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4488 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4489 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4490 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4491 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4492 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4493 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4494 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4495 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4496 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4497 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4498 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4499 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4500 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4501 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4502 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4503 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4504 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4505 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4506 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4507 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4508 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4509 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4510 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4511 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4512 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4513 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4514 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4515 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 4516
Kojto 109:9296ab0bfc11 4517 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 109:9296ab0bfc11 4518 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4519 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4520 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4521 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4522 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4523 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4524 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4525 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4526 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4527 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4528 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4529 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4530 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4531 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4532 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4533 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4534 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4535 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4536 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4537 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4538 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4539 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4540 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4541 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4542 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4543 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4544 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4545 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4546 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 4547 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 4548 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 4549 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 4550
Kojto 109:9296ab0bfc11 4551 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 109:9296ab0bfc11 4552 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4553 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4554 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4555 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4556 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4557 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4558 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4559 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4560 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4561 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4562 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4563 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4564 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4565 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4566 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4567 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4568 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4569 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4570 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4571 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4572 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4573 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4574 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4575 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4576 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4577 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4578 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4579 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4580 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
Kojto 109:9296ab0bfc11 4581 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
Kojto 109:9296ab0bfc11 4582 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
Kojto 109:9296ab0bfc11 4583 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
Kojto 109:9296ab0bfc11 4584
Kojto 109:9296ab0bfc11 4585 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 109:9296ab0bfc11 4586 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
Kojto 109:9296ab0bfc11 4587 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
Kojto 109:9296ab0bfc11 4588 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
Kojto 109:9296ab0bfc11 4589 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
Kojto 109:9296ab0bfc11 4590 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
Kojto 109:9296ab0bfc11 4591 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
Kojto 109:9296ab0bfc11 4592 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
Kojto 109:9296ab0bfc11 4593 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
Kojto 109:9296ab0bfc11 4594 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
Kojto 109:9296ab0bfc11 4595 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
Kojto 109:9296ab0bfc11 4596 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
Kojto 109:9296ab0bfc11 4597 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
Kojto 109:9296ab0bfc11 4598 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
Kojto 109:9296ab0bfc11 4599 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
Kojto 109:9296ab0bfc11 4600 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
Kojto 109:9296ab0bfc11 4601 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
Kojto 109:9296ab0bfc11 4602 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
Kojto 109:9296ab0bfc11 4603 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
Kojto 109:9296ab0bfc11 4604 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
Kojto 109:9296ab0bfc11 4605 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
Kojto 109:9296ab0bfc11 4606 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
Kojto 109:9296ab0bfc11 4607 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
Kojto 109:9296ab0bfc11 4608 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
Kojto 109:9296ab0bfc11 4609 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
Kojto 109:9296ab0bfc11 4610 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
Kojto 109:9296ab0bfc11 4611 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
Kojto 109:9296ab0bfc11 4612 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
Kojto 109:9296ab0bfc11 4613 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
Kojto 109:9296ab0bfc11 4614 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
Kojto 109:9296ab0bfc11 4615 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
Kojto 109:9296ab0bfc11 4616 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
Kojto 109:9296ab0bfc11 4617 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
Kojto 109:9296ab0bfc11 4618
Kojto 109:9296ab0bfc11 4619 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 109:9296ab0bfc11 4620 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
Kojto 109:9296ab0bfc11 4621 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
Kojto 109:9296ab0bfc11 4622 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
Kojto 109:9296ab0bfc11 4623 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
Kojto 109:9296ab0bfc11 4624 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
Kojto 109:9296ab0bfc11 4625 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
Kojto 109:9296ab0bfc11 4626 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
Kojto 109:9296ab0bfc11 4627 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
Kojto 109:9296ab0bfc11 4628 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
Kojto 109:9296ab0bfc11 4629 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
Kojto 109:9296ab0bfc11 4630 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
Kojto 109:9296ab0bfc11 4631 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
Kojto 109:9296ab0bfc11 4632 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
Kojto 109:9296ab0bfc11 4633 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
Kojto 109:9296ab0bfc11 4634 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
Kojto 109:9296ab0bfc11 4635 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
Kojto 109:9296ab0bfc11 4636
Kojto 109:9296ab0bfc11 4637 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 109:9296ab0bfc11 4638 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
Kojto 109:9296ab0bfc11 4639
Kojto 109:9296ab0bfc11 4640 /******************************************************************************/
Kojto 109:9296ab0bfc11 4641 /* */
Kojto 109:9296ab0bfc11 4642 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 109:9296ab0bfc11 4643 /* */
Kojto 109:9296ab0bfc11 4644 /******************************************************************************/
Kojto 109:9296ab0bfc11 4645 /****************** Bit definition for USART_CR1 register *******************/
Kojto 109:9296ab0bfc11 4646 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 109:9296ab0bfc11 4647 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
Kojto 109:9296ab0bfc11 4648 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 109:9296ab0bfc11 4649 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 109:9296ab0bfc11 4650 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 109:9296ab0bfc11 4651 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 109:9296ab0bfc11 4652 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 109:9296ab0bfc11 4653 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 109:9296ab0bfc11 4654 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 109:9296ab0bfc11 4655 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 109:9296ab0bfc11 4656 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 109:9296ab0bfc11 4657 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 109:9296ab0bfc11 4658 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Kojto 109:9296ab0bfc11 4659 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 109:9296ab0bfc11 4660 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 109:9296ab0bfc11 4661 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 109:9296ab0bfc11 4662 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 109:9296ab0bfc11 4663 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4664 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4665 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4666 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4667 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 4668 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 109:9296ab0bfc11 4669 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4670 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4671 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4672 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4673 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 4674 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 109:9296ab0bfc11 4675 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 109:9296ab0bfc11 4676 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
Kojto 109:9296ab0bfc11 4677 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
Kojto 109:9296ab0bfc11 4678
Kojto 109:9296ab0bfc11 4679 /****************** Bit definition for USART_CR2 register *******************/
Kojto 109:9296ab0bfc11 4680 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 109:9296ab0bfc11 4681 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 109:9296ab0bfc11 4682 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 109:9296ab0bfc11 4683 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 109:9296ab0bfc11 4684 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 4685 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 4686 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 109:9296ab0bfc11 4687 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 109:9296ab0bfc11 4688 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4689 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4690 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 109:9296ab0bfc11 4691 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 109:9296ab0bfc11 4692 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 109:9296ab0bfc11 4693 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 109:9296ab0bfc11 4694 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 109:9296ab0bfc11 4695 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 109:9296ab0bfc11 4696 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Kojto 109:9296ab0bfc11 4697 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 109:9296ab0bfc11 4698 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4699 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4700 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 109:9296ab0bfc11 4701 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 109:9296ab0bfc11 4702
Kojto 109:9296ab0bfc11 4703 /****************** Bit definition for USART_CR3 register *******************/
Kojto 109:9296ab0bfc11 4704 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 4705 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 109:9296ab0bfc11 4706 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 109:9296ab0bfc11 4707 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 109:9296ab0bfc11 4708 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Kojto 109:9296ab0bfc11 4709 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Kojto 109:9296ab0bfc11 4710 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 109:9296ab0bfc11 4711 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 109:9296ab0bfc11 4712 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 109:9296ab0bfc11 4713 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 109:9296ab0bfc11 4714 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 109:9296ab0bfc11 4715 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 109:9296ab0bfc11 4716 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 109:9296ab0bfc11 4717 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 109:9296ab0bfc11 4718 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 109:9296ab0bfc11 4719 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 109:9296ab0bfc11 4720 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 109:9296ab0bfc11 4721 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4722 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4723 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4724 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 109:9296ab0bfc11 4725 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4726 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4727 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
Kojto 109:9296ab0bfc11 4728
Kojto 109:9296ab0bfc11 4729 /****************** Bit definition for USART_BRR register *******************/
Kojto 109:9296ab0bfc11 4730 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 109:9296ab0bfc11 4731 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 109:9296ab0bfc11 4732
Kojto 109:9296ab0bfc11 4733 /****************** Bit definition for USART_GTPR register ******************/
Kojto 109:9296ab0bfc11 4734 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 109:9296ab0bfc11 4735 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 109:9296ab0bfc11 4736
Kojto 109:9296ab0bfc11 4737
Kojto 109:9296ab0bfc11 4738 /******************* Bit definition for USART_RTOR register *****************/
Kojto 109:9296ab0bfc11 4739 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 109:9296ab0bfc11 4740 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 109:9296ab0bfc11 4741
Kojto 109:9296ab0bfc11 4742 /******************* Bit definition for USART_RQR register ******************/
Kojto 109:9296ab0bfc11 4743 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Kojto 109:9296ab0bfc11 4744 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Kojto 109:9296ab0bfc11 4745 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Kojto 109:9296ab0bfc11 4746 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Kojto 109:9296ab0bfc11 4747 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
Kojto 109:9296ab0bfc11 4748
Kojto 109:9296ab0bfc11 4749 /******************* Bit definition for USART_ISR register ******************/
Kojto 109:9296ab0bfc11 4750 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 109:9296ab0bfc11 4751 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 109:9296ab0bfc11 4752 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 109:9296ab0bfc11 4753 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 109:9296ab0bfc11 4754 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 109:9296ab0bfc11 4755 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 109:9296ab0bfc11 4756 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 109:9296ab0bfc11 4757 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 109:9296ab0bfc11 4758 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 109:9296ab0bfc11 4759 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 109:9296ab0bfc11 4760 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 109:9296ab0bfc11 4761 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 109:9296ab0bfc11 4762 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 109:9296ab0bfc11 4763 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 109:9296ab0bfc11 4764 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 109:9296ab0bfc11 4765 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 109:9296ab0bfc11 4766 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 109:9296ab0bfc11 4767 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 109:9296ab0bfc11 4768 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Kojto 109:9296ab0bfc11 4769 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Kojto 109:9296ab0bfc11 4770 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 4771 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 4772
Kojto 109:9296ab0bfc11 4773 /******************* Bit definition for USART_ICR register ******************/
Kojto 109:9296ab0bfc11 4774 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 109:9296ab0bfc11 4775 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 109:9296ab0bfc11 4776 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 109:9296ab0bfc11 4777 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 109:9296ab0bfc11 4778 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 109:9296ab0bfc11 4779 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 109:9296ab0bfc11 4780 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Kojto 109:9296ab0bfc11 4781 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 109:9296ab0bfc11 4782 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 109:9296ab0bfc11 4783 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Kojto 109:9296ab0bfc11 4784 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 109:9296ab0bfc11 4785 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Kojto 109:9296ab0bfc11 4786
Kojto 109:9296ab0bfc11 4787 /******************* Bit definition for USART_RDR register ******************/
Kojto 109:9296ab0bfc11 4788 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 109:9296ab0bfc11 4789
Kojto 109:9296ab0bfc11 4790 /******************* Bit definition for USART_TDR register ******************/
Kojto 109:9296ab0bfc11 4791 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 109:9296ab0bfc11 4792
Kojto 109:9296ab0bfc11 4793 /******************************************************************************/
Kojto 109:9296ab0bfc11 4794 /* */
Kojto 109:9296ab0bfc11 4795 /* USB Device General registers */
Kojto 109:9296ab0bfc11 4796 /* */
Kojto 109:9296ab0bfc11 4797 /******************************************************************************/
Kojto 109:9296ab0bfc11 4798 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
Kojto 109:9296ab0bfc11 4799 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
Kojto 109:9296ab0bfc11 4800 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
Kojto 109:9296ab0bfc11 4801 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
Kojto 109:9296ab0bfc11 4802 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
Kojto 109:9296ab0bfc11 4803 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
Kojto 109:9296ab0bfc11 4804 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
Kojto 109:9296ab0bfc11 4805
Kojto 109:9296ab0bfc11 4806 /**************************** ISTR interrupt events *************************/
Kojto 109:9296ab0bfc11 4807 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
Kojto 109:9296ab0bfc11 4808 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
Kojto 109:9296ab0bfc11 4809 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
Kojto 109:9296ab0bfc11 4810 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
Kojto 109:9296ab0bfc11 4811 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
Kojto 109:9296ab0bfc11 4812 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
Kojto 109:9296ab0bfc11 4813 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
Kojto 109:9296ab0bfc11 4814 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
Kojto 109:9296ab0bfc11 4815 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
Kojto 109:9296ab0bfc11 4816 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
Kojto 109:9296ab0bfc11 4817 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
Kojto 109:9296ab0bfc11 4818
Kojto 109:9296ab0bfc11 4819 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Kojto 109:9296ab0bfc11 4820 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Kojto 109:9296ab0bfc11 4821 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Kojto 109:9296ab0bfc11 4822 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Kojto 109:9296ab0bfc11 4823 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Kojto 109:9296ab0bfc11 4824 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Kojto 109:9296ab0bfc11 4825 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Kojto 109:9296ab0bfc11 4826 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Kojto 109:9296ab0bfc11 4827 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
Kojto 109:9296ab0bfc11 4828
Kojto 109:9296ab0bfc11 4829 /************************* CNTR control register bits definitions ***********/
Kojto 109:9296ab0bfc11 4830 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
Kojto 109:9296ab0bfc11 4831 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
Kojto 109:9296ab0bfc11 4832 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
Kojto 109:9296ab0bfc11 4833 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
Kojto 109:9296ab0bfc11 4834 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
Kojto 109:9296ab0bfc11 4835 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
Kojto 109:9296ab0bfc11 4836 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
Kojto 109:9296ab0bfc11 4837 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
Kojto 109:9296ab0bfc11 4838 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
Kojto 109:9296ab0bfc11 4839 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
Kojto 109:9296ab0bfc11 4840 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
Kojto 109:9296ab0bfc11 4841 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
Kojto 109:9296ab0bfc11 4842 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
Kojto 109:9296ab0bfc11 4843 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
Kojto 109:9296ab0bfc11 4844 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
Kojto 109:9296ab0bfc11 4845
Kojto 109:9296ab0bfc11 4846 /************************* BCDR control register bits definitions ***********/
Kojto 109:9296ab0bfc11 4847 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
Kojto 109:9296ab0bfc11 4848 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
Kojto 109:9296ab0bfc11 4849 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
Kojto 109:9296ab0bfc11 4850 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
Kojto 109:9296ab0bfc11 4851 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
Kojto 109:9296ab0bfc11 4852 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
Kojto 109:9296ab0bfc11 4853 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
Kojto 109:9296ab0bfc11 4854 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
Kojto 109:9296ab0bfc11 4855 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
Kojto 109:9296ab0bfc11 4856
Kojto 109:9296ab0bfc11 4857 /*************************** LPM register bits definitions ******************/
Kojto 109:9296ab0bfc11 4858 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
Kojto 109:9296ab0bfc11 4859 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 109:9296ab0bfc11 4860 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
Kojto 109:9296ab0bfc11 4861 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
Kojto 109:9296ab0bfc11 4862
Kojto 109:9296ab0bfc11 4863 /******************** FNR Frame Number Register bit definitions ************/
Kojto 109:9296ab0bfc11 4864 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
Kojto 109:9296ab0bfc11 4865 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
Kojto 109:9296ab0bfc11 4866 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
Kojto 109:9296ab0bfc11 4867 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
Kojto 109:9296ab0bfc11 4868 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
Kojto 109:9296ab0bfc11 4869
Kojto 109:9296ab0bfc11 4870 /******************** DADDR Device ADDRess bit definitions ****************/
Kojto 109:9296ab0bfc11 4871 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
Kojto 109:9296ab0bfc11 4872 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
Kojto 109:9296ab0bfc11 4873
Kojto 109:9296ab0bfc11 4874 /****************************** Endpoint register *************************/
Kojto 109:9296ab0bfc11 4875 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Kojto 109:9296ab0bfc11 4876 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
Kojto 109:9296ab0bfc11 4877 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
Kojto 109:9296ab0bfc11 4878 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
Kojto 109:9296ab0bfc11 4879 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
Kojto 109:9296ab0bfc11 4880 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
Kojto 109:9296ab0bfc11 4881 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
Kojto 109:9296ab0bfc11 4882 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
Kojto 109:9296ab0bfc11 4883 /* bit positions */
Kojto 109:9296ab0bfc11 4884 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
Kojto 109:9296ab0bfc11 4885 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
Kojto 109:9296ab0bfc11 4886 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
Kojto 109:9296ab0bfc11 4887 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
Kojto 109:9296ab0bfc11 4888 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
Kojto 109:9296ab0bfc11 4889 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
Kojto 109:9296ab0bfc11 4890 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
Kojto 109:9296ab0bfc11 4891 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
Kojto 109:9296ab0bfc11 4892 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
Kojto 109:9296ab0bfc11 4893 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
Kojto 109:9296ab0bfc11 4894
Kojto 109:9296ab0bfc11 4895 /* EndPoint REGister MASK (no toggle fields) */
Kojto 109:9296ab0bfc11 4896 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 109:9296ab0bfc11 4897 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 109:9296ab0bfc11 4898 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
Kojto 109:9296ab0bfc11 4899 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
Kojto 109:9296ab0bfc11 4900 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
Kojto 109:9296ab0bfc11 4901 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
Kojto 109:9296ab0bfc11 4902 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
Kojto 109:9296ab0bfc11 4903 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 109:9296ab0bfc11 4904
Kojto 109:9296ab0bfc11 4905 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 109:9296ab0bfc11 4906 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 109:9296ab0bfc11 4907 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
Kojto 109:9296ab0bfc11 4908 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
Kojto 109:9296ab0bfc11 4909 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
Kojto 109:9296ab0bfc11 4910 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
Kojto 109:9296ab0bfc11 4911 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 109:9296ab0bfc11 4912 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 109:9296ab0bfc11 4913 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 109:9296ab0bfc11 4914 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 109:9296ab0bfc11 4915 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
Kojto 109:9296ab0bfc11 4916 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
Kojto 109:9296ab0bfc11 4917 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
Kojto 109:9296ab0bfc11 4918 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
Kojto 109:9296ab0bfc11 4919 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 109:9296ab0bfc11 4920 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 109:9296ab0bfc11 4921 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 109:9296ab0bfc11 4922
Kojto 109:9296ab0bfc11 4923 /******************************************************************************/
Kojto 109:9296ab0bfc11 4924 /* */
Kojto 109:9296ab0bfc11 4925 /* Window WATCHDOG (WWDG) */
Kojto 109:9296ab0bfc11 4926 /* */
Kojto 109:9296ab0bfc11 4927 /******************************************************************************/
Kojto 109:9296ab0bfc11 4928 /******************* Bit definition for WWDG_CR register ********************/
Kojto 109:9296ab0bfc11 4929 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 109:9296ab0bfc11 4930 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4931 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4932 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4933 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4934 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4935 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 4936 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 4937
Kojto 109:9296ab0bfc11 4938 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 109:9296ab0bfc11 4939
Kojto 109:9296ab0bfc11 4940 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 109:9296ab0bfc11 4941 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 109:9296ab0bfc11 4942 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4943 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4944 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 4945 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 4946 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 4947 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 4948 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 4949
Kojto 109:9296ab0bfc11 4950 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 109:9296ab0bfc11 4951 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 4952 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 4953
Kojto 109:9296ab0bfc11 4954 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 109:9296ab0bfc11 4955
Kojto 109:9296ab0bfc11 4956 /******************* Bit definition for WWDG_SR register ********************/
Kojto 109:9296ab0bfc11 4957 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 109:9296ab0bfc11 4958
Kojto 109:9296ab0bfc11 4959 /**
Kojto 109:9296ab0bfc11 4960 * @}
Kojto 109:9296ab0bfc11 4961 */
Kojto 109:9296ab0bfc11 4962
Kojto 109:9296ab0bfc11 4963 /**
Kojto 109:9296ab0bfc11 4964 * @}
Kojto 109:9296ab0bfc11 4965 */
Kojto 109:9296ab0bfc11 4966
Kojto 109:9296ab0bfc11 4967
Kojto 109:9296ab0bfc11 4968 /** @addtogroup Exported_macro
Kojto 109:9296ab0bfc11 4969 * @{
Kojto 109:9296ab0bfc11 4970 */
Kojto 109:9296ab0bfc11 4971
Kojto 109:9296ab0bfc11 4972 /****************************** ADC Instances *********************************/
Kojto 109:9296ab0bfc11 4973 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 109:9296ab0bfc11 4974
Kojto 109:9296ab0bfc11 4975 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 109:9296ab0bfc11 4976
Kojto 109:9296ab0bfc11 4977 /******************************* CAN Instances ********************************/
Kojto 109:9296ab0bfc11 4978 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
Kojto 109:9296ab0bfc11 4979
Kojto 109:9296ab0bfc11 4980 /****************************** CEC Instances *********************************/
Kojto 109:9296ab0bfc11 4981 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
Kojto 109:9296ab0bfc11 4982
Kojto 109:9296ab0bfc11 4983 /****************************** CRC Instances *********************************/
Kojto 109:9296ab0bfc11 4984 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 109:9296ab0bfc11 4985
Kojto 109:9296ab0bfc11 4986 /******************************* DMA Instances ******************************/
Kojto 109:9296ab0bfc11 4987 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 109:9296ab0bfc11 4988 ((INSTANCE) == DMA1_Channel2) || \
Kojto 109:9296ab0bfc11 4989 ((INSTANCE) == DMA1_Channel3) || \
Kojto 109:9296ab0bfc11 4990 ((INSTANCE) == DMA1_Channel4) || \
Kojto 109:9296ab0bfc11 4991 ((INSTANCE) == DMA1_Channel5))
Kojto 109:9296ab0bfc11 4992
Kojto 109:9296ab0bfc11 4993 /****************************** GPIO Instances ********************************/
Kojto 109:9296ab0bfc11 4994 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 4995 ((INSTANCE) == GPIOB) || \
Kojto 109:9296ab0bfc11 4996 ((INSTANCE) == GPIOC) || \
Kojto 109:9296ab0bfc11 4997 ((INSTANCE) == GPIOF))
Kojto 109:9296ab0bfc11 4998
Kojto 109:9296ab0bfc11 4999 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 5000 ((INSTANCE) == GPIOB) || \
Kojto 109:9296ab0bfc11 5001 ((INSTANCE) == GPIOF))
Kojto 109:9296ab0bfc11 5002
Kojto 109:9296ab0bfc11 5003 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 5004 ((INSTANCE) == GPIOB))
Kojto 109:9296ab0bfc11 5005
Kojto 109:9296ab0bfc11 5006 /****************************** I2C Instances *********************************/
Kojto 109:9296ab0bfc11 5007 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 109:9296ab0bfc11 5008
Kojto 109:9296ab0bfc11 5009 /****************************** I2S Instances *********************************/
Kojto 109:9296ab0bfc11 5010 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
Kojto 109:9296ab0bfc11 5011
Kojto 109:9296ab0bfc11 5012 /****************************** IWDG Instances ********************************/
Kojto 109:9296ab0bfc11 5013 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 109:9296ab0bfc11 5014
Kojto 109:9296ab0bfc11 5015 /****************************** RTC Instances *********************************/
Kojto 109:9296ab0bfc11 5016 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 109:9296ab0bfc11 5017
Kojto 109:9296ab0bfc11 5018 /****************************** SMBUS Instances *********************************/
Kojto 109:9296ab0bfc11 5019 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 109:9296ab0bfc11 5020
Kojto 109:9296ab0bfc11 5021 /****************************** SPI Instances *********************************/
Kojto 109:9296ab0bfc11 5022 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 109:9296ab0bfc11 5023 ((INSTANCE) == SPI2))
Kojto 109:9296ab0bfc11 5024
Kojto 109:9296ab0bfc11 5025 /****************************** TIM Instances *********************************/
Kojto 109:9296ab0bfc11 5026 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5027 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5028 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5029 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5030 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 5031 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5032 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5033
Kojto 109:9296ab0bfc11 5034 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5035 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5036 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5037 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5038 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 5039 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5040 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5041
Kojto 109:9296ab0bfc11 5042 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5043 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5044 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5045 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5046
Kojto 109:9296ab0bfc11 5047 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5048 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5049 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5050 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5051
Kojto 109:9296ab0bfc11 5052 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5053 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5054 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5055 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5056
Kojto 109:9296ab0bfc11 5057 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5058 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5059
Kojto 109:9296ab0bfc11 5060 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5061 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5062
Kojto 109:9296ab0bfc11 5063 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5064 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5065 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5066 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5067
Kojto 109:9296ab0bfc11 5068 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5069 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5070 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5071 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5072
Kojto 109:9296ab0bfc11 5073 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5074 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5075 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5076 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5077
Kojto 109:9296ab0bfc11 5078 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5079 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5080 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5081 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5082
Kojto 109:9296ab0bfc11 5083 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5084 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5085 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5086 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5087
Kojto 109:9296ab0bfc11 5088 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5089 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5090 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5091 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5092
Kojto 109:9296ab0bfc11 5093 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5094 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5095 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5096 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5097
Kojto 109:9296ab0bfc11 5098 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5099 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5100
Kojto 109:9296ab0bfc11 5101 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5102 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5103 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5104 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5105
Kojto 109:9296ab0bfc11 5106 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5107 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5108 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5109 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5110
Kojto 109:9296ab0bfc11 5111 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5112 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5113 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5114 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5115
Kojto 109:9296ab0bfc11 5116 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5117 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5118 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5119 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5120
Kojto 109:9296ab0bfc11 5121 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5122 ((INSTANCE) == TIM2)
Kojto 109:9296ab0bfc11 5123
Kojto 109:9296ab0bfc11 5124 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5125 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5126 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5127 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5128 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5129 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5130
Kojto 109:9296ab0bfc11 5131 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5132 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5133 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5134 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5135
Kojto 109:9296ab0bfc11 5136 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 5137 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 5138 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 5139 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 5140 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 5141 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 5142 || \
Kojto 109:9296ab0bfc11 5143 (((INSTANCE) == TIM2) && \
Kojto 109:9296ab0bfc11 5144 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 5145 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 5146 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 5147 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 5148 || \
Kojto 109:9296ab0bfc11 5149 (((INSTANCE) == TIM3) && \
Kojto 109:9296ab0bfc11 5150 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 5151 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 5152 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 5153 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 5154 || \
Kojto 109:9296ab0bfc11 5155 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 5156 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 109:9296ab0bfc11 5157 || \
Kojto 109:9296ab0bfc11 5158 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 5159 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 109:9296ab0bfc11 5160
Kojto 109:9296ab0bfc11 5161 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 5162 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 5163 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 5164 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 5165 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 109:9296ab0bfc11 5166 || \
Kojto 109:9296ab0bfc11 5167 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 5168 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 109:9296ab0bfc11 5169 || \
Kojto 109:9296ab0bfc11 5170 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 5171 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 109:9296ab0bfc11 5172
Kojto 109:9296ab0bfc11 5173 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5174 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5175 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5176 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5177
Kojto 109:9296ab0bfc11 5178 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5179 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5180 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5181 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5182
Kojto 109:9296ab0bfc11 5183 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5184 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5185 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5186 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5187 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 5188 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5189 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5190
Kojto 109:9296ab0bfc11 5191 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5192 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5193
Kojto 109:9296ab0bfc11 5194 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5195 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5196
Kojto 109:9296ab0bfc11 5197 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5198 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5199 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5200 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5201 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5202 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5203
Kojto 109:9296ab0bfc11 5204 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5205 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5206 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5207 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5208 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5209 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5210
Kojto 109:9296ab0bfc11 5211 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5212 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5213 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5214 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5215
Kojto 109:9296ab0bfc11 5216 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5217 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5218 ((INSTANCE) == TIM14))
Kojto 109:9296ab0bfc11 5219
Kojto 109:9296ab0bfc11 5220 /****************************** TSC Instances *********************************/
Kojto 109:9296ab0bfc11 5221 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Kojto 109:9296ab0bfc11 5222
Kojto 109:9296ab0bfc11 5223 /*********************** UART Instances : IRDA mode ***************************/
Kojto 109:9296ab0bfc11 5224 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5225
Kojto 109:9296ab0bfc11 5226 /********************* UART Instances : Smard card mode ***********************/
Kojto 109:9296ab0bfc11 5227 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5228
Kojto 109:9296ab0bfc11 5229 /******************** USART Instances : Synchronous mode **********************/
Kojto 109:9296ab0bfc11 5230 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 5231 ((INSTANCE) == USART2))
Kojto 109:9296ab0bfc11 5232
Kojto 109:9296ab0bfc11 5233 /******************** USART Instances : auto Baud rate detection **************/
Kojto 109:9296ab0bfc11 5234 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5235
Kojto 109:9296ab0bfc11 5236 /******************** UART Instances : Asynchronous mode **********************/
Kojto 109:9296ab0bfc11 5237 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 5238 ((INSTANCE) == USART2))
Kojto 109:9296ab0bfc11 5239
Kojto 109:9296ab0bfc11 5240 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 109:9296ab0bfc11 5241 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 5242 ((INSTANCE) == USART2))
Kojto 109:9296ab0bfc11 5243
Kojto 109:9296ab0bfc11 5244 /****************** UART Instances : Hardware Flow control ********************/
Kojto 109:9296ab0bfc11 5245 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 5246 ((INSTANCE) == USART2))
Kojto 109:9296ab0bfc11 5247
Kojto 109:9296ab0bfc11 5248 /****************** UART Instances : LIN mode ********************/
Kojto 109:9296ab0bfc11 5249 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5250
Kojto 109:9296ab0bfc11 5251 /****************** UART Instances : wakeup from stop mode ********************/
Kojto 109:9296ab0bfc11 5252 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5253
Kojto 109:9296ab0bfc11 5254 /****************** UART Instances : Auto Baud Rate detection ********************/
Kojto 109:9296ab0bfc11 5255 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 5256
Kojto 109:9296ab0bfc11 5257 /****************** UART Instances : Driver enable detection ********************/
Kojto 109:9296ab0bfc11 5258 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 5259 ((INSTANCE) == USART2))
Kojto 109:9296ab0bfc11 5260 /****************************** USB Instances ********************************/
Kojto 109:9296ab0bfc11 5261 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 109:9296ab0bfc11 5262
Kojto 109:9296ab0bfc11 5263 /****************************** WWDG Instances ********************************/
Kojto 109:9296ab0bfc11 5264 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 109:9296ab0bfc11 5265
Kojto 109:9296ab0bfc11 5266 /**
Kojto 109:9296ab0bfc11 5267 * @}
Kojto 109:9296ab0bfc11 5268 */
Kojto 109:9296ab0bfc11 5269
Kojto 109:9296ab0bfc11 5270
Kojto 109:9296ab0bfc11 5271 /******************************************************************************/
Kojto 109:9296ab0bfc11 5272 /* For a painless codes migration between the STM32F0xx device product */
Kojto 109:9296ab0bfc11 5273 /* lines, the aliases defined below are put in place to overcome the */
Kojto 109:9296ab0bfc11 5274 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 109:9296ab0bfc11 5275 /* No need to update developed interrupt code when moving across */
Kojto 109:9296ab0bfc11 5276 /* product lines within the same STM32F0 Family */
Kojto 109:9296ab0bfc11 5277 /******************************************************************************/
Kojto 109:9296ab0bfc11 5278
Kojto 109:9296ab0bfc11 5279 /* Aliases for __IRQn */
Kojto 109:9296ab0bfc11 5280 #define PVD_IRQn PVD_VDDIO2_IRQn
Kojto 109:9296ab0bfc11 5281 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
Kojto 109:9296ab0bfc11 5282 #define RCC_IRQn RCC_CRS_IRQn
Kojto 109:9296ab0bfc11 5283 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Kojto 109:9296ab0bfc11 5284 #define ADC1_COMP_IRQn ADC1_IRQn
Kojto 109:9296ab0bfc11 5285
Kojto 109:9296ab0bfc11 5286 /* Aliases for __IRQHandler */
Kojto 109:9296ab0bfc11 5287 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 109:9296ab0bfc11 5288 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 109:9296ab0bfc11 5289 #define RCC_IRQHandler RCC_CRS_IRQHandler
Kojto 109:9296ab0bfc11 5290 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 109:9296ab0bfc11 5291 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
Kojto 109:9296ab0bfc11 5292
Kojto 109:9296ab0bfc11 5293 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 5294 }
Kojto 109:9296ab0bfc11 5295 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 5296
Kojto 109:9296ab0bfc11 5297 #endif /* __STM32F042x6_H */
Kojto 109:9296ab0bfc11 5298
Kojto 109:9296ab0bfc11 5299 /**
Kojto 109:9296ab0bfc11 5300 * @}
Kojto 109:9296ab0bfc11 5301 */
Kojto 109:9296ab0bfc11 5302
Kojto 109:9296ab0bfc11 5303 /**
Kojto 109:9296ab0bfc11 5304 * @}
Kojto 109:9296ab0bfc11 5305 */
Kojto 109:9296ab0bfc11 5306
Kojto 109:9296ab0bfc11 5307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/