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TARGET_DISCO_L476VG/stm32l4xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
107:4f6c30876dfa 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 107:4f6c30876dfa 1 /**
Kojto 107:4f6c30876dfa 2 ******************************************************************************
Kojto 107:4f6c30876dfa 3 * @file stm32l4xx_hal_rcc_ex.h
Kojto 107:4f6c30876dfa 4 * @author MCD Application Team
Kojto 107:4f6c30876dfa 5 * @version V1.0.0
Kojto 107:4f6c30876dfa 6 * @date 26-June-2015
Kojto 107:4f6c30876dfa 7 * @brief Header file of RCC HAL Extended module.
Kojto 107:4f6c30876dfa 8 ******************************************************************************
Kojto 107:4f6c30876dfa 9 * @attention
Kojto 107:4f6c30876dfa 10 *
Kojto 107:4f6c30876dfa 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 107:4f6c30876dfa 12 *
Kojto 107:4f6c30876dfa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 107:4f6c30876dfa 14 * are permitted provided that the following conditions are met:
Kojto 107:4f6c30876dfa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 107:4f6c30876dfa 16 * this list of conditions and the following disclaimer.
Kojto 107:4f6c30876dfa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 107:4f6c30876dfa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 107:4f6c30876dfa 19 * and/or other materials provided with the distribution.
Kojto 107:4f6c30876dfa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 107:4f6c30876dfa 21 * may be used to endorse or promote products derived from this software
Kojto 107:4f6c30876dfa 22 * without specific prior written permission.
Kojto 107:4f6c30876dfa 23 *
Kojto 107:4f6c30876dfa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 107:4f6c30876dfa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 107:4f6c30876dfa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 107:4f6c30876dfa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 107:4f6c30876dfa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 107:4f6c30876dfa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 107:4f6c30876dfa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 107:4f6c30876dfa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 107:4f6c30876dfa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 107:4f6c30876dfa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 107:4f6c30876dfa 34 *
Kojto 107:4f6c30876dfa 35 ******************************************************************************
Kojto 107:4f6c30876dfa 36 */
Kojto 107:4f6c30876dfa 37
Kojto 107:4f6c30876dfa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 107:4f6c30876dfa 39 #ifndef __STM32L4xx_HAL_RCC_EX_H
Kojto 107:4f6c30876dfa 40 #define __STM32L4xx_HAL_RCC_EX_H
Kojto 107:4f6c30876dfa 41
Kojto 107:4f6c30876dfa 42 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 43 extern "C" {
Kojto 107:4f6c30876dfa 44 #endif
Kojto 107:4f6c30876dfa 45
Kojto 107:4f6c30876dfa 46 /* Includes ------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 47 #include "stm32l4xx_hal_def.h"
Kojto 107:4f6c30876dfa 48
Kojto 107:4f6c30876dfa 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 107:4f6c30876dfa 50 * @{
Kojto 107:4f6c30876dfa 51 */
Kojto 107:4f6c30876dfa 52
Kojto 107:4f6c30876dfa 53 /** @addtogroup RCCEx
Kojto 107:4f6c30876dfa 54 * @{
Kojto 107:4f6c30876dfa 55 */
Kojto 107:4f6c30876dfa 56
Kojto 107:4f6c30876dfa 57 /* Exported types ------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 58
Kojto 107:4f6c30876dfa 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 107:4f6c30876dfa 60 * @{
Kojto 107:4f6c30876dfa 61 */
Kojto 107:4f6c30876dfa 62
Kojto 107:4f6c30876dfa 63 /**
Kojto 107:4f6c30876dfa 64 * @brief PLLSAI1 Clock structure definition
Kojto 107:4f6c30876dfa 65 */
Kojto 107:4f6c30876dfa 66 typedef struct
Kojto 107:4f6c30876dfa 67 {
Kojto 107:4f6c30876dfa 68
Kojto 107:4f6c30876dfa 69 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 107:4f6c30876dfa 70 This parameter must be a number between 8 and 86. */
Kojto 107:4f6c30876dfa 71
Kojto 107:4f6c30876dfa 72 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 73 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 107:4f6c30876dfa 74
Kojto 107:4f6c30876dfa 75 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 107:4f6c30876dfa 76 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto 107:4f6c30876dfa 77
Kojto 107:4f6c30876dfa 78 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
Kojto 107:4f6c30876dfa 79 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 107:4f6c30876dfa 80
Kojto 107:4f6c30876dfa 81 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
Kojto 107:4f6c30876dfa 82 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
Kojto 107:4f6c30876dfa 83 }RCC_PLLSAI1InitTypeDef;
Kojto 107:4f6c30876dfa 84
Kojto 107:4f6c30876dfa 85 /**
Kojto 107:4f6c30876dfa 86 * @brief PLLSAI2 Clock structure definition
Kojto 107:4f6c30876dfa 87 */
Kojto 107:4f6c30876dfa 88 typedef struct
Kojto 107:4f6c30876dfa 89 {
Kojto 107:4f6c30876dfa 90
Kojto 107:4f6c30876dfa 91 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 107:4f6c30876dfa 92 This parameter must be a number between 8 and 86. */
Kojto 107:4f6c30876dfa 93
Kojto 107:4f6c30876dfa 94 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 95 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 107:4f6c30876dfa 96
Kojto 107:4f6c30876dfa 97 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
Kojto 107:4f6c30876dfa 98 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 107:4f6c30876dfa 99
Kojto 107:4f6c30876dfa 100 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
Kojto 107:4f6c30876dfa 101 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
Kojto 107:4f6c30876dfa 102 }RCC_PLLSAI2InitTypeDef;
Kojto 107:4f6c30876dfa 103
Kojto 107:4f6c30876dfa 104 /**
Kojto 107:4f6c30876dfa 105 * @brief RCC extended clocks structure definition
Kojto 107:4f6c30876dfa 106 */
Kojto 107:4f6c30876dfa 107 typedef struct
Kojto 107:4f6c30876dfa 108 {
Kojto 107:4f6c30876dfa 109 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 107:4f6c30876dfa 110 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 107:4f6c30876dfa 111
Kojto 107:4f6c30876dfa 112 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
Kojto 107:4f6c30876dfa 113 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
Kojto 107:4f6c30876dfa 114
Kojto 107:4f6c30876dfa 115 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
Kojto 107:4f6c30876dfa 116 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
Kojto 107:4f6c30876dfa 117
Kojto 107:4f6c30876dfa 118 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
Kojto 107:4f6c30876dfa 119 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 107:4f6c30876dfa 120
Kojto 107:4f6c30876dfa 121 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
Kojto 107:4f6c30876dfa 122 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 107:4f6c30876dfa 123
Kojto 107:4f6c30876dfa 124 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
Kojto 107:4f6c30876dfa 125 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 107:4f6c30876dfa 126
Kojto 107:4f6c30876dfa 127 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
Kojto 107:4f6c30876dfa 128 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 107:4f6c30876dfa 129
Kojto 107:4f6c30876dfa 130 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
Kojto 107:4f6c30876dfa 131 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 107:4f6c30876dfa 132
Kojto 107:4f6c30876dfa 133 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
Kojto 107:4f6c30876dfa 134 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
Kojto 107:4f6c30876dfa 135
Kojto 107:4f6c30876dfa 136 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
Kojto 107:4f6c30876dfa 137 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 107:4f6c30876dfa 138
Kojto 107:4f6c30876dfa 139 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
Kojto 107:4f6c30876dfa 140 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 107:4f6c30876dfa 141
Kojto 107:4f6c30876dfa 142 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
Kojto 107:4f6c30876dfa 143 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 107:4f6c30876dfa 144
Kojto 107:4f6c30876dfa 145 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
Kojto 107:4f6c30876dfa 146 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 107:4f6c30876dfa 147
Kojto 107:4f6c30876dfa 148 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
Kojto 107:4f6c30876dfa 149 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
Kojto 107:4f6c30876dfa 150
Kojto 107:4f6c30876dfa 151 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
Kojto 107:4f6c30876dfa 152 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 107:4f6c30876dfa 153
Kojto 107:4f6c30876dfa 154 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
Kojto 107:4f6c30876dfa 155 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 107:4f6c30876dfa 156
Kojto 107:4f6c30876dfa 157 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 158
Kojto 107:4f6c30876dfa 159 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
Kojto 107:4f6c30876dfa 160 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 107:4f6c30876dfa 161
Kojto 107:4f6c30876dfa 162 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 163
Kojto 107:4f6c30876dfa 164 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
Kojto 107:4f6c30876dfa 165 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto 107:4f6c30876dfa 166
Kojto 107:4f6c30876dfa 167 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
Kojto 107:4f6c30876dfa 168 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
Kojto 107:4f6c30876dfa 169
Kojto 107:4f6c30876dfa 170 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
Kojto 107:4f6c30876dfa 171 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
Kojto 107:4f6c30876dfa 172
Kojto 107:4f6c30876dfa 173 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
Kojto 107:4f6c30876dfa 174 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
Kojto 107:4f6c30876dfa 175
Kojto 107:4f6c30876dfa 176 uint32_t DfsdmClockSelection; /*!< Specifies DFSDM clock source.
Kojto 107:4f6c30876dfa 177 This parameter can be a value of @ref RCCEx_DFSDM_Clock_Source */
Kojto 107:4f6c30876dfa 178
Kojto 107:4f6c30876dfa 179 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
Kojto 107:4f6c30876dfa 180 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 107:4f6c30876dfa 181 }RCC_PeriphCLKInitTypeDef;
Kojto 107:4f6c30876dfa 182
Kojto 107:4f6c30876dfa 183 /**
Kojto 107:4f6c30876dfa 184 * @}
Kojto 107:4f6c30876dfa 185 */
Kojto 107:4f6c30876dfa 186
Kojto 107:4f6c30876dfa 187 /* Exported constants --------------------------------------------------------*/
Kojto 107:4f6c30876dfa 188 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 107:4f6c30876dfa 189 * @{
Kojto 107:4f6c30876dfa 190 */
Kojto 107:4f6c30876dfa 191
Kojto 107:4f6c30876dfa 192 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
Kojto 107:4f6c30876dfa 193 * @{
Kojto 107:4f6c30876dfa 194 */
Kojto 107:4f6c30876dfa 195 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000 /*!< LSI selection for low speed clock output */
Kojto 107:4f6c30876dfa 196 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
Kojto 107:4f6c30876dfa 197 /**
Kojto 107:4f6c30876dfa 198 * @}
Kojto 107:4f6c30876dfa 199 */
Kojto 107:4f6c30876dfa 200
Kojto 107:4f6c30876dfa 201 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
Kojto 107:4f6c30876dfa 202 * @{
Kojto 107:4f6c30876dfa 203 */
Kojto 107:4f6c30876dfa 204 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 205 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 206 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 207 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 208 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 209 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 210 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 211 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 212 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 213 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 214 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 215 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 216 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 217 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 218 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 219 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 220 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 221 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 222 #define RCC_PERIPHCLK_DFSDM ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 223 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 224 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 225 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 226 /**
Kojto 107:4f6c30876dfa 227 * @}
Kojto 107:4f6c30876dfa 228 */
Kojto 107:4f6c30876dfa 229
Kojto 107:4f6c30876dfa 230
Kojto 107:4f6c30876dfa 231 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
Kojto 107:4f6c30876dfa 232 * @{
Kojto 107:4f6c30876dfa 233 */
Kojto 107:4f6c30876dfa 234 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 235 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
Kojto 107:4f6c30876dfa 236 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
Kojto 107:4f6c30876dfa 237 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
Kojto 107:4f6c30876dfa 238 /**
Kojto 107:4f6c30876dfa 239 * @}
Kojto 107:4f6c30876dfa 240 */
Kojto 107:4f6c30876dfa 241
Kojto 107:4f6c30876dfa 242 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
Kojto 107:4f6c30876dfa 243 * @{
Kojto 107:4f6c30876dfa 244 */
Kojto 107:4f6c30876dfa 245 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 246 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
Kojto 107:4f6c30876dfa 247 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
Kojto 107:4f6c30876dfa 248 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
Kojto 107:4f6c30876dfa 249 /**
Kojto 107:4f6c30876dfa 250 * @}
Kojto 107:4f6c30876dfa 251 */
Kojto 107:4f6c30876dfa 252
Kojto 107:4f6c30876dfa 253 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
Kojto 107:4f6c30876dfa 254 * @{
Kojto 107:4f6c30876dfa 255 */
Kojto 107:4f6c30876dfa 256 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 257 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
Kojto 107:4f6c30876dfa 258 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
Kojto 107:4f6c30876dfa 259 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
Kojto 107:4f6c30876dfa 260 /**
Kojto 107:4f6c30876dfa 261 * @}
Kojto 107:4f6c30876dfa 262 */
Kojto 107:4f6c30876dfa 263
Kojto 107:4f6c30876dfa 264 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
Kojto 107:4f6c30876dfa 265 * @{
Kojto 107:4f6c30876dfa 266 */
Kojto 107:4f6c30876dfa 267 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 268 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
Kojto 107:4f6c30876dfa 269 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
Kojto 107:4f6c30876dfa 270 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
Kojto 107:4f6c30876dfa 271 /**
Kojto 107:4f6c30876dfa 272 * @}
Kojto 107:4f6c30876dfa 273 */
Kojto 107:4f6c30876dfa 274
Kojto 107:4f6c30876dfa 275 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
Kojto 107:4f6c30876dfa 276 * @{
Kojto 107:4f6c30876dfa 277 */
Kojto 107:4f6c30876dfa 278 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 279 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
Kojto 107:4f6c30876dfa 280 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
Kojto 107:4f6c30876dfa 281 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
Kojto 107:4f6c30876dfa 282 /**
Kojto 107:4f6c30876dfa 283 * @}
Kojto 107:4f6c30876dfa 284 */
Kojto 107:4f6c30876dfa 285
Kojto 107:4f6c30876dfa 286 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
Kojto 107:4f6c30876dfa 287 * @{
Kojto 107:4f6c30876dfa 288 */
Kojto 107:4f6c30876dfa 289 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 290 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
Kojto 107:4f6c30876dfa 291 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
Kojto 107:4f6c30876dfa 292 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
Kojto 107:4f6c30876dfa 293 /**
Kojto 107:4f6c30876dfa 294 * @}
Kojto 107:4f6c30876dfa 295 */
Kojto 107:4f6c30876dfa 296
Kojto 107:4f6c30876dfa 297 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
Kojto 107:4f6c30876dfa 298 * @{
Kojto 107:4f6c30876dfa 299 */
Kojto 107:4f6c30876dfa 300 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 301 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
Kojto 107:4f6c30876dfa 302 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Kojto 107:4f6c30876dfa 303 /**
Kojto 107:4f6c30876dfa 304 * @}
Kojto 107:4f6c30876dfa 305 */
Kojto 107:4f6c30876dfa 306
Kojto 107:4f6c30876dfa 307 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
Kojto 107:4f6c30876dfa 308 * @{
Kojto 107:4f6c30876dfa 309 */
Kojto 107:4f6c30876dfa 310 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 311 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
Kojto 107:4f6c30876dfa 312 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
Kojto 107:4f6c30876dfa 313 /**
Kojto 107:4f6c30876dfa 314 * @}
Kojto 107:4f6c30876dfa 315 */
Kojto 107:4f6c30876dfa 316
Kojto 107:4f6c30876dfa 317 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
Kojto 107:4f6c30876dfa 318 * @{
Kojto 107:4f6c30876dfa 319 */
Kojto 107:4f6c30876dfa 320 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 321 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Kojto 107:4f6c30876dfa 322 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Kojto 107:4f6c30876dfa 323 /**
Kojto 107:4f6c30876dfa 324 * @}
Kojto 107:4f6c30876dfa 325 */
Kojto 107:4f6c30876dfa 326
Kojto 107:4f6c30876dfa 327 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
Kojto 107:4f6c30876dfa 328 * @{
Kojto 107:4f6c30876dfa 329 */
Kojto 107:4f6c30876dfa 330 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 331 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
Kojto 107:4f6c30876dfa 332 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
Kojto 107:4f6c30876dfa 333 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
Kojto 107:4f6c30876dfa 334 /**
Kojto 107:4f6c30876dfa 335 * @}
Kojto 107:4f6c30876dfa 336 */
Kojto 107:4f6c30876dfa 337
Kojto 107:4f6c30876dfa 338 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
Kojto 107:4f6c30876dfa 339 * @{
Kojto 107:4f6c30876dfa 340 */
Kojto 107:4f6c30876dfa 341 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 342 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
Kojto 107:4f6c30876dfa 343 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
Kojto 107:4f6c30876dfa 344 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
Kojto 107:4f6c30876dfa 345 /**
Kojto 107:4f6c30876dfa 346 * @}
Kojto 107:4f6c30876dfa 347 */
Kojto 107:4f6c30876dfa 348
Kojto 107:4f6c30876dfa 349 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
Kojto 107:4f6c30876dfa 350 * @{
Kojto 107:4f6c30876dfa 351 */
Kojto 107:4f6c30876dfa 352 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 353 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
Kojto 107:4f6c30876dfa 354 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
Kojto 107:4f6c30876dfa 355 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
Kojto 107:4f6c30876dfa 356 /**
Kojto 107:4f6c30876dfa 357 * @}
Kojto 107:4f6c30876dfa 358 */
Kojto 107:4f6c30876dfa 359
Kojto 107:4f6c30876dfa 360 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
Kojto 107:4f6c30876dfa 361 * @{
Kojto 107:4f6c30876dfa 362 */
Kojto 107:4f6c30876dfa 363 #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 364 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
Kojto 107:4f6c30876dfa 365 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
Kojto 107:4f6c30876dfa 366 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
Kojto 107:4f6c30876dfa 367 /**
Kojto 107:4f6c30876dfa 368 * @}
Kojto 107:4f6c30876dfa 369 */
Kojto 107:4f6c30876dfa 370
Kojto 107:4f6c30876dfa 371 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
Kojto 107:4f6c30876dfa 372 * @{
Kojto 107:4f6c30876dfa 373 */
Kojto 107:4f6c30876dfa 374 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 375 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 107:4f6c30876dfa 376 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 107:4f6c30876dfa 377 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 107:4f6c30876dfa 378 /**
Kojto 107:4f6c30876dfa 379 * @}
Kojto 107:4f6c30876dfa 380 */
Kojto 107:4f6c30876dfa 381
Kojto 107:4f6c30876dfa 382 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
Kojto 107:4f6c30876dfa 383 * @{
Kojto 107:4f6c30876dfa 384 */
Kojto 107:4f6c30876dfa 385 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 386 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 107:4f6c30876dfa 387 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 107:4f6c30876dfa 388 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 107:4f6c30876dfa 389 /**
Kojto 107:4f6c30876dfa 390 * @}
Kojto 107:4f6c30876dfa 391 */
Kojto 107:4f6c30876dfa 392
Kojto 107:4f6c30876dfa 393 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 394 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
Kojto 107:4f6c30876dfa 395 * @{
Kojto 107:4f6c30876dfa 396 */
Kojto 107:4f6c30876dfa 397 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 398 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 107:4f6c30876dfa 399 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 107:4f6c30876dfa 400 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 107:4f6c30876dfa 401 /**
Kojto 107:4f6c30876dfa 402 * @}
Kojto 107:4f6c30876dfa 403 */
Kojto 107:4f6c30876dfa 404 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 405
Kojto 107:4f6c30876dfa 406 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
Kojto 107:4f6c30876dfa 407 * @{
Kojto 107:4f6c30876dfa 408 */
Kojto 107:4f6c30876dfa 409 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 410 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
Kojto 107:4f6c30876dfa 411 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
Kojto 107:4f6c30876dfa 412 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
Kojto 107:4f6c30876dfa 413 /**
Kojto 107:4f6c30876dfa 414 * @}
Kojto 107:4f6c30876dfa 415 */
Kojto 107:4f6c30876dfa 416
Kojto 107:4f6c30876dfa 417 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
Kojto 107:4f6c30876dfa 418 * @{
Kojto 107:4f6c30876dfa 419 */
Kojto 107:4f6c30876dfa 420 #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 421 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
Kojto 107:4f6c30876dfa 422 /**
Kojto 107:4f6c30876dfa 423 * @}
Kojto 107:4f6c30876dfa 424 */
Kojto 107:4f6c30876dfa 425
Kojto 107:4f6c30876dfa 426 /** @defgroup RCCEx_DFSDM_Clock_Source DFSDM Clock Source
Kojto 107:4f6c30876dfa 427 * @{
Kojto 107:4f6c30876dfa 428 */
Kojto 107:4f6c30876dfa 429 #define RCC_DFSDMCLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 430 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_CCIPR_DFSDMSEL
Kojto 107:4f6c30876dfa 431 /**
Kojto 107:4f6c30876dfa 432 * @}
Kojto 107:4f6c30876dfa 433 */
Kojto 107:4f6c30876dfa 434
Kojto 107:4f6c30876dfa 435 /**
Kojto 107:4f6c30876dfa 436 * @}
Kojto 107:4f6c30876dfa 437 */
Kojto 107:4f6c30876dfa 438
Kojto 107:4f6c30876dfa 439 /* Exported macros -----------------------------------------------------------*/
Kojto 107:4f6c30876dfa 440 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 107:4f6c30876dfa 441 * @{
Kojto 107:4f6c30876dfa 442 */
Kojto 107:4f6c30876dfa 443
Kojto 107:4f6c30876dfa 444 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto 107:4f6c30876dfa 445 * @brief Enable or disable the AHB2 peripheral clock.
Kojto 107:4f6c30876dfa 446 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 447 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 448 * using it.
Kojto 107:4f6c30876dfa 449 * @{
Kojto 107:4f6c30876dfa 450 */
Kojto 107:4f6c30876dfa 451
Kojto 107:4f6c30876dfa 452 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 453 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 454 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 455 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 107:4f6c30876dfa 456 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 457 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 107:4f6c30876dfa 458 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 459 } while(0)
Kojto 107:4f6c30876dfa 460
Kojto 107:4f6c30876dfa 461 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
Kojto 107:4f6c30876dfa 462 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 463
Kojto 107:4f6c30876dfa 464
Kojto 107:4f6c30876dfa 465 #if defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 466 #define __HAL_RCC_AES_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 467 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 468 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 107:4f6c30876dfa 469 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 470 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 107:4f6c30876dfa 471 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 472 } while(0)
Kojto 107:4f6c30876dfa 473
Kojto 107:4f6c30876dfa 474 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
Kojto 107:4f6c30876dfa 475 #endif /* STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 476
Kojto 107:4f6c30876dfa 477 /**
Kojto 107:4f6c30876dfa 478 * @}
Kojto 107:4f6c30876dfa 479 */
Kojto 107:4f6c30876dfa 480
Kojto 107:4f6c30876dfa 481 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 107:4f6c30876dfa 482 * @brief Enable or disable the APB1 peripheral clock.
Kojto 107:4f6c30876dfa 483 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 484 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 485 * using it.
Kojto 107:4f6c30876dfa 486 * @{
Kojto 107:4f6c30876dfa 487 */
Kojto 107:4f6c30876dfa 488 #if defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 489 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 490 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 491 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 107:4f6c30876dfa 492 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 493 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 107:4f6c30876dfa 494 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 495 } while(0)
Kojto 107:4f6c30876dfa 496
Kojto 107:4f6c30876dfa 497 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
Kojto 107:4f6c30876dfa 498 #endif /* STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 499
Kojto 107:4f6c30876dfa 500 /**
Kojto 107:4f6c30876dfa 501 * @}
Kojto 107:4f6c30876dfa 502 */
Kojto 107:4f6c30876dfa 503
Kojto 107:4f6c30876dfa 504 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto 107:4f6c30876dfa 505 * @brief Macros to get the status of the AHB2 peripheral clock.
Kojto 107:4f6c30876dfa 506 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 507 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 508 * using it.
Kojto 107:4f6c30876dfa 509 * @{
Kojto 107:4f6c30876dfa 510 */
Kojto 107:4f6c30876dfa 511
Kojto 107:4f6c30876dfa 512 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 513 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
Kojto 107:4f6c30876dfa 514
Kojto 107:4f6c30876dfa 515 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
Kojto 107:4f6c30876dfa 516 #endif /* STM32L475xx || STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 517
Kojto 107:4f6c30876dfa 518
Kojto 107:4f6c30876dfa 519 #if defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 520 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
Kojto 107:4f6c30876dfa 521
Kojto 107:4f6c30876dfa 522 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
Kojto 107:4f6c30876dfa 523 #endif /* STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 524
Kojto 107:4f6c30876dfa 525 /**
Kojto 107:4f6c30876dfa 526 * @}
Kojto 107:4f6c30876dfa 527 */
Kojto 107:4f6c30876dfa 528
Kojto 107:4f6c30876dfa 529 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 107:4f6c30876dfa 530 * @brief Macros to get the status of the APB1 peripheral clock.
Kojto 107:4f6c30876dfa 531 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 532 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 533 * using it.
Kojto 107:4f6c30876dfa 534 * @{
Kojto 107:4f6c30876dfa 535 */
Kojto 107:4f6c30876dfa 536 #if defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 537 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
Kojto 107:4f6c30876dfa 538
Kojto 107:4f6c30876dfa 539 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
Kojto 107:4f6c30876dfa 540 #endif /* STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 541
Kojto 107:4f6c30876dfa 542 /**
Kojto 107:4f6c30876dfa 543 * @}
Kojto 107:4f6c30876dfa 544 */
Kojto 107:4f6c30876dfa 545
Kojto 107:4f6c30876dfa 546 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
Kojto 107:4f6c30876dfa 547 * @brief Force or release AHB2 peripheral reset.
Kojto 107:4f6c30876dfa 548 * @{
Kojto 107:4f6c30876dfa 549 */
Kojto 107:4f6c30876dfa 550
Kojto 107:4f6c30876dfa 551 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 552 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 107:4f6c30876dfa 553
Kojto 107:4f6c30876dfa 554 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 107:4f6c30876dfa 555 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 556
Kojto 107:4f6c30876dfa 557 #if defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 558 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 107:4f6c30876dfa 559
Kojto 107:4f6c30876dfa 560 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 107:4f6c30876dfa 561 #endif /* STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 562
Kojto 107:4f6c30876dfa 563 /**
Kojto 107:4f6c30876dfa 564 * @}
Kojto 107:4f6c30876dfa 565 */
Kojto 107:4f6c30876dfa 566
Kojto 107:4f6c30876dfa 567
Kojto 107:4f6c30876dfa 568 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Kojto 107:4f6c30876dfa 569 * @brief Force or release APB1 peripheral reset.
Kojto 107:4f6c30876dfa 570 * @{
Kojto 107:4f6c30876dfa 571 */
Kojto 107:4f6c30876dfa 572 #if defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 573 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 107:4f6c30876dfa 574
Kojto 107:4f6c30876dfa 575 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 107:4f6c30876dfa 576 #endif /* STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 577
Kojto 107:4f6c30876dfa 578 /**
Kojto 107:4f6c30876dfa 579 * @}
Kojto 107:4f6c30876dfa 580 */
Kojto 107:4f6c30876dfa 581
Kojto 107:4f6c30876dfa 582
Kojto 107:4f6c30876dfa 583 /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
Kojto 107:4f6c30876dfa 584 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 585 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 586 * power consumption.
Kojto 107:4f6c30876dfa 587 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 588 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 589 * @{
Kojto 107:4f6c30876dfa 590 */
Kojto 107:4f6c30876dfa 591
Kojto 107:4f6c30876dfa 592 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 593 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 107:4f6c30876dfa 594
Kojto 107:4f6c30876dfa 595 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 107:4f6c30876dfa 596 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 597
Kojto 107:4f6c30876dfa 598 #if defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 599 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 107:4f6c30876dfa 600
Kojto 107:4f6c30876dfa 601 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 107:4f6c30876dfa 602 #endif /* STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 603
Kojto 107:4f6c30876dfa 604 /**
Kojto 107:4f6c30876dfa 605 * @}
Kojto 107:4f6c30876dfa 606 */
Kojto 107:4f6c30876dfa 607
Kojto 107:4f6c30876dfa 608
Kojto 107:4f6c30876dfa 609 /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Kojto 107:4f6c30876dfa 610 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 611 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 612 * power consumption.
Kojto 107:4f6c30876dfa 613 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 614 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 615 * @{
Kojto 107:4f6c30876dfa 616 */
Kojto 107:4f6c30876dfa 617
Kojto 107:4f6c30876dfa 618 #if defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 619 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 107:4f6c30876dfa 620
Kojto 107:4f6c30876dfa 621 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 107:4f6c30876dfa 622 #endif /* STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 623
Kojto 107:4f6c30876dfa 624 /**
Kojto 107:4f6c30876dfa 625 * @}
Kojto 107:4f6c30876dfa 626 */
Kojto 107:4f6c30876dfa 627
Kojto 107:4f6c30876dfa 628 /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enable Disable Status
Kojto 107:4f6c30876dfa 629 * @brief Macros to get the status of the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 630 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 631 * power consumption.
Kojto 107:4f6c30876dfa 632 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 633 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 634 * @{
Kojto 107:4f6c30876dfa 635 */
Kojto 107:4f6c30876dfa 636
Kojto 107:4f6c30876dfa 637 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 638 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
Kojto 107:4f6c30876dfa 639
Kojto 107:4f6c30876dfa 640 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
Kojto 107:4f6c30876dfa 641 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 642
Kojto 107:4f6c30876dfa 643 #if defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 644 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
Kojto 107:4f6c30876dfa 645
Kojto 107:4f6c30876dfa 646 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
Kojto 107:4f6c30876dfa 647 #endif /* STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 648
Kojto 107:4f6c30876dfa 649 /**
Kojto 107:4f6c30876dfa 650 * @}
Kojto 107:4f6c30876dfa 651 */
Kojto 107:4f6c30876dfa 652
Kojto 107:4f6c30876dfa 653
Kojto 107:4f6c30876dfa 654 /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
Kojto 107:4f6c30876dfa 655 * @brief Macros to get the status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 656 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 657 * power consumption.
Kojto 107:4f6c30876dfa 658 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 659 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 660 * @{
Kojto 107:4f6c30876dfa 661 */
Kojto 107:4f6c30876dfa 662
Kojto 107:4f6c30876dfa 663 #if defined(STM32L476xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 664 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
Kojto 107:4f6c30876dfa 665
Kojto 107:4f6c30876dfa 666 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
Kojto 107:4f6c30876dfa 667 #endif /* STM32L476xx || STM32L486xx */
Kojto 107:4f6c30876dfa 668
Kojto 107:4f6c30876dfa 669 /**
Kojto 107:4f6c30876dfa 670 * @}
Kojto 107:4f6c30876dfa 671 */
Kojto 107:4f6c30876dfa 672
Kojto 107:4f6c30876dfa 673 /**
Kojto 107:4f6c30876dfa 674 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
Kojto 107:4f6c30876dfa 675 *
Kojto 107:4f6c30876dfa 676 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 107:4f6c30876dfa 677 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 678 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 679 *
Kojto 107:4f6c30876dfa 680 * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 107:4f6c30876dfa 681 * This parameter must be a number between 8 and 86.
Kojto 107:4f6c30876dfa 682 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 683 * output frequency is between 64 and 344 MHz.
Kojto 107:4f6c30876dfa 684 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 107:4f6c30876dfa 685 *
Kojto 107:4f6c30876dfa 686 * @param __PLLSAI1P__: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 687 * This parameter must be a number in the range (7 or 17).
Kojto 107:4f6c30876dfa 688 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 107:4f6c30876dfa 689 *
Kojto 107:4f6c30876dfa 690 * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 107:4f6c30876dfa 691 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 107:4f6c30876dfa 692 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 107:4f6c30876dfa 693 *
Kojto 107:4f6c30876dfa 694 * @param __PLLSAI1R__: specifies the division factor for SAR ADC clock.
Kojto 107:4f6c30876dfa 695 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 107:4f6c30876dfa 696 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 107:4f6c30876dfa 697 *
Kojto 107:4f6c30876dfa 698 * @retval None
Kojto 107:4f6c30876dfa 699 */
Kojto 107:4f6c30876dfa 700 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
Kojto 107:4f6c30876dfa 701 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << 8U) | (((__PLLSAI1P__) >> 4U) << 17U) | \
Kojto 107:4f6c30876dfa 702 ((((__PLLSAI1Q__) >> 1U) - 1) << 21U) | ((((__PLLSAI1R__) >> 1U) - 1) << 25U))
Kojto 107:4f6c30876dfa 703
Kojto 107:4f6c30876dfa 704 /**
Kojto 107:4f6c30876dfa 705 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
Kojto 107:4f6c30876dfa 706 *
Kojto 107:4f6c30876dfa 707 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 107:4f6c30876dfa 708 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 709 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 710 *
Kojto 107:4f6c30876dfa 711 * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 107:4f6c30876dfa 712 * This parameter must be a number between 8 and 86.
Kojto 107:4f6c30876dfa 713 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 714 * output frequency is between 64 and 344 MHz.
Kojto 107:4f6c30876dfa 715 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 107:4f6c30876dfa 716 *
Kojto 107:4f6c30876dfa 717 * @retval None
Kojto 107:4f6c30876dfa 718 */
Kojto 107:4f6c30876dfa 719 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
Kojto 107:4f6c30876dfa 720 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << 8U)
Kojto 107:4f6c30876dfa 721
Kojto 107:4f6c30876dfa 722 /** @brief Macro to configure the PLLSAI1 clock division factor P.
Kojto 107:4f6c30876dfa 723 *
Kojto 107:4f6c30876dfa 724 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 107:4f6c30876dfa 725 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 726 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 727 *
Kojto 107:4f6c30876dfa 728 * @param __PLLSAI1P__: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 729 * This parameter must be a number in the range (7 or 17).
Kojto 107:4f6c30876dfa 730 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 107:4f6c30876dfa 731 *
Kojto 107:4f6c30876dfa 732 * @retval None
Kojto 107:4f6c30876dfa 733 */
Kojto 107:4f6c30876dfa 734 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
Kojto 107:4f6c30876dfa 735 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << 17U)
Kojto 107:4f6c30876dfa 736
Kojto 107:4f6c30876dfa 737 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
Kojto 107:4f6c30876dfa 738 *
Kojto 107:4f6c30876dfa 739 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 107:4f6c30876dfa 740 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 741 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 742 *
Kojto 107:4f6c30876dfa 743 * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 107:4f6c30876dfa 744 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 107:4f6c30876dfa 745 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 107:4f6c30876dfa 746 *
Kojto 107:4f6c30876dfa 747 * @retval None
Kojto 107:4f6c30876dfa 748 */
Kojto 107:4f6c30876dfa 749 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
Kojto 107:4f6c30876dfa 750 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1) << 21U)
Kojto 107:4f6c30876dfa 751
Kojto 107:4f6c30876dfa 752 /** @brief Macro to configure the PLLSAI1 clock division factor R.
Kojto 107:4f6c30876dfa 753 *
Kojto 107:4f6c30876dfa 754 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 107:4f6c30876dfa 755 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 756 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 757 *
Kojto 107:4f6c30876dfa 758 * @param __PLLSAI1R__: specifies the division factor for ADC clock.
Kojto 107:4f6c30876dfa 759 * This parameter must be in the range (2, 4, 6 or 8)
Kojto 107:4f6c30876dfa 760 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 107:4f6c30876dfa 761 *
Kojto 107:4f6c30876dfa 762 * @retval None
Kojto 107:4f6c30876dfa 763 */
Kojto 107:4f6c30876dfa 764 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
Kojto 107:4f6c30876dfa 765 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1) << 25U)
Kojto 107:4f6c30876dfa 766
Kojto 107:4f6c30876dfa 767 /**
Kojto 107:4f6c30876dfa 768 * @brief Macros to enable or disable the PLLSAI1.
Kojto 107:4f6c30876dfa 769 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 107:4f6c30876dfa 770 * @retval None
Kojto 107:4f6c30876dfa 771 */
Kojto 107:4f6c30876dfa 772
Kojto 107:4f6c30876dfa 773 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 107:4f6c30876dfa 774
Kojto 107:4f6c30876dfa 775 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 107:4f6c30876dfa 776
Kojto 107:4f6c30876dfa 777 /**
Kojto 107:4f6c30876dfa 778 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 107:4f6c30876dfa 779 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 107:4f6c30876dfa 780 * This is mainly used to save Power.
Kojto 107:4f6c30876dfa 781 * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output.
Kojto 107:4f6c30876dfa 782 * This parameter can be one or a combination of the following values:
Kojto 107:4f6c30876dfa 783 * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve
Kojto 107:4f6c30876dfa 784 * high-quality audio performance on SAI interface in case.
Kojto 107:4f6c30876dfa 785 * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 107:4f6c30876dfa 786 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 107:4f6c30876dfa 787 * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral.
Kojto 107:4f6c30876dfa 788 * @retval None
Kojto 107:4f6c30876dfa 789 */
Kojto 107:4f6c30876dfa 790
Kojto 107:4f6c30876dfa 791 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 107:4f6c30876dfa 792
Kojto 107:4f6c30876dfa 793 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 107:4f6c30876dfa 794
Kojto 107:4f6c30876dfa 795 /**
Kojto 107:4f6c30876dfa 796 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 107:4f6c30876dfa 797 * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output.
Kojto 107:4f6c30876dfa 798 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 799 * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve
Kojto 107:4f6c30876dfa 800 * high-quality audio performance on SAI interface in case.
Kojto 107:4f6c30876dfa 801 * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 107:4f6c30876dfa 802 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 107:4f6c30876dfa 803 * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral.
Kojto 107:4f6c30876dfa 804 * @retval SET / RESET
Kojto 107:4f6c30876dfa 805 */
Kojto 107:4f6c30876dfa 806 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 107:4f6c30876dfa 807
Kojto 107:4f6c30876dfa 808 /**
Kojto 107:4f6c30876dfa 809 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
Kojto 107:4f6c30876dfa 810 *
Kojto 107:4f6c30876dfa 811 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 107:4f6c30876dfa 812 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 813 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 814 *
Kojto 107:4f6c30876dfa 815 * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 107:4f6c30876dfa 816 * This parameter must be a number between 8 and 86.
Kojto 107:4f6c30876dfa 817 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 818 * output frequency is between 64 and 344 MHz.
Kojto 107:4f6c30876dfa 819 *
Kojto 107:4f6c30876dfa 820 * @param __PLLSAI2P__: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 821 * This parameter must be a number in the range (7 or 17).
Kojto 107:4f6c30876dfa 822 *
Kojto 107:4f6c30876dfa 823 *
Kojto 107:4f6c30876dfa 824 * @param __PLLSAI2R__: specifies the division factor for SAR ADC clock.
Kojto 107:4f6c30876dfa 825 * This parameter must be in the range (2, 4, 6 or 8)
Kojto 107:4f6c30876dfa 826 *
Kojto 107:4f6c30876dfa 827 * @retval None
Kojto 107:4f6c30876dfa 828 */
Kojto 107:4f6c30876dfa 829
Kojto 107:4f6c30876dfa 830 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
Kojto 107:4f6c30876dfa 831 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << 8U) | (((__PLLSAI2P__) >> 4U) << 17U) | \
Kojto 107:4f6c30876dfa 832 ((((__PLLSAI2R__) >> 1U) - 1) << 25U))
Kojto 107:4f6c30876dfa 833
Kojto 107:4f6c30876dfa 834 /**
Kojto 107:4f6c30876dfa 835 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
Kojto 107:4f6c30876dfa 836 *
Kojto 107:4f6c30876dfa 837 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 107:4f6c30876dfa 838 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 839 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 840 *
Kojto 107:4f6c30876dfa 841 * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 107:4f6c30876dfa 842 * This parameter must be a number between 8 and 86.
Kojto 107:4f6c30876dfa 843 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 844 * output frequency is between 64 and 344 MHz.
Kojto 107:4f6c30876dfa 845 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
Kojto 107:4f6c30876dfa 846 *
Kojto 107:4f6c30876dfa 847 * @retval None
Kojto 107:4f6c30876dfa 848 */
Kojto 107:4f6c30876dfa 849 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
Kojto 107:4f6c30876dfa 850 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << 8U)
Kojto 107:4f6c30876dfa 851
Kojto 107:4f6c30876dfa 852 /** @brief Macro to configure the PLLSAI2 clock division factor P.
Kojto 107:4f6c30876dfa 853 *
Kojto 107:4f6c30876dfa 854 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 107:4f6c30876dfa 855 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 856 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 857 *
Kojto 107:4f6c30876dfa 858 * @param __PLLSAI2P__: specifies the division factor.
Kojto 107:4f6c30876dfa 859 * This parameter must be a number in the range (7 or 17).
Kojto 107:4f6c30876dfa 860 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
Kojto 107:4f6c30876dfa 861 *
Kojto 107:4f6c30876dfa 862 * @retval None
Kojto 107:4f6c30876dfa 863 */
Kojto 107:4f6c30876dfa 864 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
Kojto 107:4f6c30876dfa 865 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << 17U)
Kojto 107:4f6c30876dfa 866
Kojto 107:4f6c30876dfa 867 /** @brief Macro to configure the PLLSAI2 clock division factor R.
Kojto 107:4f6c30876dfa 868 *
Kojto 107:4f6c30876dfa 869 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 107:4f6c30876dfa 870 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 107:4f6c30876dfa 871 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 107:4f6c30876dfa 872 *
Kojto 107:4f6c30876dfa 873 * @param __PLLSAI2R__: specifies the division factor.
Kojto 107:4f6c30876dfa 874 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 107:4f6c30876dfa 875 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2Q__
Kojto 107:4f6c30876dfa 876 *
Kojto 107:4f6c30876dfa 877 * @retval None
Kojto 107:4f6c30876dfa 878 */
Kojto 107:4f6c30876dfa 879 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
Kojto 107:4f6c30876dfa 880 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1) << 25U)
Kojto 107:4f6c30876dfa 881
Kojto 107:4f6c30876dfa 882 /**
Kojto 107:4f6c30876dfa 883 * @brief Macros to enable or disable the PLLSAI2.
Kojto 107:4f6c30876dfa 884 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 107:4f6c30876dfa 885 * @retval None
Kojto 107:4f6c30876dfa 886 */
Kojto 107:4f6c30876dfa 887
Kojto 107:4f6c30876dfa 888 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 107:4f6c30876dfa 889
Kojto 107:4f6c30876dfa 890 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 107:4f6c30876dfa 891
Kojto 107:4f6c30876dfa 892 /**
Kojto 107:4f6c30876dfa 893 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 107:4f6c30876dfa 894 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 107:4f6c30876dfa 895 * This is mainly used to save Power.
Kojto 107:4f6c30876dfa 896 * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output.
Kojto 107:4f6c30876dfa 897 * This parameter can be one or a combination of the following values:
Kojto 107:4f6c30876dfa 898 * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve
Kojto 107:4f6c30876dfa 899 * high-quality audio performance on SAI interface in case.
Kojto 107:4f6c30876dfa 900 * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral.
Kojto 107:4f6c30876dfa 901 * @retval None
Kojto 107:4f6c30876dfa 902 */
Kojto 107:4f6c30876dfa 903
Kojto 107:4f6c30876dfa 904 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 107:4f6c30876dfa 905
Kojto 107:4f6c30876dfa 906 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 107:4f6c30876dfa 907
Kojto 107:4f6c30876dfa 908 /**
Kojto 107:4f6c30876dfa 909 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 107:4f6c30876dfa 910 * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output.
Kojto 107:4f6c30876dfa 911 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 912 * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve
Kojto 107:4f6c30876dfa 913 * high-quality audio performance on SAI interface in case.
Kojto 107:4f6c30876dfa 914 * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral.
Kojto 107:4f6c30876dfa 915 * @retval SET / RESET
Kojto 107:4f6c30876dfa 916 */
Kojto 107:4f6c30876dfa 917 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 107:4f6c30876dfa 918
Kojto 107:4f6c30876dfa 919 /**
Kojto 107:4f6c30876dfa 920 * @brief Macro to configure the SAI1 clock source.
Kojto 107:4f6c30876dfa 921 * @param __SAI1_CLKSOURCE__: defines the SAI1 clock source. This clock is derived
Kojto 107:4f6c30876dfa 922 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
Kojto 107:4f6c30876dfa 923 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 924 * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 107:4f6c30876dfa 925 * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 107:4f6c30876dfa 926 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 107:4f6c30876dfa 927 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 107:4f6c30876dfa 928 * @retval None
Kojto 107:4f6c30876dfa 929 */
Kojto 107:4f6c30876dfa 930 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
Kojto 107:4f6c30876dfa 931 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 932
Kojto 107:4f6c30876dfa 933 /** @brief Macro to get the SAI1 clock source.
Kojto 107:4f6c30876dfa 934 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 935 * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 107:4f6c30876dfa 936 * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 107:4f6c30876dfa 937 * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 107:4f6c30876dfa 938 * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 107:4f6c30876dfa 939 */
Kojto 107:4f6c30876dfa 940 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
Kojto 107:4f6c30876dfa 941
Kojto 107:4f6c30876dfa 942 /**
Kojto 107:4f6c30876dfa 943 * @brief Macro to configure the SAI2 clock source.
Kojto 107:4f6c30876dfa 944 * @param __SAI2_CLKSOURCE__: defines the SAI2 clock source. This clock is derived
Kojto 107:4f6c30876dfa 945 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
Kojto 107:4f6c30876dfa 946 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 947 * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 107:4f6c30876dfa 948 * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 107:4f6c30876dfa 949 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 107:4f6c30876dfa 950 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 107:4f6c30876dfa 951 * @retval None
Kojto 107:4f6c30876dfa 952 */
Kojto 107:4f6c30876dfa 953 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
Kojto 107:4f6c30876dfa 954 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 955
Kojto 107:4f6c30876dfa 956 /** @brief Macro to get the SAI2 clock source.
Kojto 107:4f6c30876dfa 957 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 958 * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 107:4f6c30876dfa 959 * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 107:4f6c30876dfa 960 * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 107:4f6c30876dfa 961 * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 107:4f6c30876dfa 962 */
Kojto 107:4f6c30876dfa 963 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
Kojto 107:4f6c30876dfa 964
Kojto 107:4f6c30876dfa 965 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 107:4f6c30876dfa 966 *
Kojto 107:4f6c30876dfa 967 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
Kojto 107:4f6c30876dfa 968 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 969 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 107:4f6c30876dfa 970 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 107:4f6c30876dfa 971 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 107:4f6c30876dfa 972 * @retval None
Kojto 107:4f6c30876dfa 973 */
Kojto 107:4f6c30876dfa 974 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 975 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 976
Kojto 107:4f6c30876dfa 977 /** @brief Macro to get the I2C1 clock source.
Kojto 107:4f6c30876dfa 978 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 979 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 107:4f6c30876dfa 980 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 107:4f6c30876dfa 981 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 107:4f6c30876dfa 982 */
Kojto 107:4f6c30876dfa 983 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Kojto 107:4f6c30876dfa 984
Kojto 107:4f6c30876dfa 985 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 107:4f6c30876dfa 986 *
Kojto 107:4f6c30876dfa 987 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
Kojto 107:4f6c30876dfa 988 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 989 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 107:4f6c30876dfa 990 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 107:4f6c30876dfa 991 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 107:4f6c30876dfa 992 * @retval None
Kojto 107:4f6c30876dfa 993 */
Kojto 107:4f6c30876dfa 994 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 995 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 996
Kojto 107:4f6c30876dfa 997 /** @brief Macro to get the I2C2 clock source.
Kojto 107:4f6c30876dfa 998 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 999 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 107:4f6c30876dfa 1000 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 107:4f6c30876dfa 1001 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 107:4f6c30876dfa 1002 */
Kojto 107:4f6c30876dfa 1003 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Kojto 107:4f6c30876dfa 1004
Kojto 107:4f6c30876dfa 1005 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 107:4f6c30876dfa 1006 *
Kojto 107:4f6c30876dfa 1007 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
Kojto 107:4f6c30876dfa 1008 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1009 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 107:4f6c30876dfa 1010 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 107:4f6c30876dfa 1011 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 107:4f6c30876dfa 1012 * @retval None
Kojto 107:4f6c30876dfa 1013 */
Kojto 107:4f6c30876dfa 1014 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1015 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1016
Kojto 107:4f6c30876dfa 1017 /** @brief Macro to get the I2C3 clock source.
Kojto 107:4f6c30876dfa 1018 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1019 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 107:4f6c30876dfa 1020 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 107:4f6c30876dfa 1021 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 107:4f6c30876dfa 1022 */
Kojto 107:4f6c30876dfa 1023 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Kojto 107:4f6c30876dfa 1024
Kojto 107:4f6c30876dfa 1025 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 107:4f6c30876dfa 1026 *
Kojto 107:4f6c30876dfa 1027 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
Kojto 107:4f6c30876dfa 1028 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1029 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 107:4f6c30876dfa 1030 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 107:4f6c30876dfa 1031 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 107:4f6c30876dfa 1032 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 107:4f6c30876dfa 1033 * @retval None
Kojto 107:4f6c30876dfa 1034 */
Kojto 107:4f6c30876dfa 1035 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1036 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1037
Kojto 107:4f6c30876dfa 1038 /** @brief Macro to get the USART1 clock source.
Kojto 107:4f6c30876dfa 1039 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1040 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 107:4f6c30876dfa 1041 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 107:4f6c30876dfa 1042 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 107:4f6c30876dfa 1043 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 107:4f6c30876dfa 1044 */
Kojto 107:4f6c30876dfa 1045 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Kojto 107:4f6c30876dfa 1046
Kojto 107:4f6c30876dfa 1047 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 107:4f6c30876dfa 1048 *
Kojto 107:4f6c30876dfa 1049 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
Kojto 107:4f6c30876dfa 1050 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1051 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 107:4f6c30876dfa 1052 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 107:4f6c30876dfa 1053 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 107:4f6c30876dfa 1054 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 107:4f6c30876dfa 1055 * @retval None
Kojto 107:4f6c30876dfa 1056 */
Kojto 107:4f6c30876dfa 1057 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1058 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1059
Kojto 107:4f6c30876dfa 1060 /** @brief Macro to get the USART2 clock source.
Kojto 107:4f6c30876dfa 1061 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1062 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 107:4f6c30876dfa 1063 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 107:4f6c30876dfa 1064 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 107:4f6c30876dfa 1065 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 107:4f6c30876dfa 1066 */
Kojto 107:4f6c30876dfa 1067 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Kojto 107:4f6c30876dfa 1068
Kojto 107:4f6c30876dfa 1069 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 107:4f6c30876dfa 1070 *
Kojto 107:4f6c30876dfa 1071 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
Kojto 107:4f6c30876dfa 1072 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1073 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 107:4f6c30876dfa 1074 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 107:4f6c30876dfa 1075 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 107:4f6c30876dfa 1076 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 107:4f6c30876dfa 1077 * @retval None
Kojto 107:4f6c30876dfa 1078 */
Kojto 107:4f6c30876dfa 1079 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1080 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1081
Kojto 107:4f6c30876dfa 1082 /** @brief Macro to get the USART3 clock source.
Kojto 107:4f6c30876dfa 1083 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1084 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 107:4f6c30876dfa 1085 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 107:4f6c30876dfa 1086 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 107:4f6c30876dfa 1087 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 107:4f6c30876dfa 1088 */
Kojto 107:4f6c30876dfa 1089 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Kojto 107:4f6c30876dfa 1090
Kojto 107:4f6c30876dfa 1091 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 107:4f6c30876dfa 1092 *
Kojto 107:4f6c30876dfa 1093 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
Kojto 107:4f6c30876dfa 1094 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1095 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 107:4f6c30876dfa 1096 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 107:4f6c30876dfa 1097 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 107:4f6c30876dfa 1098 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 107:4f6c30876dfa 1099 * @retval None
Kojto 107:4f6c30876dfa 1100 */
Kojto 107:4f6c30876dfa 1101 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1102 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1103
Kojto 107:4f6c30876dfa 1104 /** @brief Macro to get the UART4 clock source.
Kojto 107:4f6c30876dfa 1105 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1106 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 107:4f6c30876dfa 1107 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 107:4f6c30876dfa 1108 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 107:4f6c30876dfa 1109 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 107:4f6c30876dfa 1110 */
Kojto 107:4f6c30876dfa 1111 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
Kojto 107:4f6c30876dfa 1112
Kojto 107:4f6c30876dfa 1113 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 107:4f6c30876dfa 1114 *
Kojto 107:4f6c30876dfa 1115 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
Kojto 107:4f6c30876dfa 1116 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1117 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 107:4f6c30876dfa 1118 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 107:4f6c30876dfa 1119 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 107:4f6c30876dfa 1120 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 107:4f6c30876dfa 1121 * @retval None
Kojto 107:4f6c30876dfa 1122 */
Kojto 107:4f6c30876dfa 1123 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1124 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1125
Kojto 107:4f6c30876dfa 1126 /** @brief Macro to get the UART5 clock source.
Kojto 107:4f6c30876dfa 1127 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1128 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 107:4f6c30876dfa 1129 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 107:4f6c30876dfa 1130 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 107:4f6c30876dfa 1131 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 107:4f6c30876dfa 1132 */
Kojto 107:4f6c30876dfa 1133 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
Kojto 107:4f6c30876dfa 1134
Kojto 107:4f6c30876dfa 1135 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
Kojto 107:4f6c30876dfa 1136 *
Kojto 107:4f6c30876dfa 1137 * @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source.
Kojto 107:4f6c30876dfa 1138 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1139 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1140 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1141 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1142 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1143 * @retval None
Kojto 107:4f6c30876dfa 1144 */
Kojto 107:4f6c30876dfa 1145 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1146 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1147
Kojto 107:4f6c30876dfa 1148 /** @brief Macro to get the LPUART1 clock source.
Kojto 107:4f6c30876dfa 1149 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1150 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1151 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1152 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1153 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1154 */
Kojto 107:4f6c30876dfa 1155 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Kojto 107:4f6c30876dfa 1156
Kojto 107:4f6c30876dfa 1157 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 107:4f6c30876dfa 1158 *
Kojto 107:4f6c30876dfa 1159 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
Kojto 107:4f6c30876dfa 1160 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1161 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 1162 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 1163 * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 1164 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 1165 * @retval None
Kojto 107:4f6c30876dfa 1166 */
Kojto 107:4f6c30876dfa 1167 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1168 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1169
Kojto 107:4f6c30876dfa 1170 /** @brief Macro to get the LPTIM1 clock source.
Kojto 107:4f6c30876dfa 1171 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1172 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1173 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1174 * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1175 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1176 */
Kojto 107:4f6c30876dfa 1177 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Kojto 107:4f6c30876dfa 1178
Kojto 107:4f6c30876dfa 1179 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
Kojto 107:4f6c30876dfa 1180 *
Kojto 107:4f6c30876dfa 1181 * @param __LPTIM2_CLKSOURCE__: specifies the LPTIM2 clock source.
Kojto 107:4f6c30876dfa 1182 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1183 * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPTIM2 clock
Kojto 107:4f6c30876dfa 1184 * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPTIM2 clock
Kojto 107:4f6c30876dfa 1185 * @arg RCC_LPTIM2CLKSOURCE_HSI : LSI selected as LPTIM2 clock
Kojto 107:4f6c30876dfa 1186 * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPTIM2 clock
Kojto 107:4f6c30876dfa 1187 * @retval None
Kojto 107:4f6c30876dfa 1188 */
Kojto 107:4f6c30876dfa 1189 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1190 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1191
Kojto 107:4f6c30876dfa 1192 /** @brief Macro to get the LPTIM2 clock source.
Kojto 107:4f6c30876dfa 1193 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1194 * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1195 * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1196 * @arg RCC_LPTIM2CLKSOURCE_HSI : System Clock selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1197 * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPUART1 clock
Kojto 107:4f6c30876dfa 1198 */
Kojto 107:4f6c30876dfa 1199 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Kojto 107:4f6c30876dfa 1200
Kojto 107:4f6c30876dfa 1201 /** @brief Macro to configure the SDMMC1 clock.
Kojto 107:4f6c30876dfa 1202 *
Kojto 107:4f6c30876dfa 1203 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 107:4f6c30876dfa 1204 *
Kojto 107:4f6c30876dfa 1205 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
Kojto 107:4f6c30876dfa 1206 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1207 * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1208 * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1209 * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1210 * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL Clock selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1211 * @retval None
Kojto 107:4f6c30876dfa 1212 */
Kojto 107:4f6c30876dfa 1213 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1214 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1215
Kojto 107:4f6c30876dfa 1216 /** @brief Macro to get the SDMMC1 clock.
Kojto 107:4f6c30876dfa 1217 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1218 * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1219 * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1220 * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1221 * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 1222 */
Kojto 107:4f6c30876dfa 1223 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 107:4f6c30876dfa 1224
Kojto 107:4f6c30876dfa 1225 /** @brief Macro to configure the RNG clock.
Kojto 107:4f6c30876dfa 1226 *
Kojto 107:4f6c30876dfa 1227 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 107:4f6c30876dfa 1228 *
Kojto 107:4f6c30876dfa 1229 * @param __RNG_CLKSOURCE__: specifies the RNG clock source.
Kojto 107:4f6c30876dfa 1230 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1231 * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock
Kojto 107:4f6c30876dfa 1232 * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock
Kojto 107:4f6c30876dfa 1233 * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as RNG clock
Kojto 107:4f6c30876dfa 1234 * @arg RCC_RNGCLKSOURCE_PLL: PLL Clock selected as RNG clock
Kojto 107:4f6c30876dfa 1235 * @retval None
Kojto 107:4f6c30876dfa 1236 */
Kojto 107:4f6c30876dfa 1237 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1238 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1239
Kojto 107:4f6c30876dfa 1240 /** @brief Macro to get the RNG clock.
Kojto 107:4f6c30876dfa 1241 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1242 * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock
Kojto 107:4f6c30876dfa 1243 * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock
Kojto 107:4f6c30876dfa 1244 * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
Kojto 107:4f6c30876dfa 1245 * @arg RCC_RNGCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as RNG clock
Kojto 107:4f6c30876dfa 1246 */
Kojto 107:4f6c30876dfa 1247 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 107:4f6c30876dfa 1248
Kojto 107:4f6c30876dfa 1249 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 1250 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 107:4f6c30876dfa 1251 *
Kojto 107:4f6c30876dfa 1252 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 107:4f6c30876dfa 1253 *
Kojto 107:4f6c30876dfa 1254 * @param __USB_CLKSOURCE__: specifies the USB clock source.
Kojto 107:4f6c30876dfa 1255 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1256 * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock
Kojto 107:4f6c30876dfa 1257 * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock
Kojto 107:4f6c30876dfa 1258 * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 107:4f6c30876dfa 1259 * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 107:4f6c30876dfa 1260 * @retval None
Kojto 107:4f6c30876dfa 1261 */
Kojto 107:4f6c30876dfa 1262 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1263 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1264
Kojto 107:4f6c30876dfa 1265 /** @brief Macro to get the USB clock source.
Kojto 107:4f6c30876dfa 1266 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1267 * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock
Kojto 107:4f6c30876dfa 1268 * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock
Kojto 107:4f6c30876dfa 1269 * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 107:4f6c30876dfa 1270 * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 107:4f6c30876dfa 1271 */
Kojto 107:4f6c30876dfa 1272 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 107:4f6c30876dfa 1273
Kojto 107:4f6c30876dfa 1274 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 1275
Kojto 107:4f6c30876dfa 1276 /** @brief Macro to configure the ADC interface clock.
Kojto 107:4f6c30876dfa 1277 * @param __ADC_CLKSOURCE__: specifies the ADC digital interface clock source.
Kojto 107:4f6c30876dfa 1278 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1279 * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1280 * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1281 * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1282 * @retval None
Kojto 107:4f6c30876dfa 1283 */
Kojto 107:4f6c30876dfa 1284 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1285 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1286
Kojto 107:4f6c30876dfa 1287 /** @brief Macro to get the ADC clock source.
Kojto 107:4f6c30876dfa 1288 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1289 * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1290 * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1291 * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock
Kojto 107:4f6c30876dfa 1292 */
Kojto 107:4f6c30876dfa 1293 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Kojto 107:4f6c30876dfa 1294
Kojto 107:4f6c30876dfa 1295 /** @brief Macro to configure the SWPMI1 clock.
Kojto 107:4f6c30876dfa 1296 * @param __SWPMI1_CLKSOURCE__: specifies the SWPMI1 clock source.
Kojto 107:4f6c30876dfa 1297 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1298 * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock
Kojto 107:4f6c30876dfa 1299 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Kojto 107:4f6c30876dfa 1300 * @retval None
Kojto 107:4f6c30876dfa 1301 */
Kojto 107:4f6c30876dfa 1302 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1303 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1304
Kojto 107:4f6c30876dfa 1305 /** @brief Macro to get the SWPMI1 clock source.
Kojto 107:4f6c30876dfa 1306 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1307 * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock
Kojto 107:4f6c30876dfa 1308 * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
Kojto 107:4f6c30876dfa 1309 */
Kojto 107:4f6c30876dfa 1310 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
Kojto 107:4f6c30876dfa 1311
Kojto 107:4f6c30876dfa 1312 /** @brief Macro to configure the DFSDM clock.
Kojto 107:4f6c30876dfa 1313 * @param __DFSDM_CLKSOURCE__: specifies the DFSDM clock source.
Kojto 107:4f6c30876dfa 1314 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 1315 * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock
Kojto 107:4f6c30876dfa 1316 * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock
Kojto 107:4f6c30876dfa 1317 * @retval None
Kojto 107:4f6c30876dfa 1318 */
Kojto 107:4f6c30876dfa 1319 #define __HAL_RCC_DFSDM_CONFIG(__DFSDM_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 1320 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, (uint32_t)(__DFSDM_CLKSOURCE__))
Kojto 107:4f6c30876dfa 1321
Kojto 107:4f6c30876dfa 1322 /** @brief Macro to get the DFSDM clock source.
Kojto 107:4f6c30876dfa 1323 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 1324 * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock
Kojto 107:4f6c30876dfa 1325 * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock
Kojto 107:4f6c30876dfa 1326 */
Kojto 107:4f6c30876dfa 1327 #define __HAL_RCC_GET_DFSDM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDMSEL)))
Kojto 107:4f6c30876dfa 1328
Kojto 107:4f6c30876dfa 1329
Kojto 107:4f6c30876dfa 1330 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
Kojto 107:4f6c30876dfa 1331 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 107:4f6c30876dfa 1332 * @{
Kojto 107:4f6c30876dfa 1333 */
Kojto 107:4f6c30876dfa 1334
Kojto 107:4f6c30876dfa 1335 /** @brief Enable PLLSAI1RDY interrupt.
Kojto 107:4f6c30876dfa 1336 * @retval None
Kojto 107:4f6c30876dfa 1337 */
Kojto 107:4f6c30876dfa 1338 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 107:4f6c30876dfa 1339
Kojto 107:4f6c30876dfa 1340 /** @brief Disable PLLSAI1RDY interrupt.
Kojto 107:4f6c30876dfa 1341 * @retval None
Kojto 107:4f6c30876dfa 1342 */
Kojto 107:4f6c30876dfa 1343 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 107:4f6c30876dfa 1344
Kojto 107:4f6c30876dfa 1345 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
Kojto 107:4f6c30876dfa 1346 * @retval None
Kojto 107:4f6c30876dfa 1347 */
Kojto 107:4f6c30876dfa 1348 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
Kojto 107:4f6c30876dfa 1349
Kojto 107:4f6c30876dfa 1350 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
Kojto 107:4f6c30876dfa 1351 * @retval TRUE or FALSE.
Kojto 107:4f6c30876dfa 1352 */
Kojto 107:4f6c30876dfa 1353 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
Kojto 107:4f6c30876dfa 1354
Kojto 107:4f6c30876dfa 1355 /** @brief Check whether the PLLSAI1RDY flag is set or not.
Kojto 107:4f6c30876dfa 1356 * @retval TRUE or FALSE.
Kojto 107:4f6c30876dfa 1357 */
Kojto 107:4f6c30876dfa 1358 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
Kojto 107:4f6c30876dfa 1359
Kojto 107:4f6c30876dfa 1360 /** @brief Enable PLLSAI2RDY interrupt.
Kojto 107:4f6c30876dfa 1361 * @retval None
Kojto 107:4f6c30876dfa 1362 */
Kojto 107:4f6c30876dfa 1363 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 107:4f6c30876dfa 1364
Kojto 107:4f6c30876dfa 1365 /** @brief Disable PLLSAI2RDY interrupt.
Kojto 107:4f6c30876dfa 1366 * @retval None
Kojto 107:4f6c30876dfa 1367 */
Kojto 107:4f6c30876dfa 1368 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 107:4f6c30876dfa 1369
Kojto 107:4f6c30876dfa 1370 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
Kojto 107:4f6c30876dfa 1371 * @retval None
Kojto 107:4f6c30876dfa 1372 */
Kojto 107:4f6c30876dfa 1373 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
Kojto 107:4f6c30876dfa 1374
Kojto 107:4f6c30876dfa 1375 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
Kojto 107:4f6c30876dfa 1376 * @retval TRUE or FALSE.
Kojto 107:4f6c30876dfa 1377 */
Kojto 107:4f6c30876dfa 1378 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
Kojto 107:4f6c30876dfa 1379
Kojto 107:4f6c30876dfa 1380 /** @brief Check whether the PLLSAI2RDY flag is set or not.
Kojto 107:4f6c30876dfa 1381 * @retval TRUE or FALSE.
Kojto 107:4f6c30876dfa 1382 */
Kojto 107:4f6c30876dfa 1383 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
Kojto 107:4f6c30876dfa 1384
Kojto 107:4f6c30876dfa 1385 /**
Kojto 107:4f6c30876dfa 1386 * @}
Kojto 107:4f6c30876dfa 1387 */
Kojto 107:4f6c30876dfa 1388
Kojto 107:4f6c30876dfa 1389 /**
Kojto 107:4f6c30876dfa 1390 * @}
Kojto 107:4f6c30876dfa 1391 */
Kojto 107:4f6c30876dfa 1392
Kojto 107:4f6c30876dfa 1393 /* Exported functions --------------------------------------------------------*/
Kojto 107:4f6c30876dfa 1394 /** @addtogroup RCCEx_Exported_Functions
Kojto 107:4f6c30876dfa 1395 * @{
Kojto 107:4f6c30876dfa 1396 */
Kojto 107:4f6c30876dfa 1397
Kojto 107:4f6c30876dfa 1398 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 107:4f6c30876dfa 1399 * @{
Kojto 107:4f6c30876dfa 1400 */
Kojto 107:4f6c30876dfa 1401
Kojto 107:4f6c30876dfa 1402 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 107:4f6c30876dfa 1403 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 107:4f6c30876dfa 1404 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 107:4f6c30876dfa 1405
Kojto 107:4f6c30876dfa 1406 /**
Kojto 107:4f6c30876dfa 1407 * @}
Kojto 107:4f6c30876dfa 1408 */
Kojto 107:4f6c30876dfa 1409
Kojto 107:4f6c30876dfa 1410 /** @addtogroup RCCEx_Exported_Functions_Group2
Kojto 107:4f6c30876dfa 1411 * @{
Kojto 107:4f6c30876dfa 1412 */
Kojto 107:4f6c30876dfa 1413
Kojto 107:4f6c30876dfa 1414 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
Kojto 107:4f6c30876dfa 1415 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
Kojto 107:4f6c30876dfa 1416 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
Kojto 107:4f6c30876dfa 1417 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
Kojto 107:4f6c30876dfa 1418 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
Kojto 107:4f6c30876dfa 1419 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
Kojto 107:4f6c30876dfa 1420 void HAL_RCCEx_EnableLSECSS(void);
Kojto 107:4f6c30876dfa 1421 void HAL_RCCEx_DisableLSECSS(void);
Kojto 107:4f6c30876dfa 1422 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
Kojto 107:4f6c30876dfa 1423 void HAL_RCCEx_DisableLSCO(void);
Kojto 107:4f6c30876dfa 1424 void HAL_RCCEx_EnableMSIPLLMode(void);
Kojto 107:4f6c30876dfa 1425 void HAL_RCCEx_DisableMSIPLLMode(void);
Kojto 107:4f6c30876dfa 1426
Kojto 107:4f6c30876dfa 1427 /**
Kojto 107:4f6c30876dfa 1428 * @}
Kojto 107:4f6c30876dfa 1429 */
Kojto 107:4f6c30876dfa 1430
Kojto 107:4f6c30876dfa 1431 /**
Kojto 107:4f6c30876dfa 1432 * @}
Kojto 107:4f6c30876dfa 1433 */
Kojto 107:4f6c30876dfa 1434
Kojto 107:4f6c30876dfa 1435 /* Private macros ------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 1436 /** @addtogroup RCCEx_Private_Macros
Kojto 107:4f6c30876dfa 1437 * @{
Kojto 107:4f6c30876dfa 1438 */
Kojto 107:4f6c30876dfa 1439
Kojto 107:4f6c30876dfa 1440 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
Kojto 107:4f6c30876dfa 1441 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
Kojto 107:4f6c30876dfa 1442
Kojto 107:4f6c30876dfa 1443 #if defined(STM32L471xx)
Kojto 107:4f6c30876dfa 1444
Kojto 107:4f6c30876dfa 1445 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 107:4f6c30876dfa 1446 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 107:4f6c30876dfa 1447 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 107:4f6c30876dfa 1448 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 107:4f6c30876dfa 1449 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 107:4f6c30876dfa 1450 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 107:4f6c30876dfa 1451 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 107:4f6c30876dfa 1452 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 107:4f6c30876dfa 1453 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 107:4f6c30876dfa 1454 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 107:4f6c30876dfa 1455 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 107:4f6c30876dfa 1456 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 107:4f6c30876dfa 1457 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 107:4f6c30876dfa 1458 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 107:4f6c30876dfa 1459 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 107:4f6c30876dfa 1460 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 107:4f6c30876dfa 1461 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \
Kojto 107:4f6c30876dfa 1462 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 107:4f6c30876dfa 1463 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 107:4f6c30876dfa 1464 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 107:4f6c30876dfa 1465
Kojto 107:4f6c30876dfa 1466 #else /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 1467
Kojto 107:4f6c30876dfa 1468 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 107:4f6c30876dfa 1469 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 107:4f6c30876dfa 1470 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 107:4f6c30876dfa 1471 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 107:4f6c30876dfa 1472 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 107:4f6c30876dfa 1473 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 107:4f6c30876dfa 1474 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 107:4f6c30876dfa 1475 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 107:4f6c30876dfa 1476 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 107:4f6c30876dfa 1477 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 107:4f6c30876dfa 1478 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 107:4f6c30876dfa 1479 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 107:4f6c30876dfa 1480 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 107:4f6c30876dfa 1481 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 107:4f6c30876dfa 1482 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 107:4f6c30876dfa 1483 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 107:4f6c30876dfa 1484 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 107:4f6c30876dfa 1485 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \
Kojto 107:4f6c30876dfa 1486 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 107:4f6c30876dfa 1487 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 107:4f6c30876dfa 1488 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 107:4f6c30876dfa 1489
Kojto 107:4f6c30876dfa 1490 #endif /* STM32L471xx */
Kojto 107:4f6c30876dfa 1491
Kojto 107:4f6c30876dfa 1492 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1493 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 107:4f6c30876dfa 1494 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1495 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1496 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1497
Kojto 107:4f6c30876dfa 1498 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1499 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1500 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1501 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1502 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1503
Kojto 107:4f6c30876dfa 1504 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1505 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1506 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1507 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1508 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1509
Kojto 107:4f6c30876dfa 1510 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1511 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1512 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1513 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1514 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1515
Kojto 107:4f6c30876dfa 1516 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1517 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1518 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1519 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1520 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1521
Kojto 107:4f6c30876dfa 1522 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1523 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1524 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 1525 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 1526 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1527
Kojto 107:4f6c30876dfa 1528 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1529 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1530 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 1531 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1532
Kojto 107:4f6c30876dfa 1533 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1534 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1535 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 1536 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1537
Kojto 107:4f6c30876dfa 1538 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1539 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 1540 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 1541 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1542
Kojto 107:4f6c30876dfa 1543 #define IS_RCC_SAI1CLK(__SOURCE__) \
Kojto 107:4f6c30876dfa 1544 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
Kojto 107:4f6c30876dfa 1545 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
Kojto 107:4f6c30876dfa 1546 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
Kojto 107:4f6c30876dfa 1547 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
Kojto 107:4f6c30876dfa 1548
Kojto 107:4f6c30876dfa 1549 #define IS_RCC_SAI2CLK(__SOURCE__) \
Kojto 107:4f6c30876dfa 1550 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
Kojto 107:4f6c30876dfa 1551 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
Kojto 107:4f6c30876dfa 1552 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
Kojto 107:4f6c30876dfa 1553 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
Kojto 107:4f6c30876dfa 1554
Kojto 107:4f6c30876dfa 1555 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
Kojto 107:4f6c30876dfa 1556 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
Kojto 107:4f6c30876dfa 1557 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 107:4f6c30876dfa 1558 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 107:4f6c30876dfa 1559 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 107:4f6c30876dfa 1560
Kojto 107:4f6c30876dfa 1561 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
Kojto 107:4f6c30876dfa 1562 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
Kojto 107:4f6c30876dfa 1563 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
Kojto 107:4f6c30876dfa 1564 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
Kojto 107:4f6c30876dfa 1565 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
Kojto 107:4f6c30876dfa 1566
Kojto 107:4f6c30876dfa 1567 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1568 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
Kojto 107:4f6c30876dfa 1569 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
Kojto 107:4f6c30876dfa 1570 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
Kojto 107:4f6c30876dfa 1571 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
Kojto 107:4f6c30876dfa 1572
Kojto 107:4f6c30876dfa 1573 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1574 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
Kojto 107:4f6c30876dfa 1575 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
Kojto 107:4f6c30876dfa 1576 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
Kojto 107:4f6c30876dfa 1577 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
Kojto 107:4f6c30876dfa 1578
Kojto 107:4f6c30876dfa 1579 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 107:4f6c30876dfa 1580 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1581 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
Kojto 107:4f6c30876dfa 1582 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
Kojto 107:4f6c30876dfa 1583 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
Kojto 107:4f6c30876dfa 1584 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
Kojto 107:4f6c30876dfa 1585 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 107:4f6c30876dfa 1586
Kojto 107:4f6c30876dfa 1587 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1588 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
Kojto 107:4f6c30876dfa 1589 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
Kojto 107:4f6c30876dfa 1590 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
Kojto 107:4f6c30876dfa 1591 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
Kojto 107:4f6c30876dfa 1592
Kojto 107:4f6c30876dfa 1593 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1594 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
Kojto 107:4f6c30876dfa 1595 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 1596
Kojto 107:4f6c30876dfa 1597 #define IS_RCC_DFSDMCLKSOURCE(__SOURCE__) \
Kojto 107:4f6c30876dfa 1598 (((__SOURCE__) == RCC_DFSDMCLKSOURCE_PCLK) || \
Kojto 107:4f6c30876dfa 1599 ((__SOURCE__) == RCC_DFSDMCLKSOURCE_SYSCLK))
Kojto 107:4f6c30876dfa 1600
Kojto 107:4f6c30876dfa 1601
Kojto 107:4f6c30876dfa 1602 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
Kojto 107:4f6c30876dfa 1603
Kojto 107:4f6c30876dfa 1604 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17))
Kojto 107:4f6c30876dfa 1605
Kojto 107:4f6c30876dfa 1606 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \
Kojto 107:4f6c30876dfa 1607 ((__VALUE__) == 6) || ((__VALUE__) == 8))
Kojto 107:4f6c30876dfa 1608
Kojto 107:4f6c30876dfa 1609 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \
Kojto 107:4f6c30876dfa 1610 ((__VALUE__) == 6) || ((__VALUE__) == 8))
Kojto 107:4f6c30876dfa 1611
Kojto 107:4f6c30876dfa 1612 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
Kojto 107:4f6c30876dfa 1613
Kojto 107:4f6c30876dfa 1614 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17))
Kojto 107:4f6c30876dfa 1615
Kojto 107:4f6c30876dfa 1616 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \
Kojto 107:4f6c30876dfa 1617 ((__VALUE__) == 6) || ((__VALUE__) == 8))
Kojto 107:4f6c30876dfa 1618
Kojto 107:4f6c30876dfa 1619 /**
Kojto 107:4f6c30876dfa 1620 * @}
Kojto 107:4f6c30876dfa 1621 */
Kojto 107:4f6c30876dfa 1622
Kojto 107:4f6c30876dfa 1623 /**
Kojto 107:4f6c30876dfa 1624 * @}
Kojto 107:4f6c30876dfa 1625 */
Kojto 107:4f6c30876dfa 1626
Kojto 107:4f6c30876dfa 1627 /**
Kojto 107:4f6c30876dfa 1628 * @}
Kojto 107:4f6c30876dfa 1629 */
Kojto 107:4f6c30876dfa 1630
Kojto 107:4f6c30876dfa 1631 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 1632 }
Kojto 107:4f6c30876dfa 1633 #endif
Kojto 107:4f6c30876dfa 1634
Kojto 107:4f6c30876dfa 1635 #endif /* __STM32L4xx_HAL_RCC_EX_H */
Kojto 107:4f6c30876dfa 1636
Kojto 107:4f6c30876dfa 1637 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/