mbed-F401 - mbed library with additional peripherals for ST F…

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Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

UART2 : PA_3 rx, PA_2 tx
UART3 : PC_7 rx, PC_6 tx
I2C2 : PB_3 SDA, PB_10 SCL
I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_rcc.c@70:c1fbde68b492, 2014-01-07 (annotated)

Committer:: mbed_official
Date:: Tue Jan 07 11:00:05 2014 +0000
Revision:: 70:c1fbde68b492
Parent:: 52:a51c77007319
Child:: 84:f54042cbc282

Synchronized with git revision 3f438a307904431f2782db3c8fa49946b9fc1d85



Full URL: https://github.com/mbedmicro/mbed/commit/3f438a307904431f2782db3c8fa49946b9fc1d85/



[NUCLEO_F103RB] license text changed + sleep hal updated

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	52:a51c77007319	1	/**
mbed_official	52:a51c77007319	2	******************************************************************************
mbed_official	52:a51c77007319	3	* @file stm32f10x_rcc.c
mbed_official	52:a51c77007319	4	* @author MCD Application Team
mbed_official	52:a51c77007319	5	* @version V3.5.0
mbed_official	52:a51c77007319	6	* @date 11-March-2011
mbed_official	52:a51c77007319	7	* @brief This file provides all the RCC firmware functions.
mbed_official	70:c1fbde68b492	8	*******************************************************************************
mbed_official	70:c1fbde68b492	9	* Copyright (c) 2014, STMicroelectronics
mbed_official	70:c1fbde68b492	10	* All rights reserved.
mbed_official	70:c1fbde68b492	11	*
mbed_official	70:c1fbde68b492	12	* Redistribution and use in source and binary forms, with or without
mbed_official	70:c1fbde68b492	13	* modification, are permitted provided that the following conditions are met:
mbed_official	70:c1fbde68b492	14	*
mbed_official	70:c1fbde68b492	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	70:c1fbde68b492	16	* this list of conditions and the following disclaimer.
mbed_official	70:c1fbde68b492	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	70:c1fbde68b492	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	70:c1fbde68b492	19	* and/or other materials provided with the distribution.
mbed_official	70:c1fbde68b492	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	70:c1fbde68b492	21	* may be used to endorse or promote products derived from this software
mbed_official	70:c1fbde68b492	22	* without specific prior written permission.
mbed_official	70:c1fbde68b492	23	*
mbed_official	70:c1fbde68b492	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	70:c1fbde68b492	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	70:c1fbde68b492	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	70:c1fbde68b492	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	70:c1fbde68b492	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	70:c1fbde68b492	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	70:c1fbde68b492	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	70:c1fbde68b492	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	70:c1fbde68b492	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	70:c1fbde68b492	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	70:c1fbde68b492	34	*******************************************************************************
mbed_official	70:c1fbde68b492	35	*/
mbed_official	52:a51c77007319	36
mbed_official	52:a51c77007319	37	/* Includes ------------------------------------------------------------------*/
mbed_official	52:a51c77007319	38	#include "stm32f10x_rcc.h"
mbed_official	52:a51c77007319	39
mbed_official	52:a51c77007319	40	/** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official	52:a51c77007319	41	* @{
mbed_official	52:a51c77007319	42	*/
mbed_official	52:a51c77007319	43
mbed_official	52:a51c77007319	44	/** @defgroup RCC
mbed_official	52:a51c77007319	45	* @brief RCC driver modules
mbed_official	52:a51c77007319	46	* @{
mbed_official	52:a51c77007319	47	*/
mbed_official	52:a51c77007319	48
mbed_official	52:a51c77007319	49	/** @defgroup RCC_Private_TypesDefinitions
mbed_official	52:a51c77007319	50	* @{
mbed_official	52:a51c77007319	51	*/
mbed_official	52:a51c77007319	52
mbed_official	52:a51c77007319	53	/**
mbed_official	52:a51c77007319	54	* @}
mbed_official	52:a51c77007319	55	*/
mbed_official	52:a51c77007319	56
mbed_official	52:a51c77007319	57	/** @defgroup RCC_Private_Defines
mbed_official	52:a51c77007319	58	* @{
mbed_official	52:a51c77007319	59	*/
mbed_official	52:a51c77007319	60
mbed_official	52:a51c77007319	61	/* ------------ RCC registers bit address in the alias region ----------- */
mbed_official	52:a51c77007319	62	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	52:a51c77007319	63
mbed_official	52:a51c77007319	64	/* --- CR Register ---*/
mbed_official	52:a51c77007319	65
mbed_official	52:a51c77007319	66	/* Alias word address of HSION bit */
mbed_official	52:a51c77007319	67	#define CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	52:a51c77007319	68	#define HSION_BitNumber 0x00
mbed_official	52:a51c77007319	69	#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official	52:a51c77007319	70
mbed_official	52:a51c77007319	71	/* Alias word address of PLLON bit */
mbed_official	52:a51c77007319	72	#define PLLON_BitNumber 0x18
mbed_official	52:a51c77007319	73	#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official	52:a51c77007319	74
mbed_official	52:a51c77007319	75	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	76	/* Alias word address of PLL2ON bit */
mbed_official	52:a51c77007319	77	#define PLL2ON_BitNumber 0x1A
mbed_official	52:a51c77007319	78	#define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
mbed_official	52:a51c77007319	79
mbed_official	52:a51c77007319	80	/* Alias word address of PLL3ON bit */
mbed_official	52:a51c77007319	81	#define PLL3ON_BitNumber 0x1C
mbed_official	52:a51c77007319	82	#define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
mbed_official	52:a51c77007319	83	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	84
mbed_official	52:a51c77007319	85	/* Alias word address of CSSON bit */
mbed_official	52:a51c77007319	86	#define CSSON_BitNumber 0x13
mbed_official	52:a51c77007319	87	#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official	52:a51c77007319	88
mbed_official	52:a51c77007319	89	/* --- CFGR Register ---*/
mbed_official	52:a51c77007319	90
mbed_official	52:a51c77007319	91	/* Alias word address of USBPRE bit */
mbed_official	52:a51c77007319	92	#define CFGR_OFFSET (RCC_OFFSET + 0x04)
mbed_official	52:a51c77007319	93
mbed_official	52:a51c77007319	94	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	95	#define USBPRE_BitNumber 0x16
mbed_official	52:a51c77007319	96	#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
mbed_official	52:a51c77007319	97	#else
mbed_official	52:a51c77007319	98	#define OTGFSPRE_BitNumber 0x16
mbed_official	52:a51c77007319	99	#define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
mbed_official	52:a51c77007319	100	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	101
mbed_official	52:a51c77007319	102	/* --- BDCR Register ---*/
mbed_official	52:a51c77007319	103
mbed_official	52:a51c77007319	104	/* Alias word address of RTCEN bit */
mbed_official	52:a51c77007319	105	#define BDCR_OFFSET (RCC_OFFSET + 0x20)
mbed_official	52:a51c77007319	106	#define RTCEN_BitNumber 0x0F
mbed_official	52:a51c77007319	107	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official	52:a51c77007319	108
mbed_official	52:a51c77007319	109	/* Alias word address of BDRST bit */
mbed_official	52:a51c77007319	110	#define BDRST_BitNumber 0x10
mbed_official	52:a51c77007319	111	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
mbed_official	52:a51c77007319	112
mbed_official	52:a51c77007319	113	/* --- CSR Register ---*/
mbed_official	52:a51c77007319	114
mbed_official	52:a51c77007319	115	/* Alias word address of LSION bit */
mbed_official	52:a51c77007319	116	#define CSR_OFFSET (RCC_OFFSET + 0x24)
mbed_official	52:a51c77007319	117	#define LSION_BitNumber 0x00
mbed_official	52:a51c77007319	118	#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official	52:a51c77007319	119
mbed_official	52:a51c77007319	120	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	121	/* --- CFGR2 Register ---*/
mbed_official	52:a51c77007319	122
mbed_official	52:a51c77007319	123	/* Alias word address of I2S2SRC bit */
mbed_official	52:a51c77007319	124	#define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
mbed_official	52:a51c77007319	125	#define I2S2SRC_BitNumber 0x11
mbed_official	52:a51c77007319	126	#define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
mbed_official	52:a51c77007319	127
mbed_official	52:a51c77007319	128	/* Alias word address of I2S3SRC bit */
mbed_official	52:a51c77007319	129	#define I2S3SRC_BitNumber 0x12
mbed_official	52:a51c77007319	130	#define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
mbed_official	52:a51c77007319	131	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	132
mbed_official	52:a51c77007319	133	/* ---------------------- RCC registers bit mask ------------------------ */
mbed_official	52:a51c77007319	134
mbed_official	52:a51c77007319	135	/* CR register bit mask */
mbed_official	52:a51c77007319	136	#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
mbed_official	52:a51c77007319	137	#define CR_HSEBYP_Set ((uint32_t)0x00040000)
mbed_official	52:a51c77007319	138	#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
mbed_official	52:a51c77007319	139	#define CR_HSEON_Set ((uint32_t)0x00010000)
mbed_official	52:a51c77007319	140	#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
mbed_official	52:a51c77007319	141
mbed_official	52:a51c77007319	142	/* CFGR register bit mask */
mbed_official	52:a51c77007319	143	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL) \|\| defined (STM32F10X_CL)
mbed_official	52:a51c77007319	144	#define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
mbed_official	52:a51c77007319	145	#else
mbed_official	52:a51c77007319	146	#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
mbed_official	52:a51c77007319	147	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	148
mbed_official	52:a51c77007319	149	#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
mbed_official	52:a51c77007319	150	#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
mbed_official	52:a51c77007319	151	#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
mbed_official	52:a51c77007319	152	#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
mbed_official	52:a51c77007319	153	#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
mbed_official	52:a51c77007319	154	#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
mbed_official	52:a51c77007319	155	#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
mbed_official	52:a51c77007319	156	#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
mbed_official	52:a51c77007319	157	#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
mbed_official	52:a51c77007319	158	#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
mbed_official	52:a51c77007319	159	#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
mbed_official	52:a51c77007319	160	#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
mbed_official	52:a51c77007319	161	#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
mbed_official	52:a51c77007319	162
mbed_official	52:a51c77007319	163	/* CSR register bit mask */
mbed_official	52:a51c77007319	164	#define CSR_RMVF_Set ((uint32_t)0x01000000)
mbed_official	52:a51c77007319	165
mbed_official	52:a51c77007319	166	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL) \|\| defined (STM32F10X_CL)
mbed_official	52:a51c77007319	167	/* CFGR2 register bit mask */
mbed_official	52:a51c77007319	168	#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
mbed_official	52:a51c77007319	169	#define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
mbed_official	52:a51c77007319	170	#endif
mbed_official	52:a51c77007319	171	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	172	#define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
mbed_official	52:a51c77007319	173	#define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
mbed_official	52:a51c77007319	174	#define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
mbed_official	52:a51c77007319	175	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	176
mbed_official	52:a51c77007319	177	/* RCC Flag Mask */
mbed_official	52:a51c77007319	178	#define FLAG_Mask ((uint8_t)0x1F)
mbed_official	52:a51c77007319	179
mbed_official	52:a51c77007319	180	/* CIR register byte 2 (Bits[15:8]) base address */
mbed_official	52:a51c77007319	181	#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
mbed_official	52:a51c77007319	182
mbed_official	52:a51c77007319	183	/* CIR register byte 3 (Bits[23:16]) base address */
mbed_official	52:a51c77007319	184	#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
mbed_official	52:a51c77007319	185
mbed_official	52:a51c77007319	186	/* CFGR register byte 4 (Bits[31:24]) base address */
mbed_official	52:a51c77007319	187	#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
mbed_official	52:a51c77007319	188
mbed_official	52:a51c77007319	189	/* BDCR register base address */
mbed_official	52:a51c77007319	190	#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
mbed_official	52:a51c77007319	191
mbed_official	52:a51c77007319	192	/**
mbed_official	52:a51c77007319	193	* @}
mbed_official	52:a51c77007319	194	*/
mbed_official	52:a51c77007319	195
mbed_official	52:a51c77007319	196	/** @defgroup RCC_Private_Macros
mbed_official	52:a51c77007319	197	* @{
mbed_official	52:a51c77007319	198	*/
mbed_official	52:a51c77007319	199
mbed_official	52:a51c77007319	200	/**
mbed_official	52:a51c77007319	201	* @}
mbed_official	52:a51c77007319	202	*/
mbed_official	52:a51c77007319	203
mbed_official	52:a51c77007319	204	/** @defgroup RCC_Private_Variables
mbed_official	52:a51c77007319	205	* @{
mbed_official	52:a51c77007319	206	*/
mbed_official	52:a51c77007319	207
mbed_official	52:a51c77007319	208	static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	52:a51c77007319	209	static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
mbed_official	52:a51c77007319	210
mbed_official	52:a51c77007319	211	/**
mbed_official	52:a51c77007319	212	* @}
mbed_official	52:a51c77007319	213	*/
mbed_official	52:a51c77007319	214
mbed_official	52:a51c77007319	215	/** @defgroup RCC_Private_FunctionPrototypes
mbed_official	52:a51c77007319	216	* @{
mbed_official	52:a51c77007319	217	*/
mbed_official	52:a51c77007319	218
mbed_official	52:a51c77007319	219	/**
mbed_official	52:a51c77007319	220	* @}
mbed_official	52:a51c77007319	221	*/
mbed_official	52:a51c77007319	222
mbed_official	52:a51c77007319	223	/** @defgroup RCC_Private_Functions
mbed_official	52:a51c77007319	224	* @{
mbed_official	52:a51c77007319	225	*/
mbed_official	52:a51c77007319	226
mbed_official	52:a51c77007319	227	/**
mbed_official	52:a51c77007319	228	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	52:a51c77007319	229	* @param None
mbed_official	52:a51c77007319	230	* @retval None
mbed_official	52:a51c77007319	231	*/
mbed_official	52:a51c77007319	232	void RCC_DeInit(void)
mbed_official	52:a51c77007319	233	{
mbed_official	52:a51c77007319	234	/* Set HSION bit */
mbed_official	52:a51c77007319	235	RCC->CR \|= (uint32_t)0x00000001;
mbed_official	52:a51c77007319	236
mbed_official	52:a51c77007319	237	/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
mbed_official	52:a51c77007319	238	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	239	RCC->CFGR &= (uint32_t)0xF8FF0000;
mbed_official	52:a51c77007319	240	#else
mbed_official	52:a51c77007319	241	RCC->CFGR &= (uint32_t)0xF0FF0000;
mbed_official	52:a51c77007319	242	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	243
mbed_official	52:a51c77007319	244	/* Reset HSEON, CSSON and PLLON bits */
mbed_official	52:a51c77007319	245	RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official	52:a51c77007319	246
mbed_official	52:a51c77007319	247	/* Reset HSEBYP bit */
mbed_official	52:a51c77007319	248	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	52:a51c77007319	249
mbed_official	52:a51c77007319	250	/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
mbed_official	52:a51c77007319	251	RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official	52:a51c77007319	252
mbed_official	52:a51c77007319	253	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	254	/* Reset PLL2ON and PLL3ON bits */
mbed_official	52:a51c77007319	255	RCC->CR &= (uint32_t)0xEBFFFFFF;
mbed_official	52:a51c77007319	256
mbed_official	52:a51c77007319	257	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	258	RCC->CIR = 0x00FF0000;
mbed_official	52:a51c77007319	259
mbed_official	52:a51c77007319	260	/* Reset CFGR2 register */
mbed_official	52:a51c77007319	261	RCC->CFGR2 = 0x00000000;
mbed_official	52:a51c77007319	262	#elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
mbed_official	52:a51c77007319	263	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	264	RCC->CIR = 0x009F0000;
mbed_official	52:a51c77007319	265
mbed_official	52:a51c77007319	266	/* Reset CFGR2 register */
mbed_official	52:a51c77007319	267	RCC->CFGR2 = 0x00000000;
mbed_official	52:a51c77007319	268	#else
mbed_official	52:a51c77007319	269	/* Disable all interrupts and clear pending bits */
mbed_official	52:a51c77007319	270	RCC->CIR = 0x009F0000;
mbed_official	52:a51c77007319	271	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	272
mbed_official	52:a51c77007319	273	}
mbed_official	52:a51c77007319	274
mbed_official	52:a51c77007319	275	/**
mbed_official	52:a51c77007319	276	* @brief Configures the External High Speed oscillator (HSE).
mbed_official	52:a51c77007319	277	* @note HSE can not be stopped if it is used directly or through the PLL as system clock.
mbed_official	52:a51c77007319	278	* @param RCC_HSE: specifies the new state of the HSE.
mbed_official	52:a51c77007319	279	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	280	* @arg RCC_HSE_OFF: HSE oscillator OFF
mbed_official	52:a51c77007319	281	* @arg RCC_HSE_ON: HSE oscillator ON
mbed_official	52:a51c77007319	282	* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official	52:a51c77007319	283	* @retval None
mbed_official	52:a51c77007319	284	*/
mbed_official	52:a51c77007319	285	void RCC_HSEConfig(uint32_t RCC_HSE)
mbed_official	52:a51c77007319	286	{
mbed_official	52:a51c77007319	287	/* Check the parameters */
mbed_official	52:a51c77007319	288	assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official	52:a51c77007319	289	/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official	52:a51c77007319	290	/* Reset HSEON bit */
mbed_official	52:a51c77007319	291	RCC->CR &= CR_HSEON_Reset;
mbed_official	52:a51c77007319	292	/* Reset HSEBYP bit */
mbed_official	52:a51c77007319	293	RCC->CR &= CR_HSEBYP_Reset;
mbed_official	52:a51c77007319	294	/* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
mbed_official	52:a51c77007319	295	switch(RCC_HSE)
mbed_official	52:a51c77007319	296	{
mbed_official	52:a51c77007319	297	case RCC_HSE_ON:
mbed_official	52:a51c77007319	298	/* Set HSEON bit */
mbed_official	52:a51c77007319	299	RCC->CR \|= CR_HSEON_Set;
mbed_official	52:a51c77007319	300	break;
mbed_official	52:a51c77007319	301
mbed_official	52:a51c77007319	302	case RCC_HSE_Bypass:
mbed_official	52:a51c77007319	303	/* Set HSEBYP and HSEON bits */
mbed_official	52:a51c77007319	304	RCC->CR \|= CR_HSEBYP_Set \| CR_HSEON_Set;
mbed_official	52:a51c77007319	305	break;
mbed_official	52:a51c77007319	306
mbed_official	52:a51c77007319	307	default:
mbed_official	52:a51c77007319	308	break;
mbed_official	52:a51c77007319	309	}
mbed_official	52:a51c77007319	310	}
mbed_official	52:a51c77007319	311
mbed_official	52:a51c77007319	312	/**
mbed_official	52:a51c77007319	313	* @brief Waits for HSE start-up.
mbed_official	52:a51c77007319	314	* @param None
mbed_official	52:a51c77007319	315	* @retval An ErrorStatus enumuration value:
mbed_official	52:a51c77007319	316	* - SUCCESS: HSE oscillator is stable and ready to use
mbed_official	52:a51c77007319	317	* - ERROR: HSE oscillator not yet ready
mbed_official	52:a51c77007319	318	*/
mbed_official	52:a51c77007319	319	ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official	52:a51c77007319	320	{
mbed_official	52:a51c77007319	321	__IO uint32_t StartUpCounter = 0;
mbed_official	52:a51c77007319	322	ErrorStatus status = ERROR;
mbed_official	52:a51c77007319	323	FlagStatus HSEStatus = RESET;
mbed_official	52:a51c77007319	324
mbed_official	52:a51c77007319	325	/* Wait till HSE is ready and if Time out is reached exit */
mbed_official	52:a51c77007319	326	do
mbed_official	52:a51c77007319	327	{
mbed_official	52:a51c77007319	328	HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official	52:a51c77007319	329	StartUpCounter++;
mbed_official	52:a51c77007319	330	} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official	52:a51c77007319	331
mbed_official	52:a51c77007319	332	if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official	52:a51c77007319	333	{
mbed_official	52:a51c77007319	334	status = SUCCESS;
mbed_official	52:a51c77007319	335	}
mbed_official	52:a51c77007319	336	else
mbed_official	52:a51c77007319	337	{
mbed_official	52:a51c77007319	338	status = ERROR;
mbed_official	52:a51c77007319	339	}
mbed_official	52:a51c77007319	340	return (status);
mbed_official	52:a51c77007319	341	}
mbed_official	52:a51c77007319	342
mbed_official	52:a51c77007319	343	/**
mbed_official	52:a51c77007319	344	* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official	52:a51c77007319	345	* @param HSICalibrationValue: specifies the calibration trimming value.
mbed_official	52:a51c77007319	346	* This parameter must be a number between 0 and 0x1F.
mbed_official	52:a51c77007319	347	* @retval None
mbed_official	52:a51c77007319	348	*/
mbed_official	52:a51c77007319	349	void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official	52:a51c77007319	350	{
mbed_official	52:a51c77007319	351	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	352	/* Check the parameters */
mbed_official	52:a51c77007319	353	assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official	52:a51c77007319	354	tmpreg = RCC->CR;
mbed_official	52:a51c77007319	355	/* Clear HSITRIM[4:0] bits */
mbed_official	52:a51c77007319	356	tmpreg &= CR_HSITRIM_Mask;
mbed_official	52:a51c77007319	357	/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official	52:a51c77007319	358	tmpreg \|= (uint32_t)HSICalibrationValue << 3;
mbed_official	52:a51c77007319	359	/* Store the new value */
mbed_official	52:a51c77007319	360	RCC->CR = tmpreg;
mbed_official	52:a51c77007319	361	}
mbed_official	52:a51c77007319	362
mbed_official	52:a51c77007319	363	/**
mbed_official	52:a51c77007319	364	* @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official	52:a51c77007319	365	* @note HSI can not be stopped if it is used directly or through the PLL as system clock.
mbed_official	52:a51c77007319	366	* @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	367	* @retval None
mbed_official	52:a51c77007319	368	*/
mbed_official	52:a51c77007319	369	void RCC_HSICmd(FunctionalState NewState)
mbed_official	52:a51c77007319	370	{
mbed_official	52:a51c77007319	371	/* Check the parameters */
mbed_official	52:a51c77007319	372	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	373	(__IO uint32_t ) CR_HSION_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	374	}
mbed_official	52:a51c77007319	375
mbed_official	52:a51c77007319	376	/**
mbed_official	52:a51c77007319	377	* @brief Configures the PLL clock source and multiplication factor.
mbed_official	52:a51c77007319	378	* @note This function must be used only when the PLL is disabled.
mbed_official	52:a51c77007319	379	* @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official	52:a51c77007319	380	* For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
mbed_official	52:a51c77007319	381	* this parameter can be one of the following values:
mbed_official	52:a51c77007319	382	* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
mbed_official	52:a51c77007319	383	* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
mbed_official	52:a51c77007319	384	* For @b other_STM32_devices, this parameter can be one of the following values:
mbed_official	52:a51c77007319	385	* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
mbed_official	52:a51c77007319	386	* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
mbed_official	52:a51c77007319	387	* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
mbed_official	52:a51c77007319	388	* @param RCC_PLLMul: specifies the PLL multiplication factor.
mbed_official	52:a51c77007319	389	* For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
mbed_official	52:a51c77007319	390	* For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
mbed_official	52:a51c77007319	391	* @retval None
mbed_official	52:a51c77007319	392	*/
mbed_official	52:a51c77007319	393	void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
mbed_official	52:a51c77007319	394	{
mbed_official	52:a51c77007319	395	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	396
mbed_official	52:a51c77007319	397	/* Check the parameters */
mbed_official	52:a51c77007319	398	assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official	52:a51c77007319	399	assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official	52:a51c77007319	400
mbed_official	52:a51c77007319	401	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	402	/* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official	52:a51c77007319	403	tmpreg &= CFGR_PLL_Mask;
mbed_official	52:a51c77007319	404	/* Set the PLL configuration bits */
mbed_official	52:a51c77007319	405	tmpreg \|= RCC_PLLSource \| RCC_PLLMul;
mbed_official	52:a51c77007319	406	/* Store the new value */
mbed_official	52:a51c77007319	407	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	408	}
mbed_official	52:a51c77007319	409
mbed_official	52:a51c77007319	410	/**
mbed_official	52:a51c77007319	411	* @brief Enables or disables the PLL.
mbed_official	52:a51c77007319	412	* @note The PLL can not be disabled if it is used as system clock.
mbed_official	52:a51c77007319	413	* @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	414	* @retval None
mbed_official	52:a51c77007319	415	*/
mbed_official	52:a51c77007319	416	void RCC_PLLCmd(FunctionalState NewState)
mbed_official	52:a51c77007319	417	{
mbed_official	52:a51c77007319	418	/* Check the parameters */
mbed_official	52:a51c77007319	419	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	420
mbed_official	52:a51c77007319	421	(__IO uint32_t ) CR_PLLON_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	422	}
mbed_official	52:a51c77007319	423
mbed_official	52:a51c77007319	424	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL) \|\| defined (STM32F10X_CL)
mbed_official	52:a51c77007319	425	/**
mbed_official	52:a51c77007319	426	* @brief Configures the PREDIV1 division factor.
mbed_official	52:a51c77007319	427	* @note
mbed_official	52:a51c77007319	428	* - This function must be used only when the PLL is disabled.
mbed_official	52:a51c77007319	429	* - This function applies only to STM32 Connectivity line and Value line
mbed_official	52:a51c77007319	430	* devices.
mbed_official	52:a51c77007319	431	* @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
mbed_official	52:a51c77007319	432	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	433	* @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
mbed_official	52:a51c77007319	434	* @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
mbed_official	52:a51c77007319	435	* @note
mbed_official	52:a51c77007319	436	* For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
mbed_official	52:a51c77007319	437	* @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
mbed_official	52:a51c77007319	438	* This parameter can be RCC_PREDIV1_Divx where x:[1,16]
mbed_official	52:a51c77007319	439	* @retval None
mbed_official	52:a51c77007319	440	*/
mbed_official	52:a51c77007319	441	void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
mbed_official	52:a51c77007319	442	{
mbed_official	52:a51c77007319	443	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	444
mbed_official	52:a51c77007319	445	/* Check the parameters */
mbed_official	52:a51c77007319	446	assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
mbed_official	52:a51c77007319	447	assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
mbed_official	52:a51c77007319	448
mbed_official	52:a51c77007319	449	tmpreg = RCC->CFGR2;
mbed_official	52:a51c77007319	450	/* Clear PREDIV1[3:0] and PREDIV1SRC bits */
mbed_official	52:a51c77007319	451	tmpreg &= ~(CFGR2_PREDIV1 \| CFGR2_PREDIV1SRC);
mbed_official	52:a51c77007319	452	/* Set the PREDIV1 clock source and division factor */
mbed_official	52:a51c77007319	453	tmpreg \|= RCC_PREDIV1_Source \| RCC_PREDIV1_Div ;
mbed_official	52:a51c77007319	454	/* Store the new value */
mbed_official	52:a51c77007319	455	RCC->CFGR2 = tmpreg;
mbed_official	52:a51c77007319	456	}
mbed_official	52:a51c77007319	457	#endif
mbed_official	52:a51c77007319	458
mbed_official	52:a51c77007319	459	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	460	/**
mbed_official	52:a51c77007319	461	* @brief Configures the PREDIV2 division factor.
mbed_official	52:a51c77007319	462	* @note
mbed_official	52:a51c77007319	463	* - This function must be used only when both PLL2 and PLL3 are disabled.
mbed_official	52:a51c77007319	464	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	465	* @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
mbed_official	52:a51c77007319	466	* This parameter can be RCC_PREDIV2_Divx where x:[1,16]
mbed_official	52:a51c77007319	467	* @retval None
mbed_official	52:a51c77007319	468	*/
mbed_official	52:a51c77007319	469	void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
mbed_official	52:a51c77007319	470	{
mbed_official	52:a51c77007319	471	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	472
mbed_official	52:a51c77007319	473	/* Check the parameters */
mbed_official	52:a51c77007319	474	assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
mbed_official	52:a51c77007319	475
mbed_official	52:a51c77007319	476	tmpreg = RCC->CFGR2;
mbed_official	52:a51c77007319	477	/* Clear PREDIV2[3:0] bits */
mbed_official	52:a51c77007319	478	tmpreg &= ~CFGR2_PREDIV2;
mbed_official	52:a51c77007319	479	/* Set the PREDIV2 division factor */
mbed_official	52:a51c77007319	480	tmpreg \|= RCC_PREDIV2_Div;
mbed_official	52:a51c77007319	481	/* Store the new value */
mbed_official	52:a51c77007319	482	RCC->CFGR2 = tmpreg;
mbed_official	52:a51c77007319	483	}
mbed_official	52:a51c77007319	484
mbed_official	52:a51c77007319	485	/**
mbed_official	52:a51c77007319	486	* @brief Configures the PLL2 multiplication factor.
mbed_official	52:a51c77007319	487	* @note
mbed_official	52:a51c77007319	488	* - This function must be used only when the PLL2 is disabled.
mbed_official	52:a51c77007319	489	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	490	* @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
mbed_official	52:a51c77007319	491	* This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
mbed_official	52:a51c77007319	492	* @retval None
mbed_official	52:a51c77007319	493	*/
mbed_official	52:a51c77007319	494	void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
mbed_official	52:a51c77007319	495	{
mbed_official	52:a51c77007319	496	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	497
mbed_official	52:a51c77007319	498	/* Check the parameters */
mbed_official	52:a51c77007319	499	assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
mbed_official	52:a51c77007319	500
mbed_official	52:a51c77007319	501	tmpreg = RCC->CFGR2;
mbed_official	52:a51c77007319	502	/* Clear PLL2Mul[3:0] bits */
mbed_official	52:a51c77007319	503	tmpreg &= ~CFGR2_PLL2MUL;
mbed_official	52:a51c77007319	504	/* Set the PLL2 configuration bits */
mbed_official	52:a51c77007319	505	tmpreg \|= RCC_PLL2Mul;
mbed_official	52:a51c77007319	506	/* Store the new value */
mbed_official	52:a51c77007319	507	RCC->CFGR2 = tmpreg;
mbed_official	52:a51c77007319	508	}
mbed_official	52:a51c77007319	509
mbed_official	52:a51c77007319	510
mbed_official	52:a51c77007319	511	/**
mbed_official	52:a51c77007319	512	* @brief Enables or disables the PLL2.
mbed_official	52:a51c77007319	513	* @note
mbed_official	52:a51c77007319	514	* - The PLL2 can not be disabled if it is used indirectly as system clock
mbed_official	52:a51c77007319	515	* (i.e. it is used as PLL clock entry that is used as System clock).
mbed_official	52:a51c77007319	516	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	517	* @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	518	* @retval None
mbed_official	52:a51c77007319	519	*/
mbed_official	52:a51c77007319	520	void RCC_PLL2Cmd(FunctionalState NewState)
mbed_official	52:a51c77007319	521	{
mbed_official	52:a51c77007319	522	/* Check the parameters */
mbed_official	52:a51c77007319	523	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	524
mbed_official	52:a51c77007319	525	(__IO uint32_t ) CR_PLL2ON_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	526	}
mbed_official	52:a51c77007319	527
mbed_official	52:a51c77007319	528
mbed_official	52:a51c77007319	529	/**
mbed_official	52:a51c77007319	530	* @brief Configures the PLL3 multiplication factor.
mbed_official	52:a51c77007319	531	* @note
mbed_official	52:a51c77007319	532	* - This function must be used only when the PLL3 is disabled.
mbed_official	52:a51c77007319	533	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	534	* @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
mbed_official	52:a51c77007319	535	* This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
mbed_official	52:a51c77007319	536	* @retval None
mbed_official	52:a51c77007319	537	*/
mbed_official	52:a51c77007319	538	void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
mbed_official	52:a51c77007319	539	{
mbed_official	52:a51c77007319	540	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	541
mbed_official	52:a51c77007319	542	/* Check the parameters */
mbed_official	52:a51c77007319	543	assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
mbed_official	52:a51c77007319	544
mbed_official	52:a51c77007319	545	tmpreg = RCC->CFGR2;
mbed_official	52:a51c77007319	546	/* Clear PLL3Mul[3:0] bits */
mbed_official	52:a51c77007319	547	tmpreg &= ~CFGR2_PLL3MUL;
mbed_official	52:a51c77007319	548	/* Set the PLL3 configuration bits */
mbed_official	52:a51c77007319	549	tmpreg \|= RCC_PLL3Mul;
mbed_official	52:a51c77007319	550	/* Store the new value */
mbed_official	52:a51c77007319	551	RCC->CFGR2 = tmpreg;
mbed_official	52:a51c77007319	552	}
mbed_official	52:a51c77007319	553
mbed_official	52:a51c77007319	554
mbed_official	52:a51c77007319	555	/**
mbed_official	52:a51c77007319	556	* @brief Enables or disables the PLL3.
mbed_official	52:a51c77007319	557	* @note This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	558	* @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	559	* @retval None
mbed_official	52:a51c77007319	560	*/
mbed_official	52:a51c77007319	561	void RCC_PLL3Cmd(FunctionalState NewState)
mbed_official	52:a51c77007319	562	{
mbed_official	52:a51c77007319	563	/* Check the parameters */
mbed_official	52:a51c77007319	564
mbed_official	52:a51c77007319	565	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	566	(__IO uint32_t ) CR_PLL3ON_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	567	}
mbed_official	52:a51c77007319	568	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	569
mbed_official	52:a51c77007319	570	/**
mbed_official	52:a51c77007319	571	* @brief Configures the system clock (SYSCLK).
mbed_official	52:a51c77007319	572	* @param RCC_SYSCLKSource: specifies the clock source used as system clock.
mbed_official	52:a51c77007319	573	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	574	* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
mbed_official	52:a51c77007319	575	* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
mbed_official	52:a51c77007319	576	* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
mbed_official	52:a51c77007319	577	* @retval None
mbed_official	52:a51c77007319	578	*/
mbed_official	52:a51c77007319	579	void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official	52:a51c77007319	580	{
mbed_official	52:a51c77007319	581	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	582	/* Check the parameters */
mbed_official	52:a51c77007319	583	assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official	52:a51c77007319	584	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	585	/* Clear SW[1:0] bits */
mbed_official	52:a51c77007319	586	tmpreg &= CFGR_SW_Mask;
mbed_official	52:a51c77007319	587	/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official	52:a51c77007319	588	tmpreg \|= RCC_SYSCLKSource;
mbed_official	52:a51c77007319	589	/* Store the new value */
mbed_official	52:a51c77007319	590	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	591	}
mbed_official	52:a51c77007319	592
mbed_official	52:a51c77007319	593	/**
mbed_official	52:a51c77007319	594	* @brief Returns the clock source used as system clock.
mbed_official	52:a51c77007319	595	* @param None
mbed_official	52:a51c77007319	596	* @retval The clock source used as system clock. The returned value can
mbed_official	52:a51c77007319	597	* be one of the following:
mbed_official	52:a51c77007319	598	* - 0x00: HSI used as system clock
mbed_official	52:a51c77007319	599	* - 0x04: HSE used as system clock
mbed_official	52:a51c77007319	600	* - 0x08: PLL used as system clock
mbed_official	52:a51c77007319	601	*/
mbed_official	52:a51c77007319	602	uint8_t RCC_GetSYSCLKSource(void)
mbed_official	52:a51c77007319	603	{
mbed_official	52:a51c77007319	604	return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
mbed_official	52:a51c77007319	605	}
mbed_official	52:a51c77007319	606
mbed_official	52:a51c77007319	607	/**
mbed_official	52:a51c77007319	608	* @brief Configures the AHB clock (HCLK).
mbed_official	52:a51c77007319	609	* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official	52:a51c77007319	610	* the system clock (SYSCLK).
mbed_official	52:a51c77007319	611	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	612	* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official	52:a51c77007319	613	* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official	52:a51c77007319	614	* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official	52:a51c77007319	615	* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official	52:a51c77007319	616	* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official	52:a51c77007319	617	* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official	52:a51c77007319	618	* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official	52:a51c77007319	619	* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official	52:a51c77007319	620	* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official	52:a51c77007319	621	* @retval None
mbed_official	52:a51c77007319	622	*/
mbed_official	52:a51c77007319	623	void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official	52:a51c77007319	624	{
mbed_official	52:a51c77007319	625	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	626	/* Check the parameters */
mbed_official	52:a51c77007319	627	assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official	52:a51c77007319	628	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	629	/* Clear HPRE[3:0] bits */
mbed_official	52:a51c77007319	630	tmpreg &= CFGR_HPRE_Reset_Mask;
mbed_official	52:a51c77007319	631	/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official	52:a51c77007319	632	tmpreg \|= RCC_SYSCLK;
mbed_official	52:a51c77007319	633	/* Store the new value */
mbed_official	52:a51c77007319	634	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	635	}
mbed_official	52:a51c77007319	636
mbed_official	52:a51c77007319	637	/**
mbed_official	52:a51c77007319	638	* @brief Configures the Low Speed APB clock (PCLK1).
mbed_official	52:a51c77007319	639	* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
mbed_official	52:a51c77007319	640	* the AHB clock (HCLK).
mbed_official	52:a51c77007319	641	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	642	* @arg RCC_HCLK_Div1: APB1 clock = HCLK
mbed_official	52:a51c77007319	643	* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
mbed_official	52:a51c77007319	644	* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
mbed_official	52:a51c77007319	645	* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
mbed_official	52:a51c77007319	646	* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
mbed_official	52:a51c77007319	647	* @retval None
mbed_official	52:a51c77007319	648	*/
mbed_official	52:a51c77007319	649	void RCC_PCLK1Config(uint32_t RCC_HCLK)
mbed_official	52:a51c77007319	650	{
mbed_official	52:a51c77007319	651	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	652	/* Check the parameters */
mbed_official	52:a51c77007319	653	assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official	52:a51c77007319	654	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	655	/* Clear PPRE1[2:0] bits */
mbed_official	52:a51c77007319	656	tmpreg &= CFGR_PPRE1_Reset_Mask;
mbed_official	52:a51c77007319	657	/* Set PPRE1[2:0] bits according to RCC_HCLK value */
mbed_official	52:a51c77007319	658	tmpreg \|= RCC_HCLK;
mbed_official	52:a51c77007319	659	/* Store the new value */
mbed_official	52:a51c77007319	660	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	661	}
mbed_official	52:a51c77007319	662
mbed_official	52:a51c77007319	663	/**
mbed_official	52:a51c77007319	664	* @brief Configures the High Speed APB clock (PCLK2).
mbed_official	52:a51c77007319	665	* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
mbed_official	52:a51c77007319	666	* the AHB clock (HCLK).
mbed_official	52:a51c77007319	667	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	668	* @arg RCC_HCLK_Div1: APB2 clock = HCLK
mbed_official	52:a51c77007319	669	* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
mbed_official	52:a51c77007319	670	* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
mbed_official	52:a51c77007319	671	* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
mbed_official	52:a51c77007319	672	* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
mbed_official	52:a51c77007319	673	* @retval None
mbed_official	52:a51c77007319	674	*/
mbed_official	52:a51c77007319	675	void RCC_PCLK2Config(uint32_t RCC_HCLK)
mbed_official	52:a51c77007319	676	{
mbed_official	52:a51c77007319	677	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	678	/* Check the parameters */
mbed_official	52:a51c77007319	679	assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official	52:a51c77007319	680	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	681	/* Clear PPRE2[2:0] bits */
mbed_official	52:a51c77007319	682	tmpreg &= CFGR_PPRE2_Reset_Mask;
mbed_official	52:a51c77007319	683	/* Set PPRE2[2:0] bits according to RCC_HCLK value */
mbed_official	52:a51c77007319	684	tmpreg \|= RCC_HCLK << 3;
mbed_official	52:a51c77007319	685	/* Store the new value */
mbed_official	52:a51c77007319	686	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	687	}
mbed_official	52:a51c77007319	688
mbed_official	52:a51c77007319	689	/**
mbed_official	52:a51c77007319	690	* @brief Enables or disables the specified RCC interrupts.
mbed_official	52:a51c77007319	691	* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official	52:a51c77007319	692	*
mbed_official	52:a51c77007319	693	* For @b STM32_Connectivity_line_devices, this parameter can be any combination
mbed_official	52:a51c77007319	694	* of the following values
mbed_official	52:a51c77007319	695	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	696	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	697	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	698	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	699	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	700	* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
mbed_official	52:a51c77007319	701	* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
mbed_official	52:a51c77007319	702	*
mbed_official	52:a51c77007319	703	* For @b other_STM32_devices, this parameter can be any combination of the
mbed_official	52:a51c77007319	704	* following values
mbed_official	52:a51c77007319	705	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	706	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	707	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	708	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	709	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	710	*
mbed_official	52:a51c77007319	711	* @param NewState: new state of the specified RCC interrupts.
mbed_official	52:a51c77007319	712	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	713	* @retval None
mbed_official	52:a51c77007319	714	*/
mbed_official	52:a51c77007319	715	void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official	52:a51c77007319	716	{
mbed_official	52:a51c77007319	717	/* Check the parameters */
mbed_official	52:a51c77007319	718	assert_param(IS_RCC_IT(RCC_IT));
mbed_official	52:a51c77007319	719	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	720	if (NewState != DISABLE)
mbed_official	52:a51c77007319	721	{
mbed_official	52:a51c77007319	722	/* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
mbed_official	52:a51c77007319	723	(__IO uint8_t ) CIR_BYTE2_ADDRESS \|= RCC_IT;
mbed_official	52:a51c77007319	724	}
mbed_official	52:a51c77007319	725	else
mbed_official	52:a51c77007319	726	{
mbed_official	52:a51c77007319	727	/* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
mbed_official	52:a51c77007319	728	(__IO uint8_t ) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official	52:a51c77007319	729	}
mbed_official	52:a51c77007319	730	}
mbed_official	52:a51c77007319	731
mbed_official	52:a51c77007319	732	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	733	/**
mbed_official	52:a51c77007319	734	* @brief Configures the USB clock (USBCLK).
mbed_official	52:a51c77007319	735	* @param RCC_USBCLKSource: specifies the USB clock source. This clock is
mbed_official	52:a51c77007319	736	* derived from the PLL output.
mbed_official	52:a51c77007319	737	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	738	* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
mbed_official	52:a51c77007319	739	* clock source
mbed_official	52:a51c77007319	740	* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
mbed_official	52:a51c77007319	741	* @retval None
mbed_official	52:a51c77007319	742	*/
mbed_official	52:a51c77007319	743	void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
mbed_official	52:a51c77007319	744	{
mbed_official	52:a51c77007319	745	/* Check the parameters */
mbed_official	52:a51c77007319	746	assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
mbed_official	52:a51c77007319	747
mbed_official	52:a51c77007319	748	(__IO uint32_t ) CFGR_USBPRE_BB = RCC_USBCLKSource;
mbed_official	52:a51c77007319	749	}
mbed_official	52:a51c77007319	750	#else
mbed_official	52:a51c77007319	751	/**
mbed_official	52:a51c77007319	752	* @brief Configures the USB OTG FS clock (OTGFSCLK).
mbed_official	52:a51c77007319	753	* This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	754	* @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
mbed_official	52:a51c77007319	755	* This clock is derived from the PLL output.
mbed_official	52:a51c77007319	756	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	757	* @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
mbed_official	52:a51c77007319	758	* @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
mbed_official	52:a51c77007319	759	* @retval None
mbed_official	52:a51c77007319	760	*/
mbed_official	52:a51c77007319	761	void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
mbed_official	52:a51c77007319	762	{
mbed_official	52:a51c77007319	763	/* Check the parameters */
mbed_official	52:a51c77007319	764	assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
mbed_official	52:a51c77007319	765
mbed_official	52:a51c77007319	766	(__IO uint32_t ) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
mbed_official	52:a51c77007319	767	}
mbed_official	52:a51c77007319	768	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	769
mbed_official	52:a51c77007319	770	/**
mbed_official	52:a51c77007319	771	* @brief Configures the ADC clock (ADCCLK).
mbed_official	52:a51c77007319	772	* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
mbed_official	52:a51c77007319	773	* the APB2 clock (PCLK2).
mbed_official	52:a51c77007319	774	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	775	* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
mbed_official	52:a51c77007319	776	* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
mbed_official	52:a51c77007319	777	* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
mbed_official	52:a51c77007319	778	* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
mbed_official	52:a51c77007319	779	* @retval None
mbed_official	52:a51c77007319	780	*/
mbed_official	52:a51c77007319	781	void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
mbed_official	52:a51c77007319	782	{
mbed_official	52:a51c77007319	783	uint32_t tmpreg = 0;
mbed_official	52:a51c77007319	784	/* Check the parameters */
mbed_official	52:a51c77007319	785	assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
mbed_official	52:a51c77007319	786	tmpreg = RCC->CFGR;
mbed_official	52:a51c77007319	787	/* Clear ADCPRE[1:0] bits */
mbed_official	52:a51c77007319	788	tmpreg &= CFGR_ADCPRE_Reset_Mask;
mbed_official	52:a51c77007319	789	/* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
mbed_official	52:a51c77007319	790	tmpreg \|= RCC_PCLK2;
mbed_official	52:a51c77007319	791	/* Store the new value */
mbed_official	52:a51c77007319	792	RCC->CFGR = tmpreg;
mbed_official	52:a51c77007319	793	}
mbed_official	52:a51c77007319	794
mbed_official	52:a51c77007319	795	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	796	/**
mbed_official	52:a51c77007319	797	* @brief Configures the I2S2 clock source(I2S2CLK).
mbed_official	52:a51c77007319	798	* @note
mbed_official	52:a51c77007319	799	* - This function must be called before enabling I2S2 APB clock.
mbed_official	52:a51c77007319	800	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	801	* @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
mbed_official	52:a51c77007319	802	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	803	* @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
mbed_official	52:a51c77007319	804	* @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
mbed_official	52:a51c77007319	805	* @retval None
mbed_official	52:a51c77007319	806	*/
mbed_official	52:a51c77007319	807	void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
mbed_official	52:a51c77007319	808	{
mbed_official	52:a51c77007319	809	/* Check the parameters */
mbed_official	52:a51c77007319	810	assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
mbed_official	52:a51c77007319	811
mbed_official	52:a51c77007319	812	(__IO uint32_t ) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
mbed_official	52:a51c77007319	813	}
mbed_official	52:a51c77007319	814
mbed_official	52:a51c77007319	815	/**
mbed_official	52:a51c77007319	816	* @brief Configures the I2S3 clock source(I2S2CLK).
mbed_official	52:a51c77007319	817	* @note
mbed_official	52:a51c77007319	818	* - This function must be called before enabling I2S3 APB clock.
mbed_official	52:a51c77007319	819	* - This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	820	* @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
mbed_official	52:a51c77007319	821	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	822	* @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
mbed_official	52:a51c77007319	823	* @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
mbed_official	52:a51c77007319	824	* @retval None
mbed_official	52:a51c77007319	825	*/
mbed_official	52:a51c77007319	826	void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
mbed_official	52:a51c77007319	827	{
mbed_official	52:a51c77007319	828	/* Check the parameters */
mbed_official	52:a51c77007319	829	assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
mbed_official	52:a51c77007319	830
mbed_official	52:a51c77007319	831	(__IO uint32_t ) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
mbed_official	52:a51c77007319	832	}
mbed_official	52:a51c77007319	833	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	834
mbed_official	52:a51c77007319	835	/**
mbed_official	52:a51c77007319	836	* @brief Configures the External Low Speed oscillator (LSE).
mbed_official	52:a51c77007319	837	* @param RCC_LSE: specifies the new state of the LSE.
mbed_official	52:a51c77007319	838	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	839	* @arg RCC_LSE_OFF: LSE oscillator OFF
mbed_official	52:a51c77007319	840	* @arg RCC_LSE_ON: LSE oscillator ON
mbed_official	52:a51c77007319	841	* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official	52:a51c77007319	842	* @retval None
mbed_official	52:a51c77007319	843	*/
mbed_official	52:a51c77007319	844	void RCC_LSEConfig(uint8_t RCC_LSE)
mbed_official	52:a51c77007319	845	{
mbed_official	52:a51c77007319	846	/* Check the parameters */
mbed_official	52:a51c77007319	847	assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official	52:a51c77007319	848	/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official	52:a51c77007319	849	/* Reset LSEON bit */
mbed_official	52:a51c77007319	850	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_OFF;
mbed_official	52:a51c77007319	851	/* Reset LSEBYP bit */
mbed_official	52:a51c77007319	852	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_OFF;
mbed_official	52:a51c77007319	853	/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
mbed_official	52:a51c77007319	854	switch(RCC_LSE)
mbed_official	52:a51c77007319	855	{
mbed_official	52:a51c77007319	856	case RCC_LSE_ON:
mbed_official	52:a51c77007319	857	/* Set LSEON bit */
mbed_official	52:a51c77007319	858	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_ON;
mbed_official	52:a51c77007319	859	break;
mbed_official	52:a51c77007319	860
mbed_official	52:a51c77007319	861	case RCC_LSE_Bypass:
mbed_official	52:a51c77007319	862	/* Set LSEBYP and LSEON bits */
mbed_official	52:a51c77007319	863	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_Bypass \| RCC_LSE_ON;
mbed_official	52:a51c77007319	864	break;
mbed_official	52:a51c77007319	865
mbed_official	52:a51c77007319	866	default:
mbed_official	52:a51c77007319	867	break;
mbed_official	52:a51c77007319	868	}
mbed_official	52:a51c77007319	869	}
mbed_official	52:a51c77007319	870
mbed_official	52:a51c77007319	871	/**
mbed_official	52:a51c77007319	872	* @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official	52:a51c77007319	873	* @note LSI can not be disabled if the IWDG is running.
mbed_official	52:a51c77007319	874	* @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	875	* @retval None
mbed_official	52:a51c77007319	876	*/
mbed_official	52:a51c77007319	877	void RCC_LSICmd(FunctionalState NewState)
mbed_official	52:a51c77007319	878	{
mbed_official	52:a51c77007319	879	/* Check the parameters */
mbed_official	52:a51c77007319	880	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	881	(__IO uint32_t ) CSR_LSION_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	882	}
mbed_official	52:a51c77007319	883
mbed_official	52:a51c77007319	884	/**
mbed_official	52:a51c77007319	885	* @brief Configures the RTC clock (RTCCLK).
mbed_official	52:a51c77007319	886	* @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
mbed_official	52:a51c77007319	887	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	52:a51c77007319	888	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	889	* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official	52:a51c77007319	890	* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official	52:a51c77007319	891	* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
mbed_official	52:a51c77007319	892	* @retval None
mbed_official	52:a51c77007319	893	*/
mbed_official	52:a51c77007319	894	void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official	52:a51c77007319	895	{
mbed_official	52:a51c77007319	896	/* Check the parameters */
mbed_official	52:a51c77007319	897	assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official	52:a51c77007319	898	/* Select the RTC clock source */
mbed_official	52:a51c77007319	899	RCC->BDCR \|= RCC_RTCCLKSource;
mbed_official	52:a51c77007319	900	}
mbed_official	52:a51c77007319	901
mbed_official	52:a51c77007319	902	/**
mbed_official	52:a51c77007319	903	* @brief Enables or disables the RTC clock.
mbed_official	52:a51c77007319	904	* @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
mbed_official	52:a51c77007319	905	* @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	906	* @retval None
mbed_official	52:a51c77007319	907	*/
mbed_official	52:a51c77007319	908	void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official	52:a51c77007319	909	{
mbed_official	52:a51c77007319	910	/* Check the parameters */
mbed_official	52:a51c77007319	911	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	912	(__IO uint32_t ) BDCR_RTCEN_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	913	}
mbed_official	52:a51c77007319	914
mbed_official	52:a51c77007319	915	/**
mbed_official	52:a51c77007319	916	* @brief Returns the frequencies of different on chip clocks.
mbed_official	52:a51c77007319	917	* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official	52:a51c77007319	918	* the clocks frequencies.
mbed_official	52:a51c77007319	919	* @note The result of this function could be not correct when using
mbed_official	52:a51c77007319	920	* fractional value for HSE crystal.
mbed_official	52:a51c77007319	921	* @retval None
mbed_official	52:a51c77007319	922	*/
mbed_official	52:a51c77007319	923	void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official	52:a51c77007319	924	{
mbed_official	52:a51c77007319	925	uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
mbed_official	52:a51c77007319	926
mbed_official	52:a51c77007319	927	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	928	uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
mbed_official	52:a51c77007319	929	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	930
mbed_official	52:a51c77007319	931	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
mbed_official	52:a51c77007319	932	uint32_t prediv1factor = 0;
mbed_official	52:a51c77007319	933	#endif
mbed_official	52:a51c77007319	934
mbed_official	52:a51c77007319	935	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	52:a51c77007319	936	tmp = RCC->CFGR & CFGR_SWS_Mask;
mbed_official	52:a51c77007319	937
mbed_official	52:a51c77007319	938	switch (tmp)
mbed_official	52:a51c77007319	939	{
mbed_official	52:a51c77007319	940	case 0x00: /* HSI used as system clock */
mbed_official	52:a51c77007319	941	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official	52:a51c77007319	942	break;
mbed_official	52:a51c77007319	943	case 0x04: /* HSE used as system clock */
mbed_official	52:a51c77007319	944	RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official	52:a51c77007319	945	break;
mbed_official	52:a51c77007319	946	case 0x08: /* PLL used as system clock */
mbed_official	52:a51c77007319	947
mbed_official	52:a51c77007319	948	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	52:a51c77007319	949	pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
mbed_official	52:a51c77007319	950	pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
mbed_official	52:a51c77007319	951
mbed_official	52:a51c77007319	952	#ifndef STM32F10X_CL
mbed_official	52:a51c77007319	953	pllmull = ( pllmull >> 18) + 2;
mbed_official	52:a51c77007319	954
mbed_official	52:a51c77007319	955	if (pllsource == 0x00)
mbed_official	52:a51c77007319	956	{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official	52:a51c77007319	957	RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	958	}
mbed_official	52:a51c77007319	959	else
mbed_official	52:a51c77007319	960	{
mbed_official	52:a51c77007319	961	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
mbed_official	52:a51c77007319	962	prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
mbed_official	52:a51c77007319	963	/* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	964	RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	965	#else
mbed_official	52:a51c77007319	966	/* HSE selected as PLL clock entry */
mbed_official	52:a51c77007319	967	if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
mbed_official	52:a51c77007319	968	{/* HSE oscillator clock divided by 2 */
mbed_official	52:a51c77007319	969	RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	970	}
mbed_official	52:a51c77007319	971	else
mbed_official	52:a51c77007319	972	{
mbed_official	52:a51c77007319	973	RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
mbed_official	52:a51c77007319	974	}
mbed_official	52:a51c77007319	975	#endif
mbed_official	52:a51c77007319	976	}
mbed_official	52:a51c77007319	977	#else
mbed_official	52:a51c77007319	978	pllmull = pllmull >> 18;
mbed_official	52:a51c77007319	979
mbed_official	52:a51c77007319	980	if (pllmull != 0x0D)
mbed_official	52:a51c77007319	981	{
mbed_official	52:a51c77007319	982	pllmull += 2;
mbed_official	52:a51c77007319	983	}
mbed_official	52:a51c77007319	984	else
mbed_official	52:a51c77007319	985	{ /* PLL multiplication factor = PLL input clock * 6.5 */
mbed_official	52:a51c77007319	986	pllmull = 13 / 2;
mbed_official	52:a51c77007319	987	}
mbed_official	52:a51c77007319	988
mbed_official	52:a51c77007319	989	if (pllsource == 0x00)
mbed_official	52:a51c77007319	990	{/* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official	52:a51c77007319	991	RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
mbed_official	52:a51c77007319	992	}
mbed_official	52:a51c77007319	993	else
mbed_official	52:a51c77007319	994	{/* PREDIV1 selected as PLL clock entry */
mbed_official	52:a51c77007319	995
mbed_official	52:a51c77007319	996	/* Get PREDIV1 clock source and division factor */
mbed_official	52:a51c77007319	997	prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
mbed_official	52:a51c77007319	998	prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
mbed_official	52:a51c77007319	999
mbed_official	52:a51c77007319	1000	if (prediv1source == 0)
mbed_official	52:a51c77007319	1001	{ /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	1002	RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	1003	}
mbed_official	52:a51c77007319	1004	else
mbed_official	52:a51c77007319	1005	{/* PLL2 clock selected as PREDIV1 clock entry */
mbed_official	52:a51c77007319	1006
mbed_official	52:a51c77007319	1007	/* Get PREDIV2 division factor and PLL2 multiplication factor */
mbed_official	52:a51c77007319	1008	prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
mbed_official	52:a51c77007319	1009	pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
mbed_official	52:a51c77007319	1010	RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
mbed_official	52:a51c77007319	1011	}
mbed_official	52:a51c77007319	1012	}
mbed_official	52:a51c77007319	1013	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	1014	break;
mbed_official	52:a51c77007319	1015
mbed_official	52:a51c77007319	1016	default:
mbed_official	52:a51c77007319	1017	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official	52:a51c77007319	1018	break;
mbed_official	52:a51c77007319	1019	}
mbed_official	52:a51c77007319	1020
mbed_official	52:a51c77007319	1021	/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
mbed_official	52:a51c77007319	1022	/* Get HCLK prescaler */
mbed_official	52:a51c77007319	1023	tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
mbed_official	52:a51c77007319	1024	tmp = tmp >> 4;
mbed_official	52:a51c77007319	1025	presc = APBAHBPrescTable[tmp];
mbed_official	52:a51c77007319	1026	/* HCLK clock frequency */
mbed_official	52:a51c77007319	1027	RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
mbed_official	52:a51c77007319	1028	/* Get PCLK1 prescaler */
mbed_official	52:a51c77007319	1029	tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
mbed_official	52:a51c77007319	1030	tmp = tmp >> 8;
mbed_official	52:a51c77007319	1031	presc = APBAHBPrescTable[tmp];
mbed_official	52:a51c77007319	1032	/* PCLK1 clock frequency */
mbed_official	52:a51c77007319	1033	RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official	52:a51c77007319	1034	/* Get PCLK2 prescaler */
mbed_official	52:a51c77007319	1035	tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
mbed_official	52:a51c77007319	1036	tmp = tmp >> 11;
mbed_official	52:a51c77007319	1037	presc = APBAHBPrescTable[tmp];
mbed_official	52:a51c77007319	1038	/* PCLK2 clock frequency */
mbed_official	52:a51c77007319	1039	RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official	52:a51c77007319	1040	/* Get ADCCLK prescaler */
mbed_official	52:a51c77007319	1041	tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
mbed_official	52:a51c77007319	1042	tmp = tmp >> 14;
mbed_official	52:a51c77007319	1043	presc = ADCPrescTable[tmp];
mbed_official	52:a51c77007319	1044	/* ADCCLK clock frequency */
mbed_official	52:a51c77007319	1045	RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
mbed_official	52:a51c77007319	1046	}
mbed_official	52:a51c77007319	1047
mbed_official	52:a51c77007319	1048	/**
mbed_official	52:a51c77007319	1049	* @brief Enables or disables the AHB peripheral clock.
mbed_official	52:a51c77007319	1050	* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official	52:a51c77007319	1051	*
mbed_official	52:a51c77007319	1052	* For @b STM32_Connectivity_line_devices, this parameter can be any combination
mbed_official	52:a51c77007319	1053	* of the following values:
mbed_official	52:a51c77007319	1054	* @arg RCC_AHBPeriph_DMA1
mbed_official	52:a51c77007319	1055	* @arg RCC_AHBPeriph_DMA2
mbed_official	52:a51c77007319	1056	* @arg RCC_AHBPeriph_SRAM
mbed_official	52:a51c77007319	1057	* @arg RCC_AHBPeriph_FLITF
mbed_official	52:a51c77007319	1058	* @arg RCC_AHBPeriph_CRC
mbed_official	52:a51c77007319	1059	* @arg RCC_AHBPeriph_OTG_FS
mbed_official	52:a51c77007319	1060	* @arg RCC_AHBPeriph_ETH_MAC
mbed_official	52:a51c77007319	1061	* @arg RCC_AHBPeriph_ETH_MAC_Tx
mbed_official	52:a51c77007319	1062	* @arg RCC_AHBPeriph_ETH_MAC_Rx
mbed_official	52:a51c77007319	1063	*
mbed_official	52:a51c77007319	1064	* For @b other_STM32_devices, this parameter can be any combination of the
mbed_official	52:a51c77007319	1065	* following values:
mbed_official	52:a51c77007319	1066	* @arg RCC_AHBPeriph_DMA1
mbed_official	52:a51c77007319	1067	* @arg RCC_AHBPeriph_DMA2
mbed_official	52:a51c77007319	1068	* @arg RCC_AHBPeriph_SRAM
mbed_official	52:a51c77007319	1069	* @arg RCC_AHBPeriph_FLITF
mbed_official	52:a51c77007319	1070	* @arg RCC_AHBPeriph_CRC
mbed_official	52:a51c77007319	1071	* @arg RCC_AHBPeriph_FSMC
mbed_official	52:a51c77007319	1072	* @arg RCC_AHBPeriph_SDIO
mbed_official	52:a51c77007319	1073	*
mbed_official	52:a51c77007319	1074	* @note SRAM and FLITF clock can be disabled only during sleep mode.
mbed_official	52:a51c77007319	1075	* @param NewState: new state of the specified peripheral clock.
mbed_official	52:a51c77007319	1076	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1077	* @retval None
mbed_official	52:a51c77007319	1078	*/
mbed_official	52:a51c77007319	1079	void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	52:a51c77007319	1080	{
mbed_official	52:a51c77007319	1081	/* Check the parameters */
mbed_official	52:a51c77007319	1082	assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official	52:a51c77007319	1083	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1084
mbed_official	52:a51c77007319	1085	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1086	{
mbed_official	52:a51c77007319	1087	RCC->AHBENR \|= RCC_AHBPeriph;
mbed_official	52:a51c77007319	1088	}
mbed_official	52:a51c77007319	1089	else
mbed_official	52:a51c77007319	1090	{
mbed_official	52:a51c77007319	1091	RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official	52:a51c77007319	1092	}
mbed_official	52:a51c77007319	1093	}
mbed_official	52:a51c77007319	1094
mbed_official	52:a51c77007319	1095	/**
mbed_official	52:a51c77007319	1096	* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official	52:a51c77007319	1097	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official	52:a51c77007319	1098	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	1099	* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
mbed_official	52:a51c77007319	1100	* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
mbed_official	52:a51c77007319	1101	* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
mbed_official	52:a51c77007319	1102	* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
mbed_official	52:a51c77007319	1103	* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
mbed_official	52:a51c77007319	1104	* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
mbed_official	52:a51c77007319	1105	* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
mbed_official	52:a51c77007319	1106	* @param NewState: new state of the specified peripheral clock.
mbed_official	52:a51c77007319	1107	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1108	* @retval None
mbed_official	52:a51c77007319	1109	*/
mbed_official	52:a51c77007319	1110	void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	52:a51c77007319	1111	{
mbed_official	52:a51c77007319	1112	/* Check the parameters */
mbed_official	52:a51c77007319	1113	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	52:a51c77007319	1114	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1115	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1116	{
mbed_official	52:a51c77007319	1117	RCC->APB2ENR \|= RCC_APB2Periph;
mbed_official	52:a51c77007319	1118	}
mbed_official	52:a51c77007319	1119	else
mbed_official	52:a51c77007319	1120	{
mbed_official	52:a51c77007319	1121	RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official	52:a51c77007319	1122	}
mbed_official	52:a51c77007319	1123	}
mbed_official	52:a51c77007319	1124
mbed_official	52:a51c77007319	1125	/**
mbed_official	52:a51c77007319	1126	* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official	52:a51c77007319	1127	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official	52:a51c77007319	1128	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	1129	* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
mbed_official	52:a51c77007319	1130	* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
mbed_official	52:a51c77007319	1131	* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
mbed_official	52:a51c77007319	1132	* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
mbed_official	52:a51c77007319	1133	* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
mbed_official	52:a51c77007319	1134	* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
mbed_official	52:a51c77007319	1135	* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
mbed_official	52:a51c77007319	1136	* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
mbed_official	52:a51c77007319	1137	* @param NewState: new state of the specified peripheral clock.
mbed_official	52:a51c77007319	1138	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1139	* @retval None
mbed_official	52:a51c77007319	1140	*/
mbed_official	52:a51c77007319	1141	void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	52:a51c77007319	1142	{
mbed_official	52:a51c77007319	1143	/* Check the parameters */
mbed_official	52:a51c77007319	1144	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	52:a51c77007319	1145	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1146	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1147	{
mbed_official	52:a51c77007319	1148	RCC->APB1ENR \|= RCC_APB1Periph;
mbed_official	52:a51c77007319	1149	}
mbed_official	52:a51c77007319	1150	else
mbed_official	52:a51c77007319	1151	{
mbed_official	52:a51c77007319	1152	RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official	52:a51c77007319	1153	}
mbed_official	52:a51c77007319	1154	}
mbed_official	52:a51c77007319	1155
mbed_official	52:a51c77007319	1156	#ifdef STM32F10X_CL
mbed_official	52:a51c77007319	1157	/**
mbed_official	52:a51c77007319	1158	* @brief Forces or releases AHB peripheral reset.
mbed_official	52:a51c77007319	1159	* @note This function applies only to STM32 Connectivity line devices.
mbed_official	52:a51c77007319	1160	* @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official	52:a51c77007319	1161	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	1162	* @arg RCC_AHBPeriph_OTG_FS
mbed_official	52:a51c77007319	1163	* @arg RCC_AHBPeriph_ETH_MAC
mbed_official	52:a51c77007319	1164	* @param NewState: new state of the specified peripheral reset.
mbed_official	52:a51c77007319	1165	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1166	* @retval None
mbed_official	52:a51c77007319	1167	*/
mbed_official	52:a51c77007319	1168	void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	52:a51c77007319	1169	{
mbed_official	52:a51c77007319	1170	/* Check the parameters */
mbed_official	52:a51c77007319	1171	assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
mbed_official	52:a51c77007319	1172	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1173
mbed_official	52:a51c77007319	1174	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1175	{
mbed_official	52:a51c77007319	1176	RCC->AHBRSTR \|= RCC_AHBPeriph;
mbed_official	52:a51c77007319	1177	}
mbed_official	52:a51c77007319	1178	else
mbed_official	52:a51c77007319	1179	{
mbed_official	52:a51c77007319	1180	RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official	52:a51c77007319	1181	}
mbed_official	52:a51c77007319	1182	}
mbed_official	52:a51c77007319	1183	#endif /* STM32F10X_CL */
mbed_official	52:a51c77007319	1184
mbed_official	52:a51c77007319	1185	/**
mbed_official	52:a51c77007319	1186	* @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official	52:a51c77007319	1187	* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official	52:a51c77007319	1188	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	1189	* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
mbed_official	52:a51c77007319	1190	* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
mbed_official	52:a51c77007319	1191	* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
mbed_official	52:a51c77007319	1192	* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
mbed_official	52:a51c77007319	1193	* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
mbed_official	52:a51c77007319	1194	* RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
mbed_official	52:a51c77007319	1195	* RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
mbed_official	52:a51c77007319	1196	* @param NewState: new state of the specified peripheral reset.
mbed_official	52:a51c77007319	1197	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1198	* @retval None
mbed_official	52:a51c77007319	1199	*/
mbed_official	52:a51c77007319	1200	void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	52:a51c77007319	1201	{
mbed_official	52:a51c77007319	1202	/* Check the parameters */
mbed_official	52:a51c77007319	1203	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	52:a51c77007319	1204	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1205	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1206	{
mbed_official	52:a51c77007319	1207	RCC->APB2RSTR \|= RCC_APB2Periph;
mbed_official	52:a51c77007319	1208	}
mbed_official	52:a51c77007319	1209	else
mbed_official	52:a51c77007319	1210	{
mbed_official	52:a51c77007319	1211	RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official	52:a51c77007319	1212	}
mbed_official	52:a51c77007319	1213	}
mbed_official	52:a51c77007319	1214
mbed_official	52:a51c77007319	1215	/**
mbed_official	52:a51c77007319	1216	* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official	52:a51c77007319	1217	* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official	52:a51c77007319	1218	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	1219	* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
mbed_official	52:a51c77007319	1220	* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
mbed_official	52:a51c77007319	1221	* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
mbed_official	52:a51c77007319	1222	* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
mbed_official	52:a51c77007319	1223	* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
mbed_official	52:a51c77007319	1224	* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
mbed_official	52:a51c77007319	1225	* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
mbed_official	52:a51c77007319	1226	* RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
mbed_official	52:a51c77007319	1227	* @param NewState: new state of the specified peripheral clock.
mbed_official	52:a51c77007319	1228	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1229	* @retval None
mbed_official	52:a51c77007319	1230	*/
mbed_official	52:a51c77007319	1231	void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	52:a51c77007319	1232	{
mbed_official	52:a51c77007319	1233	/* Check the parameters */
mbed_official	52:a51c77007319	1234	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	52:a51c77007319	1235	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1236	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1237	{
mbed_official	52:a51c77007319	1238	RCC->APB1RSTR \|= RCC_APB1Periph;
mbed_official	52:a51c77007319	1239	}
mbed_official	52:a51c77007319	1240	else
mbed_official	52:a51c77007319	1241	{
mbed_official	52:a51c77007319	1242	RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official	52:a51c77007319	1243	}
mbed_official	52:a51c77007319	1244	}
mbed_official	52:a51c77007319	1245
mbed_official	52:a51c77007319	1246	/**
mbed_official	52:a51c77007319	1247	* @brief Forces or releases the Backup domain reset.
mbed_official	52:a51c77007319	1248	* @param NewState: new state of the Backup domain reset.
mbed_official	52:a51c77007319	1249	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1250	* @retval None
mbed_official	52:a51c77007319	1251	*/
mbed_official	52:a51c77007319	1252	void RCC_BackupResetCmd(FunctionalState NewState)
mbed_official	52:a51c77007319	1253	{
mbed_official	52:a51c77007319	1254	/* Check the parameters */
mbed_official	52:a51c77007319	1255	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1256	(__IO uint32_t ) BDCR_BDRST_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	1257	}
mbed_official	52:a51c77007319	1258
mbed_official	52:a51c77007319	1259	/**
mbed_official	52:a51c77007319	1260	* @brief Enables or disables the Clock Security System.
mbed_official	52:a51c77007319	1261	* @param NewState: new state of the Clock Security System..
mbed_official	52:a51c77007319	1262	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1263	* @retval None
mbed_official	52:a51c77007319	1264	*/
mbed_official	52:a51c77007319	1265	void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official	52:a51c77007319	1266	{
mbed_official	52:a51c77007319	1267	/* Check the parameters */
mbed_official	52:a51c77007319	1268	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1269	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)NewState;
mbed_official	52:a51c77007319	1270	}
mbed_official	52:a51c77007319	1271
mbed_official	52:a51c77007319	1272	/**
mbed_official	52:a51c77007319	1273	* @brief Selects the clock source to output on MCO pin.
mbed_official	52:a51c77007319	1274	* @param RCC_MCO: specifies the clock source to output.
mbed_official	52:a51c77007319	1275	*
mbed_official	52:a51c77007319	1276	* For @b STM32_Connectivity_line_devices, this parameter can be one of the
mbed_official	52:a51c77007319	1277	* following values:
mbed_official	52:a51c77007319	1278	* @arg RCC_MCO_NoClock: No clock selected
mbed_official	52:a51c77007319	1279	* @arg RCC_MCO_SYSCLK: System clock selected
mbed_official	52:a51c77007319	1280	* @arg RCC_MCO_HSI: HSI oscillator clock selected
mbed_official	52:a51c77007319	1281	* @arg RCC_MCO_HSE: HSE oscillator clock selected
mbed_official	52:a51c77007319	1282	* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
mbed_official	52:a51c77007319	1283	* @arg RCC_MCO_PLL2CLK: PLL2 clock selected
mbed_official	52:a51c77007319	1284	* @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
mbed_official	52:a51c77007319	1285	* @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
mbed_official	52:a51c77007319	1286	* @arg RCC_MCO_PLL3CLK: PLL3 clock selected
mbed_official	52:a51c77007319	1287	*
mbed_official	52:a51c77007319	1288	* For @b other_STM32_devices, this parameter can be one of the following values:
mbed_official	52:a51c77007319	1289	* @arg RCC_MCO_NoClock: No clock selected
mbed_official	52:a51c77007319	1290	* @arg RCC_MCO_SYSCLK: System clock selected
mbed_official	52:a51c77007319	1291	* @arg RCC_MCO_HSI: HSI oscillator clock selected
mbed_official	52:a51c77007319	1292	* @arg RCC_MCO_HSE: HSE oscillator clock selected
mbed_official	52:a51c77007319	1293	* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
mbed_official	52:a51c77007319	1294	*
mbed_official	52:a51c77007319	1295	* @retval None
mbed_official	52:a51c77007319	1296	*/
mbed_official	52:a51c77007319	1297	void RCC_MCOConfig(uint8_t RCC_MCO)
mbed_official	52:a51c77007319	1298	{
mbed_official	52:a51c77007319	1299	/* Check the parameters */
mbed_official	52:a51c77007319	1300	assert_param(IS_RCC_MCO(RCC_MCO));
mbed_official	52:a51c77007319	1301
mbed_official	52:a51c77007319	1302	/* Perform Byte access to MCO bits to select the MCO source */
mbed_official	52:a51c77007319	1303	(__IO uint8_t ) CFGR_BYTE4_ADDRESS = RCC_MCO;
mbed_official	52:a51c77007319	1304	}
mbed_official	52:a51c77007319	1305
mbed_official	52:a51c77007319	1306	/**
mbed_official	52:a51c77007319	1307	* @brief Checks whether the specified RCC flag is set or not.
mbed_official	52:a51c77007319	1308	* @param RCC_FLAG: specifies the flag to check.
mbed_official	52:a51c77007319	1309	*
mbed_official	52:a51c77007319	1310	* For @b STM32_Connectivity_line_devices, this parameter can be one of the
mbed_official	52:a51c77007319	1311	* following values:
mbed_official	52:a51c77007319	1312	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	52:a51c77007319	1313	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	52:a51c77007319	1314	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	52:a51c77007319	1315	* @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
mbed_official	52:a51c77007319	1316	* @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
mbed_official	52:a51c77007319	1317	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	52:a51c77007319	1318	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	52:a51c77007319	1319	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	52:a51c77007319	1320	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	52:a51c77007319	1321	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	52:a51c77007319	1322	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	52:a51c77007319	1323	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	52:a51c77007319	1324	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	52:a51c77007319	1325	*
mbed_official	52:a51c77007319	1326	* For @b other_STM32_devices, this parameter can be one of the following values:
mbed_official	52:a51c77007319	1327	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	52:a51c77007319	1328	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	52:a51c77007319	1329	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	52:a51c77007319	1330	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	52:a51c77007319	1331	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	52:a51c77007319	1332	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	52:a51c77007319	1333	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	52:a51c77007319	1334	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	52:a51c77007319	1335	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	52:a51c77007319	1336	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	52:a51c77007319	1337	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	52:a51c77007319	1338	*
mbed_official	52:a51c77007319	1339	* @retval The new state of RCC_FLAG (SET or RESET).
mbed_official	52:a51c77007319	1340	*/
mbed_official	52:a51c77007319	1341	FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official	52:a51c77007319	1342	{
mbed_official	52:a51c77007319	1343	uint32_t tmp = 0;
mbed_official	52:a51c77007319	1344	uint32_t statusreg = 0;
mbed_official	52:a51c77007319	1345	FlagStatus bitstatus = RESET;
mbed_official	52:a51c77007319	1346	/* Check the parameters */
mbed_official	52:a51c77007319	1347	assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official	52:a51c77007319	1348
mbed_official	52:a51c77007319	1349	/* Get the RCC register index */
mbed_official	52:a51c77007319	1350	tmp = RCC_FLAG >> 5;
mbed_official	52:a51c77007319	1351	if (tmp == 1) /* The flag to check is in CR register */
mbed_official	52:a51c77007319	1352	{
mbed_official	52:a51c77007319	1353	statusreg = RCC->CR;
mbed_official	52:a51c77007319	1354	}
mbed_official	52:a51c77007319	1355	else if (tmp == 2) /* The flag to check is in BDCR register */
mbed_official	52:a51c77007319	1356	{
mbed_official	52:a51c77007319	1357	statusreg = RCC->BDCR;
mbed_official	52:a51c77007319	1358	}
mbed_official	52:a51c77007319	1359	else /* The flag to check is in CSR register */
mbed_official	52:a51c77007319	1360	{
mbed_official	52:a51c77007319	1361	statusreg = RCC->CSR;
mbed_official	52:a51c77007319	1362	}
mbed_official	52:a51c77007319	1363
mbed_official	52:a51c77007319	1364	/* Get the flag position */
mbed_official	52:a51c77007319	1365	tmp = RCC_FLAG & FLAG_Mask;
mbed_official	52:a51c77007319	1366	if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official	52:a51c77007319	1367	{
mbed_official	52:a51c77007319	1368	bitstatus = SET;
mbed_official	52:a51c77007319	1369	}
mbed_official	52:a51c77007319	1370	else
mbed_official	52:a51c77007319	1371	{
mbed_official	52:a51c77007319	1372	bitstatus = RESET;
mbed_official	52:a51c77007319	1373	}
mbed_official	52:a51c77007319	1374
mbed_official	52:a51c77007319	1375	/* Return the flag status */
mbed_official	52:a51c77007319	1376	return bitstatus;
mbed_official	52:a51c77007319	1377	}
mbed_official	52:a51c77007319	1378
mbed_official	52:a51c77007319	1379	/**
mbed_official	52:a51c77007319	1380	* @brief Clears the RCC reset flags.
mbed_official	52:a51c77007319	1381	* @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	52:a51c77007319	1382	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
mbed_official	52:a51c77007319	1383	* @param None
mbed_official	52:a51c77007319	1384	* @retval None
mbed_official	52:a51c77007319	1385	*/
mbed_official	52:a51c77007319	1386	void RCC_ClearFlag(void)
mbed_official	52:a51c77007319	1387	{
mbed_official	52:a51c77007319	1388	/* Set RMVF bit to clear the reset flags */
mbed_official	52:a51c77007319	1389	RCC->CSR \|= CSR_RMVF_Set;
mbed_official	52:a51c77007319	1390	}
mbed_official	52:a51c77007319	1391
mbed_official	52:a51c77007319	1392	/**
mbed_official	52:a51c77007319	1393	* @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official	52:a51c77007319	1394	* @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official	52:a51c77007319	1395	*
mbed_official	52:a51c77007319	1396	* For @b STM32_Connectivity_line_devices, this parameter can be one of the
mbed_official	52:a51c77007319	1397	* following values:
mbed_official	52:a51c77007319	1398	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	1399	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	1400	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	1401	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	1402	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	1403	* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
mbed_official	52:a51c77007319	1404	* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
mbed_official	52:a51c77007319	1405	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	52:a51c77007319	1406	*
mbed_official	52:a51c77007319	1407	* For @b other_STM32_devices, this parameter can be one of the following values:
mbed_official	52:a51c77007319	1408	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	1409	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	1410	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	1411	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	1412	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	1413	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	52:a51c77007319	1414	*
mbed_official	52:a51c77007319	1415	* @retval The new state of RCC_IT (SET or RESET).
mbed_official	52:a51c77007319	1416	*/
mbed_official	52:a51c77007319	1417	ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official	52:a51c77007319	1418	{
mbed_official	52:a51c77007319	1419	ITStatus bitstatus = RESET;
mbed_official	52:a51c77007319	1420	/* Check the parameters */
mbed_official	52:a51c77007319	1421	assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official	52:a51c77007319	1422
mbed_official	52:a51c77007319	1423	/* Check the status of the specified RCC interrupt */
mbed_official	52:a51c77007319	1424	if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official	52:a51c77007319	1425	{
mbed_official	52:a51c77007319	1426	bitstatus = SET;
mbed_official	52:a51c77007319	1427	}
mbed_official	52:a51c77007319	1428	else
mbed_official	52:a51c77007319	1429	{
mbed_official	52:a51c77007319	1430	bitstatus = RESET;
mbed_official	52:a51c77007319	1431	}
mbed_official	52:a51c77007319	1432
mbed_official	52:a51c77007319	1433	/* Return the RCC_IT status */
mbed_official	52:a51c77007319	1434	return bitstatus;
mbed_official	52:a51c77007319	1435	}
mbed_official	52:a51c77007319	1436
mbed_official	52:a51c77007319	1437	/**
mbed_official	52:a51c77007319	1438	* @brief Clears the RCC's interrupt pending bits.
mbed_official	52:a51c77007319	1439	* @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official	52:a51c77007319	1440	*
mbed_official	52:a51c77007319	1441	* For @b STM32_Connectivity_line_devices, this parameter can be any combination
mbed_official	52:a51c77007319	1442	* of the following values:
mbed_official	52:a51c77007319	1443	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	1444	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	1445	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	1446	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	1447	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	1448	* @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
mbed_official	52:a51c77007319	1449	* @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
mbed_official	52:a51c77007319	1450	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	52:a51c77007319	1451	*
mbed_official	52:a51c77007319	1452	* For @b other_STM32_devices, this parameter can be any combination of the
mbed_official	52:a51c77007319	1453	* following values:
mbed_official	52:a51c77007319	1454	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	52:a51c77007319	1455	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	52:a51c77007319	1456	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	52:a51c77007319	1457	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	52:a51c77007319	1458	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	52:a51c77007319	1459	*
mbed_official	52:a51c77007319	1460	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	52:a51c77007319	1461	* @retval None
mbed_official	52:a51c77007319	1462	*/
mbed_official	52:a51c77007319	1463	void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official	52:a51c77007319	1464	{
mbed_official	52:a51c77007319	1465	/* Check the parameters */
mbed_official	52:a51c77007319	1466	assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official	52:a51c77007319	1467
mbed_official	52:a51c77007319	1468	/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official	52:a51c77007319	1469	pending bits */
mbed_official	52:a51c77007319	1470	(__IO uint8_t ) CIR_BYTE3_ADDRESS = RCC_IT;
mbed_official	52:a51c77007319	1471	}
mbed_official	52:a51c77007319	1472
mbed_official	52:a51c77007319	1473	/**
mbed_official	52:a51c77007319	1474	* @}
mbed_official	52:a51c77007319	1475	*/
mbed_official	52:a51c77007319	1476
mbed_official	52:a51c77007319	1477	/**
mbed_official	52:a51c77007319	1478	* @}
mbed_official	52:a51c77007319	1479	*/
mbed_official	52:a51c77007319	1480
mbed_official	52:a51c77007319	1481	/**
mbed_official	52:a51c77007319	1482	* @}
mbed_official	52:a51c77007319	1483	*/
mbed_official	52:a51c77007319	1484
mbed_official	52:a51c77007319	1485	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2014
Imports:	301
Forks:	0
Commits:	115
Dependents:	0
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Followers:	15
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_rcc.c@70:c1fbde68b492, 2014-01-07 (annotated)

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