mbed library with additional peripherals for ST F401 board
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This mbed LIB has additional peripherals for ST F401 board
- UART2 : PA_3 rx, PA_2 tx
- UART3 : PC_7 rx, PC_6 tx
- I2C2 : PB_3 SDA, PB_10 SCL
- I2C3 : PB_4 SDA, PA_8 SCL
targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c@76:aeb1df146756, 2014-01-27 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Jan 27 14:30:07 2014 +0000
- Revision:
- 76:aeb1df146756
- Parent:
- 70:c1fbde68b492
- Child:
- 84:f54042cbc282
Synchronized with git revision a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd
Full URL: https://github.com/mbedmicro/mbed/commit/a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd/
Add NUCLEO_L152RE
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 52:a51c77007319 | 1 | /* mbed Microcontroller Library |
mbed_official | 70:c1fbde68b492 | 2 | * Copyright (c) 2014, STMicroelectronics |
mbed_official | 70:c1fbde68b492 | 3 | * All rights reserved. |
mbed_official | 52:a51c77007319 | 4 | * |
mbed_official | 70:c1fbde68b492 | 5 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 70:c1fbde68b492 | 6 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 52:a51c77007319 | 7 | * |
mbed_official | 70:c1fbde68b492 | 8 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 9 | * this list of conditions and the following disclaimer. |
mbed_official | 70:c1fbde68b492 | 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 70:c1fbde68b492 | 11 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 70:c1fbde68b492 | 12 | * and/or other materials provided with the distribution. |
mbed_official | 70:c1fbde68b492 | 13 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 70:c1fbde68b492 | 14 | * may be used to endorse or promote products derived from this software |
mbed_official | 70:c1fbde68b492 | 15 | * without specific prior written permission. |
mbed_official | 52:a51c77007319 | 16 | * |
mbed_official | 70:c1fbde68b492 | 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 70:c1fbde68b492 | 18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 70:c1fbde68b492 | 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 70:c1fbde68b492 | 20 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 70:c1fbde68b492 | 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 70:c1fbde68b492 | 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 70:c1fbde68b492 | 23 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 70:c1fbde68b492 | 24 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 70:c1fbde68b492 | 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 70:c1fbde68b492 | 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 52:a51c77007319 | 27 | */ |
mbed_official | 52:a51c77007319 | 28 | #include <stddef.h> |
mbed_official | 52:a51c77007319 | 29 | #include "us_ticker_api.h" |
mbed_official | 52:a51c77007319 | 30 | #include "PeripheralNames.h" |
mbed_official | 52:a51c77007319 | 31 | |
mbed_official | 76:aeb1df146756 | 32 | // Timers selection: |
mbed_official | 76:aeb1df146756 | 33 | // The Master timer clocks the Slave timer |
mbed_official | 76:aeb1df146756 | 34 | |
mbed_official | 76:aeb1df146756 | 35 | #define TIM_MST TIM1 |
mbed_official | 76:aeb1df146756 | 36 | #define TIM_MST_IRQ TIM1_CC_IRQn |
mbed_official | 76:aeb1df146756 | 37 | #define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE) |
mbed_official | 76:aeb1df146756 | 38 | |
mbed_official | 76:aeb1df146756 | 39 | #define TIM_SLV TIM4 |
mbed_official | 76:aeb1df146756 | 40 | #define TIM_SLV_IRQ TIM4_IRQn |
mbed_official | 76:aeb1df146756 | 41 | #define TIM_SLV_RCC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE) |
mbed_official | 76:aeb1df146756 | 42 | |
mbed_official | 76:aeb1df146756 | 43 | #define MST_SLV_ITR TIM_TS_ITR0 |
mbed_official | 76:aeb1df146756 | 44 | |
mbed_official | 52:a51c77007319 | 45 | int us_ticker_inited = 0; |
mbed_official | 52:a51c77007319 | 46 | |
mbed_official | 52:a51c77007319 | 47 | void us_ticker_init(void) { |
mbed_official | 52:a51c77007319 | 48 | |
mbed_official | 52:a51c77007319 | 49 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
mbed_official | 52:a51c77007319 | 50 | TIM_OCInitTypeDef TIM_OCInitStructure; |
mbed_official | 52:a51c77007319 | 51 | |
mbed_official | 52:a51c77007319 | 52 | if (us_ticker_inited) return; |
mbed_official | 52:a51c77007319 | 53 | us_ticker_inited = 1; |
mbed_official | 52:a51c77007319 | 54 | |
mbed_official | 52:a51c77007319 | 55 | // Enable Timers clock |
mbed_official | 76:aeb1df146756 | 56 | TIM_MST_RCC; |
mbed_official | 76:aeb1df146756 | 57 | TIM_SLV_RCC; |
mbed_official | 52:a51c77007319 | 58 | |
mbed_official | 76:aeb1df146756 | 59 | // Master and Slave timers time base configuration |
mbed_official | 54:24d77221bceb | 60 | TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); |
mbed_official | 52:a51c77007319 | 61 | TIM_TimeBaseStructure.TIM_Period = 0xFFFF; |
mbed_official | 52:a51c77007319 | 62 | TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
mbed_official | 52:a51c77007319 | 63 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
mbed_official | 52:a51c77007319 | 64 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; |
mbed_official | 76:aeb1df146756 | 65 | TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); |
mbed_official | 52:a51c77007319 | 66 | TIM_TimeBaseStructure.TIM_Prescaler = 0; |
mbed_official | 76:aeb1df146756 | 67 | TIM_TimeBaseInit(TIM_SLV, &TIM_TimeBaseStructure); |
mbed_official | 52:a51c77007319 | 68 | |
mbed_official | 52:a51c77007319 | 69 | // Master timer configuration |
mbed_official | 54:24d77221bceb | 70 | TIM_OCStructInit(&TIM_OCInitStructure); |
mbed_official | 52:a51c77007319 | 71 | TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; |
mbed_official | 52:a51c77007319 | 72 | TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; |
mbed_official | 52:a51c77007319 | 73 | TIM_OCInitStructure.TIM_Pulse = 0; |
mbed_official | 52:a51c77007319 | 74 | TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; |
mbed_official | 76:aeb1df146756 | 75 | TIM_OC1Init(TIM_MST, &TIM_OCInitStructure); |
mbed_official | 76:aeb1df146756 | 76 | TIM_SelectMasterSlaveMode(TIM_MST, TIM_MasterSlaveMode_Enable); |
mbed_official | 76:aeb1df146756 | 77 | TIM_SelectOutputTrigger(TIM_MST, TIM_TRGOSource_Update); |
mbed_official | 52:a51c77007319 | 78 | |
mbed_official | 52:a51c77007319 | 79 | // Slave timer configuration |
mbed_official | 76:aeb1df146756 | 80 | TIM_SelectSlaveMode(TIM_SLV, TIM_SlaveMode_External1); |
mbed_official | 76:aeb1df146756 | 81 | // The connection between Master and Slave is done here |
mbed_official | 76:aeb1df146756 | 82 | TIM_SelectInputTrigger(TIM_SLV, MST_SLV_ITR); |
mbed_official | 52:a51c77007319 | 83 | |
mbed_official | 52:a51c77007319 | 84 | // Enable timers |
mbed_official | 76:aeb1df146756 | 85 | TIM_Cmd(TIM_SLV, ENABLE); |
mbed_official | 76:aeb1df146756 | 86 | TIM_Cmd(TIM_MST, ENABLE); |
mbed_official | 52:a51c77007319 | 87 | } |
mbed_official | 52:a51c77007319 | 88 | |
mbed_official | 52:a51c77007319 | 89 | uint32_t us_ticker_read() { |
mbed_official | 54:24d77221bceb | 90 | uint32_t counter, counter2; |
mbed_official | 52:a51c77007319 | 91 | if (!us_ticker_inited) us_ticker_init(); |
mbed_official | 76:aeb1df146756 | 92 | // A situation might appear when Master overflows right after Slave is read and before the |
mbed_official | 76:aeb1df146756 | 93 | // new (overflowed) value of Master is read. Which would make the code below consider the |
mbed_official | 76:aeb1df146756 | 94 | // previous (incorrect) value of Slave and the new value of Master, which would return a |
mbed_official | 54:24d77221bceb | 95 | // value in the past. Avoid this by computing consecutive values of the timer until they |
mbed_official | 54:24d77221bceb | 96 | // are properly ordered. |
mbed_official | 76:aeb1df146756 | 97 | counter = (uint32_t)((uint32_t)TIM_GetCounter(TIM_SLV) << 16); |
mbed_official | 76:aeb1df146756 | 98 | counter += (uint32_t)TIM_GetCounter(TIM_MST); |
mbed_official | 54:24d77221bceb | 99 | while (1) { |
mbed_official | 76:aeb1df146756 | 100 | counter2 = (uint32_t)((uint32_t)TIM_GetCounter(TIM_SLV) << 16); |
mbed_official | 76:aeb1df146756 | 101 | counter2 += (uint32_t)TIM_GetCounter(TIM_MST); |
mbed_official | 76:aeb1df146756 | 102 | if (counter2 > counter) { |
mbed_official | 54:24d77221bceb | 103 | break; |
mbed_official | 76:aeb1df146756 | 104 | } |
mbed_official | 54:24d77221bceb | 105 | counter = counter2; |
mbed_official | 54:24d77221bceb | 106 | } |
mbed_official | 54:24d77221bceb | 107 | return counter2; |
mbed_official | 52:a51c77007319 | 108 | } |
mbed_official | 52:a51c77007319 | 109 | |
mbed_official | 52:a51c77007319 | 110 | void us_ticker_set_interrupt(unsigned int timestamp) { |
mbed_official | 52:a51c77007319 | 111 | if (timestamp > 0xFFFF) { |
mbed_official | 76:aeb1df146756 | 112 | TIM_SetCompare1(TIM_SLV, (uint16_t)((timestamp >> 16) & 0xFFFF)); |
mbed_official | 76:aeb1df146756 | 113 | TIM_ITConfig(TIM_SLV, TIM_IT_CC1, ENABLE); |
mbed_official | 76:aeb1df146756 | 114 | NVIC_SetVector(TIM_SLV_IRQ, (uint32_t)us_ticker_irq_handler); |
mbed_official | 76:aeb1df146756 | 115 | NVIC_EnableIRQ(TIM_SLV_IRQ); |
mbed_official | 52:a51c77007319 | 116 | } |
mbed_official | 52:a51c77007319 | 117 | else { |
mbed_official | 76:aeb1df146756 | 118 | TIM_SetCompare1(TIM_MST, (uint16_t)timestamp); |
mbed_official | 76:aeb1df146756 | 119 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); |
mbed_official | 76:aeb1df146756 | 120 | NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler); |
mbed_official | 76:aeb1df146756 | 121 | NVIC_EnableIRQ(TIM_MST_IRQ); |
mbed_official | 52:a51c77007319 | 122 | } |
mbed_official | 52:a51c77007319 | 123 | } |
mbed_official | 52:a51c77007319 | 124 | |
mbed_official | 52:a51c77007319 | 125 | void us_ticker_disable_interrupt(void) { |
mbed_official | 76:aeb1df146756 | 126 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE); |
mbed_official | 76:aeb1df146756 | 127 | TIM_ITConfig(TIM_SLV, TIM_IT_CC1, DISABLE); |
mbed_official | 52:a51c77007319 | 128 | } |
mbed_official | 52:a51c77007319 | 129 | |
mbed_official | 52:a51c77007319 | 130 | void us_ticker_clear_interrupt(void) { |
mbed_official | 76:aeb1df146756 | 131 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); |
mbed_official | 76:aeb1df146756 | 132 | TIM_ClearITPendingBit(TIM_SLV, TIM_IT_CC1); |
mbed_official | 52:a51c77007319 | 133 | } |