mbed-F401 - mbed library with additional peripherals for ST F…

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Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

UART2 : PA_3 rx, PA_2 tx
UART3 : PC_7 rx, PC_6 tx
I2C2 : PB_3 SDA, PB_10 SCL
I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx.h@76:aeb1df146756, 2014-01-27 (annotated)

Committer:: mbed_official
Date:: Mon Jan 27 14:30:07 2014 +0000
Revision:: 76:aeb1df146756
Child:: 80:66393a7b209d

Synchronized with git revision a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd



Full URL: https://github.com/mbedmicro/mbed/commit/a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd/



Add NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	76:aeb1df146756	1	/**
mbed_official	76:aeb1df146756	2	******************************************************************************
mbed_official	76:aeb1df146756	3	* @file stm32l1xx.h
mbed_official	76:aeb1df146756	4	* @author MCD Application Team
mbed_official	76:aeb1df146756	5	* @version V1.2.0
mbed_official	76:aeb1df146756	6	* @date 22-February-2013
mbed_official	76:aeb1df146756	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
mbed_official	76:aeb1df146756	8	* This file contains all the peripheral register's definitions, bits
mbed_official	76:aeb1df146756	9	* definitions and memory mapping for STM32L1xx High-density, Medium-density
mbed_official	76:aeb1df146756	10	* and Medium-density Plus devices.
mbed_official	76:aeb1df146756	11	*
mbed_official	76:aeb1df146756	12	* The file is the unique include file that the application programmer
mbed_official	76:aeb1df146756	13	* is using in the C source code, usually in main.c. This file contains:
mbed_official	76:aeb1df146756	14	* - Configuration section that allows to select:
mbed_official	76:aeb1df146756	15	* - The device used in the target application
mbed_official	76:aeb1df146756	16	* - To use or not the peripherals drivers in application code(i.e.
mbed_official	76:aeb1df146756	17	* code will be based on direct access to peripherals registers
mbed_official	76:aeb1df146756	18	* rather than drivers API), this option is controlled by
mbed_official	76:aeb1df146756	19	* "#define USE_STDPERIPH_DRIVER"
mbed_official	76:aeb1df146756	20	* - To change few application-specific parameters such as the HSE
mbed_official	76:aeb1df146756	21	* crystal frequency
mbed_official	76:aeb1df146756	22	* - Data structures and the address mapping for all peripherals
mbed_official	76:aeb1df146756	23	* - Peripheral's registers declarations and bits definition
mbed_official	76:aeb1df146756	24	* - Macros to access peripherals registers hardware
mbed_official	76:aeb1df146756	25	*
mbed_official	76:aeb1df146756	26	******************************************************************************
mbed_official	76:aeb1df146756	27	* @attention
mbed_official	76:aeb1df146756	28	*
mbed_official	76:aeb1df146756	29	* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
mbed_official	76:aeb1df146756	30	*
mbed_official	76:aeb1df146756	31	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official	76:aeb1df146756	32	* You may not use this file except in compliance with the License.
mbed_official	76:aeb1df146756	33	* You may obtain a copy of the License at:
mbed_official	76:aeb1df146756	34	*
mbed_official	76:aeb1df146756	35	* http://www.st.com/software_license_agreement_liberty_v2
mbed_official	76:aeb1df146756	36	*
mbed_official	76:aeb1df146756	37	* Unless required by applicable law or agreed to in writing, software
mbed_official	76:aeb1df146756	38	* distributed under the License is distributed on an "AS IS" BASIS,
mbed_official	76:aeb1df146756	39	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official	76:aeb1df146756	40	* See the License for the specific language governing permissions and
mbed_official	76:aeb1df146756	41	* limitations under the License.
mbed_official	76:aeb1df146756	42	*
mbed_official	76:aeb1df146756	43	******************************************************************************
mbed_official	76:aeb1df146756	44	*/
mbed_official	76:aeb1df146756	45
mbed_official	76:aeb1df146756	46	/** @addtogroup CMSIS
mbed_official	76:aeb1df146756	47	* @{
mbed_official	76:aeb1df146756	48	*/
mbed_official	76:aeb1df146756	49
mbed_official	76:aeb1df146756	50	/** @addtogroup stm32l1xx
mbed_official	76:aeb1df146756	51	* @{
mbed_official	76:aeb1df146756	52	*/
mbed_official	76:aeb1df146756	53
mbed_official	76:aeb1df146756	54	#ifndef __STM32L1XX_H
mbed_official	76:aeb1df146756	55	#define __STM32L1XX_H
mbed_official	76:aeb1df146756	56
mbed_official	76:aeb1df146756	57	#ifdef __cplusplus
mbed_official	76:aeb1df146756	58	extern "C" {
mbed_official	76:aeb1df146756	59	#endif
mbed_official	76:aeb1df146756	60
mbed_official	76:aeb1df146756	61	/** @addtogroup Library_configuration_section
mbed_official	76:aeb1df146756	62	* @{
mbed_official	76:aeb1df146756	63	*/
mbed_official	76:aeb1df146756	64
mbed_official	76:aeb1df146756	65	/* Uncomment the line below according to the target STM32L device used in your
mbed_official	76:aeb1df146756	66	application
mbed_official	76:aeb1df146756	67	*/
mbed_official	76:aeb1df146756	68
mbed_official	76:aeb1df146756	69	#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
mbed_official	76:aeb1df146756	70
mbed_official	76:aeb1df146756	71	/* #define STM32L1XX_MD / /!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
mbed_official	76:aeb1df146756	72	STM32L151xBxx, STM32L152x6xx, STM32L152x8xx and STM32L152xBxx.
mbed_official	76:aeb1df146756	73	- Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
mbed_official	76:aeb1df146756	74	STM32L100x8xx and STM32L100xBxx. */
mbed_official	76:aeb1df146756	75
mbed_official	76:aeb1df146756	76	//#define STM32L1XX_MDP /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
mbed_official	76:aeb1df146756	77	// - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
mbed_official	76:aeb1df146756	78
mbed_official	76:aeb1df146756	79	#define STM32L1XX_HD /!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx /
mbed_official	76:aeb1df146756	80	#endif
mbed_official	76:aeb1df146756	81	/* Tip: To avoid modifying this file each time you need to switch between these
mbed_official	76:aeb1df146756	82	devices, you can define the device in your toolchain compiler preprocessor.
mbed_official	76:aeb1df146756	83	*/
mbed_official	76:aeb1df146756	84
mbed_official	76:aeb1df146756	85	#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
mbed_official	76:aeb1df146756	86	#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
mbed_official	76:aeb1df146756	87	#endif
mbed_official	76:aeb1df146756	88
mbed_official	76:aeb1df146756	89	#if !defined USE_STDPERIPH_DRIVER
mbed_official	76:aeb1df146756	90	/**
mbed_official	76:aeb1df146756	91	* @brief Comment the line below if you will not use the peripherals drivers.
mbed_official	76:aeb1df146756	92	In this case, these drivers will not be included and the application code will
mbed_official	76:aeb1df146756	93	be based on direct access to peripherals registers
mbed_official	76:aeb1df146756	94	*/
mbed_official	76:aeb1df146756	95	#define USE_STDPERIPH_DRIVER
mbed_official	76:aeb1df146756	96	#endif
mbed_official	76:aeb1df146756	97
mbed_official	76:aeb1df146756	98	/**
mbed_official	76:aeb1df146756	99	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
mbed_official	76:aeb1df146756	100	used in your application
mbed_official	76:aeb1df146756	101
mbed_official	76:aeb1df146756	102	Tip: To avoid modifying this file each time you need to use different HSE, you
mbed_official	76:aeb1df146756	103	can define the HSE value in your toolchain compiler preprocessor.
mbed_official	76:aeb1df146756	104	*/
mbed_official	76:aeb1df146756	105	#if !defined (HSE_VALUE)
mbed_official	76:aeb1df146756	106	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External oscillator in Hz /
mbed_official	76:aeb1df146756	107	#endif
mbed_official	76:aeb1df146756	108
mbed_official	76:aeb1df146756	109	/**
mbed_official	76:aeb1df146756	110	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
mbed_official	76:aeb1df146756	111	Timeout value
mbed_official	76:aeb1df146756	112	*/
mbed_official	76:aeb1df146756	113	#if !defined (HSE_STARTUP_TIMEOUT)
mbed_official	76:aeb1df146756	114	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /!< Time out for HSE start up /
mbed_official	76:aeb1df146756	115	#endif
mbed_official	76:aeb1df146756	116
mbed_official	76:aeb1df146756	117	/**
mbed_official	76:aeb1df146756	118	* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
mbed_official	76:aeb1df146756	119	Timeout value
mbed_official	76:aeb1df146756	120	*/
mbed_official	76:aeb1df146756	121	#if !defined (HSI_STARTUP_TIMEOUT)
mbed_official	76:aeb1df146756	122	#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /!< Time out for HSI start up /
mbed_official	76:aeb1df146756	123	#endif
mbed_official	76:aeb1df146756	124
mbed_official	76:aeb1df146756	125	#if !defined (HSI_VALUE)
mbed_official	76:aeb1df146756	126	#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
mbed_official	76:aeb1df146756	127	The real value may vary depending on the variations
mbed_official	76:aeb1df146756	128	in voltage and temperature. */
mbed_official	76:aeb1df146756	129	#endif
mbed_official	76:aeb1df146756	130
mbed_official	76:aeb1df146756	131	#if !defined (LSI_VALUE)
mbed_official	76:aeb1df146756	132	#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
mbed_official	76:aeb1df146756	133	The real value may vary depending on the variations
mbed_official	76:aeb1df146756	134	in voltage and temperature. */
mbed_official	76:aeb1df146756	135	#endif
mbed_official	76:aeb1df146756	136
mbed_official	76:aeb1df146756	137	#if !defined (LSE_VALUE)
mbed_official	76:aeb1df146756	138	#define LSE_VALUE ((uint32_t)32768) /!< Value of the External Low Speed oscillator in Hz /
mbed_official	76:aeb1df146756	139	#endif
mbed_official	76:aeb1df146756	140
mbed_official	76:aeb1df146756	141	/**
mbed_official	76:aeb1df146756	142	* @brief STM32L1xx Standard Peripheral Library version number V1.2.0
mbed_official	76:aeb1df146756	143	*/
mbed_official	76:aeb1df146756	144	#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
mbed_official	76:aeb1df146756	145	#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x02) /!< [23:16] sub1 version /
mbed_official	76:aeb1df146756	146	#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
mbed_official	76:aeb1df146756	147	#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
mbed_official	76:aeb1df146756	148	#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
mbed_official	76:aeb1df146756	149	\|(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
mbed_official	76:aeb1df146756	150	\|(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
mbed_official	76:aeb1df146756	151	\|(__STM32L1XX_STDPERIPH_VERSION_RC))
mbed_official	76:aeb1df146756	152
mbed_official	76:aeb1df146756	153	/**
mbed_official	76:aeb1df146756	154	* @}
mbed_official	76:aeb1df146756	155	*/
mbed_official	76:aeb1df146756	156
mbed_official	76:aeb1df146756	157	/** @addtogroup Configuration_section_for_CMSIS
mbed_official	76:aeb1df146756	158	* @{
mbed_official	76:aeb1df146756	159	*/
mbed_official	76:aeb1df146756	160
mbed_official	76:aeb1df146756	161	/**
mbed_official	76:aeb1df146756	162	* @brief STM32L1xx Interrupt Number Definition, according to the selected device
mbed_official	76:aeb1df146756	163	* in @ref Library_configuration_section
mbed_official	76:aeb1df146756	164	*/
mbed_official	76:aeb1df146756	165	#define __CM3_REV 0x200 /!< Cortex-M3 Revision r2p0 /
mbed_official	76:aeb1df146756	166	#define __MPU_PRESENT 1 /!< STM32L1 provides MPU /
mbed_official	76:aeb1df146756	167	#define __NVIC_PRIO_BITS 4 /!< STM32L1 uses 4 Bits for the Priority Levels /
mbed_official	76:aeb1df146756	168	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	76:aeb1df146756	169
mbed_official	76:aeb1df146756	170	/!< Interrupt Number Definition /
mbed_official	76:aeb1df146756	171	typedef enum IRQn
mbed_official	76:aeb1df146756	172	{
mbed_official	76:aeb1df146756	173	/**** Cortex-M3 Processor Exceptions Numbers ****************************************************/
mbed_official	76:aeb1df146756	174	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
mbed_official	76:aeb1df146756	175	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
mbed_official	76:aeb1df146756	176	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
mbed_official	76:aeb1df146756	177	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
mbed_official	76:aeb1df146756	178	SVC_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
mbed_official	76:aeb1df146756	179	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
mbed_official	76:aeb1df146756	180	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
mbed_official	76:aeb1df146756	181	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
mbed_official	76:aeb1df146756	182
mbed_official	76:aeb1df146756	183	/**** STM32L specific Interrupt Numbers *********************************************************/
mbed_official	76:aeb1df146756	184	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
mbed_official	76:aeb1df146756	185	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
mbed_official	76:aeb1df146756	186	TAMPER_STAMP_IRQn = 2, /!< Tamper and Time Stamp through EXTI Line Interrupts /
mbed_official	76:aeb1df146756	187	RTC_WKUP_IRQn = 3, /!< RTC Wakeup Timer through EXTI Line Interrupt /
mbed_official	76:aeb1df146756	188	FLASH_IRQn = 4, /!< FLASH global Interrupt /
mbed_official	76:aeb1df146756	189	RCC_IRQn = 5, /!< RCC global Interrupt /
mbed_official	76:aeb1df146756	190	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
mbed_official	76:aeb1df146756	191	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
mbed_official	76:aeb1df146756	192	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
mbed_official	76:aeb1df146756	193	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
mbed_official	76:aeb1df146756	194	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
mbed_official	76:aeb1df146756	195	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
mbed_official	76:aeb1df146756	196	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
mbed_official	76:aeb1df146756	197	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
mbed_official	76:aeb1df146756	198	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
mbed_official	76:aeb1df146756	199	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
mbed_official	76:aeb1df146756	200	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
mbed_official	76:aeb1df146756	201	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
mbed_official	76:aeb1df146756	202	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
mbed_official	76:aeb1df146756	203	USB_HP_IRQn = 19, /!< USB High Priority Interrupt /
mbed_official	76:aeb1df146756	204	USB_LP_IRQn = 20, /!< USB Low Priority Interrupt /
mbed_official	76:aeb1df146756	205	DAC_IRQn = 21, /!< DAC Interrupt /
mbed_official	76:aeb1df146756	206	COMP_IRQn = 22, /!< Comparator through EXTI Line Interrupt /
mbed_official	76:aeb1df146756	207	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
mbed_official	76:aeb1df146756	208	LCD_IRQn = 24, /!< LCD Interrupt /
mbed_official	76:aeb1df146756	209	TIM9_IRQn = 25, /!< TIM9 global Interrupt /
mbed_official	76:aeb1df146756	210	TIM10_IRQn = 26, /!< TIM10 global Interrupt /
mbed_official	76:aeb1df146756	211	TIM11_IRQn = 27, /!< TIM11 global Interrupt /
mbed_official	76:aeb1df146756	212	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
mbed_official	76:aeb1df146756	213	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
mbed_official	76:aeb1df146756	214	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
mbed_official	76:aeb1df146756	215	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
mbed_official	76:aeb1df146756	216	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
mbed_official	76:aeb1df146756	217	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
mbed_official	76:aeb1df146756	218	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
mbed_official	76:aeb1df146756	219	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
mbed_official	76:aeb1df146756	220	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
mbed_official	76:aeb1df146756	221	USART1_IRQn = 37, /!< USART1 global Interrupt /
mbed_official	76:aeb1df146756	222	USART2_IRQn = 38, /!< USART2 global Interrupt /
mbed_official	76:aeb1df146756	223	USART3_IRQn = 39, /!< USART3 global Interrupt /
mbed_official	76:aeb1df146756	224	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
mbed_official	76:aeb1df146756	225	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
mbed_official	76:aeb1df146756	226	USB_FS_WKUP_IRQn = 42, /!< USB FS WakeUp from suspend through EXTI Line Interrupt /
mbed_official	76:aeb1df146756	227	TIM6_IRQn = 43, /!< TIM6 global Interrupt /
mbed_official	76:aeb1df146756	228	#ifdef STM32L1XX_MD
mbed_official	76:aeb1df146756	229	TIM7_IRQn = 44 /!< TIM7 global Interrupt /
mbed_official	76:aeb1df146756	230	#endif /* STM32L1XX_MD */
mbed_official	76:aeb1df146756	231
mbed_official	76:aeb1df146756	232	#ifdef STM32L1XX_MDP
mbed_official	76:aeb1df146756	233	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
mbed_official	76:aeb1df146756	234	TIM5_IRQn = 46, /!< TIM5 global Interrupt /
mbed_official	76:aeb1df146756	235	SPI3_IRQn = 47, /!< SPI3 global Interrupt /
mbed_official	76:aeb1df146756	236	DMA2_Channel1_IRQn = 50, /!< DMA2 Channel 1 global Interrupt /
mbed_official	76:aeb1df146756	237	DMA2_Channel2_IRQn = 51, /!< DMA2 Channel 2 global Interrupt /
mbed_official	76:aeb1df146756	238	DMA2_Channel3_IRQn = 52, /!< DMA2 Channel 3 global Interrupt /
mbed_official	76:aeb1df146756	239	DMA2_Channel4_IRQn = 53, /!< DMA2 Channel 4 global Interrupt /
mbed_official	76:aeb1df146756	240	DMA2_Channel5_IRQn = 54, /!< DMA2 Channel 5 global Interrupt /
mbed_official	76:aeb1df146756	241	AES_IRQn = 55, /!< AES global Interrupt /
mbed_official	76:aeb1df146756	242	COMP_ACQ_IRQn = 56 /!< Comparator Channel Acquisition global Interrupt /
mbed_official	76:aeb1df146756	243	#endif /* STM32L1XX_MDP */
mbed_official	76:aeb1df146756	244
mbed_official	76:aeb1df146756	245	#ifdef STM32L1XX_HD
mbed_official	76:aeb1df146756	246	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
mbed_official	76:aeb1df146756	247	SDIO_IRQn = 45, /!< SDIO global Interrupt /
mbed_official	76:aeb1df146756	248	TIM5_IRQn = 46, /!< TIM5 global Interrupt /
mbed_official	76:aeb1df146756	249	SPI3_IRQn = 47, /!< SPI3 global Interrupt /
mbed_official	76:aeb1df146756	250	UART4_IRQn = 48, /!< UART4 global Interrupt /
mbed_official	76:aeb1df146756	251	UART5_IRQn = 49, /!< UART5 global Interrupt /
mbed_official	76:aeb1df146756	252	DMA2_Channel1_IRQn = 50, /!< DMA2 Channel 1 global Interrupt /
mbed_official	76:aeb1df146756	253	DMA2_Channel2_IRQn = 51, /!< DMA2 Channel 2 global Interrupt /
mbed_official	76:aeb1df146756	254	DMA2_Channel3_IRQn = 52, /!< DMA2 Channel 3 global Interrupt /
mbed_official	76:aeb1df146756	255	DMA2_Channel4_IRQn = 53, /!< DMA2 Channel 4 global Interrupt /
mbed_official	76:aeb1df146756	256	DMA2_Channel5_IRQn = 54, /!< DMA2 Channel 5 global Interrupt /
mbed_official	76:aeb1df146756	257	AES_IRQn = 55, /!< AES global Interrupt /
mbed_official	76:aeb1df146756	258	COMP_ACQ_IRQn = 56 /!< Comparator Channel Acquisition global Interrupt /
mbed_official	76:aeb1df146756	259	#endif /* STM32L1XX_HD */
mbed_official	76:aeb1df146756	260	} IRQn_Type;
mbed_official	76:aeb1df146756	261
mbed_official	76:aeb1df146756	262	/**
mbed_official	76:aeb1df146756	263	* @}
mbed_official	76:aeb1df146756	264	*/
mbed_official	76:aeb1df146756	265
mbed_official	76:aeb1df146756	266	#include "core_cm3.h"
mbed_official	76:aeb1df146756	267	#include "system_stm32l1xx.h"
mbed_official	76:aeb1df146756	268	#include <stdint.h>
mbed_official	76:aeb1df146756	269
mbed_official	76:aeb1df146756	270	/** @addtogroup Exported_types
mbed_official	76:aeb1df146756	271	* @{
mbed_official	76:aeb1df146756	272	*/
mbed_official	76:aeb1df146756	273
mbed_official	76:aeb1df146756	274	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
mbed_official	76:aeb1df146756	275
mbed_official	76:aeb1df146756	276	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
mbed_official	76:aeb1df146756	277	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
mbed_official	76:aeb1df146756	278
mbed_official	76:aeb1df146756	279	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
mbed_official	76:aeb1df146756	280
mbed_official	76:aeb1df146756	281	/**
mbed_official	76:aeb1df146756	282	* @brief __RAM_FUNC definition
mbed_official	76:aeb1df146756	283	*/
mbed_official	76:aeb1df146756	284	#if defined ( __CC_ARM )
mbed_official	76:aeb1df146756	285	/* ARM Compiler
mbed_official	76:aeb1df146756	286	------------
mbed_official	76:aeb1df146756	287	RAM functions are defined using the toolchain options.
mbed_official	76:aeb1df146756	288	Functions that are executed in RAM should reside in a separate source module.
mbed_official	76:aeb1df146756	289	Using the 'Options for File' dialog you can simply change the 'Code / Const'
mbed_official	76:aeb1df146756	290	area of a module to a memory space in physical RAM.
mbed_official	76:aeb1df146756	291	Available memory areas are declared in the 'Target' tab of the 'Options for Target'
mbed_official	76:aeb1df146756	292	dialog.
mbed_official	76:aeb1df146756	293	*/
mbed_official	76:aeb1df146756	294	#define __RAM_FUNC FLASH_Status
mbed_official	76:aeb1df146756	295
mbed_official	76:aeb1df146756	296	#elif defined ( __ICCARM__ )
mbed_official	76:aeb1df146756	297	/* ICCARM Compiler
mbed_official	76:aeb1df146756	298	---------------
mbed_official	76:aeb1df146756	299	RAM functions are defined using a specific toolchain keyword "__ramfunc".
mbed_official	76:aeb1df146756	300	*/
mbed_official	76:aeb1df146756	301	#define __RAM_FUNC __ramfunc FLASH_Status
mbed_official	76:aeb1df146756	302
mbed_official	76:aeb1df146756	303	#elif defined ( __GNUC__ )
mbed_official	76:aeb1df146756	304	/* GNU Compiler
mbed_official	76:aeb1df146756	305	------------
mbed_official	76:aeb1df146756	306	RAM functions are defined using a specific toolchain attribute
mbed_official	76:aeb1df146756	307	"__attribute__((section(".data")))".
mbed_official	76:aeb1df146756	308	*/
mbed_official	76:aeb1df146756	309	#define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
mbed_official	76:aeb1df146756	310
mbed_official	76:aeb1df146756	311	#elif defined ( __TASKING__ )
mbed_official	76:aeb1df146756	312	/* TASKING Compiler
mbed_official	76:aeb1df146756	313	----------------
mbed_official	76:aeb1df146756	314	RAM functions are defined using a specific toolchain pragma. This pragma is
mbed_official	76:aeb1df146756	315	defined in the stm32l1xx_flash_ramfunc.c
mbed_official	76:aeb1df146756	316	*/
mbed_official	76:aeb1df146756	317	#define __RAM_FUNC FLASH_Status
mbed_official	76:aeb1df146756	318
mbed_official	76:aeb1df146756	319	#endif
mbed_official	76:aeb1df146756	320
mbed_official	76:aeb1df146756	321	/**
mbed_official	76:aeb1df146756	322	* @}
mbed_official	76:aeb1df146756	323	*/
mbed_official	76:aeb1df146756	324
mbed_official	76:aeb1df146756	325	/** @addtogroup Peripheral_registers_structures
mbed_official	76:aeb1df146756	326	* @{
mbed_official	76:aeb1df146756	327	*/
mbed_official	76:aeb1df146756	328
mbed_official	76:aeb1df146756	329	/**
mbed_official	76:aeb1df146756	330	* @brief Analog to Digital Converter
mbed_official	76:aeb1df146756	331	*/
mbed_official	76:aeb1df146756	332
mbed_official	76:aeb1df146756	333	typedef struct
mbed_official	76:aeb1df146756	334	{
mbed_official	76:aeb1df146756	335	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	336	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
mbed_official	76:aeb1df146756	337	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
mbed_official	76:aeb1df146756	338	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
mbed_official	76:aeb1df146756	339	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
mbed_official	76:aeb1df146756	340	__IO uint32_t SMPR3; /!< ADC sample time register 3, Address offset: 0x14 /
mbed_official	76:aeb1df146756	341	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x18 /
mbed_official	76:aeb1df146756	342	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x1C /
mbed_official	76:aeb1df146756	343	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x20 /
mbed_official	76:aeb1df146756	344	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x24 /
mbed_official	76:aeb1df146756	345	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	346	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	347	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
mbed_official	76:aeb1df146756	348	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
mbed_official	76:aeb1df146756	349	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
mbed_official	76:aeb1df146756	350	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
mbed_official	76:aeb1df146756	351	__IO uint32_t SQR5; /!< ADC regular sequence register 5, Address offset: 0x40 /
mbed_official	76:aeb1df146756	352	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x44 /
mbed_official	76:aeb1df146756	353	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x48 /
mbed_official	76:aeb1df146756	354	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x4C /
mbed_official	76:aeb1df146756	355	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x50 /
mbed_official	76:aeb1df146756	356	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x54 /
mbed_official	76:aeb1df146756	357	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x58 /
mbed_official	76:aeb1df146756	358	__IO uint32_t SMPR0; /!< ADC sample time register 0, Address offset: 0x5C /
mbed_official	76:aeb1df146756	359	} ADC_TypeDef;
mbed_official	76:aeb1df146756	360
mbed_official	76:aeb1df146756	361	typedef struct
mbed_official	76:aeb1df146756	362	{
mbed_official	76:aeb1df146756	363	__IO uint32_t CSR; /!< ADC common status register, Address offset: ADC1 base address + 0x300 /
mbed_official	76:aeb1df146756	364	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
mbed_official	76:aeb1df146756	365	} ADC_Common_TypeDef;
mbed_official	76:aeb1df146756	366
mbed_official	76:aeb1df146756	367
mbed_official	76:aeb1df146756	368	/**
mbed_official	76:aeb1df146756	369	* @brief AES hardware accelerator
mbed_official	76:aeb1df146756	370	*/
mbed_official	76:aeb1df146756	371
mbed_official	76:aeb1df146756	372	typedef struct
mbed_official	76:aeb1df146756	373	{
mbed_official	76:aeb1df146756	374	__IO uint32_t CR; /!< AES control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	375	__IO uint32_t SR; /!< AES status register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	376	__IO uint32_t DINR; /!< AES data input register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	377	__IO uint32_t DOUTR; /!< AES data output register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	378	__IO uint32_t KEYR0; /!< AES key register 0, Address offset: 0x10 /
mbed_official	76:aeb1df146756	379	__IO uint32_t KEYR1; /!< AES key register 1, Address offset: 0x14 /
mbed_official	76:aeb1df146756	380	__IO uint32_t KEYR2; /!< AES key register 2, Address offset: 0x18 /
mbed_official	76:aeb1df146756	381	__IO uint32_t KEYR3; /!< AES key register 3, Address offset: 0x1C /
mbed_official	76:aeb1df146756	382	__IO uint32_t IVR0; /!< AES initialization vector register 0, Address offset: 0x20 /
mbed_official	76:aeb1df146756	383	__IO uint32_t IVR1; /!< AES initialization vector register 1, Address offset: 0x24 /
mbed_official	76:aeb1df146756	384	__IO uint32_t IVR2; /!< AES initialization vector register 2, Address offset: 0x28 /
mbed_official	76:aeb1df146756	385	__IO uint32_t IVR3; /!< AES initialization vector register 3, Address offset: 0x2C /
mbed_official	76:aeb1df146756	386	} AES_TypeDef;
mbed_official	76:aeb1df146756	387
mbed_official	76:aeb1df146756	388	/**
mbed_official	76:aeb1df146756	389	* @brief Comparator
mbed_official	76:aeb1df146756	390	*/
mbed_official	76:aeb1df146756	391
mbed_official	76:aeb1df146756	392	typedef struct
mbed_official	76:aeb1df146756	393	{
mbed_official	76:aeb1df146756	394	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	395	} COMP_TypeDef;
mbed_official	76:aeb1df146756	396
mbed_official	76:aeb1df146756	397	/**
mbed_official	76:aeb1df146756	398	* @brief CRC calculation unit
mbed_official	76:aeb1df146756	399	*/
mbed_official	76:aeb1df146756	400
mbed_official	76:aeb1df146756	401	typedef struct
mbed_official	76:aeb1df146756	402	{
mbed_official	76:aeb1df146756	403	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	404	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	405	uint8_t RESERVED0; /!< Reserved, 0x05 /
mbed_official	76:aeb1df146756	406	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	407	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	408	} CRC_TypeDef;
mbed_official	76:aeb1df146756	409
mbed_official	76:aeb1df146756	410	/**
mbed_official	76:aeb1df146756	411	* @brief Digital to Analog Converter
mbed_official	76:aeb1df146756	412	*/
mbed_official	76:aeb1df146756	413
mbed_official	76:aeb1df146756	414	typedef struct
mbed_official	76:aeb1df146756	415	{
mbed_official	76:aeb1df146756	416	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	417	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	418	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	419	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	420	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	421	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	422	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	423	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	424	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	425	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
mbed_official	76:aeb1df146756	426	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	427	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	428	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
mbed_official	76:aeb1df146756	429	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
mbed_official	76:aeb1df146756	430	} DAC_TypeDef;
mbed_official	76:aeb1df146756	431
mbed_official	76:aeb1df146756	432	/**
mbed_official	76:aeb1df146756	433	* @brief Debug MCU
mbed_official	76:aeb1df146756	434	*/
mbed_official	76:aeb1df146756	435
mbed_official	76:aeb1df146756	436	typedef struct
mbed_official	76:aeb1df146756	437	{
mbed_official	76:aeb1df146756	438	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
mbed_official	76:aeb1df146756	439	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	440	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	441	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	442	}DBGMCU_TypeDef;
mbed_official	76:aeb1df146756	443
mbed_official	76:aeb1df146756	444	/**
mbed_official	76:aeb1df146756	445	* @brief DMA Controller
mbed_official	76:aeb1df146756	446	*/
mbed_official	76:aeb1df146756	447
mbed_official	76:aeb1df146756	448	typedef struct
mbed_official	76:aeb1df146756	449	{
mbed_official	76:aeb1df146756	450	__IO uint32_t CCR; /!< DMA channel x configuration register /
mbed_official	76:aeb1df146756	451	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
mbed_official	76:aeb1df146756	452	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
mbed_official	76:aeb1df146756	453	__IO uint32_t CMAR; /!< DMA channel x memory address register /
mbed_official	76:aeb1df146756	454	} DMA_Channel_TypeDef;
mbed_official	76:aeb1df146756	455
mbed_official	76:aeb1df146756	456	typedef struct
mbed_official	76:aeb1df146756	457	{
mbed_official	76:aeb1df146756	458	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	459	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	460	} DMA_TypeDef;
mbed_official	76:aeb1df146756	461
mbed_official	76:aeb1df146756	462	/**
mbed_official	76:aeb1df146756	463	* @brief External Interrupt/Event Controller
mbed_official	76:aeb1df146756	464	*/
mbed_official	76:aeb1df146756	465
mbed_official	76:aeb1df146756	466	typedef struct
mbed_official	76:aeb1df146756	467	{
mbed_official	76:aeb1df146756	468	__IO uint32_t IMR; /!< EXTI interrupt mask register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	469	__IO uint32_t EMR; /!< EXTI event mask register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	470	__IO uint32_t RTSR; /!< EXTI rising edge trigger selection register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	471	__IO uint32_t FTSR; /!< EXTI Falling edge trigger selection register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	472	__IO uint32_t SWIER; /!< EXTI software interrupt event register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	473	__IO uint32_t PR; /!< EXTI pending register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	474	} EXTI_TypeDef;
mbed_official	76:aeb1df146756	475
mbed_official	76:aeb1df146756	476	/**
mbed_official	76:aeb1df146756	477	* @brief FLASH Registers
mbed_official	76:aeb1df146756	478	*/
mbed_official	76:aeb1df146756	479
mbed_official	76:aeb1df146756	480	typedef struct
mbed_official	76:aeb1df146756	481	{
mbed_official	76:aeb1df146756	482	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	483	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	484	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	485	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
mbed_official	76:aeb1df146756	486	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	487	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	488	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	489	__IO uint32_t OBR; /!< Option byte register, Address offset: 0x1c /
mbed_official	76:aeb1df146756	490	__IO uint32_t WRPR; /!< Write protection register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	491	uint32_t RESERVED[23]; /!< Reserved, 0x24 /
mbed_official	76:aeb1df146756	492	__IO uint32_t WRPR1; /!< Write protection register 1, Address offset: 0x28 /
mbed_official	76:aeb1df146756	493	__IO uint32_t WRPR2; /!< Write protection register 2, Address offset: 0x2C /
mbed_official	76:aeb1df146756	494	} FLASH_TypeDef;
mbed_official	76:aeb1df146756	495
mbed_official	76:aeb1df146756	496	/**
mbed_official	76:aeb1df146756	497	* @brief Option Bytes Registers
mbed_official	76:aeb1df146756	498	*/
mbed_official	76:aeb1df146756	499
mbed_official	76:aeb1df146756	500	typedef struct
mbed_official	76:aeb1df146756	501	{
mbed_official	76:aeb1df146756	502	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	503	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	504	__IO uint32_t WRP01; /!< write protection register 0 1, Address offset: 0x08 /
mbed_official	76:aeb1df146756	505	__IO uint32_t WRP23; /!< write protection register 2 3, Address offset: 0x0C /
mbed_official	76:aeb1df146756	506	__IO uint32_t WRP45; /!< write protection register 4 5, Address offset: 0x10 /
mbed_official	76:aeb1df146756	507	__IO uint32_t WRP67; /!< write protection register 6 7, Address offset: 0x14 /
mbed_official	76:aeb1df146756	508	__IO uint32_t WRP89; /!< write protection register 8 9, Address offset: 0x18 /
mbed_official	76:aeb1df146756	509	__IO uint32_t WRP1011; /!< write protection register 10 11, Address offset: 0x1C /
mbed_official	76:aeb1df146756	510	} OB_TypeDef;
mbed_official	76:aeb1df146756	511
mbed_official	76:aeb1df146756	512	/**
mbed_official	76:aeb1df146756	513	* @brief Operational Amplifier (OPAMP)
mbed_official	76:aeb1df146756	514	*/
mbed_official	76:aeb1df146756	515
mbed_official	76:aeb1df146756	516	typedef struct
mbed_official	76:aeb1df146756	517	{
mbed_official	76:aeb1df146756	518	__IO uint32_t CSR; /!< OPAMP control/status register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	519	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
mbed_official	76:aeb1df146756	520	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
mbed_official	76:aeb1df146756	521	} OPAMP_TypeDef;
mbed_official	76:aeb1df146756	522
mbed_official	76:aeb1df146756	523	/**
mbed_official	76:aeb1df146756	524	* @brief Flexible Static Memory Controller
mbed_official	76:aeb1df146756	525	*/
mbed_official	76:aeb1df146756	526
mbed_official	76:aeb1df146756	527	typedef struct
mbed_official	76:aeb1df146756	528	{
mbed_official	76:aeb1df146756	529	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
mbed_official	76:aeb1df146756	530	} FSMC_Bank1_TypeDef;
mbed_official	76:aeb1df146756	531
mbed_official	76:aeb1df146756	532	/**
mbed_official	76:aeb1df146756	533	* @brief Flexible Static Memory Controller Bank1E
mbed_official	76:aeb1df146756	534	*/
mbed_official	76:aeb1df146756	535
mbed_official	76:aeb1df146756	536	typedef struct
mbed_official	76:aeb1df146756	537	{
mbed_official	76:aeb1df146756	538	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
mbed_official	76:aeb1df146756	539	} FSMC_Bank1E_TypeDef;
mbed_official	76:aeb1df146756	540
mbed_official	76:aeb1df146756	541	/**
mbed_official	76:aeb1df146756	542	* @brief General Purpose IO
mbed_official	76:aeb1df146756	543	*/
mbed_official	76:aeb1df146756	544
mbed_official	76:aeb1df146756	545	typedef struct
mbed_official	76:aeb1df146756	546	{
mbed_official	76:aeb1df146756	547	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	548	__IO uint16_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	549	uint16_t RESERVED0; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	550	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	551	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	552	__IO uint16_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	553	uint16_t RESERVED1; /!< Reserved, 0x12 /
mbed_official	76:aeb1df146756	554	__IO uint16_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	555	uint16_t RESERVED2; /!< Reserved, 0x16 /
mbed_official	76:aeb1df146756	556	__IO uint16_t BSRRL; /!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 /
mbed_official	76:aeb1df146756	557	__IO uint16_t BSRRH; /!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A /
mbed_official	76:aeb1df146756	558	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	559	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
mbed_official	76:aeb1df146756	560	__IO uint16_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	561	uint16_t RESERVED3; /!< Reserved, 0x2A /
mbed_official	76:aeb1df146756	562	} GPIO_TypeDef;
mbed_official	76:aeb1df146756	563
mbed_official	76:aeb1df146756	564	/**
mbed_official	76:aeb1df146756	565	* @brief SysTem Configuration
mbed_official	76:aeb1df146756	566	*/
mbed_official	76:aeb1df146756	567
mbed_official	76:aeb1df146756	568	typedef struct
mbed_official	76:aeb1df146756	569	{
mbed_official	76:aeb1df146756	570	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	571	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	572	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
mbed_official	76:aeb1df146756	573	} SYSCFG_TypeDef;
mbed_official	76:aeb1df146756	574
mbed_official	76:aeb1df146756	575	/**
mbed_official	76:aeb1df146756	576	* @brief Inter-integrated Circuit Interface
mbed_official	76:aeb1df146756	577	*/
mbed_official	76:aeb1df146756	578
mbed_official	76:aeb1df146756	579	typedef struct
mbed_official	76:aeb1df146756	580	{
mbed_official	76:aeb1df146756	581	__IO uint16_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
mbed_official	76:aeb1df146756	582	uint16_t RESERVED0; /!< Reserved, 0x02 /
mbed_official	76:aeb1df146756	583	__IO uint16_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
mbed_official	76:aeb1df146756	584	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	585	__IO uint16_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
mbed_official	76:aeb1df146756	586	uint16_t RESERVED2; /!< Reserved, 0x0A /
mbed_official	76:aeb1df146756	587	__IO uint16_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
mbed_official	76:aeb1df146756	588	uint16_t RESERVED3; /!< Reserved, 0x0E /
mbed_official	76:aeb1df146756	589	__IO uint16_t DR; /!< I2C Data register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	590	uint16_t RESERVED4; /!< Reserved, 0x12 /
mbed_official	76:aeb1df146756	591	__IO uint16_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
mbed_official	76:aeb1df146756	592	uint16_t RESERVED5; /!< Reserved, 0x16 /
mbed_official	76:aeb1df146756	593	__IO uint16_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
mbed_official	76:aeb1df146756	594	uint16_t RESERVED6; /!< Reserved, 0x1A /
mbed_official	76:aeb1df146756	595	__IO uint16_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	596	uint16_t RESERVED7; /!< Reserved, 0x1E /
mbed_official	76:aeb1df146756	597	__IO uint16_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	598	uint16_t RESERVED8; /!< Reserved, 0x22 /
mbed_official	76:aeb1df146756	599	} I2C_TypeDef;
mbed_official	76:aeb1df146756	600
mbed_official	76:aeb1df146756	601	/**
mbed_official	76:aeb1df146756	602	* @brief Independent WATCHDOG
mbed_official	76:aeb1df146756	603	*/
mbed_official	76:aeb1df146756	604
mbed_official	76:aeb1df146756	605	typedef struct
mbed_official	76:aeb1df146756	606	{
mbed_official	76:aeb1df146756	607	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	608	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	609	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	610	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	611	} IWDG_TypeDef;
mbed_official	76:aeb1df146756	612
mbed_official	76:aeb1df146756	613
mbed_official	76:aeb1df146756	614	/**
mbed_official	76:aeb1df146756	615	* @brief LCD
mbed_official	76:aeb1df146756	616	*/
mbed_official	76:aeb1df146756	617
mbed_official	76:aeb1df146756	618	typedef struct
mbed_official	76:aeb1df146756	619	{
mbed_official	76:aeb1df146756	620	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	621	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	622	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	623	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	624	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
mbed_official	76:aeb1df146756	625	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
mbed_official	76:aeb1df146756	626	} LCD_TypeDef;
mbed_official	76:aeb1df146756	627
mbed_official	76:aeb1df146756	628	/**
mbed_official	76:aeb1df146756	629	* @brief Power Control
mbed_official	76:aeb1df146756	630	*/
mbed_official	76:aeb1df146756	631
mbed_official	76:aeb1df146756	632	typedef struct
mbed_official	76:aeb1df146756	633	{
mbed_official	76:aeb1df146756	634	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	635	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	636	} PWR_TypeDef;
mbed_official	76:aeb1df146756	637
mbed_official	76:aeb1df146756	638	/**
mbed_official	76:aeb1df146756	639	* @brief Reset and Clock Control
mbed_official	76:aeb1df146756	640	*/
mbed_official	76:aeb1df146756	641
mbed_official	76:aeb1df146756	642	typedef struct
mbed_official	76:aeb1df146756	643	{
mbed_official	76:aeb1df146756	644	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	645	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	646	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	647	__IO uint32_t CIR; /!< RCC Clock interrupt register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	648	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	649	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	650	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	651	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	652	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	653	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x24 /
mbed_official	76:aeb1df146756	654	__IO uint32_t AHBLPENR; /!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	655	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	656	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 /
mbed_official	76:aeb1df146756	657	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x34 /
mbed_official	76:aeb1df146756	658	} RCC_TypeDef;
mbed_official	76:aeb1df146756	659
mbed_official	76:aeb1df146756	660	/**
mbed_official	76:aeb1df146756	661	* @brief Routing Interface
mbed_official	76:aeb1df146756	662	*/
mbed_official	76:aeb1df146756	663
mbed_official	76:aeb1df146756	664	typedef struct
mbed_official	76:aeb1df146756	665	{
mbed_official	76:aeb1df146756	666	__IO uint32_t ICR; /!< RI input capture register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	667	__IO uint32_t ASCR1; /!< RI analog switches control register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	668	__IO uint32_t ASCR2; /!< RI analog switch control register 2, Address offset: 0x08 /
mbed_official	76:aeb1df146756	669	__IO uint32_t HYSCR1; /!< RI hysteresis control register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	670	__IO uint32_t HYSCR2; /!< RI Hysteresis control register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	671	__IO uint32_t HYSCR3; /!< RI Hysteresis control register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	672	__IO uint32_t HYSCR4; /!< RI Hysteresis control register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	673	} RI_TypeDef;
mbed_official	76:aeb1df146756	674
mbed_official	76:aeb1df146756	675	/**
mbed_official	76:aeb1df146756	676	* @brief Real-Time Clock
mbed_official	76:aeb1df146756	677	*/
mbed_official	76:aeb1df146756	678
mbed_official	76:aeb1df146756	679	typedef struct
mbed_official	76:aeb1df146756	680	{
mbed_official	76:aeb1df146756	681	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	682	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	683	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	684	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	685	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	686	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	687	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	688	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	689	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	690	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
mbed_official	76:aeb1df146756	691	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	692	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	693	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
mbed_official	76:aeb1df146756	694	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
mbed_official	76:aeb1df146756	695	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
mbed_official	76:aeb1df146756	696	__IO uint32_t CALR; /!< RRTC calibration register, Address offset: 0x3C /
mbed_official	76:aeb1df146756	697	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
mbed_official	76:aeb1df146756	698	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
mbed_official	76:aeb1df146756	699	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
mbed_official	76:aeb1df146756	700	uint32_t RESERVED7; /!< Reserved, 0x4C /
mbed_official	76:aeb1df146756	701	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
mbed_official	76:aeb1df146756	702	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
mbed_official	76:aeb1df146756	703	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
mbed_official	76:aeb1df146756	704	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
mbed_official	76:aeb1df146756	705	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
mbed_official	76:aeb1df146756	706	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
mbed_official	76:aeb1df146756	707	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
mbed_official	76:aeb1df146756	708	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
mbed_official	76:aeb1df146756	709	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
mbed_official	76:aeb1df146756	710	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
mbed_official	76:aeb1df146756	711	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
mbed_official	76:aeb1df146756	712	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
mbed_official	76:aeb1df146756	713	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
mbed_official	76:aeb1df146756	714	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
mbed_official	76:aeb1df146756	715	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
mbed_official	76:aeb1df146756	716	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
mbed_official	76:aeb1df146756	717	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
mbed_official	76:aeb1df146756	718	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
mbed_official	76:aeb1df146756	719	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
mbed_official	76:aeb1df146756	720	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
mbed_official	76:aeb1df146756	721	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
mbed_official	76:aeb1df146756	722	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
mbed_official	76:aeb1df146756	723	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
mbed_official	76:aeb1df146756	724	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
mbed_official	76:aeb1df146756	725	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
mbed_official	76:aeb1df146756	726	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
mbed_official	76:aeb1df146756	727	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
mbed_official	76:aeb1df146756	728	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
mbed_official	76:aeb1df146756	729	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
mbed_official	76:aeb1df146756	730	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
mbed_official	76:aeb1df146756	731	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
mbed_official	76:aeb1df146756	732	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
mbed_official	76:aeb1df146756	733	} RTC_TypeDef;
mbed_official	76:aeb1df146756	734
mbed_official	76:aeb1df146756	735	/**
mbed_official	76:aeb1df146756	736	* @brief SD host Interface
mbed_official	76:aeb1df146756	737	*/
mbed_official	76:aeb1df146756	738
mbed_official	76:aeb1df146756	739	typedef struct
mbed_official	76:aeb1df146756	740	{
mbed_official	76:aeb1df146756	741	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	742	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	743	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	744	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	745	__I uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	746	__I uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	747	__I uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	748	__I uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	749	__I uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	750	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
mbed_official	76:aeb1df146756	751	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
mbed_official	76:aeb1df146756	752	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	753	__I uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
mbed_official	76:aeb1df146756	754	__I uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
mbed_official	76:aeb1df146756	755	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
mbed_official	76:aeb1df146756	756	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
mbed_official	76:aeb1df146756	757	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
mbed_official	76:aeb1df146756	758	__I uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
mbed_official	76:aeb1df146756	759	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
mbed_official	76:aeb1df146756	760	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
mbed_official	76:aeb1df146756	761	} SDIO_TypeDef;
mbed_official	76:aeb1df146756	762
mbed_official	76:aeb1df146756	763	/**
mbed_official	76:aeb1df146756	764	* @brief Serial Peripheral Interface
mbed_official	76:aeb1df146756	765	*/
mbed_official	76:aeb1df146756	766
mbed_official	76:aeb1df146756	767	typedef struct
mbed_official	76:aeb1df146756	768	{
mbed_official	76:aeb1df146756	769	__IO uint16_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
mbed_official	76:aeb1df146756	770	uint16_t RESERVED0; /!< Reserved, 0x02 /
mbed_official	76:aeb1df146756	771	__IO uint16_t CR2; /!< SPI control register 2, Address offset: 0x04 /
mbed_official	76:aeb1df146756	772	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	773	__IO uint16_t SR; /!< SPI status register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	774	uint16_t RESERVED2; /!< Reserved, 0x0A /
mbed_official	76:aeb1df146756	775	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	776	uint16_t RESERVED3; /!< Reserved, 0x0E /
mbed_official	76:aeb1df146756	777	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
mbed_official	76:aeb1df146756	778	uint16_t RESERVED4; /!< Reserved, 0x12 /
mbed_official	76:aeb1df146756	779	__IO uint16_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
mbed_official	76:aeb1df146756	780	uint16_t RESERVED5; /!< Reserved, 0x16 /
mbed_official	76:aeb1df146756	781	__IO uint16_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
mbed_official	76:aeb1df146756	782	uint16_t RESERVED6; /!< Reserved, 0x1A /
mbed_official	76:aeb1df146756	783	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
mbed_official	76:aeb1df146756	784	uint16_t RESERVED7; /!< Reserved, 0x1E /
mbed_official	76:aeb1df146756	785	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	786	uint16_t RESERVED8; /!< Reserved, 0x22 /
mbed_official	76:aeb1df146756	787	} SPI_TypeDef;
mbed_official	76:aeb1df146756	788
mbed_official	76:aeb1df146756	789	/**
mbed_official	76:aeb1df146756	790	* @brief TIM
mbed_official	76:aeb1df146756	791	*/
mbed_official	76:aeb1df146756	792
mbed_official	76:aeb1df146756	793	typedef struct
mbed_official	76:aeb1df146756	794	{
mbed_official	76:aeb1df146756	795	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
mbed_official	76:aeb1df146756	796	uint16_t RESERVED0; /!< Reserved, 0x02 /
mbed_official	76:aeb1df146756	797	__IO uint16_t CR2; /!< TIM control register 2, Address offset: 0x04 /
mbed_official	76:aeb1df146756	798	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	799	__IO uint16_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	800	uint16_t RESERVED2; /!< Reserved, 0x0A /
mbed_official	76:aeb1df146756	801	__IO uint16_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
mbed_official	76:aeb1df146756	802	uint16_t RESERVED3; /!< Reserved, 0x0E /
mbed_official	76:aeb1df146756	803	__IO uint16_t SR; /!< TIM status register, Address offset: 0x10 /
mbed_official	76:aeb1df146756	804	uint16_t RESERVED4; /!< Reserved, 0x12 /
mbed_official	76:aeb1df146756	805	__IO uint16_t EGR; /!< TIM event generation register, Address offset: 0x14 /
mbed_official	76:aeb1df146756	806	uint16_t RESERVED5; /!< Reserved, 0x16 /
mbed_official	76:aeb1df146756	807	__IO uint16_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
mbed_official	76:aeb1df146756	808	uint16_t RESERVED6; /!< Reserved, 0x1A /
mbed_official	76:aeb1df146756	809	__IO uint16_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
mbed_official	76:aeb1df146756	810	uint16_t RESERVED7; /!< Reserved, 0x1E /
mbed_official	76:aeb1df146756	811	__IO uint16_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
mbed_official	76:aeb1df146756	812	uint16_t RESERVED8; /!< Reserved, 0x22 /
mbed_official	76:aeb1df146756	813	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
mbed_official	76:aeb1df146756	814	__IO uint16_t PSC; /!< TIM prescaler, Address offset: 0x28 /
mbed_official	76:aeb1df146756	815	uint16_t RESERVED10; /!< Reserved, 0x2A /
mbed_official	76:aeb1df146756	816	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
mbed_official	76:aeb1df146756	817	uint32_t RESERVED12; /!< Reserved, 0x30 /
mbed_official	76:aeb1df146756	818	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
mbed_official	76:aeb1df146756	819	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
mbed_official	76:aeb1df146756	820	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
mbed_official	76:aeb1df146756	821	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
mbed_official	76:aeb1df146756	822	uint32_t RESERVED17; /!< Reserved, 0x44 /
mbed_official	76:aeb1df146756	823	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
mbed_official	76:aeb1df146756	824	uint16_t RESERVED18; /!< Reserved, 0x4A /
mbed_official	76:aeb1df146756	825	__IO uint16_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
mbed_official	76:aeb1df146756	826	uint16_t RESERVED19; /!< Reserved, 0x4E /
mbed_official	76:aeb1df146756	827	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
mbed_official	76:aeb1df146756	828	uint16_t RESERVED20; /!< Reserved, 0x52 /
mbed_official	76:aeb1df146756	829	} TIM_TypeDef;
mbed_official	76:aeb1df146756	830
mbed_official	76:aeb1df146756	831	/**
mbed_official	76:aeb1df146756	832	* @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official	76:aeb1df146756	833	*/
mbed_official	76:aeb1df146756	834
mbed_official	76:aeb1df146756	835	typedef struct
mbed_official	76:aeb1df146756	836	{
mbed_official	76:aeb1df146756	837	__IO uint16_t SR; /!< USART Status register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	838	uint16_t RESERVED0; /!< Reserved, 0x02 /
mbed_official	76:aeb1df146756	839	__IO uint16_t DR; /!< USART Data register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	840	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	76:aeb1df146756	841	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	842	uint16_t RESERVED2; /!< Reserved, 0x0A /
mbed_official	76:aeb1df146756	843	__IO uint16_t CR1; /!< USART Control register 1, Address offset: 0x0C /
mbed_official	76:aeb1df146756	844	uint16_t RESERVED3; /!< Reserved, 0x0E /
mbed_official	76:aeb1df146756	845	__IO uint16_t CR2; /!< USART Control register 2, Address offset: 0x10 /
mbed_official	76:aeb1df146756	846	uint16_t RESERVED4; /!< Reserved, 0x12 /
mbed_official	76:aeb1df146756	847	__IO uint16_t CR3; /!< USART Control register 3, Address offset: 0x14 /
mbed_official	76:aeb1df146756	848	uint16_t RESERVED5; /!< Reserved, 0x16 /
mbed_official	76:aeb1df146756	849	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
mbed_official	76:aeb1df146756	850	uint16_t RESERVED6; /!< Reserved, 0x1A /
mbed_official	76:aeb1df146756	851	} USART_TypeDef;
mbed_official	76:aeb1df146756	852
mbed_official	76:aeb1df146756	853	/**
mbed_official	76:aeb1df146756	854	* @brief Window WATCHDOG
mbed_official	76:aeb1df146756	855	*/
mbed_official	76:aeb1df146756	856
mbed_official	76:aeb1df146756	857	typedef struct
mbed_official	76:aeb1df146756	858	{
mbed_official	76:aeb1df146756	859	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
mbed_official	76:aeb1df146756	860	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
mbed_official	76:aeb1df146756	861	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
mbed_official	76:aeb1df146756	862	} WWDG_TypeDef;
mbed_official	76:aeb1df146756	863
mbed_official	76:aeb1df146756	864	/**
mbed_official	76:aeb1df146756	865	* @}
mbed_official	76:aeb1df146756	866	*/
mbed_official	76:aeb1df146756	867
mbed_official	76:aeb1df146756	868	/** @addtogroup Peripheral_memory_map
mbed_official	76:aeb1df146756	869	* @{
mbed_official	76:aeb1df146756	870	*/
mbed_official	76:aeb1df146756	871
mbed_official	76:aeb1df146756	872	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
mbed_official	76:aeb1df146756	873	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
mbed_official	76:aeb1df146756	874	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
mbed_official	76:aeb1df146756	875
mbed_official	76:aeb1df146756	876	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
mbed_official	76:aeb1df146756	877	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
mbed_official	76:aeb1df146756	878
mbed_official	76:aeb1df146756	879	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
mbed_official	76:aeb1df146756	880
mbed_official	76:aeb1df146756	881	/!< Peripheral memory map /
mbed_official	76:aeb1df146756	882	#define APB1PERIPH_BASE PERIPH_BASE
mbed_official	76:aeb1df146756	883	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
mbed_official	76:aeb1df146756	884	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
mbed_official	76:aeb1df146756	885
mbed_official	76:aeb1df146756	886	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official	76:aeb1df146756	887	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official	76:aeb1df146756	888	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official	76:aeb1df146756	889	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official	76:aeb1df146756	890	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official	76:aeb1df146756	891	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official	76:aeb1df146756	892	#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
mbed_official	76:aeb1df146756	893	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official	76:aeb1df146756	894	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official	76:aeb1df146756	895	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official	76:aeb1df146756	896	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official	76:aeb1df146756	897	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official	76:aeb1df146756	898	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official	76:aeb1df146756	899	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official	76:aeb1df146756	900	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official	76:aeb1df146756	901	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official	76:aeb1df146756	902	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official	76:aeb1df146756	903	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official	76:aeb1df146756	904	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official	76:aeb1df146756	905	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official	76:aeb1df146756	906	#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
mbed_official	76:aeb1df146756	907	#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
mbed_official	76:aeb1df146756	908	#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
mbed_official	76:aeb1df146756	909
mbed_official	76:aeb1df146756	910	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official	76:aeb1df146756	911	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official	76:aeb1df146756	912	#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
mbed_official	76:aeb1df146756	913	#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
mbed_official	76:aeb1df146756	914	#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official	76:aeb1df146756	915	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
mbed_official	76:aeb1df146756	916	#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
mbed_official	76:aeb1df146756	917	#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official	76:aeb1df146756	918	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official	76:aeb1df146756	919	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official	76:aeb1df146756	920
mbed_official	76:aeb1df146756	921	#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
mbed_official	76:aeb1df146756	922	#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
mbed_official	76:aeb1df146756	923	#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
mbed_official	76:aeb1df146756	924	#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
mbed_official	76:aeb1df146756	925	#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
mbed_official	76:aeb1df146756	926	#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
mbed_official	76:aeb1df146756	927	#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
mbed_official	76:aeb1df146756	928	#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
mbed_official	76:aeb1df146756	929	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
mbed_official	76:aeb1df146756	930	#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
mbed_official	76:aeb1df146756	931
mbed_official	76:aeb1df146756	932
mbed_official	76:aeb1df146756	933	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /!< FLASH registers base address /
mbed_official	76:aeb1df146756	934	#define OB_BASE ((uint32_t)0x1FF80000) /!< FLASH Option Bytes base address /
mbed_official	76:aeb1df146756	935
mbed_official	76:aeb1df146756	936	#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
mbed_official	76:aeb1df146756	937	#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
mbed_official	76:aeb1df146756	938	#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
mbed_official	76:aeb1df146756	939	#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
mbed_official	76:aeb1df146756	940	#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
mbed_official	76:aeb1df146756	941	#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
mbed_official	76:aeb1df146756	942	#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
mbed_official	76:aeb1df146756	943	#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
mbed_official	76:aeb1df146756	944
mbed_official	76:aeb1df146756	945	#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)
mbed_official	76:aeb1df146756	946	#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
mbed_official	76:aeb1df146756	947	#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
mbed_official	76:aeb1df146756	948	#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
mbed_official	76:aeb1df146756	949	#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
mbed_official	76:aeb1df146756	950	#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
mbed_official	76:aeb1df146756	951
mbed_official	76:aeb1df146756	952	#define AES_BASE ((uint32_t)0x50060000)
mbed_official	76:aeb1df146756	953
mbed_official	76:aeb1df146756	954	#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /!< FSMC Bank1 registers base address /
mbed_official	76:aeb1df146756	955	#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /!< FSMC Bank1E registers base address /
mbed_official	76:aeb1df146756	956
mbed_official	76:aeb1df146756	957	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
mbed_official	76:aeb1df146756	958
mbed_official	76:aeb1df146756	959	/**
mbed_official	76:aeb1df146756	960	* @}
mbed_official	76:aeb1df146756	961	*/
mbed_official	76:aeb1df146756	962
mbed_official	76:aeb1df146756	963	/** @addtogroup Peripheral_declaration
mbed_official	76:aeb1df146756	964	* @{
mbed_official	76:aeb1df146756	965	*/
mbed_official	76:aeb1df146756	966
mbed_official	76:aeb1df146756	967	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official	76:aeb1df146756	968	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official	76:aeb1df146756	969	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official	76:aeb1df146756	970	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official	76:aeb1df146756	971	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official	76:aeb1df146756	972	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official	76:aeb1df146756	973	#define LCD ((LCD_TypeDef *) LCD_BASE)
mbed_official	76:aeb1df146756	974	#define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official	76:aeb1df146756	975	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official	76:aeb1df146756	976	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official	76:aeb1df146756	977	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official	76:aeb1df146756	978	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official	76:aeb1df146756	979	#define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official	76:aeb1df146756	980	#define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official	76:aeb1df146756	981	#define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official	76:aeb1df146756	982	#define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official	76:aeb1df146756	983	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official	76:aeb1df146756	984	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official	76:aeb1df146756	985	#define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official	76:aeb1df146756	986	#define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official	76:aeb1df146756	987	#define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official	76:aeb1df146756	988	#define RI ((RI_TypeDef *) RI_BASE)
mbed_official	76:aeb1df146756	989	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official	76:aeb1df146756	990	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official	76:aeb1df146756	991	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official	76:aeb1df146756	992
mbed_official	76:aeb1df146756	993	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official	76:aeb1df146756	994	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official	76:aeb1df146756	995	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official	76:aeb1df146756	996	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official	76:aeb1df146756	997	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official	76:aeb1df146756	998	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official	76:aeb1df146756	999	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official	76:aeb1df146756	1000	#define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official	76:aeb1df146756	1001	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official	76:aeb1df146756	1002	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official	76:aeb1df146756	1003	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official	76:aeb1df146756	1004	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official	76:aeb1df146756	1005	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official	76:aeb1df146756	1006	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official	76:aeb1df146756	1007	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official	76:aeb1df146756	1008	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official	76:aeb1df146756	1009
mbed_official	76:aeb1df146756	1010	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official	76:aeb1df146756	1011	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official	76:aeb1df146756	1012	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official	76:aeb1df146756	1013	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official	76:aeb1df146756	1014	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official	76:aeb1df146756	1015	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official	76:aeb1df146756	1016
mbed_official	76:aeb1df146756	1017	#define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official	76:aeb1df146756	1018	#define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official	76:aeb1df146756	1019
mbed_official	76:aeb1df146756	1020	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official	76:aeb1df146756	1021	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official	76:aeb1df146756	1022	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official	76:aeb1df146756	1023	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official	76:aeb1df146756	1024	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official	76:aeb1df146756	1025	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official	76:aeb1df146756	1026	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official	76:aeb1df146756	1027	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official	76:aeb1df146756	1028
mbed_official	76:aeb1df146756	1029	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official	76:aeb1df146756	1030	#define OB ((OB_TypeDef *) OB_BASE)
mbed_official	76:aeb1df146756	1031
mbed_official	76:aeb1df146756	1032	#define AES ((AES_TypeDef *) AES_BASE)
mbed_official	76:aeb1df146756	1033
mbed_official	76:aeb1df146756	1034	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
mbed_official	76:aeb1df146756	1035	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
mbed_official	76:aeb1df146756	1036
mbed_official	76:aeb1df146756	1037	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official	76:aeb1df146756	1038
mbed_official	76:aeb1df146756	1039	/**
mbed_official	76:aeb1df146756	1040	* @}
mbed_official	76:aeb1df146756	1041	*/
mbed_official	76:aeb1df146756	1042
mbed_official	76:aeb1df146756	1043	/** @addtogroup Exported_constants
mbed_official	76:aeb1df146756	1044	* @{
mbed_official	76:aeb1df146756	1045	*/
mbed_official	76:aeb1df146756	1046
mbed_official	76:aeb1df146756	1047	/** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official	76:aeb1df146756	1048	* @{
mbed_official	76:aeb1df146756	1049	*/
mbed_official	76:aeb1df146756	1050
mbed_official	76:aeb1df146756	1051	/******************************************************************************/
mbed_official	76:aeb1df146756	1052	/* Peripheral Registers Bits Definition */
mbed_official	76:aeb1df146756	1053	/******************************************************************************/
mbed_official	76:aeb1df146756	1054	/******************************************************************************/
mbed_official	76:aeb1df146756	1055	/* */
mbed_official	76:aeb1df146756	1056	/* Analog to Digital Converter (ADC) */
mbed_official	76:aeb1df146756	1057	/* */
mbed_official	76:aeb1df146756	1058	/******************************************************************************/
mbed_official	76:aeb1df146756	1059
mbed_official	76:aeb1df146756	1060	/****************** Bit definition for ADC_SR register ******************/
mbed_official	76:aeb1df146756	1061	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
mbed_official	76:aeb1df146756	1062	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
mbed_official	76:aeb1df146756	1063	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
mbed_official	76:aeb1df146756	1064	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
mbed_official	76:aeb1df146756	1065	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
mbed_official	76:aeb1df146756	1066	#define ADC_SR_OVR ((uint32_t)0x00000020) /!< Overrun flag /
mbed_official	76:aeb1df146756	1067	#define ADC_SR_ADONS ((uint32_t)0x00000040) /!< ADC ON status /
mbed_official	76:aeb1df146756	1068	#define ADC_SR_RCNR ((uint32_t)0x00000100) /!< Regular channel not ready flag /
mbed_official	76:aeb1df146756	1069	#define ADC_SR_JCNR ((uint32_t)0x00000200) /!< Injected channel not ready flag /
mbed_official	76:aeb1df146756	1070
mbed_official	76:aeb1df146756	1071	/***************** Bit definition for ADC_CR1 register ******************/
mbed_official	76:aeb1df146756	1072	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
mbed_official	76:aeb1df146756	1073	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1074	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1075	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1076	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1077	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1078
mbed_official	76:aeb1df146756	1079	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
mbed_official	76:aeb1df146756	1080	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
mbed_official	76:aeb1df146756	1081	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
mbed_official	76:aeb1df146756	1082	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
mbed_official	76:aeb1df146756	1083	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
mbed_official	76:aeb1df146756	1084	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
mbed_official	76:aeb1df146756	1085	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
mbed_official	76:aeb1df146756	1086	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
mbed_official	76:aeb1df146756	1087
mbed_official	76:aeb1df146756	1088	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
mbed_official	76:aeb1df146756	1089	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1090	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1091	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1092
mbed_official	76:aeb1df146756	1093	#define ADC_CR1_PDD ((uint32_t)0x00010000) /!< Power Down during Delay phase /
mbed_official	76:aeb1df146756	1094	#define ADC_CR1_PDI ((uint32_t)0x00020000) /!< Power Down during Idle phase /
mbed_official	76:aeb1df146756	1095
mbed_official	76:aeb1df146756	1096	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
mbed_official	76:aeb1df146756	1097	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
mbed_official	76:aeb1df146756	1098
mbed_official	76:aeb1df146756	1099	#define ADC_CR1_RES ((uint32_t)0x03000000) /!< RES[1:0] bits (Resolution) /
mbed_official	76:aeb1df146756	1100	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1101	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1102
mbed_official	76:aeb1df146756	1103	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!< Overrun interrupt enable /
mbed_official	76:aeb1df146756	1104
mbed_official	76:aeb1df146756	1105	/***************** Bit definition for ADC_CR2 register ******************/
mbed_official	76:aeb1df146756	1106	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
mbed_official	76:aeb1df146756	1107	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
mbed_official	76:aeb1df146756	1108	#define ADC_CR2_CFG ((uint32_t)0x00000004) /!< ADC Configuration /
mbed_official	76:aeb1df146756	1109
mbed_official	76:aeb1df146756	1110	#define ADC_CR2_DELS ((uint32_t)0x00000070) /!< DELS[2:0] bits (Delay selection) /
mbed_official	76:aeb1df146756	1111	#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	1112	#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	1113	#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	1114
mbed_official	76:aeb1df146756	1115	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
mbed_official	76:aeb1df146756	1116	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!< DMA disable selection (Single ADC) /
mbed_official	76:aeb1df146756	1117	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!< End of conversion selection /
mbed_official	76:aeb1df146756	1118	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
mbed_official	76:aeb1df146756	1119
mbed_official	76:aeb1df146756	1120	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!< JEXTSEL[3:0] bits (External event select for injected group) /
mbed_official	76:aeb1df146756	1121	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1122	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1123	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1124	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1125
mbed_official	76:aeb1df146756	1126	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) /
mbed_official	76:aeb1df146756	1127	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1128	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1129
mbed_official	76:aeb1df146756	1130	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!< Start Conversion of injected channels /
mbed_official	76:aeb1df146756	1131
mbed_official	76:aeb1df146756	1132	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!< EXTSEL[3:0] bits (External Event Select for regular group) /
mbed_official	76:aeb1df146756	1133	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1134	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1135	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1136	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1137
mbed_official	76:aeb1df146756	1138	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
mbed_official	76:aeb1df146756	1139	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1140	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1141
mbed_official	76:aeb1df146756	1142	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!< Start Conversion of regular channels /
mbed_official	76:aeb1df146756	1143
mbed_official	76:aeb1df146756	1144	/**************** Bit definition for ADC_SMPR1 register *****************/
mbed_official	76:aeb1df146756	1145	#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /!< SMP20[2:0] bits (Channel 20 Sample time selection) /
mbed_official	76:aeb1df146756	1146	#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1147	#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1148	#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1149
mbed_official	76:aeb1df146756	1150	#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /!< SMP21[2:0] bits (Channel 21 Sample time selection) /
mbed_official	76:aeb1df146756	1151	#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	76:aeb1df146756	1152	#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	76:aeb1df146756	1153	#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	76:aeb1df146756	1154
mbed_official	76:aeb1df146756	1155	#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /!< SMP22[2:0] bits (Channel 22 Sample time selection) /
mbed_official	76:aeb1df146756	1156	#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	76:aeb1df146756	1157	#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	76:aeb1df146756	1158	#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	76:aeb1df146756	1159
mbed_official	76:aeb1df146756	1160	#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /!< SMP23[2:0] bits (Channel 23 Sample time selection) /
mbed_official	76:aeb1df146756	1161	#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	76:aeb1df146756	1162	#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	76:aeb1df146756	1163	#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /!< Bit 2 /
mbed_official	76:aeb1df146756	1164
mbed_official	76:aeb1df146756	1165	#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /!< SMP24[2:0] bits (Channel 24 Sample time selection) /
mbed_official	76:aeb1df146756	1166	#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1167	#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1168	#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1169
mbed_official	76:aeb1df146756	1170	#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /!< SMP25[2:0] bits (Channel 25 Sample time selection) /
mbed_official	76:aeb1df146756	1171	#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1172	#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1173	#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1174
mbed_official	76:aeb1df146756	1175	#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /!< SMP26[2:0] bits (Channel 26 Sample time selection) /
mbed_official	76:aeb1df146756	1176	#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1177	#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1178	#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1179
mbed_official	76:aeb1df146756	1180	#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /!< SMP27[2:0] bits (Channel 27 Sample time selection) /
mbed_official	76:aeb1df146756	1181	#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1182	#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1183	#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1184
mbed_official	76:aeb1df146756	1185	#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /!< SMP28[2:0] bits (Channel 28 Sample time selection) /
mbed_official	76:aeb1df146756	1186	#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1187	#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1188	#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1189
mbed_official	76:aeb1df146756	1190	#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /!< SMP29[2:0] bits (Channel 29 Sample time selection) /
mbed_official	76:aeb1df146756	1191	#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1192	#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1193	#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1194
mbed_official	76:aeb1df146756	1195	/**************** Bit definition for ADC_SMPR2 register *****************/
mbed_official	76:aeb1df146756	1196	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
mbed_official	76:aeb1df146756	1197	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1198	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1199	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1200
mbed_official	76:aeb1df146756	1201	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
mbed_official	76:aeb1df146756	1202	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	76:aeb1df146756	1203	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	76:aeb1df146756	1204	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	76:aeb1df146756	1205
mbed_official	76:aeb1df146756	1206	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
mbed_official	76:aeb1df146756	1207	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	76:aeb1df146756	1208	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	76:aeb1df146756	1209	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	76:aeb1df146756	1210
mbed_official	76:aeb1df146756	1211	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
mbed_official	76:aeb1df146756	1212	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	76:aeb1df146756	1213	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	76:aeb1df146756	1214	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
mbed_official	76:aeb1df146756	1215
mbed_official	76:aeb1df146756	1216	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
mbed_official	76:aeb1df146756	1217	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1218	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1219	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1220
mbed_official	76:aeb1df146756	1221	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 5 Sample time selection) /
mbed_official	76:aeb1df146756	1222	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1223	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1224	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1225
mbed_official	76:aeb1df146756	1226	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
mbed_official	76:aeb1df146756	1227	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1228	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1229	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1230
mbed_official	76:aeb1df146756	1231	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
mbed_official	76:aeb1df146756	1232	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1233	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1234	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1235
mbed_official	76:aeb1df146756	1236	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< SMP18[2:0] bits (Channel 18 Sample time selection) /
mbed_official	76:aeb1df146756	1237	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1238	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1239	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1240
mbed_official	76:aeb1df146756	1241	#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /!< SMP19[2:0] bits (Channel 19 Sample time selection) /
mbed_official	76:aeb1df146756	1242	#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1243	#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1244	#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1245
mbed_official	76:aeb1df146756	1246	/**************** Bit definition for ADC_SMPR3 register *****************/
mbed_official	76:aeb1df146756	1247	#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
mbed_official	76:aeb1df146756	1248	#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1249	#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1250	#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1251
mbed_official	76:aeb1df146756	1252	#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
mbed_official	76:aeb1df146756	1253	#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	76:aeb1df146756	1254	#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	76:aeb1df146756	1255	#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	76:aeb1df146756	1256
mbed_official	76:aeb1df146756	1257	#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
mbed_official	76:aeb1df146756	1258	#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	76:aeb1df146756	1259	#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	76:aeb1df146756	1260	#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	76:aeb1df146756	1261
mbed_official	76:aeb1df146756	1262	#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
mbed_official	76:aeb1df146756	1263	#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	76:aeb1df146756	1264	#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	76:aeb1df146756	1265	#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
mbed_official	76:aeb1df146756	1266
mbed_official	76:aeb1df146756	1267	#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
mbed_official	76:aeb1df146756	1268	#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1269	#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1270	#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1271
mbed_official	76:aeb1df146756	1272	#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
mbed_official	76:aeb1df146756	1273	#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1274	#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1275	#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1276
mbed_official	76:aeb1df146756	1277	#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
mbed_official	76:aeb1df146756	1278	#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1279	#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1280	#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1281
mbed_official	76:aeb1df146756	1282	#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
mbed_official	76:aeb1df146756	1283	#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1284	#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1285	#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1286
mbed_official	76:aeb1df146756	1287	#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
mbed_official	76:aeb1df146756	1288	#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1289	#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1290	#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1291
mbed_official	76:aeb1df146756	1292	#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
mbed_official	76:aeb1df146756	1293	#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1294	#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1295	#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1296
mbed_official	76:aeb1df146756	1297	/**************** Bit definition for ADC_JOFR1 register *****************/
mbed_official	76:aeb1df146756	1298	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
mbed_official	76:aeb1df146756	1299
mbed_official	76:aeb1df146756	1300	/**************** Bit definition for ADC_JOFR2 register *****************/
mbed_official	76:aeb1df146756	1301	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
mbed_official	76:aeb1df146756	1302
mbed_official	76:aeb1df146756	1303	/**************** Bit definition for ADC_JOFR3 register *****************/
mbed_official	76:aeb1df146756	1304	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
mbed_official	76:aeb1df146756	1305
mbed_official	76:aeb1df146756	1306	/**************** Bit definition for ADC_JOFR4 register *****************/
mbed_official	76:aeb1df146756	1307	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
mbed_official	76:aeb1df146756	1308
mbed_official	76:aeb1df146756	1309	/***************** Bit definition for ADC_HTR register ******************/
mbed_official	76:aeb1df146756	1310	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
mbed_official	76:aeb1df146756	1311
mbed_official	76:aeb1df146756	1312	/***************** Bit definition for ADC_LTR register ******************/
mbed_official	76:aeb1df146756	1313	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
mbed_official	76:aeb1df146756	1314
mbed_official	76:aeb1df146756	1315	/***************** Bit definition for ADC_SQR1 register *****************/
mbed_official	76:aeb1df146756	1316	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
mbed_official	76:aeb1df146756	1317	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1318	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1319	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1320	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1321
mbed_official	76:aeb1df146756	1322	#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /!< SQ28[4:0] bits (25th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1323	#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1324	#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1325	#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1326	#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1327	#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1328
mbed_official	76:aeb1df146756	1329	#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /!< SQ27[4:0] bits (27th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1330	#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1331	#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1332	#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1333	#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1334	#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1335
mbed_official	76:aeb1df146756	1336	#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /!< SQ26[4:0] bits (26th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1337	#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1338	#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1339	#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1340	#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1341	#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1342
mbed_official	76:aeb1df146756	1343	#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /!< SQ25[4:0] bits (25th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1344	#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1345	#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1346	#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1347	#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1348	#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1349
mbed_official	76:aeb1df146756	1350	/***************** Bit definition for ADC_SQR2 register *****************/
mbed_official	76:aeb1df146756	1351	#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /!< SQ19[4:0] bits (19th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1352	#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1353	#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1354	#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1355	#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1356	#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1357
mbed_official	76:aeb1df146756	1358	#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /!< SQ20[4:0] bits (20th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1359	#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1360	#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1361	#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1362	#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1363	#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1364
mbed_official	76:aeb1df146756	1365	#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /!< SQ21[4:0] bits (21th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1366	#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1367	#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1368	#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1369	#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1370	#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1371
mbed_official	76:aeb1df146756	1372	#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /!< SQ22[4:0] bits (22th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1373	#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1374	#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1375	#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1376	#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1377	#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1378
mbed_official	76:aeb1df146756	1379	#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /!< SQ23[4:0] bits (23th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1380	#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1381	#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1382	#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1383	#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1384	#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1385
mbed_official	76:aeb1df146756	1386	#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /!< SQ24[4:0] bits (24th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1387	#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1388	#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1389	#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1390	#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1391	#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1392
mbed_official	76:aeb1df146756	1393	/***************** Bit definition for ADC_SQR3 register *****************/
mbed_official	76:aeb1df146756	1394	#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1395	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1396	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1397	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1398	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1399	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1400
mbed_official	76:aeb1df146756	1401	#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1402	#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1403	#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1404	#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1405	#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1406	#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1407
mbed_official	76:aeb1df146756	1408	#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1409	#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1410	#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1411	#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1412	#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1413	#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1414
mbed_official	76:aeb1df146756	1415	#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1416	#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1417	#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1418	#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1419	#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1420	#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1421
mbed_official	76:aeb1df146756	1422	#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /!< SQ17[4:0] bits (17th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1423	#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1424	#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1425	#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1426	#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1427	#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1428
mbed_official	76:aeb1df146756	1429	#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /!< SQ18[4:0] bits (18th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1430	#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1431	#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1432	#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1433	#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1434	#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1435
mbed_official	76:aeb1df146756	1436	/***************** Bit definition for ADC_SQR4 register *****************/
mbed_official	76:aeb1df146756	1437	#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1438	#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1439	#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1440	#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1441	#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1442	#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1443
mbed_official	76:aeb1df146756	1444	#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1445	#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1446	#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1447	#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1448	#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1449	#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1450
mbed_official	76:aeb1df146756	1451	#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1452	#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1453	#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1454	#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1455	#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1456	#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1457
mbed_official	76:aeb1df146756	1458	#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1459	#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1460	#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1461	#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1462	#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1463	#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1464
mbed_official	76:aeb1df146756	1465	#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1466	#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1467	#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1468	#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1469	#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1470	#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1471
mbed_official	76:aeb1df146756	1472	#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1473	#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1474	#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1475	#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1476	#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1477	#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1478
mbed_official	76:aeb1df146756	1479	/***************** Bit definition for ADC_SQR5 register *****************/
mbed_official	76:aeb1df146756	1480	#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
mbed_official	76:aeb1df146756	1481	#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1482	#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1483	#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1484	#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1485	#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1486
mbed_official	76:aeb1df146756	1487	#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
mbed_official	76:aeb1df146756	1488	#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1489	#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1490	#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1491	#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1492	#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1493
mbed_official	76:aeb1df146756	1494	#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
mbed_official	76:aeb1df146756	1495	#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1496	#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1497	#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1498	#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1499	#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1500
mbed_official	76:aeb1df146756	1501	#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1502	#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1503	#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1504	#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1505	#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1506	#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1507
mbed_official	76:aeb1df146756	1508	#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1509	#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1510	#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1511	#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1512	#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1513	#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1514
mbed_official	76:aeb1df146756	1515	#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
mbed_official	76:aeb1df146756	1516	#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1517	#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1518	#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1519	#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1520	#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1521
mbed_official	76:aeb1df146756	1522
mbed_official	76:aeb1df146756	1523	/***************** Bit definition for ADC_JSQR register *****************/
mbed_official	76:aeb1df146756	1524	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
mbed_official	76:aeb1df146756	1525	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1526	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1527	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1528	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	1529	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	1530
mbed_official	76:aeb1df146756	1531	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
mbed_official	76:aeb1df146756	1532	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1533	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1534	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	76:aeb1df146756	1535	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
mbed_official	76:aeb1df146756	1536	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
mbed_official	76:aeb1df146756	1537
mbed_official	76:aeb1df146756	1538	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
mbed_official	76:aeb1df146756	1539	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1540	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1541	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1542	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1543	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1544
mbed_official	76:aeb1df146756	1545	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
mbed_official	76:aeb1df146756	1546	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1547	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1548	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1549	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1550	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1551
mbed_official	76:aeb1df146756	1552	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
mbed_official	76:aeb1df146756	1553	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1554	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1555
mbed_official	76:aeb1df146756	1556	/***************** Bit definition for ADC_JDR1 register *****************/
mbed_official	76:aeb1df146756	1557	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
mbed_official	76:aeb1df146756	1558
mbed_official	76:aeb1df146756	1559	/***************** Bit definition for ADC_JDR2 register *****************/
mbed_official	76:aeb1df146756	1560	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
mbed_official	76:aeb1df146756	1561
mbed_official	76:aeb1df146756	1562	/***************** Bit definition for ADC_JDR3 register *****************/
mbed_official	76:aeb1df146756	1563	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
mbed_official	76:aeb1df146756	1564
mbed_official	76:aeb1df146756	1565	/***************** Bit definition for ADC_JDR4 register *****************/
mbed_official	76:aeb1df146756	1566	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
mbed_official	76:aeb1df146756	1567
mbed_official	76:aeb1df146756	1568	/****************** Bit definition for ADC_DR register ******************/
mbed_official	76:aeb1df146756	1569	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
mbed_official	76:aeb1df146756	1570
mbed_official	76:aeb1df146756	1571	/**************** Bit definition for ADC_SMPR0 register *****************/
mbed_official	76:aeb1df146756	1572	#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /!< SMP30[2:0] bits (Channel 30 Sample time selection) /
mbed_official	76:aeb1df146756	1573	#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	1574	#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	1575	#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	1576
mbed_official	76:aeb1df146756	1577	#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /!< SMP31[2:0] bits (Channel 31 Sample time selection) /
mbed_official	76:aeb1df146756	1578	#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	76:aeb1df146756	1579	#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	76:aeb1df146756	1580	#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	76:aeb1df146756	1581
mbed_official	76:aeb1df146756	1582	/***************** Bit definition for ADC_CSR register ******************/
mbed_official	76:aeb1df146756	1583	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!< ADC1 Analog watchdog flag /
mbed_official	76:aeb1df146756	1584	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!< ADC1 End of conversion /
mbed_official	76:aeb1df146756	1585	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!< ADC1 Injected channel end of conversion /
mbed_official	76:aeb1df146756	1586	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!< ADC1 Injected channel Start flag /
mbed_official	76:aeb1df146756	1587	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!< ADC1 Regular channel Start flag /
mbed_official	76:aeb1df146756	1588	#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /!< ADC1 overrun flag /
mbed_official	76:aeb1df146756	1589	#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /!< ADON status of ADC1 /
mbed_official	76:aeb1df146756	1590
mbed_official	76:aeb1df146756	1591	/***************** Bit definition for ADC_CCR register ******************/
mbed_official	76:aeb1df146756	1592	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!< ADC prescaler/
mbed_official	76:aeb1df146756	1593	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1594	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1595	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
mbed_official	76:aeb1df146756	1596
mbed_official	76:aeb1df146756	1597	/******************************************************************************/
mbed_official	76:aeb1df146756	1598	/* */
mbed_official	76:aeb1df146756	1599	/* Advanced Encryption Standard (AES) */
mbed_official	76:aeb1df146756	1600	/* */
mbed_official	76:aeb1df146756	1601	/******************************************************************************/
mbed_official	76:aeb1df146756	1602	/***************** Bit definition for AES_CR register *******************/
mbed_official	76:aeb1df146756	1603	#define AES_CR_EN ((uint32_t)0x00000001) /!< AES Enable /
mbed_official	76:aeb1df146756	1604	#define AES_CR_DATATYPE ((uint32_t)0x00000006) /!< Data type selection /
mbed_official	76:aeb1df146756	1605	#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /!< Bit 0 /
mbed_official	76:aeb1df146756	1606	#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /!< Bit 1 /
mbed_official	76:aeb1df146756	1607
mbed_official	76:aeb1df146756	1608	#define AES_CR_MODE ((uint32_t)0x00000018) /!< AES Mode Of Operation /
mbed_official	76:aeb1df146756	1609	#define AES_CR_MODE_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	76:aeb1df146756	1610	#define AES_CR_MODE_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	76:aeb1df146756	1611
mbed_official	76:aeb1df146756	1612	#define AES_CR_CHMOD ((uint32_t)0x00000060) /!< AES Chaining Mode /
mbed_official	76:aeb1df146756	1613	#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	76:aeb1df146756	1614	#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	76:aeb1df146756	1615
mbed_official	76:aeb1df146756	1616	#define AES_CR_CCFC ((uint32_t)0x00000080) /!< Computation Complete Flag Clear /
mbed_official	76:aeb1df146756	1617	#define AES_CR_ERRC ((uint32_t)0x00000100) /!< Error Clear /
mbed_official	76:aeb1df146756	1618	#define AES_CR_CCIE ((uint32_t)0x00000200) /!< Computation Complete Interrupt Enable /
mbed_official	76:aeb1df146756	1619	#define AES_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
mbed_official	76:aeb1df146756	1620	#define AES_CR_DMAINEN ((uint32_t)0x00000800) /!< DMA ENable managing the data input phase /
mbed_official	76:aeb1df146756	1621	#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /!< DMA Enable managing the data output phase /
mbed_official	76:aeb1df146756	1622
mbed_official	76:aeb1df146756	1623	/***************** Bit definition for AES_SR register *******************/
mbed_official	76:aeb1df146756	1624	#define AES_SR_CCF ((uint32_t)0x00000001) /!< Computation Complete Flag /
mbed_official	76:aeb1df146756	1625	#define AES_SR_RDERR ((uint32_t)0x00000002) /!< Read Error Flag /
mbed_official	76:aeb1df146756	1626	#define AES_SR_WRERR ((uint32_t)0x00000004) /!< Write Error Flag /
mbed_official	76:aeb1df146756	1627
mbed_official	76:aeb1df146756	1628	/***************** Bit definition for AES_DINR register *****************/
mbed_official	76:aeb1df146756	1629	#define AES_DINR ((uint32_t)0x0000FFFF) /!< AES Data Input Register /
mbed_official	76:aeb1df146756	1630
mbed_official	76:aeb1df146756	1631	/***************** Bit definition for AES_DOUTR register ****************/
mbed_official	76:aeb1df146756	1632	#define AES_DOUTR ((uint32_t)0x0000FFFF) /!< AES Data Output Register /
mbed_official	76:aeb1df146756	1633
mbed_official	76:aeb1df146756	1634	/***************** Bit definition for AES_KEYR0 register ****************/
mbed_official	76:aeb1df146756	1635	#define AES_KEYR0 ((uint32_t)0x0000FFFF) /!< AES Key Register 0 /
mbed_official	76:aeb1df146756	1636
mbed_official	76:aeb1df146756	1637	/***************** Bit definition for AES_KEYR1 register ****************/
mbed_official	76:aeb1df146756	1638	#define AES_KEYR1 ((uint32_t)0x0000FFFF) /!< AES Key Register 1 /
mbed_official	76:aeb1df146756	1639
mbed_official	76:aeb1df146756	1640	/***************** Bit definition for AES_KEYR2 register ****************/
mbed_official	76:aeb1df146756	1641	#define AES_KEYR2 ((uint32_t)0x0000FFFF) /!< AES Key Register 2 /
mbed_official	76:aeb1df146756	1642
mbed_official	76:aeb1df146756	1643	/***************** Bit definition for AES_KEYR3 register ****************/
mbed_official	76:aeb1df146756	1644	#define AES_KEYR3 ((uint32_t)0x0000FFFF) /!< AES Key Register 3 /
mbed_official	76:aeb1df146756	1645
mbed_official	76:aeb1df146756	1646	/***************** Bit definition for AES_IVR0 register *****************/
mbed_official	76:aeb1df146756	1647	#define AES_IVR0 ((uint32_t)0x0000FFFF) /!< AES Initialization Vector Register 0 /
mbed_official	76:aeb1df146756	1648
mbed_official	76:aeb1df146756	1649	/***************** Bit definition for AES_IVR1 register *****************/
mbed_official	76:aeb1df146756	1650	#define AES_IVR1 ((uint32_t)0x0000FFFF) /!< AES Initialization Vector Register 1 /
mbed_official	76:aeb1df146756	1651
mbed_official	76:aeb1df146756	1652	/***************** Bit definition for AES_IVR2 register *****************/
mbed_official	76:aeb1df146756	1653	#define AES_IVR2 ((uint32_t)0x0000FFFF) /!< AES Initialization Vector Register 2 /
mbed_official	76:aeb1df146756	1654
mbed_official	76:aeb1df146756	1655	/***************** Bit definition for AES_IVR3 register *****************/
mbed_official	76:aeb1df146756	1656	#define AES_IVR3 ((uint32_t)0x0000FFFF) /!< AES Initialization Vector Register 3 /
mbed_official	76:aeb1df146756	1657
mbed_official	76:aeb1df146756	1658	/******************************************************************************/
mbed_official	76:aeb1df146756	1659	/* */
mbed_official	76:aeb1df146756	1660	/* Analog Comparators (COMP) */
mbed_official	76:aeb1df146756	1661	/* */
mbed_official	76:aeb1df146756	1662	/******************************************************************************/
mbed_official	76:aeb1df146756	1663
mbed_official	76:aeb1df146756	1664	/**************** Bit definition for COMP_CSR register ******************/
mbed_official	76:aeb1df146756	1665	#define COMP_CSR_10KPU ((uint32_t)0x00000001) /!< 10K pull-up resistor /
mbed_official	76:aeb1df146756	1666	#define COMP_CSR_400KPU ((uint32_t)0x00000002) /!< 400K pull-up resistor /
mbed_official	76:aeb1df146756	1667	#define COMP_CSR_10KPD ((uint32_t)0x00000004) /!< 10K pull-down resistor /
mbed_official	76:aeb1df146756	1668	#define COMP_CSR_400KPD ((uint32_t)0x00000008) /!< 400K pull-down resistor /
mbed_official	76:aeb1df146756	1669
mbed_official	76:aeb1df146756	1670	#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /!< Comparator 1 enable /
mbed_official	76:aeb1df146756	1671	#define COMP_CSR_SW1 ((uint32_t)0x00000020) /!< SW1 analog switch enable /
mbed_official	76:aeb1df146756	1672	#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /!< Comparator 1 output /
mbed_official	76:aeb1df146756	1673
mbed_official	76:aeb1df146756	1674	#define COMP_CSR_SPEED ((uint32_t)0x00001000) /!< Comparator 2 speed /
mbed_official	76:aeb1df146756	1675	#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /!< Comparator 2 ouput /
mbed_official	76:aeb1df146756	1676
mbed_official	76:aeb1df146756	1677	#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /!< Comparator Vref Enable /
mbed_official	76:aeb1df146756	1678	#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /!< Window mode enable /
mbed_official	76:aeb1df146756	1679
mbed_official	76:aeb1df146756	1680	#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /!< INSEL[2:0] Inversion input Selection /
mbed_official	76:aeb1df146756	1681	#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1682	#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1683	#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1684
mbed_official	76:aeb1df146756	1685	#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /!< OUTSEL[2:0] comparator 2 output redirection /
mbed_official	76:aeb1df146756	1686	#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1687	#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1688	#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1689
mbed_official	76:aeb1df146756	1690	#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /!< Bit 26 /
mbed_official	76:aeb1df146756	1691	#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /!< Bit 27 /
mbed_official	76:aeb1df146756	1692	#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /!< Bit 28 /
mbed_official	76:aeb1df146756	1693
mbed_official	76:aeb1df146756	1694	#define COMP_CSR_CAIE ((uint32_t)0x20000000) /!< Bit 29 /
mbed_official	76:aeb1df146756	1695	#define COMP_CSR_CAIF ((uint32_t)0x40000000) /!< Bit 30 /
mbed_official	76:aeb1df146756	1696	#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /!< Bit 31 /
mbed_official	76:aeb1df146756	1697
mbed_official	76:aeb1df146756	1698	/******************************************************************************/
mbed_official	76:aeb1df146756	1699	/* */
mbed_official	76:aeb1df146756	1700	/* Operational Amplifier (OPAMP) */
mbed_official	76:aeb1df146756	1701	/* */
mbed_official	76:aeb1df146756	1702	/******************************************************************************/
mbed_official	76:aeb1df146756	1703	/***************** Bit definition for OPAMP_CSR register ****************/
mbed_official	76:aeb1df146756	1704	#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /!< OPAMP1 disable /
mbed_official	76:aeb1df146756	1705	#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /!< Switch 3 for OPAMP1 Enable /
mbed_official	76:aeb1df146756	1706	#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /!< Switch 4 for OPAMP1 Enable /
mbed_official	76:aeb1df146756	1707	#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /!< Switch 5 for OPAMP1 Enable /
mbed_official	76:aeb1df146756	1708	#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /!< Switch 6 for OPAMP1 Enable /
mbed_official	76:aeb1df146756	1709	#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /!< OPAMP1 Offset calibration for P differential pair /
mbed_official	76:aeb1df146756	1710	#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /!< OPAMP1 Offset calibration for N differential pair /
mbed_official	76:aeb1df146756	1711	#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /!< OPAMP1 Low power enable /
mbed_official	76:aeb1df146756	1712	#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /!< OPAMP2 disable /
mbed_official	76:aeb1df146756	1713	#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /!< Switch 3 for OPAMP2 Enable /
mbed_official	76:aeb1df146756	1714	#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /!< Switch 4 for OPAMP2 Enable /
mbed_official	76:aeb1df146756	1715	#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /!< Switch 5 for OPAMP2 Enable /
mbed_official	76:aeb1df146756	1716	#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /!< Switch 6 for OPAMP2 Enable /
mbed_official	76:aeb1df146756	1717	#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /!< OPAMP2 Offset calibration for P differential pair /
mbed_official	76:aeb1df146756	1718	#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /!< OPAMP2 Offset calibration for N differential pair /
mbed_official	76:aeb1df146756	1719	#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /!< OPAMP2 Low power enable /
mbed_official	76:aeb1df146756	1720	#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /!< OPAMP3 disable /
mbed_official	76:aeb1df146756	1721	#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /!< Switch 3 for OPAMP3 Enable /
mbed_official	76:aeb1df146756	1722	#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /!< Switch 4 for OPAMP3 Enable /
mbed_official	76:aeb1df146756	1723	#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /!< Switch 5 for OPAMP3 Enable /
mbed_official	76:aeb1df146756	1724	#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /!< Switch 6 for OPAMP3 Enable /
mbed_official	76:aeb1df146756	1725	#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /!< OPAMP3 Offset calibration for P differential pair /
mbed_official	76:aeb1df146756	1726	#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /!< OPAMP3 Offset calibration for N differential pair /
mbed_official	76:aeb1df146756	1727	#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /!< OPAMP3 Low power enable /
mbed_official	76:aeb1df146756	1728	#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /!< Switch ANA Enable for OPAMP1 /
mbed_official	76:aeb1df146756	1729	#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /!< Switch ANA Enable for OPAMP2 /
mbed_official	76:aeb1df146756	1730	#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /!< Switch ANA Enable for OPAMP3 /
mbed_official	76:aeb1df146756	1731	#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /!< Switch 7 for OPAMP2 Enable /
mbed_official	76:aeb1df146756	1732	#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /!< Power range selection /
mbed_official	76:aeb1df146756	1733	#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /!< OPAMP1 calibration output /
mbed_official	76:aeb1df146756	1734	#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /!< OPAMP2 calibration output /
mbed_official	76:aeb1df146756	1735	#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /!< OPAMP3 calibration output /
mbed_official	76:aeb1df146756	1736
mbed_official	76:aeb1df146756	1737	/***************** Bit definition for OPAMP_OTR register ****************/
mbed_official	76:aeb1df146756	1738	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /!< Offset trim for OPAMP1 /
mbed_official	76:aeb1df146756	1739	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /!< Offset trim for OPAMP2 /
mbed_official	76:aeb1df146756	1740	#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /!< Offset trim for OPAMP2 /
mbed_official	76:aeb1df146756	1741	#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /!< Switch to OPAMP offset user trimmed values /
mbed_official	76:aeb1df146756	1742
mbed_official	76:aeb1df146756	1743	/***************** Bit definition for OPAMP_LPOTR register **************/
mbed_official	76:aeb1df146756	1744	#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /!< Offset trim in low power for OPAMP1 /
mbed_official	76:aeb1df146756	1745	#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /!< Offset trim in low power for OPAMP2 /
mbed_official	76:aeb1df146756	1746	#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /!< Offset trim in low power for OPAMP3 /
mbed_official	76:aeb1df146756	1747
mbed_official	76:aeb1df146756	1748	/******************************************************************************/
mbed_official	76:aeb1df146756	1749	/* */
mbed_official	76:aeb1df146756	1750	/* CRC calculation unit (CRC) */
mbed_official	76:aeb1df146756	1751	/* */
mbed_official	76:aeb1df146756	1752	/******************************************************************************/
mbed_official	76:aeb1df146756	1753
mbed_official	76:aeb1df146756	1754	/***************** Bit definition for CRC_DR register *******************/
mbed_official	76:aeb1df146756	1755	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
mbed_official	76:aeb1df146756	1756
mbed_official	76:aeb1df146756	1757	/***************** Bit definition for CRC_IDR register ******************/
mbed_official	76:aeb1df146756	1758	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
mbed_official	76:aeb1df146756	1759
mbed_official	76:aeb1df146756	1760	/****************** Bit definition for CRC_CR register ******************/
mbed_official	76:aeb1df146756	1761	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
mbed_official	76:aeb1df146756	1762
mbed_official	76:aeb1df146756	1763	/******************************************************************************/
mbed_official	76:aeb1df146756	1764	/* */
mbed_official	76:aeb1df146756	1765	/* Digital to Analog Converter (DAC) */
mbed_official	76:aeb1df146756	1766	/* */
mbed_official	76:aeb1df146756	1767	/******************************************************************************/
mbed_official	76:aeb1df146756	1768
mbed_official	76:aeb1df146756	1769	/****************** Bit definition for DAC_CR register ******************/
mbed_official	76:aeb1df146756	1770	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
mbed_official	76:aeb1df146756	1771	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
mbed_official	76:aeb1df146756	1772	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
mbed_official	76:aeb1df146756	1773
mbed_official	76:aeb1df146756	1774	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
mbed_official	76:aeb1df146756	1775	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
mbed_official	76:aeb1df146756	1776	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
mbed_official	76:aeb1df146756	1777	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
mbed_official	76:aeb1df146756	1778
mbed_official	76:aeb1df146756	1779	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
mbed_official	76:aeb1df146756	1780	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
mbed_official	76:aeb1df146756	1781	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
mbed_official	76:aeb1df146756	1782
mbed_official	76:aeb1df146756	1783	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
mbed_official	76:aeb1df146756	1784	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	76:aeb1df146756	1785	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	76:aeb1df146756	1786	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	76:aeb1df146756	1787	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	76:aeb1df146756	1788
mbed_official	76:aeb1df146756	1789	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
mbed_official	76:aeb1df146756	1790	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun interrupt enable /
mbed_official	76:aeb1df146756	1791	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
mbed_official	76:aeb1df146756	1792	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
mbed_official	76:aeb1df146756	1793	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
mbed_official	76:aeb1df146756	1794
mbed_official	76:aeb1df146756	1795	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
mbed_official	76:aeb1df146756	1796	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
mbed_official	76:aeb1df146756	1797	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
mbed_official	76:aeb1df146756	1798	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
mbed_official	76:aeb1df146756	1799
mbed_official	76:aeb1df146756	1800	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
mbed_official	76:aeb1df146756	1801	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
mbed_official	76:aeb1df146756	1802	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
mbed_official	76:aeb1df146756	1803
mbed_official	76:aeb1df146756	1804	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
mbed_official	76:aeb1df146756	1805	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
mbed_official	76:aeb1df146756	1806	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
mbed_official	76:aeb1df146756	1807	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
mbed_official	76:aeb1df146756	1808	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
mbed_official	76:aeb1df146756	1809
mbed_official	76:aeb1df146756	1810	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
mbed_official	76:aeb1df146756	1811	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun interrupt enable /
mbed_official	76:aeb1df146756	1812	/*************** Bit definition for DAC_SWTRIGR register ****************/
mbed_official	76:aeb1df146756	1813	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!<DAC channel1 software trigger /
mbed_official	76:aeb1df146756	1814	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!<DAC channel2 software trigger /
mbed_official	76:aeb1df146756	1815
mbed_official	76:aeb1df146756	1816	/*************** Bit definition for DAC_DHR12R1 register ****************/
mbed_official	76:aeb1df146756	1817	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!<DAC channel1 12-bit Right aligned data /
mbed_official	76:aeb1df146756	1818
mbed_official	76:aeb1df146756	1819	/*************** Bit definition for DAC_DHR12L1 register ****************/
mbed_official	76:aeb1df146756	1820	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!<DAC channel1 12-bit Left aligned data /
mbed_official	76:aeb1df146756	1821
mbed_official	76:aeb1df146756	1822	/**************** Bit definition for DAC_DHR8R1 register ****************/
mbed_official	76:aeb1df146756	1823	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!<DAC channel1 8-bit Right aligned data /
mbed_official	76:aeb1df146756	1824
mbed_official	76:aeb1df146756	1825	/*************** Bit definition for DAC_DHR12R2 register ****************/
mbed_official	76:aeb1df146756	1826	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!<DAC channel2 12-bit Right aligned data /
mbed_official	76:aeb1df146756	1827
mbed_official	76:aeb1df146756	1828	/*************** Bit definition for DAC_DHR12L2 register ****************/
mbed_official	76:aeb1df146756	1829	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!<DAC channel2 12-bit Left aligned data /
mbed_official	76:aeb1df146756	1830
mbed_official	76:aeb1df146756	1831	/**************** Bit definition for DAC_DHR8R2 register ****************/
mbed_official	76:aeb1df146756	1832	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!<DAC channel2 8-bit Right aligned data /
mbed_official	76:aeb1df146756	1833
mbed_official	76:aeb1df146756	1834	/*************** Bit definition for DAC_DHR12RD register ****************/
mbed_official	76:aeb1df146756	1835	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
mbed_official	76:aeb1df146756	1836	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
mbed_official	76:aeb1df146756	1837
mbed_official	76:aeb1df146756	1838	/*************** Bit definition for DAC_DHR12LD register ****************/
mbed_official	76:aeb1df146756	1839	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
mbed_official	76:aeb1df146756	1840	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
mbed_official	76:aeb1df146756	1841
mbed_official	76:aeb1df146756	1842	/**************** Bit definition for DAC_DHR8RD register ****************/
mbed_official	76:aeb1df146756	1843	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!<DAC channel1 8-bit Right aligned data /
mbed_official	76:aeb1df146756	1844	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!<DAC channel2 8-bit Right aligned data /
mbed_official	76:aeb1df146756	1845
mbed_official	76:aeb1df146756	1846	/***************** Bit definition for DAC_DOR1 register *****************/
mbed_official	76:aeb1df146756	1847	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!<DAC channel1 data output /
mbed_official	76:aeb1df146756	1848
mbed_official	76:aeb1df146756	1849	/***************** Bit definition for DAC_DOR2 register *****************/
mbed_official	76:aeb1df146756	1850	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!<DAC channel2 data output /
mbed_official	76:aeb1df146756	1851
mbed_official	76:aeb1df146756	1852	/****************** Bit definition for DAC_SR register ******************/
mbed_official	76:aeb1df146756	1853	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
mbed_official	76:aeb1df146756	1854	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
mbed_official	76:aeb1df146756	1855
mbed_official	76:aeb1df146756	1856	/******************************************************************************/
mbed_official	76:aeb1df146756	1857	/* */
mbed_official	76:aeb1df146756	1858	/* Debug MCU (DBGMCU) */
mbed_official	76:aeb1df146756	1859	/* */
mbed_official	76:aeb1df146756	1860	/******************************************************************************/
mbed_official	76:aeb1df146756	1861
mbed_official	76:aeb1df146756	1862	/************** Bit definition for DBGMCU_IDCODE register ***************/
mbed_official	76:aeb1df146756	1863	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
mbed_official	76:aeb1df146756	1864
mbed_official	76:aeb1df146756	1865	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
mbed_official	76:aeb1df146756	1866	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1867	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	1868	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	1869	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	1870	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	76:aeb1df146756	1871	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	76:aeb1df146756	1872	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	76:aeb1df146756	1873	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	76:aeb1df146756	1874	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	76:aeb1df146756	1875	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	76:aeb1df146756	1876	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	76:aeb1df146756	1877	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	76:aeb1df146756	1878	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	76:aeb1df146756	1879	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	76:aeb1df146756	1880	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	76:aeb1df146756	1881	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	76:aeb1df146756	1882
mbed_official	76:aeb1df146756	1883	/**************** Bit definition for DBGMCU_CR register *****************/
mbed_official	76:aeb1df146756	1884	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
mbed_official	76:aeb1df146756	1885	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
mbed_official	76:aeb1df146756	1886	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
mbed_official	76:aeb1df146756	1887	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
mbed_official	76:aeb1df146756	1888
mbed_official	76:aeb1df146756	1889	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
mbed_official	76:aeb1df146756	1890	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	76:aeb1df146756	1891	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	76:aeb1df146756	1892
mbed_official	76:aeb1df146756	1893	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official	76:aeb1df146756	1894
mbed_official	76:aeb1df146756	1895	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1896	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1897	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /!< TIM4 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1898	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /!< TIM5 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1899	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1900	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1901	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Counter stopped when Core is halted /
mbed_official	76:aeb1df146756	1902	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
mbed_official	76:aeb1df146756	1903	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
mbed_official	76:aeb1df146756	1904	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< SMBUS timeout mode stopped when Core is halted /
mbed_official	76:aeb1df146756	1905	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /!< SMBUS timeout mode stopped when Core is halted /
mbed_official	76:aeb1df146756	1906
mbed_official	76:aeb1df146756	1907	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official	76:aeb1df146756	1908
mbed_official	76:aeb1df146756	1909	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /!< TIM9 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1910	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /!< TIM10 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1911	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /!< TIM11 counter stopped when core is halted /
mbed_official	76:aeb1df146756	1912
mbed_official	76:aeb1df146756	1913	/******************************************************************************/
mbed_official	76:aeb1df146756	1914	/* */
mbed_official	76:aeb1df146756	1915	/* DMA Controller (DMA) */
mbed_official	76:aeb1df146756	1916	/* */
mbed_official	76:aeb1df146756	1917	/******************************************************************************/
mbed_official	76:aeb1df146756	1918
mbed_official	76:aeb1df146756	1919	/***************** Bit definition for DMA_ISR register ******************/
mbed_official	76:aeb1df146756	1920	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
mbed_official	76:aeb1df146756	1921	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
mbed_official	76:aeb1df146756	1922	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
mbed_official	76:aeb1df146756	1923	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
mbed_official	76:aeb1df146756	1924	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
mbed_official	76:aeb1df146756	1925	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
mbed_official	76:aeb1df146756	1926	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
mbed_official	76:aeb1df146756	1927	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
mbed_official	76:aeb1df146756	1928	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
mbed_official	76:aeb1df146756	1929	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
mbed_official	76:aeb1df146756	1930	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
mbed_official	76:aeb1df146756	1931	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
mbed_official	76:aeb1df146756	1932	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
mbed_official	76:aeb1df146756	1933	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
mbed_official	76:aeb1df146756	1934	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
mbed_official	76:aeb1df146756	1935	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
mbed_official	76:aeb1df146756	1936	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
mbed_official	76:aeb1df146756	1937	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
mbed_official	76:aeb1df146756	1938	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
mbed_official	76:aeb1df146756	1939	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
mbed_official	76:aeb1df146756	1940	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
mbed_official	76:aeb1df146756	1941	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
mbed_official	76:aeb1df146756	1942	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
mbed_official	76:aeb1df146756	1943	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
mbed_official	76:aeb1df146756	1944	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
mbed_official	76:aeb1df146756	1945	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
mbed_official	76:aeb1df146756	1946	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
mbed_official	76:aeb1df146756	1947	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
mbed_official	76:aeb1df146756	1948
mbed_official	76:aeb1df146756	1949	/***************** Bit definition for DMA_IFCR register *****************/
mbed_official	76:aeb1df146756	1950	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clearr /
mbed_official	76:aeb1df146756	1951	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
mbed_official	76:aeb1df146756	1952	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
mbed_official	76:aeb1df146756	1953	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
mbed_official	76:aeb1df146756	1954	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
mbed_official	76:aeb1df146756	1955	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
mbed_official	76:aeb1df146756	1956	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
mbed_official	76:aeb1df146756	1957	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
mbed_official	76:aeb1df146756	1958	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
mbed_official	76:aeb1df146756	1959	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
mbed_official	76:aeb1df146756	1960	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
mbed_official	76:aeb1df146756	1961	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
mbed_official	76:aeb1df146756	1962	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
mbed_official	76:aeb1df146756	1963	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
mbed_official	76:aeb1df146756	1964	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
mbed_official	76:aeb1df146756	1965	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
mbed_official	76:aeb1df146756	1966	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
mbed_official	76:aeb1df146756	1967	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
mbed_official	76:aeb1df146756	1968	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
mbed_official	76:aeb1df146756	1969	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
mbed_official	76:aeb1df146756	1970	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
mbed_official	76:aeb1df146756	1971	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
mbed_official	76:aeb1df146756	1972	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
mbed_official	76:aeb1df146756	1973	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
mbed_official	76:aeb1df146756	1974	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
mbed_official	76:aeb1df146756	1975	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
mbed_official	76:aeb1df146756	1976	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
mbed_official	76:aeb1df146756	1977	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
mbed_official	76:aeb1df146756	1978
mbed_official	76:aeb1df146756	1979	/***************** Bit definition for DMA_CCR1 register *****************/
mbed_official	76:aeb1df146756	1980	#define DMA_CCR1_EN ((uint16_t)0x0001) /!< Channel enable/
mbed_official	76:aeb1df146756	1981	#define DMA_CCR1_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	1982	#define DMA_CCR1_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	1983	#define DMA_CCR1_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	1984	#define DMA_CCR1_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	1985	#define DMA_CCR1_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	1986	#define DMA_CCR1_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	1987	#define DMA_CCR1_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	1988
mbed_official	76:aeb1df146756	1989	#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	1990	#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	1991	#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	1992
mbed_official	76:aeb1df146756	1993	#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	1994	#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	1995	#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	1996
mbed_official	76:aeb1df146756	1997	#define DMA_CCR1_PL ((uint16_t)0x3000) /!< PL[1:0] bits(Channel Priority level) /
mbed_official	76:aeb1df146756	1998	#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	1999	#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2000
mbed_official	76:aeb1df146756	2001	#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
mbed_official	76:aeb1df146756	2002
mbed_official	76:aeb1df146756	2003	/***************** Bit definition for DMA_CCR2 register *****************/
mbed_official	76:aeb1df146756	2004	#define DMA_CCR2_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2005	#define DMA_CCR2_TCIE ((uint16_t)0x0002) /!< ransfer complete interrupt enable /
mbed_official	76:aeb1df146756	2006	#define DMA_CCR2_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2007	#define DMA_CCR2_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2008	#define DMA_CCR2_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2009	#define DMA_CCR2_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2010	#define DMA_CCR2_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2011	#define DMA_CCR2_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2012
mbed_official	76:aeb1df146756	2013	#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2014	#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2015	#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2016
mbed_official	76:aeb1df146756	2017	#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2018	#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2019	#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2020
mbed_official	76:aeb1df146756	2021	#define DMA_CCR2_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2022	#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2023	#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2024
mbed_official	76:aeb1df146756	2025	#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
mbed_official	76:aeb1df146756	2026
mbed_official	76:aeb1df146756	2027	/***************** Bit definition for DMA_CCR3 register *****************/
mbed_official	76:aeb1df146756	2028	#define DMA_CCR3_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2029	#define DMA_CCR3_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	2030	#define DMA_CCR3_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2031	#define DMA_CCR3_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2032	#define DMA_CCR3_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2033	#define DMA_CCR3_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2034	#define DMA_CCR3_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2035	#define DMA_CCR3_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2036
mbed_official	76:aeb1df146756	2037	#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2038	#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2039	#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2040
mbed_official	76:aeb1df146756	2041	#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2042	#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2043	#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2044
mbed_official	76:aeb1df146756	2045	#define DMA_CCR3_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2046	#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2047	#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2048
mbed_official	76:aeb1df146756	2049	#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
mbed_official	76:aeb1df146756	2050
mbed_official	76:aeb1df146756	2051	/!<*************** Bit definition for DMA_CCR4 register *****************/
mbed_official	76:aeb1df146756	2052	#define DMA_CCR4_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2053	#define DMA_CCR4_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	2054	#define DMA_CCR4_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2055	#define DMA_CCR4_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2056	#define DMA_CCR4_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2057	#define DMA_CCR4_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2058	#define DMA_CCR4_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2059	#define DMA_CCR4_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2060
mbed_official	76:aeb1df146756	2061	#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2062	#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2063	#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2064
mbed_official	76:aeb1df146756	2065	#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2066	#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2067	#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2068
mbed_official	76:aeb1df146756	2069	#define DMA_CCR4_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2070	#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2071	#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2072
mbed_official	76:aeb1df146756	2073	#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
mbed_official	76:aeb1df146756	2074
mbed_official	76:aeb1df146756	2075	/**************** Bit definition for DMA_CCR5 register *****************/
mbed_official	76:aeb1df146756	2076	#define DMA_CCR5_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2077	#define DMA_CCR5_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	2078	#define DMA_CCR5_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2079	#define DMA_CCR5_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2080	#define DMA_CCR5_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2081	#define DMA_CCR5_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2082	#define DMA_CCR5_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2083	#define DMA_CCR5_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2084
mbed_official	76:aeb1df146756	2085	#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2086	#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2087	#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2088
mbed_official	76:aeb1df146756	2089	#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2090	#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2091	#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2092
mbed_official	76:aeb1df146756	2093	#define DMA_CCR5_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2094	#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2095	#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2096
mbed_official	76:aeb1df146756	2097	#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode enable /
mbed_official	76:aeb1df146756	2098
mbed_official	76:aeb1df146756	2099	/***************** Bit definition for DMA_CCR6 register *****************/
mbed_official	76:aeb1df146756	2100	#define DMA_CCR6_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2101	#define DMA_CCR6_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	2102	#define DMA_CCR6_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2103	#define DMA_CCR6_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2104	#define DMA_CCR6_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2105	#define DMA_CCR6_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2106	#define DMA_CCR6_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2107	#define DMA_CCR6_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2108
mbed_official	76:aeb1df146756	2109	#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2110	#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2111	#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2112
mbed_official	76:aeb1df146756	2113	#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2114	#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2115	#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2116
mbed_official	76:aeb1df146756	2117	#define DMA_CCR6_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2118	#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2119	#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2120
mbed_official	76:aeb1df146756	2121	#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
mbed_official	76:aeb1df146756	2122
mbed_official	76:aeb1df146756	2123	/***************** Bit definition for DMA_CCR7 register *****************/
mbed_official	76:aeb1df146756	2124	#define DMA_CCR7_EN ((uint16_t)0x0001) /!< Channel enable /
mbed_official	76:aeb1df146756	2125	#define DMA_CCR7_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
mbed_official	76:aeb1df146756	2126	#define DMA_CCR7_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
mbed_official	76:aeb1df146756	2127	#define DMA_CCR7_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
mbed_official	76:aeb1df146756	2128	#define DMA_CCR7_DIR ((uint16_t)0x0010) /!< Data transfer direction /
mbed_official	76:aeb1df146756	2129	#define DMA_CCR7_CIRC ((uint16_t)0x0020) /!< Circular mode /
mbed_official	76:aeb1df146756	2130	#define DMA_CCR7_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
mbed_official	76:aeb1df146756	2131	#define DMA_CCR7_MINC ((uint16_t)0x0080) /!< Memory increment mode /
mbed_official	76:aeb1df146756	2132
mbed_official	76:aeb1df146756	2133	#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	76:aeb1df146756	2134	#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2135	#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2136
mbed_official	76:aeb1df146756	2137	#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	76:aeb1df146756	2138	#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	2139	#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	2140
mbed_official	76:aeb1df146756	2141	#define DMA_CCR7_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
mbed_official	76:aeb1df146756	2142	#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2143	#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2144
mbed_official	76:aeb1df146756	2145	#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode enable /
mbed_official	76:aeb1df146756	2146
mbed_official	76:aeb1df146756	2147	/**************** Bit definition for DMA_CNDTR1 register ****************/
mbed_official	76:aeb1df146756	2148	#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2149
mbed_official	76:aeb1df146756	2150	/**************** Bit definition for DMA_CNDTR2 register ****************/
mbed_official	76:aeb1df146756	2151	#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2152
mbed_official	76:aeb1df146756	2153	/**************** Bit definition for DMA_CNDTR3 register ****************/
mbed_official	76:aeb1df146756	2154	#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2155
mbed_official	76:aeb1df146756	2156	/**************** Bit definition for DMA_CNDTR4 register ****************/
mbed_official	76:aeb1df146756	2157	#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2158
mbed_official	76:aeb1df146756	2159	/**************** Bit definition for DMA_CNDTR5 register ****************/
mbed_official	76:aeb1df146756	2160	#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2161
mbed_official	76:aeb1df146756	2162	/**************** Bit definition for DMA_CNDTR6 register ****************/
mbed_official	76:aeb1df146756	2163	#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2164
mbed_official	76:aeb1df146756	2165	/**************** Bit definition for DMA_CNDTR7 register ****************/
mbed_official	76:aeb1df146756	2166	#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
mbed_official	76:aeb1df146756	2167
mbed_official	76:aeb1df146756	2168	/**************** Bit definition for DMA_CPAR1 register *****************/
mbed_official	76:aeb1df146756	2169	#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2170
mbed_official	76:aeb1df146756	2171	/**************** Bit definition for DMA_CPAR2 register *****************/
mbed_official	76:aeb1df146756	2172	#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2173
mbed_official	76:aeb1df146756	2174	/**************** Bit definition for DMA_CPAR3 register *****************/
mbed_official	76:aeb1df146756	2175	#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2176
mbed_official	76:aeb1df146756	2177
mbed_official	76:aeb1df146756	2178	/**************** Bit definition for DMA_CPAR4 register *****************/
mbed_official	76:aeb1df146756	2179	#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2180
mbed_official	76:aeb1df146756	2181	/**************** Bit definition for DMA_CPAR5 register *****************/
mbed_official	76:aeb1df146756	2182	#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2183
mbed_official	76:aeb1df146756	2184	/**************** Bit definition for DMA_CPAR6 register *****************/
mbed_official	76:aeb1df146756	2185	#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2186
mbed_official	76:aeb1df146756	2187
mbed_official	76:aeb1df146756	2188	/**************** Bit definition for DMA_CPAR7 register *****************/
mbed_official	76:aeb1df146756	2189	#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	76:aeb1df146756	2190
mbed_official	76:aeb1df146756	2191	/**************** Bit definition for DMA_CMAR1 register *****************/
mbed_official	76:aeb1df146756	2192	#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2193
mbed_official	76:aeb1df146756	2194	/**************** Bit definition for DMA_CMAR2 register *****************/
mbed_official	76:aeb1df146756	2195	#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2196
mbed_official	76:aeb1df146756	2197	/**************** Bit definition for DMA_CMAR3 register *****************/
mbed_official	76:aeb1df146756	2198	#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2199
mbed_official	76:aeb1df146756	2200
mbed_official	76:aeb1df146756	2201	/**************** Bit definition for DMA_CMAR4 register *****************/
mbed_official	76:aeb1df146756	2202	#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2203
mbed_official	76:aeb1df146756	2204	/**************** Bit definition for DMA_CMAR5 register *****************/
mbed_official	76:aeb1df146756	2205	#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2206
mbed_official	76:aeb1df146756	2207	/**************** Bit definition for DMA_CMAR6 register *****************/
mbed_official	76:aeb1df146756	2208	#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2209
mbed_official	76:aeb1df146756	2210	/**************** Bit definition for DMA_CMAR7 register *****************/
mbed_official	76:aeb1df146756	2211	#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	76:aeb1df146756	2212
mbed_official	76:aeb1df146756	2213	/******************************************************************************/
mbed_official	76:aeb1df146756	2214	/* */
mbed_official	76:aeb1df146756	2215	/* External Interrupt/Event Controller (EXTI) */
mbed_official	76:aeb1df146756	2216	/* */
mbed_official	76:aeb1df146756	2217	/******************************************************************************/
mbed_official	76:aeb1df146756	2218
mbed_official	76:aeb1df146756	2219	/***************** Bit definition for EXTI_IMR register *****************/
mbed_official	76:aeb1df146756	2220	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
mbed_official	76:aeb1df146756	2221	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
mbed_official	76:aeb1df146756	2222	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
mbed_official	76:aeb1df146756	2223	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
mbed_official	76:aeb1df146756	2224	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
mbed_official	76:aeb1df146756	2225	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
mbed_official	76:aeb1df146756	2226	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
mbed_official	76:aeb1df146756	2227	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
mbed_official	76:aeb1df146756	2228	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
mbed_official	76:aeb1df146756	2229	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
mbed_official	76:aeb1df146756	2230	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
mbed_official	76:aeb1df146756	2231	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
mbed_official	76:aeb1df146756	2232	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
mbed_official	76:aeb1df146756	2233	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
mbed_official	76:aeb1df146756	2234	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
mbed_official	76:aeb1df146756	2235	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
mbed_official	76:aeb1df146756	2236	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
mbed_official	76:aeb1df146756	2237	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
mbed_official	76:aeb1df146756	2238	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
mbed_official	76:aeb1df146756	2239	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
mbed_official	76:aeb1df146756	2240	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
mbed_official	76:aeb1df146756	2241	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
mbed_official	76:aeb1df146756	2242	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
mbed_official	76:aeb1df146756	2243	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
mbed_official	76:aeb1df146756	2244
mbed_official	76:aeb1df146756	2245	/***************** Bit definition for EXTI_EMR register *****************/
mbed_official	76:aeb1df146756	2246	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
mbed_official	76:aeb1df146756	2247	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
mbed_official	76:aeb1df146756	2248	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
mbed_official	76:aeb1df146756	2249	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
mbed_official	76:aeb1df146756	2250	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
mbed_official	76:aeb1df146756	2251	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
mbed_official	76:aeb1df146756	2252	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
mbed_official	76:aeb1df146756	2253	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
mbed_official	76:aeb1df146756	2254	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
mbed_official	76:aeb1df146756	2255	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
mbed_official	76:aeb1df146756	2256	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
mbed_official	76:aeb1df146756	2257	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
mbed_official	76:aeb1df146756	2258	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
mbed_official	76:aeb1df146756	2259	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
mbed_official	76:aeb1df146756	2260	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
mbed_official	76:aeb1df146756	2261	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
mbed_official	76:aeb1df146756	2262	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
mbed_official	76:aeb1df146756	2263	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
mbed_official	76:aeb1df146756	2264	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
mbed_official	76:aeb1df146756	2265	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
mbed_official	76:aeb1df146756	2266	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
mbed_official	76:aeb1df146756	2267	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
mbed_official	76:aeb1df146756	2268	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
mbed_official	76:aeb1df146756	2269	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
mbed_official	76:aeb1df146756	2270
mbed_official	76:aeb1df146756	2271	/**************** Bit definition for EXTI_RTSR register *****************/
mbed_official	76:aeb1df146756	2272	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
mbed_official	76:aeb1df146756	2273	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
mbed_official	76:aeb1df146756	2274	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
mbed_official	76:aeb1df146756	2275	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
mbed_official	76:aeb1df146756	2276	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
mbed_official	76:aeb1df146756	2277	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
mbed_official	76:aeb1df146756	2278	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
mbed_official	76:aeb1df146756	2279	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
mbed_official	76:aeb1df146756	2280	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
mbed_official	76:aeb1df146756	2281	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
mbed_official	76:aeb1df146756	2282	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
mbed_official	76:aeb1df146756	2283	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
mbed_official	76:aeb1df146756	2284	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
mbed_official	76:aeb1df146756	2285	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
mbed_official	76:aeb1df146756	2286	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
mbed_official	76:aeb1df146756	2287	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
mbed_official	76:aeb1df146756	2288	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
mbed_official	76:aeb1df146756	2289	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
mbed_official	76:aeb1df146756	2290	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
mbed_official	76:aeb1df146756	2291	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
mbed_official	76:aeb1df146756	2292	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
mbed_official	76:aeb1df146756	2293	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
mbed_official	76:aeb1df146756	2294	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
mbed_official	76:aeb1df146756	2295	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
mbed_official	76:aeb1df146756	2296
mbed_official	76:aeb1df146756	2297	/**************** Bit definition for EXTI_FTSR register *****************/
mbed_official	76:aeb1df146756	2298	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
mbed_official	76:aeb1df146756	2299	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
mbed_official	76:aeb1df146756	2300	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
mbed_official	76:aeb1df146756	2301	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
mbed_official	76:aeb1df146756	2302	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
mbed_official	76:aeb1df146756	2303	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
mbed_official	76:aeb1df146756	2304	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
mbed_official	76:aeb1df146756	2305	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
mbed_official	76:aeb1df146756	2306	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
mbed_official	76:aeb1df146756	2307	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
mbed_official	76:aeb1df146756	2308	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
mbed_official	76:aeb1df146756	2309	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
mbed_official	76:aeb1df146756	2310	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
mbed_official	76:aeb1df146756	2311	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
mbed_official	76:aeb1df146756	2312	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
mbed_official	76:aeb1df146756	2313	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
mbed_official	76:aeb1df146756	2314	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
mbed_official	76:aeb1df146756	2315	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
mbed_official	76:aeb1df146756	2316	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
mbed_official	76:aeb1df146756	2317	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
mbed_official	76:aeb1df146756	2318	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
mbed_official	76:aeb1df146756	2319	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
mbed_official	76:aeb1df146756	2320	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
mbed_official	76:aeb1df146756	2321	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
mbed_official	76:aeb1df146756	2322
mbed_official	76:aeb1df146756	2323	/**************** Bit definition for EXTI_SWIER register ****************/
mbed_official	76:aeb1df146756	2324	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
mbed_official	76:aeb1df146756	2325	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
mbed_official	76:aeb1df146756	2326	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
mbed_official	76:aeb1df146756	2327	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
mbed_official	76:aeb1df146756	2328	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
mbed_official	76:aeb1df146756	2329	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
mbed_official	76:aeb1df146756	2330	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
mbed_official	76:aeb1df146756	2331	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
mbed_official	76:aeb1df146756	2332	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
mbed_official	76:aeb1df146756	2333	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
mbed_official	76:aeb1df146756	2334	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
mbed_official	76:aeb1df146756	2335	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
mbed_official	76:aeb1df146756	2336	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
mbed_official	76:aeb1df146756	2337	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
mbed_official	76:aeb1df146756	2338	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
mbed_official	76:aeb1df146756	2339	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
mbed_official	76:aeb1df146756	2340	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
mbed_official	76:aeb1df146756	2341	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
mbed_official	76:aeb1df146756	2342	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
mbed_official	76:aeb1df146756	2343	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
mbed_official	76:aeb1df146756	2344	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
mbed_official	76:aeb1df146756	2345	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
mbed_official	76:aeb1df146756	2346	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
mbed_official	76:aeb1df146756	2347	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
mbed_official	76:aeb1df146756	2348
mbed_official	76:aeb1df146756	2349	/***************** Bit definition for EXTI_PR register ******************/
mbed_official	76:aeb1df146756	2350	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
mbed_official	76:aeb1df146756	2351	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
mbed_official	76:aeb1df146756	2352	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
mbed_official	76:aeb1df146756	2353	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
mbed_official	76:aeb1df146756	2354	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
mbed_official	76:aeb1df146756	2355	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
mbed_official	76:aeb1df146756	2356	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
mbed_official	76:aeb1df146756	2357	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
mbed_official	76:aeb1df146756	2358	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
mbed_official	76:aeb1df146756	2359	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
mbed_official	76:aeb1df146756	2360	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
mbed_official	76:aeb1df146756	2361	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
mbed_official	76:aeb1df146756	2362	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
mbed_official	76:aeb1df146756	2363	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
mbed_official	76:aeb1df146756	2364	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
mbed_official	76:aeb1df146756	2365	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
mbed_official	76:aeb1df146756	2366	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
mbed_official	76:aeb1df146756	2367	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
mbed_official	76:aeb1df146756	2368	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit 18 /
mbed_official	76:aeb1df146756	2369	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
mbed_official	76:aeb1df146756	2370	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit 20 /
mbed_official	76:aeb1df146756	2371	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit 21 /
mbed_official	76:aeb1df146756	2372	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit 22 /
mbed_official	76:aeb1df146756	2373	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit 23 /
mbed_official	76:aeb1df146756	2374
mbed_official	76:aeb1df146756	2375	/******************************************************************************/
mbed_official	76:aeb1df146756	2376	/* */
mbed_official	76:aeb1df146756	2377	/* FLASH, DATA EEPROM and Option Bytes Registers */
mbed_official	76:aeb1df146756	2378	/* (FLASH, DATA_EEPROM, OB) */
mbed_official	76:aeb1df146756	2379	/* */
mbed_official	76:aeb1df146756	2380	/******************************************************************************/
mbed_official	76:aeb1df146756	2381
mbed_official	76:aeb1df146756	2382	/***************** Bit definition for FLASH_ACR register ****************/
mbed_official	76:aeb1df146756	2383	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< Latency /
mbed_official	76:aeb1df146756	2384	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /!< Prefetch Buffer Enable /
mbed_official	76:aeb1df146756	2385	#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /!< Access 64 bits /
mbed_official	76:aeb1df146756	2386	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /!< Flash mode during sleep mode /
mbed_official	76:aeb1df146756	2387	#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /!< Flash mode during RUN mode /
mbed_official	76:aeb1df146756	2388
mbed_official	76:aeb1df146756	2389	/***************** Bit definition for FLASH_PECR register ****************/
mbed_official	76:aeb1df146756	2390	#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /!< FLASH_PECR and Flash data Lock /
mbed_official	76:aeb1df146756	2391	#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /!< Program matrix Lock /
mbed_official	76:aeb1df146756	2392	#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /!< Option byte matrix Lock /
mbed_official	76:aeb1df146756	2393	#define FLASH_PECR_PROG ((uint32_t)0x00000008) /!< Program matrix selection /
mbed_official	76:aeb1df146756	2394	#define FLASH_PECR_DATA ((uint32_t)0x00000010) /!< Data matrix selection /
mbed_official	76:aeb1df146756	2395	#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /!< Fixed Time Data write for Word/Half Word/Byte programming /
mbed_official	76:aeb1df146756	2396	#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /!< Page erasing mode /
mbed_official	76:aeb1df146756	2397	#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /!< Fast Page/Half Page programming mode /
mbed_official	76:aeb1df146756	2398	#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /!< Parallel Bank mode /
mbed_official	76:aeb1df146756	2399	#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /!< End of programming interrupt /
mbed_official	76:aeb1df146756	2400	#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /!< Error interrupt /
mbed_official	76:aeb1df146756	2401	#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /!< Launch the option byte loading /
mbed_official	76:aeb1df146756	2402
mbed_official	76:aeb1df146756	2403	/**************** Bit definition for FLASH_PDKEYR register ****************/
mbed_official	76:aeb1df146756	2404	#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
mbed_official	76:aeb1df146756	2405
mbed_official	76:aeb1df146756	2406	/**************** Bit definition for FLASH_PEKEYR register ****************/
mbed_official	76:aeb1df146756	2407	#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /!< FLASH_PEC and data matrix Key /
mbed_official	76:aeb1df146756	2408
mbed_official	76:aeb1df146756	2409	/**************** Bit definition for FLASH_PRGKEYR register ****************/
mbed_official	76:aeb1df146756	2410	#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /!< Program matrix Key /
mbed_official	76:aeb1df146756	2411
mbed_official	76:aeb1df146756	2412	/**************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official	76:aeb1df146756	2413	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option bytes matrix Key /
mbed_official	76:aeb1df146756	2414
mbed_official	76:aeb1df146756	2415	/**************** Bit definition for FLASH_SR register *****************/
mbed_official	76:aeb1df146756	2416	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
mbed_official	76:aeb1df146756	2417	#define FLASH_SR_EOP ((uint32_t)0x00000002) /!< End Of Programming/
mbed_official	76:aeb1df146756	2418	#define FLASH_SR_ENHV ((uint32_t)0x00000004) /!< End of high voltage /
mbed_official	76:aeb1df146756	2419	#define FLASH_SR_READY ((uint32_t)0x00000008) /!< Flash ready after low power mode /
mbed_official	76:aeb1df146756	2420
mbed_official	76:aeb1df146756	2421	#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /!< Write protected error /
mbed_official	76:aeb1df146756	2422	#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /!< Programming Alignment Error /
mbed_official	76:aeb1df146756	2423	#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /!< Size error /
mbed_official	76:aeb1df146756	2424	#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /!< Option validity error /
mbed_official	76:aeb1df146756	2425	#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /!< Option User validity error /
mbed_official	76:aeb1df146756	2426	#define FLASH_SR_RDERR ((uint32_t)0x00002000) /!< Read protected error /
mbed_official	76:aeb1df146756	2427
mbed_official	76:aeb1df146756	2428	/**************** Bit definition for FLASH_OBR register *****************/
mbed_official	76:aeb1df146756	2429	#define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /!< Read Protection /
mbed_official	76:aeb1df146756	2430	#define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits
mbed_official	76:aeb1df146756	2431	(available only in STM32L1xx Medium-density Plus devices) */
mbed_official	76:aeb1df146756	2432	#define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
mbed_official	76:aeb1df146756	2433	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /!< IWDG_SW /
mbed_official	76:aeb1df146756	2434	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /!< nRST_STOP /
mbed_official	76:aeb1df146756	2435	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /!< nRST_STDBY /
mbed_official	76:aeb1df146756	2436	#define FLASH_OBR_BFB2 ((uint32_t)0x00800000) /!< BFB2(available only in STM32L1xx High-density devices) /
mbed_official	76:aeb1df146756	2437
mbed_official	76:aeb1df146756	2438	/**************** Bit definition for FLASH_WRPR register ****************/
mbed_official	76:aeb1df146756	2439	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protection bits /
mbed_official	76:aeb1df146756	2440
mbed_official	76:aeb1df146756	2441	/**************** Bit definition for FLASH_WRPR1 register ***************/
mbed_official	76:aeb1df146756	2442	#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
mbed_official	76:aeb1df146756	2443	Medium-density Plus and High-density devices) */
mbed_official	76:aeb1df146756	2444
mbed_official	76:aeb1df146756	2445	/**************** Bit definition for FLASH_WRPR2 register ***************/
mbed_official	76:aeb1df146756	2446	#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
mbed_official	76:aeb1df146756	2447	High-density devices) */
mbed_official	76:aeb1df146756	2448	/******************************************************************************/
mbed_official	76:aeb1df146756	2449	/* */
mbed_official	76:aeb1df146756	2450	/* Flexible Static Memory Controller */
mbed_official	76:aeb1df146756	2451	/* */
mbed_official	76:aeb1df146756	2452	/******************************************************************************/
mbed_official	76:aeb1df146756	2453	/**************** Bit definition for FSMC_BCR1 register *****************/
mbed_official	76:aeb1df146756	2454	#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
mbed_official	76:aeb1df146756	2455	#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
mbed_official	76:aeb1df146756	2456
mbed_official	76:aeb1df146756	2457	#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
mbed_official	76:aeb1df146756	2458	#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	76:aeb1df146756	2459	#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	76:aeb1df146756	2460
mbed_official	76:aeb1df146756	2461	#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
mbed_official	76:aeb1df146756	2462	#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2463	#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2464
mbed_official	76:aeb1df146756	2465	#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
mbed_official	76:aeb1df146756	2466	#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
mbed_official	76:aeb1df146756	2467	#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
mbed_official	76:aeb1df146756	2468	#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
mbed_official	76:aeb1df146756	2469	#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
mbed_official	76:aeb1df146756	2470	#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /!< Write enable bit /
mbed_official	76:aeb1df146756	2471	#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
mbed_official	76:aeb1df146756	2472	#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
mbed_official	76:aeb1df146756	2473	#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
mbed_official	76:aeb1df146756	2474	#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
mbed_official	76:aeb1df146756	2475
mbed_official	76:aeb1df146756	2476	/**************** Bit definition for FSMC_BCR2 register *****************/
mbed_official	76:aeb1df146756	2477	#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
mbed_official	76:aeb1df146756	2478	#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
mbed_official	76:aeb1df146756	2479
mbed_official	76:aeb1df146756	2480	#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
mbed_official	76:aeb1df146756	2481	#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	76:aeb1df146756	2482	#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	76:aeb1df146756	2483
mbed_official	76:aeb1df146756	2484	#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
mbed_official	76:aeb1df146756	2485	#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2486	#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2487
mbed_official	76:aeb1df146756	2488	#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
mbed_official	76:aeb1df146756	2489	#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
mbed_official	76:aeb1df146756	2490	#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
mbed_official	76:aeb1df146756	2491	#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
mbed_official	76:aeb1df146756	2492	#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
mbed_official	76:aeb1df146756	2493	#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /!< Write enable bit /
mbed_official	76:aeb1df146756	2494	#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
mbed_official	76:aeb1df146756	2495	#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
mbed_official	76:aeb1df146756	2496	#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
mbed_official	76:aeb1df146756	2497	#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
mbed_official	76:aeb1df146756	2498
mbed_official	76:aeb1df146756	2499	/**************** Bit definition for FSMC_BCR3 register *****************/
mbed_official	76:aeb1df146756	2500	#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
mbed_official	76:aeb1df146756	2501	#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
mbed_official	76:aeb1df146756	2502
mbed_official	76:aeb1df146756	2503	#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
mbed_official	76:aeb1df146756	2504	#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	76:aeb1df146756	2505	#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	76:aeb1df146756	2506
mbed_official	76:aeb1df146756	2507	#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
mbed_official	76:aeb1df146756	2508	#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2509	#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2510
mbed_official	76:aeb1df146756	2511	#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
mbed_official	76:aeb1df146756	2512	#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
mbed_official	76:aeb1df146756	2513	#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit. /
mbed_official	76:aeb1df146756	2514	#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
mbed_official	76:aeb1df146756	2515	#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
mbed_official	76:aeb1df146756	2516	#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /!< Write enable bit /
mbed_official	76:aeb1df146756	2517	#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
mbed_official	76:aeb1df146756	2518	#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
mbed_official	76:aeb1df146756	2519	#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
mbed_official	76:aeb1df146756	2520	#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
mbed_official	76:aeb1df146756	2521
mbed_official	76:aeb1df146756	2522	/**************** Bit definition for FSMC_BCR4 register *****************/
mbed_official	76:aeb1df146756	2523	#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
mbed_official	76:aeb1df146756	2524	#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
mbed_official	76:aeb1df146756	2525
mbed_official	76:aeb1df146756	2526	#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
mbed_official	76:aeb1df146756	2527	#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	76:aeb1df146756	2528	#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	76:aeb1df146756	2529
mbed_official	76:aeb1df146756	2530	#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
mbed_official	76:aeb1df146756	2531	#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2532	#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2533
mbed_official	76:aeb1df146756	2534	#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
mbed_official	76:aeb1df146756	2535	#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
mbed_official	76:aeb1df146756	2536	#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
mbed_official	76:aeb1df146756	2537	#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
mbed_official	76:aeb1df146756	2538	#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
mbed_official	76:aeb1df146756	2539	#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /!< Write enable bit /
mbed_official	76:aeb1df146756	2540	#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
mbed_official	76:aeb1df146756	2541	#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
mbed_official	76:aeb1df146756	2542	#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
mbed_official	76:aeb1df146756	2543	#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
mbed_official	76:aeb1df146756	2544
mbed_official	76:aeb1df146756	2545	/**************** Bit definition for FSMC_BTR1 register ****************/
mbed_official	76:aeb1df146756	2546	#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2547	#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2548	#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2549	#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2550	#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2551
mbed_official	76:aeb1df146756	2552	#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2553	#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2554	#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2555	#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2556	#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2557
mbed_official	76:aeb1df146756	2558	#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2559	#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2560	#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2561	#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2562	#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2563
mbed_official	76:aeb1df146756	2564	#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
mbed_official	76:aeb1df146756	2565	#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2566	#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2567	#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2568	#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2569
mbed_official	76:aeb1df146756	2570	#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2571	#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2572	#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2573	#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2574	#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2575
mbed_official	76:aeb1df146756	2576	#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2577	#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2578	#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2579	#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2580	#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2581
mbed_official	76:aeb1df146756	2582	#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2583	#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2584	#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2585
mbed_official	76:aeb1df146756	2586	/**************** Bit definition for FSMC_BTR2 register *****************/
mbed_official	76:aeb1df146756	2587	#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2588	#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2589	#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2590	#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2591	#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2592
mbed_official	76:aeb1df146756	2593	#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2594	#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2595	#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2596	#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2597	#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2598
mbed_official	76:aeb1df146756	2599	#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2600	#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2601	#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2602	#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2603	#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2604
mbed_official	76:aeb1df146756	2605	#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
mbed_official	76:aeb1df146756	2606	#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2607	#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2608	#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2609	#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2610
mbed_official	76:aeb1df146756	2611	#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2612	#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2613	#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2614	#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2615	#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2616
mbed_official	76:aeb1df146756	2617	#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2618	#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2619	#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2620	#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2621	#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2622
mbed_official	76:aeb1df146756	2623	#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2624	#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2625	#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2626
mbed_official	76:aeb1df146756	2627	/***************** Bit definition for FSMC_BTR3 register *****************/
mbed_official	76:aeb1df146756	2628	#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2629	#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2630	#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2631	#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2632	#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2633
mbed_official	76:aeb1df146756	2634	#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2635	#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2636	#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2637	#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2638	#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2639
mbed_official	76:aeb1df146756	2640	#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2641	#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2642	#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2643	#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2644	#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2645
mbed_official	76:aeb1df146756	2646	#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
mbed_official	76:aeb1df146756	2647	#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2648	#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2649	#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2650	#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2651
mbed_official	76:aeb1df146756	2652	#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2653	#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2654	#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2655	#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2656	#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2657
mbed_official	76:aeb1df146756	2658	#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2659	#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2660	#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2661	#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2662	#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2663
mbed_official	76:aeb1df146756	2664	#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2665	#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2666	#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2667
mbed_official	76:aeb1df146756	2668	/**************** Bit definition for FSMC_BTR4 register *****************/
mbed_official	76:aeb1df146756	2669	#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2670	#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2671	#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2672	#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2673	#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2674
mbed_official	76:aeb1df146756	2675	#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2676	#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2677	#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2678	#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2679	#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2680
mbed_official	76:aeb1df146756	2681	#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2682	#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2683	#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2684	#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2685	#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2686
mbed_official	76:aeb1df146756	2687	#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
mbed_official	76:aeb1df146756	2688	#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2689	#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2690	#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2691	#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2692
mbed_official	76:aeb1df146756	2693	#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2694	#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2695	#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2696	#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2697	#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2698
mbed_official	76:aeb1df146756	2699	#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2700	#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2701	#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2702	#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2703	#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2704
mbed_official	76:aeb1df146756	2705	#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2706	#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2707	#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2708
mbed_official	76:aeb1df146756	2709	/**************** Bit definition for FSMC_BWTR1 register ****************/
mbed_official	76:aeb1df146756	2710	#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2711	#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2712	#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2713	#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2714	#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2715
mbed_official	76:aeb1df146756	2716	#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2717	#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2718	#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2719	#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2720	#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2721
mbed_official	76:aeb1df146756	2722	#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2723	#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2724	#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2725	#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2726	#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2727
mbed_official	76:aeb1df146756	2728	#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2729	#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2730	#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2731	#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2732	#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2733
mbed_official	76:aeb1df146756	2734	#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2735	#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2736	#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2737	#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2738	#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2739
mbed_official	76:aeb1df146756	2740	#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2741	#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2742	#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2743
mbed_official	76:aeb1df146756	2744	/**************** Bit definition for FSMC_BWTR2 register ****************/
mbed_official	76:aeb1df146756	2745	#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2746	#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2747	#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2748	#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2749	#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2750
mbed_official	76:aeb1df146756	2751	#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2752	#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2753	#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2754	#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2755	#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2756
mbed_official	76:aeb1df146756	2757	#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2758	#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2759	#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2760	#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2761	#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2762
mbed_official	76:aeb1df146756	2763	#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2764	#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2765	#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1/
mbed_official	76:aeb1df146756	2766	#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2767	#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2768
mbed_official	76:aeb1df146756	2769	#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2770	#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2771	#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2772	#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2773	#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2774
mbed_official	76:aeb1df146756	2775	#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2776	#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2777	#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2778
mbed_official	76:aeb1df146756	2779	/**************** Bit definition for FSMC_BWTR3 register ****************/
mbed_official	76:aeb1df146756	2780	#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2781	#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2782	#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2783	#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2784	#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2785
mbed_official	76:aeb1df146756	2786	#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2787	#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2788	#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2789	#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2790	#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2791
mbed_official	76:aeb1df146756	2792	#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2793	#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2794	#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2795	#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2796	#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2797
mbed_official	76:aeb1df146756	2798	#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2799	#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2800	#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2801	#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2802	#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2803
mbed_official	76:aeb1df146756	2804	#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2805	#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2806	#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2807	#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2808	#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2809
mbed_official	76:aeb1df146756	2810	#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2811	#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2812	#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2813
mbed_official	76:aeb1df146756	2814	/**************** Bit definition for FSMC_BWTR4 register ****************/
mbed_official	76:aeb1df146756	2815	#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
mbed_official	76:aeb1df146756	2816	#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	2817	#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	2818	#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	2819	#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	2820
mbed_official	76:aeb1df146756	2821	#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
mbed_official	76:aeb1df146756	2822	#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	2823	#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	2824	#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	2825	#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	2826
mbed_official	76:aeb1df146756	2827	#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
mbed_official	76:aeb1df146756	2828	#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	2829	#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	2830	#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	2831	#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	2832
mbed_official	76:aeb1df146756	2833	#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
mbed_official	76:aeb1df146756	2834	#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2835	#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2836	#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2837	#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2838
mbed_official	76:aeb1df146756	2839	#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
mbed_official	76:aeb1df146756	2840	#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2841	#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2842	#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	2843	#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	2844
mbed_official	76:aeb1df146756	2845	#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
mbed_official	76:aeb1df146756	2846	#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	2847	#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	2848
mbed_official	76:aeb1df146756	2849	/******************************************************************************/
mbed_official	76:aeb1df146756	2850	/* */
mbed_official	76:aeb1df146756	2851	/* General Purpose IOs (GPIO) */
mbed_official	76:aeb1df146756	2852	/* */
mbed_official	76:aeb1df146756	2853	/******************************************************************************/
mbed_official	76:aeb1df146756	2854	/***************** Bit definition for GPIO_MODER register ***************/
mbed_official	76:aeb1df146756	2855	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official	76:aeb1df146756	2856	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	2857	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	2858	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official	76:aeb1df146756	2859	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	2860	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	2861	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official	76:aeb1df146756	2862	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	2863	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	2864	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official	76:aeb1df146756	2865	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	2866	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	2867	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official	76:aeb1df146756	2868	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	2869	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	2870	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official	76:aeb1df146756	2871	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	2872	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	2873	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official	76:aeb1df146756	2874	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	2875	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	2876	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official	76:aeb1df146756	2877	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	2878	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	2879	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official	76:aeb1df146756	2880	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	2881	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	2882	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official	76:aeb1df146756	2883	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	2884	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	2885	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	2886	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	2887	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	2888	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official	76:aeb1df146756	2889	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	2890	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	2891	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official	76:aeb1df146756	2892	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	2893	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	2894	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official	76:aeb1df146756	2895	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	2896	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	2897	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official	76:aeb1df146756	2898	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	2899	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	2900	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official	76:aeb1df146756	2901	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	2902	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	2903
mbed_official	76:aeb1df146756	2904	/***************** Bit definition for GPIO_OTYPER register **************/
mbed_official	76:aeb1df146756	2905	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	2906	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	2907	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	2908	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	2909	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	2910	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	2911	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	2912	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	2913	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	2914	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	2915	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	2916	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	2917	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	2918	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	2919	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	2920	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	2921
mbed_official	76:aeb1df146756	2922	/***************** Bit definition for GPIO_OSPEEDR register *************/
mbed_official	76:aeb1df146756	2923	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official	76:aeb1df146756	2924	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	2925	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	2926	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official	76:aeb1df146756	2927	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	2928	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	2929	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official	76:aeb1df146756	2930	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	2931	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	2932	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official	76:aeb1df146756	2933	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	2934	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	2935	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official	76:aeb1df146756	2936	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	2937	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	2938	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official	76:aeb1df146756	2939	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	2940	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	2941	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official	76:aeb1df146756	2942	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	2943	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	2944	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official	76:aeb1df146756	2945	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	2946	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	2947	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official	76:aeb1df146756	2948	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	2949	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	2950	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official	76:aeb1df146756	2951	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	2952	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	2953	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	2954	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	2955	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	2956	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official	76:aeb1df146756	2957	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	2958	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	2959	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official	76:aeb1df146756	2960	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	2961	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	2962	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official	76:aeb1df146756	2963	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	2964	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	2965	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official	76:aeb1df146756	2966	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	2967	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	2968	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official	76:aeb1df146756	2969	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	2970	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	2971
mbed_official	76:aeb1df146756	2972	/***************** Bit definition for GPIO_PUPDR register ***************/
mbed_official	76:aeb1df146756	2973	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official	76:aeb1df146756	2974	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	2975	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	2976	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official	76:aeb1df146756	2977	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	2978	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	2979	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official	76:aeb1df146756	2980	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	2981	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	2982	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official	76:aeb1df146756	2983	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	2984	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	2985	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official	76:aeb1df146756	2986	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	2987	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	2988	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official	76:aeb1df146756	2989	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	2990	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	2991	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official	76:aeb1df146756	2992	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	2993	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	2994	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official	76:aeb1df146756	2995	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	2996	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	2997	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official	76:aeb1df146756	2998	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	2999	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3000	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official	76:aeb1df146756	3001	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3002	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3003	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	3004	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3005	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3006	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official	76:aeb1df146756	3007	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3008	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3009	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official	76:aeb1df146756	3010	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	3011	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	3012	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official	76:aeb1df146756	3013	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	3014	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	3015	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official	76:aeb1df146756	3016	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	3017	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	3018	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official	76:aeb1df146756	3019	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	3020	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	3021
mbed_official	76:aeb1df146756	3022	/**************** Bits definition for GPIO_IDR register *****************/
mbed_official	76:aeb1df146756	3023	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3024	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3025	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3026	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3027	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3028	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3029	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3030	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3031	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3032	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3033	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3034	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3035	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3036	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3037	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3038	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3039	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official	76:aeb1df146756	3040	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official	76:aeb1df146756	3041	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official	76:aeb1df146756	3042	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official	76:aeb1df146756	3043	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official	76:aeb1df146756	3044	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official	76:aeb1df146756	3045	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official	76:aeb1df146756	3046	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official	76:aeb1df146756	3047	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official	76:aeb1df146756	3048	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official	76:aeb1df146756	3049	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official	76:aeb1df146756	3050	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official	76:aeb1df146756	3051	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official	76:aeb1df146756	3052	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official	76:aeb1df146756	3053	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official	76:aeb1df146756	3054	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official	76:aeb1df146756	3055	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official	76:aeb1df146756	3056
mbed_official	76:aeb1df146756	3057	/**************** Bits definition for GPIO_ODR register *****************/
mbed_official	76:aeb1df146756	3058	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3059	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3060	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3061	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3062	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3063	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3064	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3065	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3066	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3067	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3068	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3069	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3070	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3071	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3072	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3073	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3074	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official	76:aeb1df146756	3075	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official	76:aeb1df146756	3076	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official	76:aeb1df146756	3077	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official	76:aeb1df146756	3078	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official	76:aeb1df146756	3079	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official	76:aeb1df146756	3080	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official	76:aeb1df146756	3081	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official	76:aeb1df146756	3082	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official	76:aeb1df146756	3083	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official	76:aeb1df146756	3084	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official	76:aeb1df146756	3085	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official	76:aeb1df146756	3086	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official	76:aeb1df146756	3087	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official	76:aeb1df146756	3088	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official	76:aeb1df146756	3089	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official	76:aeb1df146756	3090	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official	76:aeb1df146756	3091
mbed_official	76:aeb1df146756	3092	/***************** Bit definition for GPIO_BSRR register ****************/
mbed_official	76:aeb1df146756	3093	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3094	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3095	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3096	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3097	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3098	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3099	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3100	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3101	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3102	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3103	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3104	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3105	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3106	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3107	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3108	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3109	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3110	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3111	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3112	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3113	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3114	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3115	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3116	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3117	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	3118	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	3119	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	3120	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	3121	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	3122	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	3123	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	3124	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	3125
mbed_official	76:aeb1df146756	3126	/***************** Bit definition for GPIO_LCKR register ****************/
mbed_official	76:aeb1df146756	3127	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3128	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3129	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3130	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3131	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3132	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3133	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3134	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3135	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3136	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3137	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3138	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3139	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3140	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3141	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3142	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3143	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3144
mbed_official	76:aeb1df146756	3145	/***************** Bit definition for GPIO_AFRL register ****************/
mbed_official	76:aeb1df146756	3146	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3147	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official	76:aeb1df146756	3148	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3149	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official	76:aeb1df146756	3150	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3151	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official	76:aeb1df146756	3152	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	3153	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official	76:aeb1df146756	3154
mbed_official	76:aeb1df146756	3155	/***************** Bit definition for GPIO_AFRH register ****************/
mbed_official	76:aeb1df146756	3156	#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3157	#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)
mbed_official	76:aeb1df146756	3158	#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3159	#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)
mbed_official	76:aeb1df146756	3160	#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3161	#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)
mbed_official	76:aeb1df146756	3162	#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	3163	#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)
mbed_official	76:aeb1df146756	3164
mbed_official	76:aeb1df146756	3165	/******************************************************************************/
mbed_official	76:aeb1df146756	3166	/* */
mbed_official	76:aeb1df146756	3167	/* Inter-integrated Circuit Interface (I2C) */
mbed_official	76:aeb1df146756	3168	/* */
mbed_official	76:aeb1df146756	3169	/******************************************************************************/
mbed_official	76:aeb1df146756	3170
mbed_official	76:aeb1df146756	3171	/***************** Bit definition for I2C_CR1 register ******************/
mbed_official	76:aeb1df146756	3172	#define I2C_CR1_PE ((uint16_t)0x0001) /!< Peripheral Enable /
mbed_official	76:aeb1df146756	3173	#define I2C_CR1_SMBUS ((uint16_t)0x0002) /!< SMBus Mode /
mbed_official	76:aeb1df146756	3174	#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /!< SMBus Type /
mbed_official	76:aeb1df146756	3175	#define I2C_CR1_ENARP ((uint16_t)0x0010) /!< ARP Enable /
mbed_official	76:aeb1df146756	3176	#define I2C_CR1_ENPEC ((uint16_t)0x0020) /!< PEC Enable /
mbed_official	76:aeb1df146756	3177	#define I2C_CR1_ENGC ((uint16_t)0x0040) /!< General Call Enable /
mbed_official	76:aeb1df146756	3178	#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /!< Clock Stretching Disable (Slave mode) /
mbed_official	76:aeb1df146756	3179	#define I2C_CR1_START ((uint16_t)0x0100) /!< Start Generation /
mbed_official	76:aeb1df146756	3180	#define I2C_CR1_STOP ((uint16_t)0x0200) /!< Stop Generation /
mbed_official	76:aeb1df146756	3181	#define I2C_CR1_ACK ((uint16_t)0x0400) /!< Acknowledge Enable /
mbed_official	76:aeb1df146756	3182	#define I2C_CR1_POS ((uint16_t)0x0800) /!< Acknowledge/PEC Position (for data reception) /
mbed_official	76:aeb1df146756	3183	#define I2C_CR1_PEC ((uint16_t)0x1000) /!< Packet Error Checking /
mbed_official	76:aeb1df146756	3184	#define I2C_CR1_ALERT ((uint16_t)0x2000) /!< SMBus Alert /
mbed_official	76:aeb1df146756	3185	#define I2C_CR1_SWRST ((uint16_t)0x8000) /!< Software Reset /
mbed_official	76:aeb1df146756	3186
mbed_official	76:aeb1df146756	3187	/***************** Bit definition for I2C_CR2 register ******************/
mbed_official	76:aeb1df146756	3188	#define I2C_CR2_FREQ ((uint16_t)0x003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
mbed_official	76:aeb1df146756	3189	#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /!< Bit 0 /
mbed_official	76:aeb1df146756	3190	#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /!< Bit 1 /
mbed_official	76:aeb1df146756	3191	#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /!< Bit 2 /
mbed_official	76:aeb1df146756	3192	#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /!< Bit 3 /
mbed_official	76:aeb1df146756	3193	#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /!< Bit 4 /
mbed_official	76:aeb1df146756	3194	#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /!< Bit 5 /
mbed_official	76:aeb1df146756	3195
mbed_official	76:aeb1df146756	3196	#define I2C_CR2_ITERREN ((uint16_t)0x0100) /!< Error Interrupt Enable /
mbed_official	76:aeb1df146756	3197	#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /!< Event Interrupt Enable /
mbed_official	76:aeb1df146756	3198	#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /!< Buffer Interrupt Enable /
mbed_official	76:aeb1df146756	3199	#define I2C_CR2_DMAEN ((uint16_t)0x0800) /!< DMA Requests Enable /
mbed_official	76:aeb1df146756	3200	#define I2C_CR2_LAST ((uint16_t)0x1000) /!< DMA Last Transfer /
mbed_official	76:aeb1df146756	3201
mbed_official	76:aeb1df146756	3202	/***************** Bit definition for I2C_OAR1 register *****************/
mbed_official	76:aeb1df146756	3203	#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /!< Interface Address /
mbed_official	76:aeb1df146756	3204	#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /!< Interface Address /
mbed_official	76:aeb1df146756	3205
mbed_official	76:aeb1df146756	3206	#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /!< Bit 0 /
mbed_official	76:aeb1df146756	3207	#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /!< Bit 1 /
mbed_official	76:aeb1df146756	3208	#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /!< Bit 2 /
mbed_official	76:aeb1df146756	3209	#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /!< Bit 3 /
mbed_official	76:aeb1df146756	3210	#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /!< Bit 4 /
mbed_official	76:aeb1df146756	3211	#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /!< Bit 5 /
mbed_official	76:aeb1df146756	3212	#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /!< Bit 6 /
mbed_official	76:aeb1df146756	3213	#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /!< Bit 7 /
mbed_official	76:aeb1df146756	3214	#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /!< Bit 8 /
mbed_official	76:aeb1df146756	3215	#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /!< Bit 9 /
mbed_official	76:aeb1df146756	3216
mbed_official	76:aeb1df146756	3217	#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /!< Addressing Mode (Slave mode) /
mbed_official	76:aeb1df146756	3218
mbed_official	76:aeb1df146756	3219	/***************** Bit definition for I2C_OAR2 register *****************/
mbed_official	76:aeb1df146756	3220	#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /!< Dual addressing mode enable /
mbed_official	76:aeb1df146756	3221	#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /!< Interface address /
mbed_official	76:aeb1df146756	3222
mbed_official	76:aeb1df146756	3223	/****************** Bit definition for I2C_DR register ******************/
mbed_official	76:aeb1df146756	3224	#define I2C_DR_DR ((uint8_t)0xFF) /!< 8-bit Data Register /
mbed_official	76:aeb1df146756	3225
mbed_official	76:aeb1df146756	3226	/***************** Bit definition for I2C_SR1 register ******************/
mbed_official	76:aeb1df146756	3227	#define I2C_SR1_SB ((uint16_t)0x0001) /!< Start Bit (Master mode) /
mbed_official	76:aeb1df146756	3228	#define I2C_SR1_ADDR ((uint16_t)0x0002) /!< Address sent (master mode)/matched (slave mode) /
mbed_official	76:aeb1df146756	3229	#define I2C_SR1_BTF ((uint16_t)0x0004) /!< Byte Transfer Finished /
mbed_official	76:aeb1df146756	3230	#define I2C_SR1_ADD10 ((uint16_t)0x0008) /!< 10-bit header sent (Master mode) /
mbed_official	76:aeb1df146756	3231	#define I2C_SR1_STOPF ((uint16_t)0x0010) /!< Stop detection (Slave mode) /
mbed_official	76:aeb1df146756	3232	#define I2C_SR1_RXNE ((uint16_t)0x0040) /!< Data Register not Empty (receivers) /
mbed_official	76:aeb1df146756	3233	#define I2C_SR1_TXE ((uint16_t)0x0080) /!< Data Register Empty (transmitters) /
mbed_official	76:aeb1df146756	3234	#define I2C_SR1_BERR ((uint16_t)0x0100) /!< Bus Error /
mbed_official	76:aeb1df146756	3235	#define I2C_SR1_ARLO ((uint16_t)0x0200) /!< Arbitration Lost (master mode) /
mbed_official	76:aeb1df146756	3236	#define I2C_SR1_AF ((uint16_t)0x0400) /!< Acknowledge Failure /
mbed_official	76:aeb1df146756	3237	#define I2C_SR1_OVR ((uint16_t)0x0800) /!< Overrun/Underrun /
mbed_official	76:aeb1df146756	3238	#define I2C_SR1_PECERR ((uint16_t)0x1000) /!< PEC Error in reception /
mbed_official	76:aeb1df146756	3239	#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /!< Timeout or Tlow Error /
mbed_official	76:aeb1df146756	3240	#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /!< SMBus Alert /
mbed_official	76:aeb1df146756	3241
mbed_official	76:aeb1df146756	3242	/***************** Bit definition for I2C_SR2 register ******************/
mbed_official	76:aeb1df146756	3243	#define I2C_SR2_MSL ((uint16_t)0x0001) /!< Master/Slave /
mbed_official	76:aeb1df146756	3244	#define I2C_SR2_BUSY ((uint16_t)0x0002) /!< Bus Busy /
mbed_official	76:aeb1df146756	3245	#define I2C_SR2_TRA ((uint16_t)0x0004) /!< Transmitter/Receiver /
mbed_official	76:aeb1df146756	3246	#define I2C_SR2_GENCALL ((uint16_t)0x0010) /!< General Call Address (Slave mode) /
mbed_official	76:aeb1df146756	3247	#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /!< SMBus Device Default Address (Slave mode) /
mbed_official	76:aeb1df146756	3248	#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /!< SMBus Host Header (Slave mode) /
mbed_official	76:aeb1df146756	3249	#define I2C_SR2_DUALF ((uint16_t)0x0080) /!< Dual Flag (Slave mode) /
mbed_official	76:aeb1df146756	3250	#define I2C_SR2_PEC ((uint16_t)0xFF00) /!< Packet Error Checking Register /
mbed_official	76:aeb1df146756	3251
mbed_official	76:aeb1df146756	3252	/***************** Bit definition for I2C_CCR register ******************/
mbed_official	76:aeb1df146756	3253	#define I2C_CCR_CCR ((uint16_t)0x0FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
mbed_official	76:aeb1df146756	3254	#define I2C_CCR_DUTY ((uint16_t)0x4000) /!< Fast Mode Duty Cycle /
mbed_official	76:aeb1df146756	3255	#define I2C_CCR_FS ((uint16_t)0x8000) /!< I2C Master Mode Selection /
mbed_official	76:aeb1df146756	3256
mbed_official	76:aeb1df146756	3257	/**************** Bit definition for I2C_TRISE register *****************/
mbed_official	76:aeb1df146756	3258	#define I2C_TRISE_TRISE ((uint8_t)0x3F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
mbed_official	76:aeb1df146756	3259
mbed_official	76:aeb1df146756	3260	/******************************************************************************/
mbed_official	76:aeb1df146756	3261	/* */
mbed_official	76:aeb1df146756	3262	/* Independent WATCHDOG (IWDG) */
mbed_official	76:aeb1df146756	3263	/* */
mbed_official	76:aeb1df146756	3264	/******************************************************************************/
mbed_official	76:aeb1df146756	3265
mbed_official	76:aeb1df146756	3266	/***************** Bit definition for IWDG_KR register ******************/
mbed_official	76:aeb1df146756	3267	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!< Key value (write only, read 0000h) /
mbed_official	76:aeb1df146756	3268
mbed_official	76:aeb1df146756	3269	/***************** Bit definition for IWDG_PR register ******************/
mbed_official	76:aeb1df146756	3270	#define IWDG_PR_PR ((uint8_t)0x07) /!< PR[2:0] (Prescaler divider) /
mbed_official	76:aeb1df146756	3271	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!< Bit 0 /
mbed_official	76:aeb1df146756	3272	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!< Bit 1 /
mbed_official	76:aeb1df146756	3273	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!< Bit 2 /
mbed_official	76:aeb1df146756	3274
mbed_official	76:aeb1df146756	3275	/***************** Bit definition for IWDG_RLR register *****************/
mbed_official	76:aeb1df146756	3276	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!< Watchdog counter reload value /
mbed_official	76:aeb1df146756	3277
mbed_official	76:aeb1df146756	3278	/***************** Bit definition for IWDG_SR register ******************/
mbed_official	76:aeb1df146756	3279	#define IWDG_SR_PVU ((uint8_t)0x01) /!< Watchdog prescaler value update /
mbed_official	76:aeb1df146756	3280	#define IWDG_SR_RVU ((uint8_t)0x02) /!< Watchdog counter reload value update /
mbed_official	76:aeb1df146756	3281
mbed_official	76:aeb1df146756	3282	/******************************************************************************/
mbed_official	76:aeb1df146756	3283	/* */
mbed_official	76:aeb1df146756	3284	/* LCD Controller (LCD) */
mbed_official	76:aeb1df146756	3285	/* */
mbed_official	76:aeb1df146756	3286	/******************************************************************************/
mbed_official	76:aeb1df146756	3287
mbed_official	76:aeb1df146756	3288	/***************** Bit definition for LCD_CR register *******************/
mbed_official	76:aeb1df146756	3289	#define LCD_CR_LCDEN ((uint32_t)0x00000001) /!< LCD Enable Bit /
mbed_official	76:aeb1df146756	3290	#define LCD_CR_VSEL ((uint32_t)0x00000002) /!< Voltage source selector Bit /
mbed_official	76:aeb1df146756	3291
mbed_official	76:aeb1df146756	3292	#define LCD_CR_DUTY ((uint32_t)0x0000001C) /!< DUTY[2:0] bits (Duty selector) /
mbed_official	76:aeb1df146756	3293	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /!< Duty selector Bit 0 /
mbed_official	76:aeb1df146756	3294	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /!< Duty selector Bit 1 /
mbed_official	76:aeb1df146756	3295	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /!< Duty selector Bit 2 /
mbed_official	76:aeb1df146756	3296
mbed_official	76:aeb1df146756	3297	#define LCD_CR_BIAS ((uint32_t)0x00000060) /!< BIAS[1:0] bits (Bias selector) /
mbed_official	76:aeb1df146756	3298	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /!< Bias selector Bit 0 /
mbed_official	76:aeb1df146756	3299	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /!< Bias selector Bit 1 /
mbed_official	76:aeb1df146756	3300
mbed_official	76:aeb1df146756	3301	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /!< Mux Segment Enable Bit /
mbed_official	76:aeb1df146756	3302
mbed_official	76:aeb1df146756	3303	/***************** Bit definition for LCD_FCR register ******************/
mbed_official	76:aeb1df146756	3304	#define LCD_FCR_HD ((uint32_t)0x00000001) /!< High Drive Enable Bit /
mbed_official	76:aeb1df146756	3305	#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /!< Start of Frame Interrupt Enable Bit /
mbed_official	76:aeb1df146756	3306	#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /!< Update Display Done Interrupt Enable Bit /
mbed_official	76:aeb1df146756	3307
mbed_official	76:aeb1df146756	3308	#define LCD_FCR_PON ((uint32_t)0x00000070) /!< PON[2:0] bits (Puls ON Duration) /
mbed_official	76:aeb1df146756	3309	#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	3310	#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	3311	#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	3312
mbed_official	76:aeb1df146756	3313	#define LCD_FCR_DEAD ((uint32_t)0x00000380) /!< DEAD[2:0] bits (DEAD Time) /
mbed_official	76:aeb1df146756	3314	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /!< Bit 0 /
mbed_official	76:aeb1df146756	3315	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /!< Bit 1 /
mbed_official	76:aeb1df146756	3316	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /!< Bit 2 /
mbed_official	76:aeb1df146756	3317
mbed_official	76:aeb1df146756	3318	#define LCD_FCR_CC ((uint32_t)0x00001C00) /!< CC[2:0] bits (Contrast Control) /
mbed_official	76:aeb1df146756	3319	#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	3320	#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	3321	#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3322
mbed_official	76:aeb1df146756	3323	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /!< BLINKF[2:0] bits (Blink Frequency) /
mbed_official	76:aeb1df146756	3324	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3325	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3326	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3327
mbed_official	76:aeb1df146756	3328	#define LCD_FCR_BLINK ((uint32_t)0x00030000) /!< BLINK[1:0] bits (Blink Enable) /
mbed_official	76:aeb1df146756	3329	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3330	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3331
mbed_official	76:aeb1df146756	3332	#define LCD_FCR_DIV ((uint32_t)0x003C0000) /!< DIV[3:0] bits (Divider) /
mbed_official	76:aeb1df146756	3333	#define LCD_FCR_PS ((uint32_t)0x03C00000) /!< PS[3:0] bits (Prescaler) /
mbed_official	76:aeb1df146756	3334
mbed_official	76:aeb1df146756	3335	/***************** Bit definition for LCD_SR register *******************/
mbed_official	76:aeb1df146756	3336	#define LCD_SR_ENS ((uint32_t)0x00000001) /!< LCD Enabled Bit /
mbed_official	76:aeb1df146756	3337	#define LCD_SR_SOF ((uint32_t)0x00000002) /!< Start Of Frame Flag Bit /
mbed_official	76:aeb1df146756	3338	#define LCD_SR_UDR ((uint32_t)0x00000004) /!< Update Display Request Bit /
mbed_official	76:aeb1df146756	3339	#define LCD_SR_UDD ((uint32_t)0x00000008) /!< Update Display Done Flag Bit /
mbed_official	76:aeb1df146756	3340	#define LCD_SR_RDY ((uint32_t)0x00000010) /!< Ready Flag Bit /
mbed_official	76:aeb1df146756	3341	#define LCD_SR_FCRSR ((uint32_t)0x00000020) /!< LCD FCR Register Synchronization Flag Bit /
mbed_official	76:aeb1df146756	3342
mbed_official	76:aeb1df146756	3343	/***************** Bit definition for LCD_CLR register ******************/
mbed_official	76:aeb1df146756	3344	#define LCD_CLR_SOFC ((uint32_t)0x00000002) /!< Start Of Frame Flag Clear Bit /
mbed_official	76:aeb1df146756	3345	#define LCD_CLR_UDDC ((uint32_t)0x00000008) /!< Update Display Done Flag Clear Bit /
mbed_official	76:aeb1df146756	3346
mbed_official	76:aeb1df146756	3347	/***************** Bit definition for LCD_RAM register ******************/
mbed_official	76:aeb1df146756	3348	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /!< Segment Data Bits /
mbed_official	76:aeb1df146756	3349
mbed_official	76:aeb1df146756	3350	/******************************************************************************/
mbed_official	76:aeb1df146756	3351	/* */
mbed_official	76:aeb1df146756	3352	/* Power Control (PWR) */
mbed_official	76:aeb1df146756	3353	/* */
mbed_official	76:aeb1df146756	3354	/******************************************************************************/
mbed_official	76:aeb1df146756	3355
mbed_official	76:aeb1df146756	3356	/****************** Bit definition for PWR_CR register ******************/
mbed_official	76:aeb1df146756	3357	#define PWR_CR_LPSDSR ((uint16_t)0x0001) /!< Low-power deepsleep/sleep/low power run /
mbed_official	76:aeb1df146756	3358	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
mbed_official	76:aeb1df146756	3359	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
mbed_official	76:aeb1df146756	3360	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
mbed_official	76:aeb1df146756	3361	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
mbed_official	76:aeb1df146756	3362
mbed_official	76:aeb1df146756	3363	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
mbed_official	76:aeb1df146756	3364	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
mbed_official	76:aeb1df146756	3365	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
mbed_official	76:aeb1df146756	3366	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
mbed_official	76:aeb1df146756	3367
mbed_official	76:aeb1df146756	3368	/!< PVD level configuration /
mbed_official	76:aeb1df146756	3369	#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /!< PVD level 0 /
mbed_official	76:aeb1df146756	3370	#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /!< PVD level 1 /
mbed_official	76:aeb1df146756	3371	#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /!< PVD level 2 /
mbed_official	76:aeb1df146756	3372	#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /!< PVD level 3 /
mbed_official	76:aeb1df146756	3373	#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /!< PVD level 4 /
mbed_official	76:aeb1df146756	3374	#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /!< PVD level 5 /
mbed_official	76:aeb1df146756	3375	#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /!< PVD level 6 /
mbed_official	76:aeb1df146756	3376	#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /!< PVD level 7 /
mbed_official	76:aeb1df146756	3377
mbed_official	76:aeb1df146756	3378	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
mbed_official	76:aeb1df146756	3379	#define PWR_CR_ULP ((uint16_t)0x0200) /!< Ultra Low Power mode /
mbed_official	76:aeb1df146756	3380	#define PWR_CR_FWU ((uint16_t)0x0400) /!< Fast wakeup /
mbed_official	76:aeb1df146756	3381
mbed_official	76:aeb1df146756	3382	#define PWR_CR_VOS ((uint16_t)0x1800) /!< VOS[1:0] bits (Voltage scaling range selection) /
mbed_official	76:aeb1df146756	3383	#define PWR_CR_VOS_0 ((uint16_t)0x0800) /!< Bit 0 /
mbed_official	76:aeb1df146756	3384	#define PWR_CR_VOS_1 ((uint16_t)0x1000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3385	#define PWR_CR_LPRUN ((uint16_t)0x4000) /!< Low power run mode /
mbed_official	76:aeb1df146756	3386
mbed_official	76:aeb1df146756	3387	/***************** Bit definition for PWR_CSR register ******************/
mbed_official	76:aeb1df146756	3388	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
mbed_official	76:aeb1df146756	3389	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
mbed_official	76:aeb1df146756	3390	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
mbed_official	76:aeb1df146756	3391	#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /!< Internal voltage reference (VREFINT) ready flag /
mbed_official	76:aeb1df146756	3392	#define PWR_CSR_VOSF ((uint16_t)0x0010) /!< Voltage Scaling select flag /
mbed_official	76:aeb1df146756	3393	#define PWR_CSR_REGLPF ((uint16_t)0x0020) /!< Regulator LP flag /
mbed_official	76:aeb1df146756	3394
mbed_official	76:aeb1df146756	3395	#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /!< Enable WKUP pin 1 /
mbed_official	76:aeb1df146756	3396	#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /!< Enable WKUP pin 2 /
mbed_official	76:aeb1df146756	3397	#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /!< Enable WKUP pin 3 /
mbed_official	76:aeb1df146756	3398
mbed_official	76:aeb1df146756	3399	/******************************************************************************/
mbed_official	76:aeb1df146756	3400	/* */
mbed_official	76:aeb1df146756	3401	/* Reset and Clock Control (RCC) */
mbed_official	76:aeb1df146756	3402	/* */
mbed_official	76:aeb1df146756	3403	/******************************************************************************/
mbed_official	76:aeb1df146756	3404	/****************** Bit definition for RCC_CR register ******************/
mbed_official	76:aeb1df146756	3405	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
mbed_official	76:aeb1df146756	3406	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
mbed_official	76:aeb1df146756	3407
mbed_official	76:aeb1df146756	3408	#define RCC_CR_MSION ((uint32_t)0x00000100) /!< Internal Multi Speed clock enable /
mbed_official	76:aeb1df146756	3409	#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /!< Internal Multi Speed clock ready flag /
mbed_official	76:aeb1df146756	3410
mbed_official	76:aeb1df146756	3411	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
mbed_official	76:aeb1df146756	3412	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
mbed_official	76:aeb1df146756	3413	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
mbed_official	76:aeb1df146756	3414
mbed_official	76:aeb1df146756	3415	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
mbed_official	76:aeb1df146756	3416	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
mbed_official	76:aeb1df146756	3417	#define RCC_CR_CSSON ((uint32_t)0x10000000) /!< Clock Security System enable /
mbed_official	76:aeb1df146756	3418
mbed_official	76:aeb1df146756	3419	#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /!< RTC/LCD Prescaler /
mbed_official	76:aeb1df146756	3420	#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /!< Bit0 /
mbed_official	76:aeb1df146756	3421	#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /!< Bit1 /
mbed_official	76:aeb1df146756	3422
mbed_official	76:aeb1df146756	3423	/****************** Bit definition for RCC_ICSCR register ***************/
mbed_official	76:aeb1df146756	3424	#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /!< Internal High Speed clock Calibration /
mbed_official	76:aeb1df146756	3425	#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /!< Internal High Speed clock trimming /
mbed_official	76:aeb1df146756	3426
mbed_official	76:aeb1df146756	3427	#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /!< Internal Multi Speed clock Range /
mbed_official	76:aeb1df146756	3428	#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /!< Internal Multi Speed clock Range 65.536 KHz /
mbed_official	76:aeb1df146756	3429	#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /!< Internal Multi Speed clock Range 131.072 KHz /
mbed_official	76:aeb1df146756	3430	#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /!< Internal Multi Speed clock Range 262.144 KHz /
mbed_official	76:aeb1df146756	3431	#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /!< Internal Multi Speed clock Range 524.288 KHz /
mbed_official	76:aeb1df146756	3432	#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /!< Internal Multi Speed clock Range 1.048 MHz /
mbed_official	76:aeb1df146756	3433	#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /!< Internal Multi Speed clock Range 2.097 MHz /
mbed_official	76:aeb1df146756	3434	#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /!< Internal Multi Speed clock Range 4.194 MHz /
mbed_official	76:aeb1df146756	3435	#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /!< Internal Multi Speed clock Calibration /
mbed_official	76:aeb1df146756	3436	#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /!< Internal Multi Speed clock trimming /
mbed_official	76:aeb1df146756	3437
mbed_official	76:aeb1df146756	3438	/****************** Bit definition for RCC_CFGR register ****************/
mbed_official	76:aeb1df146756	3439	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
mbed_official	76:aeb1df146756	3440	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	3441	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	3442
mbed_official	76:aeb1df146756	3443	/!< SW configuration /
mbed_official	76:aeb1df146756	3444	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /!< MSI selected as system clock /
mbed_official	76:aeb1df146756	3445	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /!< HSI selected as system clock /
mbed_official	76:aeb1df146756	3446	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /!< HSE selected as system clock /
mbed_official	76:aeb1df146756	3447	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /!< PLL selected as system clock /
mbed_official	76:aeb1df146756	3448
mbed_official	76:aeb1df146756	3449	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
mbed_official	76:aeb1df146756	3450	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	76:aeb1df146756	3451	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	76:aeb1df146756	3452
mbed_official	76:aeb1df146756	3453	/!< SWS configuration /
mbed_official	76:aeb1df146756	3454	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /!< MSI oscillator used as system clock /
mbed_official	76:aeb1df146756	3455	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /!< HSI oscillator used as system clock /
mbed_official	76:aeb1df146756	3456	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /!< HSE oscillator used as system clock /
mbed_official	76:aeb1df146756	3457	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /!< PLL used as system clock /
mbed_official	76:aeb1df146756	3458
mbed_official	76:aeb1df146756	3459	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
mbed_official	76:aeb1df146756	3460	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	3461	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	3462	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	3463	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	3464
mbed_official	76:aeb1df146756	3465	/!< HPRE configuration /
mbed_official	76:aeb1df146756	3466	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
mbed_official	76:aeb1df146756	3467	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
mbed_official	76:aeb1df146756	3468	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
mbed_official	76:aeb1df146756	3469	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
mbed_official	76:aeb1df146756	3470	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
mbed_official	76:aeb1df146756	3471	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
mbed_official	76:aeb1df146756	3472	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
mbed_official	76:aeb1df146756	3473	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
mbed_official	76:aeb1df146756	3474	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
mbed_official	76:aeb1df146756	3475
mbed_official	76:aeb1df146756	3476	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
mbed_official	76:aeb1df146756	3477	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	3478	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	3479	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	3480
mbed_official	76:aeb1df146756	3481	/!< PPRE1 configuration /
mbed_official	76:aeb1df146756	3482	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
mbed_official	76:aeb1df146756	3483	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
mbed_official	76:aeb1df146756	3484	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
mbed_official	76:aeb1df146756	3485	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
mbed_official	76:aeb1df146756	3486	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
mbed_official	76:aeb1df146756	3487
mbed_official	76:aeb1df146756	3488	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
mbed_official	76:aeb1df146756	3489	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
mbed_official	76:aeb1df146756	3490	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3491	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3492
mbed_official	76:aeb1df146756	3493	/!< PPRE2 configuration /
mbed_official	76:aeb1df146756	3494	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
mbed_official	76:aeb1df146756	3495	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
mbed_official	76:aeb1df146756	3496	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
mbed_official	76:aeb1df146756	3497	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
mbed_official	76:aeb1df146756	3498	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
mbed_official	76:aeb1df146756	3499
mbed_official	76:aeb1df146756	3500	/!< PLL entry clock source/
mbed_official	76:aeb1df146756	3501	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
mbed_official	76:aeb1df146756	3502
mbed_official	76:aeb1df146756	3503	#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /!< HSI as PLL entry clock source /
mbed_official	76:aeb1df146756	3504	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /!< HSE as PLL entry clock source /
mbed_official	76:aeb1df146756	3505
mbed_official	76:aeb1df146756	3506
mbed_official	76:aeb1df146756	3507	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
mbed_official	76:aeb1df146756	3508	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3509	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3510	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3511	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
mbed_official	76:aeb1df146756	3512
mbed_official	76:aeb1df146756	3513	/!< PLLMUL configuration /
mbed_official	76:aeb1df146756	3514	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /!< PLL input clock 3 */
mbed_official	76:aeb1df146756	3515	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /!< PLL input clock 4 */
mbed_official	76:aeb1df146756	3516	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /!< PLL input clock 6 */
mbed_official	76:aeb1df146756	3517	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /!< PLL input clock 8 */
mbed_official	76:aeb1df146756	3518	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /!< PLL input clock 12 */
mbed_official	76:aeb1df146756	3519	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /!< PLL input clock 16 */
mbed_official	76:aeb1df146756	3520	#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /!< PLL input clock 24 */
mbed_official	76:aeb1df146756	3521	#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /!< PLL input clock 32 */
mbed_official	76:aeb1df146756	3522	#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /!< PLL input clock 48 */
mbed_official	76:aeb1df146756	3523
mbed_official	76:aeb1df146756	3524	/!< PLLDIV configuration /
mbed_official	76:aeb1df146756	3525	#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /!< PLLDIV[1:0] bits (PLL Output Division) /
mbed_official	76:aeb1df146756	3526	#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /!< Bit0 /
mbed_official	76:aeb1df146756	3527	#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /!< Bit1 /
mbed_official	76:aeb1df146756	3528
mbed_official	76:aeb1df146756	3529
mbed_official	76:aeb1df146756	3530	/!< PLLDIV configuration /
mbed_official	76:aeb1df146756	3531	#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /!< PLL clock output = CKVCO / 1 /
mbed_official	76:aeb1df146756	3532	#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /!< PLL clock output = CKVCO / 2 /
mbed_official	76:aeb1df146756	3533	#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /!< PLL clock output = CKVCO / 3 /
mbed_official	76:aeb1df146756	3534	#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /!< PLL clock output = CKVCO / 4 /
mbed_official	76:aeb1df146756	3535
mbed_official	76:aeb1df146756	3536
mbed_official	76:aeb1df146756	3537	#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
mbed_official	76:aeb1df146756	3538	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3539	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3540	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3541
mbed_official	76:aeb1df146756	3542	/!< MCO configuration /
mbed_official	76:aeb1df146756	3543	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	76:aeb1df146756	3544	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /!< System clock selected /
mbed_official	76:aeb1df146756	3545	#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /!< Internal 16 MHz RC oscillator clock selected /
mbed_official	76:aeb1df146756	3546	#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /!< Internal Medium Speed RC oscillator clock selected /
mbed_official	76:aeb1df146756	3547	#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /!< External 1-25 MHz oscillator clock selected /
mbed_official	76:aeb1df146756	3548	#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /!< PLL clock divided /
mbed_official	76:aeb1df146756	3549	#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /!< LSI selected /
mbed_official	76:aeb1df146756	3550	#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /!< LSE selected /
mbed_official	76:aeb1df146756	3551
mbed_official	76:aeb1df146756	3552	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) /
mbed_official	76:aeb1df146756	3553	#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3554	#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3555	#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	3556
mbed_official	76:aeb1df146756	3557	/!< MCO Prescaler configuration /
mbed_official	76:aeb1df146756	3558	#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /!< MCO Clock divided by 1 /
mbed_official	76:aeb1df146756	3559	#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /!< MCO Clock divided by 2 /
mbed_official	76:aeb1df146756	3560	#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /!< MCO Clock divided by 4 /
mbed_official	76:aeb1df146756	3561	#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /!< MCO Clock divided by 8 /
mbed_official	76:aeb1df146756	3562	#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /!< MCO Clock divided by 16 /
mbed_official	76:aeb1df146756	3563
mbed_official	76:aeb1df146756	3564	/!<*************** Bit definition for RCC_CIR register ******************/
mbed_official	76:aeb1df146756	3565	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
mbed_official	76:aeb1df146756	3566	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
mbed_official	76:aeb1df146756	3567	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
mbed_official	76:aeb1df146756	3568	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
mbed_official	76:aeb1df146756	3569	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
mbed_official	76:aeb1df146756	3570	#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /!< MSI Ready Interrupt flag /
mbed_official	76:aeb1df146756	3571	#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /!< LSE CSS Interrupt flag /
mbed_official	76:aeb1df146756	3572	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
mbed_official	76:aeb1df146756	3573
mbed_official	76:aeb1df146756	3574	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3575	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3576	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3577	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3578	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3579	#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /!< MSI Ready Interrupt Enable /
mbed_official	76:aeb1df146756	3580	#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /!< LSE CSS Interrupt Enable /
mbed_official	76:aeb1df146756	3581
mbed_official	76:aeb1df146756	3582	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3583	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3584	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3585	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3586	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3587	#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /!< MSI Ready Interrupt Clear /
mbed_official	76:aeb1df146756	3588	#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /!< LSE CSS Interrupt Clear /
mbed_official	76:aeb1df146756	3589	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
mbed_official	76:aeb1df146756	3590
mbed_official	76:aeb1df146756	3591
mbed_official	76:aeb1df146756	3592	/*************** Bit definition for RCC_AHBRSTR register ****************/
mbed_official	76:aeb1df146756	3593	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /!< GPIO port A reset /
mbed_official	76:aeb1df146756	3594	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /!< GPIO port B reset /
mbed_official	76:aeb1df146756	3595	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /!< GPIO port C reset /
mbed_official	76:aeb1df146756	3596	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /!< GPIO port D reset /
mbed_official	76:aeb1df146756	3597	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /!< GPIO port E reset /
mbed_official	76:aeb1df146756	3598	#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /!< GPIO port H reset /
mbed_official	76:aeb1df146756	3599	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /!< GPIO port F reset /
mbed_official	76:aeb1df146756	3600	#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /!< GPIO port G reset /
mbed_official	76:aeb1df146756	3601	#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /!< CRC reset /
mbed_official	76:aeb1df146756	3602	#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /!< FLITF reset /
mbed_official	76:aeb1df146756	3603	#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /!< DMA1 reset /
mbed_official	76:aeb1df146756	3604	#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /!< DMA2 reset /
mbed_official	76:aeb1df146756	3605	#define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) /!< AES reset /
mbed_official	76:aeb1df146756	3606	#define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) /!< FSMC reset /
mbed_official	76:aeb1df146756	3607
mbed_official	76:aeb1df146756	3608	/*************** Bit definition for RCC_APB2RSTR register ***************/
mbed_official	76:aeb1df146756	3609	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< System Configuration SYSCFG reset /
mbed_official	76:aeb1df146756	3610	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /!< TIM9 reset /
mbed_official	76:aeb1df146756	3611	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /!< TIM10 reset /
mbed_official	76:aeb1df146756	3612	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /!< TIM11 reset /
mbed_official	76:aeb1df146756	3613	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC1 reset /
mbed_official	76:aeb1df146756	3614	#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) /!< SDIO reset /
mbed_official	76:aeb1df146756	3615	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 reset /
mbed_official	76:aeb1df146756	3616	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
mbed_official	76:aeb1df146756	3617
mbed_official	76:aeb1df146756	3618	/*************** Bit definition for RCC_APB1RSTR register ***************/
mbed_official	76:aeb1df146756	3619	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
mbed_official	76:aeb1df146756	3620	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
mbed_official	76:aeb1df146756	3621	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
mbed_official	76:aeb1df146756	3622	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
mbed_official	76:aeb1df146756	3623	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
mbed_official	76:aeb1df146756	3624	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
mbed_official	76:aeb1df146756	3625	#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /!< LCD reset /
mbed_official	76:aeb1df146756	3626	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
mbed_official	76:aeb1df146756	3627	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
mbed_official	76:aeb1df146756	3628	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
mbed_official	76:aeb1df146756	3629	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
mbed_official	76:aeb1df146756	3630	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
mbed_official	76:aeb1df146756	3631	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
mbed_official	76:aeb1df146756	3632	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
mbed_official	76:aeb1df146756	3633	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
mbed_official	76:aeb1df146756	3634	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
mbed_official	76:aeb1df146756	3635	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB reset /
mbed_official	76:aeb1df146756	3636	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
mbed_official	76:aeb1df146756	3637	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
mbed_official	76:aeb1df146756	3638	#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /!< Comparator interface reset /
mbed_official	76:aeb1df146756	3639
mbed_official	76:aeb1df146756	3640	/**************** Bit definition for RCC_AHBENR register ****************/
mbed_official	76:aeb1df146756	3641	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /!< GPIO port A clock enable /
mbed_official	76:aeb1df146756	3642	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /!< GPIO port B clock enable /
mbed_official	76:aeb1df146756	3643	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /!< GPIO port C clock enable /
mbed_official	76:aeb1df146756	3644	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /!< GPIO port D clock enable /
mbed_official	76:aeb1df146756	3645	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /!< GPIO port E clock enable /
mbed_official	76:aeb1df146756	3646	#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /!< GPIO port H clock enable /
mbed_official	76:aeb1df146756	3647	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /!< GPIO port F clock enable /
mbed_official	76:aeb1df146756	3648	#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /!< GPIO port G clock enable /
mbed_official	76:aeb1df146756	3649	#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /!< CRC clock enable /
mbed_official	76:aeb1df146756	3650	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
mbed_official	76:aeb1df146756	3651	the Flash memory is in power down mode) */
mbed_official	76:aeb1df146756	3652	#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /!< DMA1 clock enable /
mbed_official	76:aeb1df146756	3653	#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /!< DMA2 clock enable /
mbed_official	76:aeb1df146756	3654	#define RCC_AHBENR_AESEN ((uint32_t)0x08000000) /!< AES clock enable /
mbed_official	76:aeb1df146756	3655	#define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) /!< FSMC clock enable /
mbed_official	76:aeb1df146756	3656
mbed_official	76:aeb1df146756	3657
mbed_official	76:aeb1df146756	3658	/**************** Bit definition for RCC_APB2ENR register ***************/
mbed_official	76:aeb1df146756	3659	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enable /
mbed_official	76:aeb1df146756	3660	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /!< TIM9 interface clock enable /
mbed_official	76:aeb1df146756	3661	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /!< TIM10 interface clock enable /
mbed_official	76:aeb1df146756	3662	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /!< TIM11 Timer clock enable /
mbed_official	76:aeb1df146756	3663	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC1 clock enable /
mbed_official	76:aeb1df146756	3664	#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) /!< SDIO clock enable /
mbed_official	76:aeb1df146756	3665	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
mbed_official	76:aeb1df146756	3666	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
mbed_official	76:aeb1df146756	3667
mbed_official	76:aeb1df146756	3668
mbed_official	76:aeb1df146756	3669	/*************** Bit definition for RCC_APB1ENR register ****************/
mbed_official	76:aeb1df146756	3670	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
mbed_official	76:aeb1df146756	3671	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
mbed_official	76:aeb1df146756	3672	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
mbed_official	76:aeb1df146756	3673	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
mbed_official	76:aeb1df146756	3674	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
mbed_official	76:aeb1df146756	3675	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
mbed_official	76:aeb1df146756	3676	#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /!< LCD clock enable /
mbed_official	76:aeb1df146756	3677	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
mbed_official	76:aeb1df146756	3678	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
mbed_official	76:aeb1df146756	3679	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
mbed_official	76:aeb1df146756	3680	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
mbed_official	76:aeb1df146756	3681	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
mbed_official	76:aeb1df146756	3682	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
mbed_official	76:aeb1df146756	3683	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
mbed_official	76:aeb1df146756	3684	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
mbed_official	76:aeb1df146756	3685	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
mbed_official	76:aeb1df146756	3686	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
mbed_official	76:aeb1df146756	3687	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
mbed_official	76:aeb1df146756	3688	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
mbed_official	76:aeb1df146756	3689	#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /!< Comparator interface clock enable /
mbed_official	76:aeb1df146756	3690
mbed_official	76:aeb1df146756	3691	/**************** Bit definition for RCC_AHBLPENR register **************/
mbed_official	76:aeb1df146756	3692	#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /!< GPIO port A clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3693	#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /!< GPIO port B clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3694	#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /!< GPIO port C clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3695	#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /!< GPIO port D clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3696	#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /!< GPIO port E clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3697	#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /!< GPIO port H clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3698	#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /!< GPIO port F clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3699	#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /!< GPIO port G clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3700	#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /!< CRC clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3701	#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
mbed_official	76:aeb1df146756	3702	(has effect only when the Flash memory is
mbed_official	76:aeb1df146756	3703	in power down mode) */
mbed_official	76:aeb1df146756	3704	#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /!< SRAM clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3705	#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /!< DMA1 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3706	#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /!< DMA2 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3707	#define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) /!< AES clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3708	#define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) /!< FSMC clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3709
mbed_official	76:aeb1df146756	3710	/**************** Bit definition for RCC_APB2LPENR register *************/
mbed_official	76:aeb1df146756	3711	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /!< System Configuration SYSCFG clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3712	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /!< TIM9 interface clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3713	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /!< TIM10 interface clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3714	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /!< TIM11 Timer clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3715	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /!< ADC1 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3716	#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) /!< SDIO clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3717	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /!< SPI1 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3718	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /!< USART1 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3719
mbed_official	76:aeb1df146756	3720	/*************** Bit definition for RCC_APB1LPENR register **************/
mbed_official	76:aeb1df146756	3721	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /!< Timer 2 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3722	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /!< Timer 3 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3723	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /!< Timer 4 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3724	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /!< Timer 5 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3725	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /!< Timer 6 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3726	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /!< Timer 7 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3727	#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /!< LCD clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3728	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /!< Window Watchdog clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3729	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /!< SPI 2 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3730	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /!< SPI 3 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3731	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /!< USART 2 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3732	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /!< USART 3 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3733	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /!< UART 4 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3734	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /!< UART 5 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3735	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /!< I2C 1 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3736	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /!< I2C 2 clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3737	#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /!< USB clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3738	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /!< Power interface clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3739	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /!< DAC interface clock enabled in sleep mode /
mbed_official	76:aeb1df146756	3740	#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /!< Comparator interface clock enabled in sleep mode/
mbed_official	76:aeb1df146756	3741
mbed_official	76:aeb1df146756	3742	/***************** Bit definition for RCC_CSR register ******************/
mbed_official	76:aeb1df146756	3743	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
mbed_official	76:aeb1df146756	3744	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
mbed_official	76:aeb1df146756	3745
mbed_official	76:aeb1df146756	3746	#define RCC_CSR_LSEON ((uint32_t)0x00000100) /!< External Low Speed oscillator enable /
mbed_official	76:aeb1df146756	3747	#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /!< External Low Speed oscillator Ready /
mbed_official	76:aeb1df146756	3748	#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /!< External Low Speed oscillator Bypass /
mbed_official	76:aeb1df146756	3749	#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /!< External Low Speed oscillator CSS Enable /
mbed_official	76:aeb1df146756	3750	#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /!< External Low Speed oscillator CSS Detected /
mbed_official	76:aeb1df146756	3751
mbed_official	76:aeb1df146756	3752	#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /!< RTCSEL[1:0] bits (RTC clock source selection) /
mbed_official	76:aeb1df146756	3753	#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	3754	#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	3755
mbed_official	76:aeb1df146756	3756	/!< RTC congiguration /
mbed_official	76:aeb1df146756	3757	#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	76:aeb1df146756	3758	#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /!< LSE oscillator clock used as RTC clock /
mbed_official	76:aeb1df146756	3759	#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /!< LSI oscillator clock used as RTC clock /
mbed_official	76:aeb1df146756	3760	#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock /
mbed_official	76:aeb1df146756	3761
mbed_official	76:aeb1df146756	3762	#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /!< RTC clock enable /
mbed_official	76:aeb1df146756	3763	#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /!< RTC reset /
mbed_official	76:aeb1df146756	3764
mbed_official	76:aeb1df146756	3765	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
mbed_official	76:aeb1df146756	3766	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< Option Bytes Loader reset flag /
mbed_official	76:aeb1df146756	3767	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
mbed_official	76:aeb1df146756	3768	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
mbed_official	76:aeb1df146756	3769	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
mbed_official	76:aeb1df146756	3770	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
mbed_official	76:aeb1df146756	3771	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
mbed_official	76:aeb1df146756	3772	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
mbed_official	76:aeb1df146756	3773
mbed_official	76:aeb1df146756	3774
mbed_official	76:aeb1df146756	3775	/******************************************************************************/
mbed_official	76:aeb1df146756	3776	/* */
mbed_official	76:aeb1df146756	3777	/* Real-Time Clock (RTC) */
mbed_official	76:aeb1df146756	3778	/* */
mbed_official	76:aeb1df146756	3779	/******************************************************************************/
mbed_official	76:aeb1df146756	3780	/****************** Bits definition for RTC_TR register *****************/
mbed_official	76:aeb1df146756	3781	#define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3782	#define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	3783	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3784	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3785	#define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3786	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3787	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3788	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3789	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3790	#define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official	76:aeb1df146756	3791	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3792	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3793	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3794	#define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3795	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3796	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3797	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3798	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3799	#define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official	76:aeb1df146756	3800	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3801	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3802	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3803	#define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3804	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3805	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3806	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3807	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3808
mbed_official	76:aeb1df146756	3809	/****************** Bits definition for RTC_DR register *****************/
mbed_official	76:aeb1df146756	3810	#define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official	76:aeb1df146756	3811	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3812	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3813	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3814	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3815	#define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3816	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3817	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3818	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3819	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3820	#define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official	76:aeb1df146756	3821	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3822	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3823	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3824	#define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3825	#define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3826	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3827	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3828	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3829	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3830	#define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official	76:aeb1df146756	3831	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3832	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3833	#define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3834	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3835	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3836	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3837	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3838
mbed_official	76:aeb1df146756	3839	/****************** Bits definition for RTC_CR register *****************/
mbed_official	76:aeb1df146756	3840	#define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3841	#define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official	76:aeb1df146756	3842	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3843	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3844	#define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3845	#define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3846	#define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3847	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3848	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3849	#define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3850	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3851	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3852	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3853	#define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3854	#define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3855	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3856	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3857	#define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3858	#define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3859	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3860	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3861	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3862	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official	76:aeb1df146756	3863	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3864	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3865	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3866
mbed_official	76:aeb1df146756	3867	/****************** Bits definition for RTC_ISR register ****************/
mbed_official	76:aeb1df146756	3868	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3869	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3870	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3871	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3872	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3873	#define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3874	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3875	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3876	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3877	#define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3878	#define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3879	#define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3880	#define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3881	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3882	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3883	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3884	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3885
mbed_official	76:aeb1df146756	3886	/****************** Bits definition for RTC_PRER register ***************/
mbed_official	76:aeb1df146756	3887	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official	76:aeb1df146756	3888	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official	76:aeb1df146756	3889
mbed_official	76:aeb1df146756	3890	/****************** Bits definition for RTC_WUTR register ***************/
mbed_official	76:aeb1df146756	3891	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official	76:aeb1df146756	3892
mbed_official	76:aeb1df146756	3893	/****************** Bits definition for RTC_CALIBR register *************/
mbed_official	76:aeb1df146756	3894	#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3895	#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official	76:aeb1df146756	3896
mbed_official	76:aeb1df146756	3897	/****************** Bits definition for RTC_ALRMAR register *************/
mbed_official	76:aeb1df146756	3898	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	3899	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	3900	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official	76:aeb1df146756	3901	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	3902	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	3903	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	3904	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	3905	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	3906	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	3907	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	3908	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3909	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3910	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	3911	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3912	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3913	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3914	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3915	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3916	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3917	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3918	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3919	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official	76:aeb1df146756	3920	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3921	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3922	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3923	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3924	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3925	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3926	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3927	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3928	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3929	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official	76:aeb1df146756	3930	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3931	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3932	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3933	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3934	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3935	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3936	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3937	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3938
mbed_official	76:aeb1df146756	3939	/****************** Bits definition for RTC_ALRMBR register *************/
mbed_official	76:aeb1df146756	3940	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	3941	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official	76:aeb1df146756	3942	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official	76:aeb1df146756	3943	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official	76:aeb1df146756	3944	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official	76:aeb1df146756	3945	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	3946	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	3947	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	3948	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	3949	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	3950	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official	76:aeb1df146756	3951	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3952	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	3953	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3954	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3955	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3956	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3957	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3958	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	3959	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	3960	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	3961	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official	76:aeb1df146756	3962	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	3963	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	3964	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	3965	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	3966	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	3967	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	3968	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	3969	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	3970	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	3971	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official	76:aeb1df146756	3972	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	3973	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	3974	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	3975	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	3976	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	3977	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	3978	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	3979	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	3980
mbed_official	76:aeb1df146756	3981	/****************** Bits definition for RTC_WPR register ****************/
mbed_official	76:aeb1df146756	3982	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official	76:aeb1df146756	3983
mbed_official	76:aeb1df146756	3984	/****************** Bits definition for RTC_SSR register ****************/
mbed_official	76:aeb1df146756	3985	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official	76:aeb1df146756	3986
mbed_official	76:aeb1df146756	3987	/****************** Bits definition for RTC_SHIFTR register *************/
mbed_official	76:aeb1df146756	3988	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official	76:aeb1df146756	3989	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official	76:aeb1df146756	3990
mbed_official	76:aeb1df146756	3991	/****************** Bits definition for RTC_TSTR register ***************/
mbed_official	76:aeb1df146756	3992	#define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official	76:aeb1df146756	3993	#define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official	76:aeb1df146756	3994	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official	76:aeb1df146756	3995	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official	76:aeb1df146756	3996	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official	76:aeb1df146756	3997	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official	76:aeb1df146756	3998	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official	76:aeb1df146756	3999	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	4000	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official	76:aeb1df146756	4001	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official	76:aeb1df146756	4002	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	4003	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	4004	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	4005	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	4006	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	4007	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	4008	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	4009	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	4010	#define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official	76:aeb1df146756	4011	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	4012	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	4013	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	4014	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	4015	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	4016	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	4017	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	4018	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	4019
mbed_official	76:aeb1df146756	4020	/****************** Bits definition for RTC_TSDR register ***************/
mbed_official	76:aeb1df146756	4021	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official	76:aeb1df146756	4022	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	4023	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	4024	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	4025	#define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	4026	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official	76:aeb1df146756	4027	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	4028	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	4029	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	4030	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	4031	#define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official	76:aeb1df146756	4032	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	4033	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	4034	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official	76:aeb1df146756	4035	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	4036	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	4037	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	4038	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	4039
mbed_official	76:aeb1df146756	4040	/****************** Bits definition for RTC_TSSSR register **************/
mbed_official	76:aeb1df146756	4041	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official	76:aeb1df146756	4042
mbed_official	76:aeb1df146756	4043	/****************** Bits definition for RTC_CAL register ***************/
mbed_official	76:aeb1df146756	4044	#define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	4045	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	4046	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	4047	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official	76:aeb1df146756	4048	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	4049	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	4050	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	4051	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	4052	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	4053	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	4054	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	4055	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	4056	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	4057
mbed_official	76:aeb1df146756	4058	/****************** Bits definition for RTC_TAFCR register **************/
mbed_official	76:aeb1df146756	4059	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official	76:aeb1df146756	4060	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official	76:aeb1df146756	4061	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official	76:aeb1df146756	4062	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official	76:aeb1df146756	4063	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official	76:aeb1df146756	4064	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official	76:aeb1df146756	4065	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official	76:aeb1df146756	4066	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official	76:aeb1df146756	4067	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official	76:aeb1df146756	4068	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official	76:aeb1df146756	4069	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official	76:aeb1df146756	4070	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official	76:aeb1df146756	4071	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official	76:aeb1df146756	4072	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official	76:aeb1df146756	4073	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official	76:aeb1df146756	4074	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official	76:aeb1df146756	4075	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official	76:aeb1df146756	4076	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official	76:aeb1df146756	4077	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official	76:aeb1df146756	4078	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official	76:aeb1df146756	4079
mbed_official	76:aeb1df146756	4080	/****************** Bits definition for RTC_ALRMASSR register ***********/
mbed_official	76:aeb1df146756	4081	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	4082	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	4083	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	4084	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	4085	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	4086	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official	76:aeb1df146756	4087
mbed_official	76:aeb1df146756	4088	/****************** Bits definition for RTC_ALRMBSSR register ***********/
mbed_official	76:aeb1df146756	4089	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official	76:aeb1df146756	4090	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official	76:aeb1df146756	4091	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official	76:aeb1df146756	4092	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official	76:aeb1df146756	4093	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official	76:aeb1df146756	4094	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official	76:aeb1df146756	4095
mbed_official	76:aeb1df146756	4096	/****************** Bits definition for RTC_BKP0R register **************/
mbed_official	76:aeb1df146756	4097	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4098
mbed_official	76:aeb1df146756	4099	/****************** Bits definition for RTC_BKP1R register **************/
mbed_official	76:aeb1df146756	4100	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4101
mbed_official	76:aeb1df146756	4102	/****************** Bits definition for RTC_BKP2R register **************/
mbed_official	76:aeb1df146756	4103	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4104
mbed_official	76:aeb1df146756	4105	/****************** Bits definition for RTC_BKP3R register **************/
mbed_official	76:aeb1df146756	4106	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4107
mbed_official	76:aeb1df146756	4108	/****************** Bits definition for RTC_BKP4R register **************/
mbed_official	76:aeb1df146756	4109	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4110
mbed_official	76:aeb1df146756	4111	/****************** Bits definition for RTC_BKP5R register **************/
mbed_official	76:aeb1df146756	4112	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4113
mbed_official	76:aeb1df146756	4114	/****************** Bits definition for RTC_BKP6R register **************/
mbed_official	76:aeb1df146756	4115	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4116
mbed_official	76:aeb1df146756	4117	/****************** Bits definition for RTC_BKP7R register **************/
mbed_official	76:aeb1df146756	4118	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4119
mbed_official	76:aeb1df146756	4120	/****************** Bits definition for RTC_BKP8R register **************/
mbed_official	76:aeb1df146756	4121	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4122
mbed_official	76:aeb1df146756	4123	/****************** Bits definition for RTC_BKP9R register **************/
mbed_official	76:aeb1df146756	4124	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4125
mbed_official	76:aeb1df146756	4126	/****************** Bits definition for RTC_BKP10R register *************/
mbed_official	76:aeb1df146756	4127	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4128
mbed_official	76:aeb1df146756	4129	/****************** Bits definition for RTC_BKP11R register *************/
mbed_official	76:aeb1df146756	4130	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4131
mbed_official	76:aeb1df146756	4132	/****************** Bits definition for RTC_BKP12R register *************/
mbed_official	76:aeb1df146756	4133	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4134
mbed_official	76:aeb1df146756	4135	/****************** Bits definition for RTC_BKP13R register *************/
mbed_official	76:aeb1df146756	4136	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4137
mbed_official	76:aeb1df146756	4138	/****************** Bits definition for RTC_BKP14R register *************/
mbed_official	76:aeb1df146756	4139	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4140
mbed_official	76:aeb1df146756	4141	/****************** Bits definition for RTC_BKP15R register *************/
mbed_official	76:aeb1df146756	4142	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4143
mbed_official	76:aeb1df146756	4144	/****************** Bits definition for RTC_BKP16R register *************/
mbed_official	76:aeb1df146756	4145	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4146
mbed_official	76:aeb1df146756	4147	/****************** Bits definition for RTC_BKP17R register *************/
mbed_official	76:aeb1df146756	4148	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4149
mbed_official	76:aeb1df146756	4150	/****************** Bits definition for RTC_BKP18R register *************/
mbed_official	76:aeb1df146756	4151	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4152
mbed_official	76:aeb1df146756	4153	/****************** Bits definition for RTC_BKP19R register *************/
mbed_official	76:aeb1df146756	4154	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4155
mbed_official	76:aeb1df146756	4156	/****************** Bits definition for RTC_BKP20R register *************/
mbed_official	76:aeb1df146756	4157	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4158
mbed_official	76:aeb1df146756	4159	/****************** Bits definition for RTC_BKP21R register *************/
mbed_official	76:aeb1df146756	4160	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4161
mbed_official	76:aeb1df146756	4162	/****************** Bits definition for RTC_BKP22R register *************/
mbed_official	76:aeb1df146756	4163	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4164
mbed_official	76:aeb1df146756	4165	/****************** Bits definition for RTC_BKP23R register *************/
mbed_official	76:aeb1df146756	4166	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4167
mbed_official	76:aeb1df146756	4168	/****************** Bits definition for RTC_BKP24R register *************/
mbed_official	76:aeb1df146756	4169	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4170
mbed_official	76:aeb1df146756	4171	/****************** Bits definition for RTC_BKP25R register *************/
mbed_official	76:aeb1df146756	4172	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4173
mbed_official	76:aeb1df146756	4174	/****************** Bits definition for RTC_BKP26R register *************/
mbed_official	76:aeb1df146756	4175	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4176
mbed_official	76:aeb1df146756	4177	/****************** Bits definition for RTC_BKP27R register *************/
mbed_official	76:aeb1df146756	4178	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4179
mbed_official	76:aeb1df146756	4180	/****************** Bits definition for RTC_BKP28R register *************/
mbed_official	76:aeb1df146756	4181	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4182
mbed_official	76:aeb1df146756	4183	/****************** Bits definition for RTC_BKP29R register *************/
mbed_official	76:aeb1df146756	4184	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4185
mbed_official	76:aeb1df146756	4186	/****************** Bits definition for RTC_BKP30R register *************/
mbed_official	76:aeb1df146756	4187	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4188
mbed_official	76:aeb1df146756	4189	/****************** Bits definition for RTC_BKP31R register *************/
mbed_official	76:aeb1df146756	4190	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
mbed_official	76:aeb1df146756	4191
mbed_official	76:aeb1df146756	4192	/******************************************************************************/
mbed_official	76:aeb1df146756	4193	/* */
mbed_official	76:aeb1df146756	4194	/* SD host Interface */
mbed_official	76:aeb1df146756	4195	/* */
mbed_official	76:aeb1df146756	4196	/******************************************************************************/
mbed_official	76:aeb1df146756	4197
mbed_official	76:aeb1df146756	4198	/**************** Bit definition for SDIO_POWER register ****************/
mbed_official	76:aeb1df146756	4199	#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
mbed_official	76:aeb1df146756	4200	#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /!< Bit 0 /
mbed_official	76:aeb1df146756	4201	#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /!< Bit 1 /
mbed_official	76:aeb1df146756	4202
mbed_official	76:aeb1df146756	4203	/**************** Bit definition for SDIO_CLKCR register ****************/
mbed_official	76:aeb1df146756	4204	#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /!< Clock divide factor /
mbed_official	76:aeb1df146756	4205	#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /!< Clock enable bit /
mbed_official	76:aeb1df146756	4206	#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /!< Power saving configuration bit /
mbed_official	76:aeb1df146756	4207	#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /!< Clock divider bypass enable bit /
mbed_official	76:aeb1df146756	4208
mbed_official	76:aeb1df146756	4209	#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
mbed_official	76:aeb1df146756	4210	#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!< Bit 0 /
mbed_official	76:aeb1df146756	4211	#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4212
mbed_official	76:aeb1df146756	4213	#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /!< SDIO_CK dephasing selection bit /
mbed_official	76:aeb1df146756	4214	#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /!< HW Flow Control enable /
mbed_official	76:aeb1df146756	4215
mbed_official	76:aeb1df146756	4216	/***************** Bit definition for SDIO_ARG register *****************/
mbed_official	76:aeb1df146756	4217	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
mbed_official	76:aeb1df146756	4218
mbed_official	76:aeb1df146756	4219	/***************** Bit definition for SDIO_CMD register *****************/
mbed_official	76:aeb1df146756	4220	#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /!< Command Index /
mbed_official	76:aeb1df146756	4221
mbed_official	76:aeb1df146756	4222	#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
mbed_official	76:aeb1df146756	4223	#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
mbed_official	76:aeb1df146756	4224	#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
mbed_official	76:aeb1df146756	4225
mbed_official	76:aeb1df146756	4226	#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /!< CPSM Waits for Interrupt Request /
mbed_official	76:aeb1df146756	4227	#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
mbed_official	76:aeb1df146756	4228	#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
mbed_official	76:aeb1df146756	4229	#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!< SD I/O suspend command /
mbed_official	76:aeb1df146756	4230	#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /!< Enable CMD completion /
mbed_official	76:aeb1df146756	4231	#define SDIO_CMD_NIEN ((uint16_t)0x2000) /!< Not Interrupt Enable /
mbed_official	76:aeb1df146756	4232	#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /!< CE-ATA command /
mbed_official	76:aeb1df146756	4233
mbed_official	76:aeb1df146756	4234	/*************** Bit definition for SDIO_RESPCMD register ***************/
mbed_official	76:aeb1df146756	4235	#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /!< Response command index /
mbed_official	76:aeb1df146756	4236
mbed_official	76:aeb1df146756	4237	/**************** Bit definition for SDIO_RESP0 register ****************/
mbed_official	76:aeb1df146756	4238	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
mbed_official	76:aeb1df146756	4239
mbed_official	76:aeb1df146756	4240	/**************** Bit definition for SDIO_RESP1 register ****************/
mbed_official	76:aeb1df146756	4241	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
mbed_official	76:aeb1df146756	4242
mbed_official	76:aeb1df146756	4243	/**************** Bit definition for SDIO_RESP2 register ****************/
mbed_official	76:aeb1df146756	4244	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
mbed_official	76:aeb1df146756	4245
mbed_official	76:aeb1df146756	4246	/**************** Bit definition for SDIO_RESP3 register ****************/
mbed_official	76:aeb1df146756	4247	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
mbed_official	76:aeb1df146756	4248
mbed_official	76:aeb1df146756	4249	/**************** Bit definition for SDIO_RESP4 register ****************/
mbed_official	76:aeb1df146756	4250	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
mbed_official	76:aeb1df146756	4251
mbed_official	76:aeb1df146756	4252	/**************** Bit definition for SDIO_DTIMER register ***************/
mbed_official	76:aeb1df146756	4253	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
mbed_official	76:aeb1df146756	4254
mbed_official	76:aeb1df146756	4255	/**************** Bit definition for SDIO_DLEN register *****************/
mbed_official	76:aeb1df146756	4256	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
mbed_official	76:aeb1df146756	4257
mbed_official	76:aeb1df146756	4258	/**************** Bit definition for SDIO_DCTRL register ****************/
mbed_official	76:aeb1df146756	4259	#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /!< Data transfer enabled bit /
mbed_official	76:aeb1df146756	4260	#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /!< Data transfer direction selection /
mbed_official	76:aeb1df146756	4261	#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /!< Data transfer mode selection /
mbed_official	76:aeb1df146756	4262	#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /!< DMA enabled bit /
mbed_official	76:aeb1df146756	4263
mbed_official	76:aeb1df146756	4264	#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
mbed_official	76:aeb1df146756	4265	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!< Bit 0 /
mbed_official	76:aeb1df146756	4266	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!< Bit 1 /
mbed_official	76:aeb1df146756	4267	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!< Bit 2 /
mbed_official	76:aeb1df146756	4268	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!< Bit 3 /
mbed_official	76:aeb1df146756	4269
mbed_official	76:aeb1df146756	4270	#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /!< Read wait start /
mbed_official	76:aeb1df146756	4271	#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /!< Read wait stop /
mbed_official	76:aeb1df146756	4272	#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /!< Read wait mode /
mbed_official	76:aeb1df146756	4273	#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /!< SD I/O enable functions /
mbed_official	76:aeb1df146756	4274
mbed_official	76:aeb1df146756	4275	/**************** Bit definition for SDIO_DCOUNT register ***************/
mbed_official	76:aeb1df146756	4276	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
mbed_official	76:aeb1df146756	4277
mbed_official	76:aeb1df146756	4278	/**************** Bit definition for SDIO_STA register ******************/
mbed_official	76:aeb1df146756	4279	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
mbed_official	76:aeb1df146756	4280	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
mbed_official	76:aeb1df146756	4281	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
mbed_official	76:aeb1df146756	4282	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
mbed_official	76:aeb1df146756	4283	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
mbed_official	76:aeb1df146756	4284	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
mbed_official	76:aeb1df146756	4285	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
mbed_official	76:aeb1df146756	4286	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
mbed_official	76:aeb1df146756	4287	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
mbed_official	76:aeb1df146756	4288	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
mbed_official	76:aeb1df146756	4289	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
mbed_official	76:aeb1df146756	4290	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
mbed_official	76:aeb1df146756	4291	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
mbed_official	76:aeb1df146756	4292	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
mbed_official	76:aeb1df146756	4293	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
mbed_official	76:aeb1df146756	4294	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
mbed_official	76:aeb1df146756	4295	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
mbed_official	76:aeb1df146756	4296	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
mbed_official	76:aeb1df146756	4297	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
mbed_official	76:aeb1df146756	4298	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
mbed_official	76:aeb1df146756	4299	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
mbed_official	76:aeb1df146756	4300	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
mbed_official	76:aeb1df146756	4301	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
mbed_official	76:aeb1df146756	4302	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
mbed_official	76:aeb1df146756	4303
mbed_official	76:aeb1df146756	4304	/***************** Bit definition for SDIO_ICR register *****************/
mbed_official	76:aeb1df146756	4305	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
mbed_official	76:aeb1df146756	4306	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
mbed_official	76:aeb1df146756	4307	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
mbed_official	76:aeb1df146756	4308	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
mbed_official	76:aeb1df146756	4309	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
mbed_official	76:aeb1df146756	4310	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
mbed_official	76:aeb1df146756	4311	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
mbed_official	76:aeb1df146756	4312	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
mbed_official	76:aeb1df146756	4313	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
mbed_official	76:aeb1df146756	4314	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
mbed_official	76:aeb1df146756	4315	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
mbed_official	76:aeb1df146756	4316	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
mbed_official	76:aeb1df146756	4317	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
mbed_official	76:aeb1df146756	4318
mbed_official	76:aeb1df146756	4319	/**************** Bit definition for SDIO_MASK register *****************/
mbed_official	76:aeb1df146756	4320	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
mbed_official	76:aeb1df146756	4321	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
mbed_official	76:aeb1df146756	4322	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
mbed_official	76:aeb1df146756	4323	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
mbed_official	76:aeb1df146756	4324	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
mbed_official	76:aeb1df146756	4325	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
mbed_official	76:aeb1df146756	4326	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
mbed_official	76:aeb1df146756	4327	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
mbed_official	76:aeb1df146756	4328	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
mbed_official	76:aeb1df146756	4329	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
mbed_official	76:aeb1df146756	4330	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
mbed_official	76:aeb1df146756	4331	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
mbed_official	76:aeb1df146756	4332	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
mbed_official	76:aeb1df146756	4333	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
mbed_official	76:aeb1df146756	4334	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
mbed_official	76:aeb1df146756	4335	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
mbed_official	76:aeb1df146756	4336	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
mbed_official	76:aeb1df146756	4337	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
mbed_official	76:aeb1df146756	4338	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
mbed_official	76:aeb1df146756	4339	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
mbed_official	76:aeb1df146756	4340	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
mbed_official	76:aeb1df146756	4341	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
mbed_official	76:aeb1df146756	4342	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
mbed_official	76:aeb1df146756	4343	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
mbed_official	76:aeb1df146756	4344
mbed_official	76:aeb1df146756	4345	/*************** Bit definition for SDIO_FIFOCNT register ***************/
mbed_official	76:aeb1df146756	4346	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
mbed_official	76:aeb1df146756	4347
mbed_official	76:aeb1df146756	4348	/**************** Bit definition for SDIO_FIFO register *****************/
mbed_official	76:aeb1df146756	4349	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
mbed_official	76:aeb1df146756	4350
mbed_official	76:aeb1df146756	4351	/******************************************************************************/
mbed_official	76:aeb1df146756	4352	/* */
mbed_official	76:aeb1df146756	4353	/* Serial Peripheral Interface (SPI) */
mbed_official	76:aeb1df146756	4354	/* */
mbed_official	76:aeb1df146756	4355	/******************************************************************************/
mbed_official	76:aeb1df146756	4356
mbed_official	76:aeb1df146756	4357	/***************** Bit definition for SPI_CR1 register ******************/
mbed_official	76:aeb1df146756	4358	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!< Clock Phase /
mbed_official	76:aeb1df146756	4359	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!< Clock Polarity /
mbed_official	76:aeb1df146756	4360	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!< Master Selection /
mbed_official	76:aeb1df146756	4361
mbed_official	76:aeb1df146756	4362	#define SPI_CR1_BR ((uint16_t)0x0038) /!< BR[2:0] bits (Baud Rate Control) /
mbed_official	76:aeb1df146756	4363	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!< Bit 0 /
mbed_official	76:aeb1df146756	4364	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!< Bit 1 /
mbed_official	76:aeb1df146756	4365	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!< Bit 2 /
mbed_official	76:aeb1df146756	4366
mbed_official	76:aeb1df146756	4367	#define SPI_CR1_SPE ((uint16_t)0x0040) /!< SPI Enable /
mbed_official	76:aeb1df146756	4368	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!< Frame Format /
mbed_official	76:aeb1df146756	4369	#define SPI_CR1_SSI ((uint16_t)0x0100) /!< Internal slave select /
mbed_official	76:aeb1df146756	4370	#define SPI_CR1_SSM ((uint16_t)0x0200) /!< Software slave management /
mbed_official	76:aeb1df146756	4371	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!< Receive only /
mbed_official	76:aeb1df146756	4372	#define SPI_CR1_DFF ((uint16_t)0x0800) /!< Data Frame Format /
mbed_official	76:aeb1df146756	4373	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!< Transmit CRC next /
mbed_official	76:aeb1df146756	4374	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!< Hardware CRC calculation enable /
mbed_official	76:aeb1df146756	4375	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!< Output enable in bidirectional mode /
mbed_official	76:aeb1df146756	4376	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!< Bidirectional data mode enable /
mbed_official	76:aeb1df146756	4377
mbed_official	76:aeb1df146756	4378	/***************** Bit definition for SPI_CR2 register ******************/
mbed_official	76:aeb1df146756	4379	#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /!< Rx Buffer DMA Enable /
mbed_official	76:aeb1df146756	4380	#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /!< Tx Buffer DMA Enable /
mbed_official	76:aeb1df146756	4381	#define SPI_CR2_SSOE ((uint8_t)0x04) /!< SS Output Enable /
mbed_official	76:aeb1df146756	4382	#define SPI_CR2_FRF ((uint8_t)0x08) /!< Frame format /
mbed_official	76:aeb1df146756	4383	#define SPI_CR2_ERRIE ((uint8_t)0x20) /!< Error Interrupt Enable /
mbed_official	76:aeb1df146756	4384	#define SPI_CR2_RXNEIE ((uint8_t)0x40) /!< RX buffer Not Empty Interrupt Enable /
mbed_official	76:aeb1df146756	4385	#define SPI_CR2_TXEIE ((uint8_t)0x80) /!< Tx buffer Empty Interrupt Enable /
mbed_official	76:aeb1df146756	4386
mbed_official	76:aeb1df146756	4387	/****************** Bit definition for SPI_SR register ******************/
mbed_official	76:aeb1df146756	4388	#define SPI_SR_RXNE ((uint8_t)0x01) /!< Receive buffer Not Empty /
mbed_official	76:aeb1df146756	4389	#define SPI_SR_TXE ((uint8_t)0x02) /!< Transmit buffer Empty /
mbed_official	76:aeb1df146756	4390	#define SPI_SR_CHSIDE ((uint8_t)0x04) /!< Channel side /
mbed_official	76:aeb1df146756	4391	#define SPI_SR_UDR ((uint8_t)0x08) /!< Underrun flag /
mbed_official	76:aeb1df146756	4392	#define SPI_SR_CRCERR ((uint8_t)0x10) /!< CRC Error flag /
mbed_official	76:aeb1df146756	4393	#define SPI_SR_MODF ((uint8_t)0x20) /!< Mode fault /
mbed_official	76:aeb1df146756	4394	#define SPI_SR_OVR ((uint8_t)0x40) /!< Overrun flag /
mbed_official	76:aeb1df146756	4395	#define SPI_SR_BSY ((uint8_t)0x80) /!< Busy flag /
mbed_official	76:aeb1df146756	4396
mbed_official	76:aeb1df146756	4397	/****************** Bit definition for SPI_DR register ******************/
mbed_official	76:aeb1df146756	4398	#define SPI_DR_DR ((uint16_t)0xFFFF) /!< Data Register /
mbed_official	76:aeb1df146756	4399
mbed_official	76:aeb1df146756	4400	/***************** Bit definition for SPI_CRCPR register ****************/
mbed_official	76:aeb1df146756	4401	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!< CRC polynomial register /
mbed_official	76:aeb1df146756	4402
mbed_official	76:aeb1df146756	4403	/**************** Bit definition for SPI_RXCRCR register ****************/
mbed_official	76:aeb1df146756	4404	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!< Rx CRC Register /
mbed_official	76:aeb1df146756	4405
mbed_official	76:aeb1df146756	4406	/**************** Bit definition for SPI_TXCRCR register ****************/
mbed_official	76:aeb1df146756	4407	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!< Tx CRC Register /
mbed_official	76:aeb1df146756	4408
mbed_official	76:aeb1df146756	4409	/**************** Bit definition for SPI_I2SCFGR register ***************/
mbed_official	76:aeb1df146756	4410	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
mbed_official	76:aeb1df146756	4411
mbed_official	76:aeb1df146756	4412	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
mbed_official	76:aeb1df146756	4413	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
mbed_official	76:aeb1df146756	4414	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
mbed_official	76:aeb1df146756	4415
mbed_official	76:aeb1df146756	4416	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
mbed_official	76:aeb1df146756	4417
mbed_official	76:aeb1df146756	4418	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
mbed_official	76:aeb1df146756	4419	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	4420	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	4421
mbed_official	76:aeb1df146756	4422	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
mbed_official	76:aeb1df146756	4423
mbed_official	76:aeb1df146756	4424	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
mbed_official	76:aeb1df146756	4425	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	4426	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	4427
mbed_official	76:aeb1df146756	4428	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
mbed_official	76:aeb1df146756	4429	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
mbed_official	76:aeb1df146756	4430
mbed_official	76:aeb1df146756	4431	/**************** Bit definition for SPI_I2SPR register *****************/
mbed_official	76:aeb1df146756	4432	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
mbed_official	76:aeb1df146756	4433	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
mbed_official	76:aeb1df146756	4434	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
mbed_official	76:aeb1df146756	4435
mbed_official	76:aeb1df146756	4436	/******************************************************************************/
mbed_official	76:aeb1df146756	4437	/* */
mbed_official	76:aeb1df146756	4438	/* System Configuration (SYSCFG) */
mbed_official	76:aeb1df146756	4439	/* */
mbed_official	76:aeb1df146756	4440	/******************************************************************************/
mbed_official	76:aeb1df146756	4441	/*************** Bit definition for SYSCFG_MEMRMP register **************/
mbed_official	76:aeb1df146756	4442	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
mbed_official	76:aeb1df146756	4443	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4444	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4445	#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /!< Boot mode Config /
mbed_official	76:aeb1df146756	4446	#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	4447	#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	4448
mbed_official	76:aeb1df146756	4449	/*************** Bit definition for SYSCFG_PMC register *****************/
mbed_official	76:aeb1df146756	4450	#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /!< SYSCFG PMC /
mbed_official	76:aeb1df146756	4451
mbed_official	76:aeb1df146756	4452	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
mbed_official	76:aeb1df146756	4453	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
mbed_official	76:aeb1df146756	4454	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
mbed_official	76:aeb1df146756	4455	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
mbed_official	76:aeb1df146756	4456	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
mbed_official	76:aeb1df146756	4457
mbed_official	76:aeb1df146756	4458	/**
mbed_official	76:aeb1df146756	4459	* @brief EXTI0 configuration
mbed_official	76:aeb1df146756	4460	*/
mbed_official	76:aeb1df146756	4461	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
mbed_official	76:aeb1df146756	4462	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
mbed_official	76:aeb1df146756	4463	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
mbed_official	76:aeb1df146756	4464	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
mbed_official	76:aeb1df146756	4465	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
mbed_official	76:aeb1df146756	4466	#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /!< PH[0] pin /
mbed_official	76:aeb1df146756	4467	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) /!< PF[0] pin /
mbed_official	76:aeb1df146756	4468	#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) /!< PG[0] pin /
mbed_official	76:aeb1df146756	4469
mbed_official	76:aeb1df146756	4470	/**
mbed_official	76:aeb1df146756	4471	* @brief EXTI1 configuration
mbed_official	76:aeb1df146756	4472	*/
mbed_official	76:aeb1df146756	4473	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
mbed_official	76:aeb1df146756	4474	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
mbed_official	76:aeb1df146756	4475	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
mbed_official	76:aeb1df146756	4476	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
mbed_official	76:aeb1df146756	4477	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
mbed_official	76:aeb1df146756	4478	#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /!< PH[1] pin /
mbed_official	76:aeb1df146756	4479	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) /!< PF[1] pin /
mbed_official	76:aeb1df146756	4480	#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) /!< PG[1] pin /
mbed_official	76:aeb1df146756	4481
mbed_official	76:aeb1df146756	4482	/**
mbed_official	76:aeb1df146756	4483	* @brief EXTI2 configuration
mbed_official	76:aeb1df146756	4484	*/
mbed_official	76:aeb1df146756	4485	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
mbed_official	76:aeb1df146756	4486	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
mbed_official	76:aeb1df146756	4487	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
mbed_official	76:aeb1df146756	4488	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
mbed_official	76:aeb1df146756	4489	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
mbed_official	76:aeb1df146756	4490	#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /!< PH[2] pin /
mbed_official	76:aeb1df146756	4491	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) /!< PF[2] pin /
mbed_official	76:aeb1df146756	4492	#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) /!< PG[2] pin /
mbed_official	76:aeb1df146756	4493
mbed_official	76:aeb1df146756	4494	/**
mbed_official	76:aeb1df146756	4495	* @brief EXTI3 configuration
mbed_official	76:aeb1df146756	4496	*/
mbed_official	76:aeb1df146756	4497	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
mbed_official	76:aeb1df146756	4498	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
mbed_official	76:aeb1df146756	4499	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
mbed_official	76:aeb1df146756	4500	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
mbed_official	76:aeb1df146756	4501	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
mbed_official	76:aeb1df146756	4502	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) /!< PF[3] pin /
mbed_official	76:aeb1df146756	4503	#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) /!< PG[3] pin /
mbed_official	76:aeb1df146756	4504
mbed_official	76:aeb1df146756	4505	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official	76:aeb1df146756	4506	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
mbed_official	76:aeb1df146756	4507	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
mbed_official	76:aeb1df146756	4508	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
mbed_official	76:aeb1df146756	4509	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
mbed_official	76:aeb1df146756	4510
mbed_official	76:aeb1df146756	4511	/**
mbed_official	76:aeb1df146756	4512	* @brief EXTI4 configuration
mbed_official	76:aeb1df146756	4513	*/
mbed_official	76:aeb1df146756	4514	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
mbed_official	76:aeb1df146756	4515	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
mbed_official	76:aeb1df146756	4516	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
mbed_official	76:aeb1df146756	4517	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
mbed_official	76:aeb1df146756	4518	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
mbed_official	76:aeb1df146756	4519	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) /!< PF[4] pin /
mbed_official	76:aeb1df146756	4520	#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) /!< PG[4] pin /
mbed_official	76:aeb1df146756	4521
mbed_official	76:aeb1df146756	4522	/**
mbed_official	76:aeb1df146756	4523	* @brief EXTI5 configuration
mbed_official	76:aeb1df146756	4524	*/
mbed_official	76:aeb1df146756	4525	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
mbed_official	76:aeb1df146756	4526	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
mbed_official	76:aeb1df146756	4527	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
mbed_official	76:aeb1df146756	4528	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
mbed_official	76:aeb1df146756	4529	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
mbed_official	76:aeb1df146756	4530	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) /!< PF[5] pin /
mbed_official	76:aeb1df146756	4531	#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) /!< PG[5] pin /
mbed_official	76:aeb1df146756	4532
mbed_official	76:aeb1df146756	4533	/**
mbed_official	76:aeb1df146756	4534	* @brief EXTI6 configuration
mbed_official	76:aeb1df146756	4535	*/
mbed_official	76:aeb1df146756	4536	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
mbed_official	76:aeb1df146756	4537	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
mbed_official	76:aeb1df146756	4538	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
mbed_official	76:aeb1df146756	4539	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
mbed_official	76:aeb1df146756	4540	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
mbed_official	76:aeb1df146756	4541	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) /!< PF[6] pin /
mbed_official	76:aeb1df146756	4542	#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) /!< PG[6] pin /
mbed_official	76:aeb1df146756	4543
mbed_official	76:aeb1df146756	4544	/**
mbed_official	76:aeb1df146756	4545	* @brief EXTI7 configuration
mbed_official	76:aeb1df146756	4546	*/
mbed_official	76:aeb1df146756	4547	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
mbed_official	76:aeb1df146756	4548	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
mbed_official	76:aeb1df146756	4549	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
mbed_official	76:aeb1df146756	4550	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
mbed_official	76:aeb1df146756	4551	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
mbed_official	76:aeb1df146756	4552	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) /!< PF[7] pin /
mbed_official	76:aeb1df146756	4553	#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) /!< PG[7] pin /
mbed_official	76:aeb1df146756	4554
mbed_official	76:aeb1df146756	4555	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official	76:aeb1df146756	4556	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
mbed_official	76:aeb1df146756	4557	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
mbed_official	76:aeb1df146756	4558	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
mbed_official	76:aeb1df146756	4559	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
mbed_official	76:aeb1df146756	4560
mbed_official	76:aeb1df146756	4561	/**
mbed_official	76:aeb1df146756	4562	* @brief EXTI8 configuration
mbed_official	76:aeb1df146756	4563	*/
mbed_official	76:aeb1df146756	4564	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
mbed_official	76:aeb1df146756	4565	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
mbed_official	76:aeb1df146756	4566	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
mbed_official	76:aeb1df146756	4567	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
mbed_official	76:aeb1df146756	4568	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
mbed_official	76:aeb1df146756	4569	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) /!< PF[8] pin /
mbed_official	76:aeb1df146756	4570	#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) /!< PG[8] pin /
mbed_official	76:aeb1df146756	4571
mbed_official	76:aeb1df146756	4572	/**
mbed_official	76:aeb1df146756	4573	* @brief EXTI9 configuration
mbed_official	76:aeb1df146756	4574	*/
mbed_official	76:aeb1df146756	4575	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
mbed_official	76:aeb1df146756	4576	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
mbed_official	76:aeb1df146756	4577	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
mbed_official	76:aeb1df146756	4578	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
mbed_official	76:aeb1df146756	4579	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
mbed_official	76:aeb1df146756	4580	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) /!< PF[9] pin /
mbed_official	76:aeb1df146756	4581	#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) /!< PG[9] pin /
mbed_official	76:aeb1df146756	4582
mbed_official	76:aeb1df146756	4583	/**
mbed_official	76:aeb1df146756	4584	* @brief EXTI10 configuration
mbed_official	76:aeb1df146756	4585	*/
mbed_official	76:aeb1df146756	4586	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
mbed_official	76:aeb1df146756	4587	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
mbed_official	76:aeb1df146756	4588	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
mbed_official	76:aeb1df146756	4589	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
mbed_official	76:aeb1df146756	4590	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PE[10] pin /
mbed_official	76:aeb1df146756	4591	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) /!< PF[10] pin /
mbed_official	76:aeb1df146756	4592	#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) /!< PG[10] pin /
mbed_official	76:aeb1df146756	4593
mbed_official	76:aeb1df146756	4594	/**
mbed_official	76:aeb1df146756	4595	* @brief EXTI11 configuration
mbed_official	76:aeb1df146756	4596	*/
mbed_official	76:aeb1df146756	4597	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
mbed_official	76:aeb1df146756	4598	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
mbed_official	76:aeb1df146756	4599	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
mbed_official	76:aeb1df146756	4600	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
mbed_official	76:aeb1df146756	4601	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
mbed_official	76:aeb1df146756	4602	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) /!< PF[11] pin /
mbed_official	76:aeb1df146756	4603	#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) /!< PG[11] pin /
mbed_official	76:aeb1df146756	4604
mbed_official	76:aeb1df146756	4605	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official	76:aeb1df146756	4606	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
mbed_official	76:aeb1df146756	4607	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
mbed_official	76:aeb1df146756	4608	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
mbed_official	76:aeb1df146756	4609	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
mbed_official	76:aeb1df146756	4610
mbed_official	76:aeb1df146756	4611	/**
mbed_official	76:aeb1df146756	4612	* @brief EXTI12 configuration
mbed_official	76:aeb1df146756	4613	*/
mbed_official	76:aeb1df146756	4614	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
mbed_official	76:aeb1df146756	4615	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
mbed_official	76:aeb1df146756	4616	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
mbed_official	76:aeb1df146756	4617	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
mbed_official	76:aeb1df146756	4618	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
mbed_official	76:aeb1df146756	4619	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) /!< PF[12] pin /
mbed_official	76:aeb1df146756	4620	#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) /!< PG[12] pin /
mbed_official	76:aeb1df146756	4621
mbed_official	76:aeb1df146756	4622	/**
mbed_official	76:aeb1df146756	4623	* @brief EXTI13 configuration
mbed_official	76:aeb1df146756	4624	*/
mbed_official	76:aeb1df146756	4625	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
mbed_official	76:aeb1df146756	4626	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
mbed_official	76:aeb1df146756	4627	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
mbed_official	76:aeb1df146756	4628	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
mbed_official	76:aeb1df146756	4629	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
mbed_official	76:aeb1df146756	4630	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) /!< PF[13] pin /
mbed_official	76:aeb1df146756	4631	#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) /!< PG[13] pin /
mbed_official	76:aeb1df146756	4632
mbed_official	76:aeb1df146756	4633	/**
mbed_official	76:aeb1df146756	4634	* @brief EXTI14 configuration
mbed_official	76:aeb1df146756	4635	*/
mbed_official	76:aeb1df146756	4636	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
mbed_official	76:aeb1df146756	4637	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
mbed_official	76:aeb1df146756	4638	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
mbed_official	76:aeb1df146756	4639	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
mbed_official	76:aeb1df146756	4640	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
mbed_official	76:aeb1df146756	4641	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) /!< PF[14] pin /
mbed_official	76:aeb1df146756	4642	#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) /!< PG[14] pin /
mbed_official	76:aeb1df146756	4643
mbed_official	76:aeb1df146756	4644	/**
mbed_official	76:aeb1df146756	4645	* @brief EXTI15 configuration
mbed_official	76:aeb1df146756	4646	*/
mbed_official	76:aeb1df146756	4647	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
mbed_official	76:aeb1df146756	4648	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
mbed_official	76:aeb1df146756	4649	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
mbed_official	76:aeb1df146756	4650	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
mbed_official	76:aeb1df146756	4651	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
mbed_official	76:aeb1df146756	4652	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) /!< PF[15] pin /
mbed_official	76:aeb1df146756	4653	#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) /!< PG[15] pin /
mbed_official	76:aeb1df146756	4654
mbed_official	76:aeb1df146756	4655	/******************************************************************************/
mbed_official	76:aeb1df146756	4656	/* */
mbed_official	76:aeb1df146756	4657	/* Routing Interface (RI) */
mbed_official	76:aeb1df146756	4658	/* */
mbed_official	76:aeb1df146756	4659	/******************************************************************************/
mbed_official	76:aeb1df146756	4660
mbed_official	76:aeb1df146756	4661	/****************** Bit definition for RI_ICR register ******************/
mbed_official	76:aeb1df146756	4662	#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /!< IC1Z[3:0] bits (Input Capture 1 select bits) /
mbed_official	76:aeb1df146756	4663	#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4664	#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4665	#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4666	#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4667
mbed_official	76:aeb1df146756	4668	#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /!< IC2Z[3:0] bits (Input Capture 2 select bits) /
mbed_official	76:aeb1df146756	4669	#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	76:aeb1df146756	4670	#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	76:aeb1df146756	4671	#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	76:aeb1df146756	4672	#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	76:aeb1df146756	4673
mbed_official	76:aeb1df146756	4674	#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /!< IC3Z[3:0] bits (Input Capture 3 select bits) /
mbed_official	76:aeb1df146756	4675	#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	4676	#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	4677	#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	4678	#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	76:aeb1df146756	4679
mbed_official	76:aeb1df146756	4680	#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /!< IC4Z[3:0] bits (Input Capture 4 select bits) /
mbed_official	76:aeb1df146756	4681	#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	76:aeb1df146756	4682	#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4683	#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /!< Bit 2 /
mbed_official	76:aeb1df146756	4684	#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /!< Bit 3 /
mbed_official	76:aeb1df146756	4685
mbed_official	76:aeb1df146756	4686	#define RI_ICR_TIM ((uint32_t)0x00030000) /!< TIM[3:0] bits (Timers select bits) /
mbed_official	76:aeb1df146756	4687	#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	4688	#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4689
mbed_official	76:aeb1df146756	4690	#define RI_ICR_IC1 ((uint32_t)0x00040000) /!< Input capture 1 /
mbed_official	76:aeb1df146756	4691	#define RI_ICR_IC2 ((uint32_t)0x00080000) /!< Input capture 2 /
mbed_official	76:aeb1df146756	4692	#define RI_ICR_IC3 ((uint32_t)0x00100000) /!< Input capture 3 /
mbed_official	76:aeb1df146756	4693	#define RI_ICR_IC4 ((uint32_t)0x00200000) /!< Input capture 4 /
mbed_official	76:aeb1df146756	4694
mbed_official	76:aeb1df146756	4695	/****************** Bit definition for RI_ASCR1 register ******************/
mbed_official	76:aeb1df146756	4696	#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) /
mbed_official	76:aeb1df146756	4697	#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4698	#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4699	#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4700	#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4701	#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	4702	#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /!< Bit 5 /
mbed_official	76:aeb1df146756	4703	#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /!< Bit 6 /
mbed_official	76:aeb1df146756	4704	#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /!< Bit 7 /
mbed_official	76:aeb1df146756	4705	#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /!< Bit 8 /
mbed_official	76:aeb1df146756	4706	#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /!< Bit 9 /
mbed_official	76:aeb1df146756	4707	#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /!< Bit 10 /
mbed_official	76:aeb1df146756	4708	#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /!< Bit 11 /
mbed_official	76:aeb1df146756	4709	#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4710	#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4711	#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4712	#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4713	#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /!< Bit 16 /
mbed_official	76:aeb1df146756	4714	#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /!< Bit 18 /
mbed_official	76:aeb1df146756	4715	#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /!< Bit 19 /
mbed_official	76:aeb1df146756	4716	#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /!< Bit 20 /
mbed_official	76:aeb1df146756	4717	#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /!< Bit 21 /
mbed_official	76:aeb1df146756	4718	#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /!< Bit 22 /
mbed_official	76:aeb1df146756	4719	#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /!< Bit 23 /
mbed_official	76:aeb1df146756	4720	#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /!< Bit 24 /
mbed_official	76:aeb1df146756	4721	#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /!< Bit 25 /
mbed_official	76:aeb1df146756	4722	#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /!< ADC analog switch selection for internal node to COMP1 /
mbed_official	76:aeb1df146756	4723	#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /!< Bit 27 /
mbed_official	76:aeb1df146756	4724	#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /!< Bit 28 /
mbed_official	76:aeb1df146756	4725	#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /!< Bit 29 /
mbed_official	76:aeb1df146756	4726	#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /!< Bit 30 /
mbed_official	76:aeb1df146756	4727	#define RI_ASCR1_SCM ((uint32_t)0x80000000) /!< I/O Switch control mode /
mbed_official	76:aeb1df146756	4728
mbed_official	76:aeb1df146756	4729	/****************** Bit definition for RI_ASCR2 register ******************/
mbed_official	76:aeb1df146756	4730	#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /!< GR10-1 selection bit /
mbed_official	76:aeb1df146756	4731	#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /!< GR10-2 selection bit /
mbed_official	76:aeb1df146756	4732	#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /!< GR10-3 selection bit /
mbed_official	76:aeb1df146756	4733	#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /!< GR10-4 selection bit /
mbed_official	76:aeb1df146756	4734	#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /!< GR6-1 selection bit /
mbed_official	76:aeb1df146756	4735	#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /!< GR6-2 selection bit /
mbed_official	76:aeb1df146756	4736	#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /!< GR5-1 selection bit /
mbed_official	76:aeb1df146756	4737	#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /!< GR5-2 selection bit /
mbed_official	76:aeb1df146756	4738	#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /!< GR5-3 selection bit /
mbed_official	76:aeb1df146756	4739	#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /!< GR4-1 selection bit /
mbed_official	76:aeb1df146756	4740	#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /!< GR4-2 selection bit /
mbed_official	76:aeb1df146756	4741	#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /!< GR4-3 selection bit /
mbed_official	76:aeb1df146756	4742	#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /!< GR4-4 selection bit /
mbed_official	76:aeb1df146756	4743	#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /!< CH0b selection bit /
mbed_official	76:aeb1df146756	4744	#define RI_ASCR2_CH1b ((uint32_t)0x00020000) /!< CH1b selection bit /
mbed_official	76:aeb1df146756	4745	#define RI_ASCR2_CH2b ((uint32_t)0x00040000) /!< CH2b selection bit /
mbed_official	76:aeb1df146756	4746	#define RI_ASCR2_CH3b ((uint32_t)0x00080000) /!< CH3b selection bit /
mbed_official	76:aeb1df146756	4747	#define RI_ASCR2_CH6b ((uint32_t)0x00100000) /!< CH6b selection bit /
mbed_official	76:aeb1df146756	4748	#define RI_ASCR2_CH7b ((uint32_t)0x00200000) /!< CH7b selection bit /
mbed_official	76:aeb1df146756	4749	#define RI_ASCR2_CH8b ((uint32_t)0x00400000) /!< CH8b selection bit /
mbed_official	76:aeb1df146756	4750	#define RI_ASCR2_CH9b ((uint32_t)0x00800000) /!< CH9b selection bit /
mbed_official	76:aeb1df146756	4751	#define RI_ASCR2_CH10b ((uint32_t)0x01000000) /!< CH10b selection bit /
mbed_official	76:aeb1df146756	4752	#define RI_ASCR2_CH11b ((uint32_t)0x02000000) /!< CH11b selection bit /
mbed_official	76:aeb1df146756	4753	#define RI_ASCR2_CH12b ((uint32_t)0x04000000) /!< CH12b selection bit /
mbed_official	76:aeb1df146756	4754	#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /!< GR6-3 selection bit /
mbed_official	76:aeb1df146756	4755	#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /!< GR6-4 selection bit /
mbed_official	76:aeb1df146756	4756	#define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) /!< GR5-4 selection bit /
mbed_official	76:aeb1df146756	4757
mbed_official	76:aeb1df146756	4758	/****************** Bit definition for RI_HYSCR1 register ******************/
mbed_official	76:aeb1df146756	4759	#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /!< PA[15:0] Port A Hysteresis selection /
mbed_official	76:aeb1df146756	4760	#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4761	#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4762	#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4763	#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4764	#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	4765	#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /!< Bit 5 /
mbed_official	76:aeb1df146756	4766	#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /!< Bit 6 /
mbed_official	76:aeb1df146756	4767	#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /!< Bit 7 /
mbed_official	76:aeb1df146756	4768	#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /!< Bit 8 /
mbed_official	76:aeb1df146756	4769	#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /!< Bit 9 /
mbed_official	76:aeb1df146756	4770	#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /!< Bit 10 /
mbed_official	76:aeb1df146756	4771	#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /!< Bit 11 /
mbed_official	76:aeb1df146756	4772	#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4773	#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4774	#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4775	#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4776
mbed_official	76:aeb1df146756	4777	#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /!< PB[15:0] Port B Hysteresis selection /
mbed_official	76:aeb1df146756	4778	#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	4779	#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4780	#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	4781	#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	4782	#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	76:aeb1df146756	4783	#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	76:aeb1df146756	4784	#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	76:aeb1df146756	4785	#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	76:aeb1df146756	4786	#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	76:aeb1df146756	4787	#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	76:aeb1df146756	4788	#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	76:aeb1df146756	4789	#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	76:aeb1df146756	4790	#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4791	#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4792	#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4793	#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4794
mbed_official	76:aeb1df146756	4795	/****************** Bit definition for RI_HYSCR2 register ******************/
mbed_official	76:aeb1df146756	4796	#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /!< PC[15:0] Port C Hysteresis selection /
mbed_official	76:aeb1df146756	4797	#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4798	#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4799	#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4800	#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4801	#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	4802	#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /!< Bit 5 /
mbed_official	76:aeb1df146756	4803	#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /!< Bit 6 /
mbed_official	76:aeb1df146756	4804	#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /!< Bit 7 /
mbed_official	76:aeb1df146756	4805	#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /!< Bit 8 /
mbed_official	76:aeb1df146756	4806	#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /!< Bit 9 /
mbed_official	76:aeb1df146756	4807	#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /!< Bit 10 /
mbed_official	76:aeb1df146756	4808	#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /!< Bit 11 /
mbed_official	76:aeb1df146756	4809	#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4810	#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4811	#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4812	#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4813
mbed_official	76:aeb1df146756	4814	#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /!< PD[15:0] Port D Hysteresis selection /
mbed_official	76:aeb1df146756	4815	#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	4816	#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4817	#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	4818	#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	4819	#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	76:aeb1df146756	4820	#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	76:aeb1df146756	4821	#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	76:aeb1df146756	4822	#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	76:aeb1df146756	4823	#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	76:aeb1df146756	4824	#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	76:aeb1df146756	4825	#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	76:aeb1df146756	4826	#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	76:aeb1df146756	4827	#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4828	#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4829	#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4830	#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4831
mbed_official	76:aeb1df146756	4832	/****************** Bit definition for RI_HYSCR3 register ******************/
mbed_official	76:aeb1df146756	4833	#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /!< PE[15:0] Port E Hysteresis selection /
mbed_official	76:aeb1df146756	4834	#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4835	#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4836	#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4837	#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4838	#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	4839	#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /!< Bit 5 /
mbed_official	76:aeb1df146756	4840	#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /!< Bit 6 /
mbed_official	76:aeb1df146756	4841	#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /!< Bit 7 /
mbed_official	76:aeb1df146756	4842	#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /!< Bit 8 /
mbed_official	76:aeb1df146756	4843	#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /!< Bit 9 /
mbed_official	76:aeb1df146756	4844	#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /!< Bit 10 /
mbed_official	76:aeb1df146756	4845	#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /!< Bit 11 /
mbed_official	76:aeb1df146756	4846	#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4847	#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4848	#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4849	#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4850
mbed_official	76:aeb1df146756	4851	#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /!< PF[15:0] Port F Hysteresis selection /
mbed_official	76:aeb1df146756	4852	#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	76:aeb1df146756	4853	#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	76:aeb1df146756	4854	#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	76:aeb1df146756	4855	#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	76:aeb1df146756	4856	#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	76:aeb1df146756	4857	#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	76:aeb1df146756	4858	#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	76:aeb1df146756	4859	#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	76:aeb1df146756	4860	#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	76:aeb1df146756	4861	#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	76:aeb1df146756	4862	#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	76:aeb1df146756	4863	#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	76:aeb1df146756	4864	#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4865	#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4866	#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4867	#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4868
mbed_official	76:aeb1df146756	4869	/****************** Bit definition for RI_HYSCR4 register ******************/
mbed_official	76:aeb1df146756	4870	#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /!< PG[15:0] Port G Hysteresis selection /
mbed_official	76:aeb1df146756	4871	#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	76:aeb1df146756	4872	#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	76:aeb1df146756	4873	#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	76:aeb1df146756	4874	#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	76:aeb1df146756	4875	#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /!< Bit 4 /
mbed_official	76:aeb1df146756	4876	#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /!< Bit 5 /
mbed_official	76:aeb1df146756	4877	#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /!< Bit 6 /
mbed_official	76:aeb1df146756	4878	#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /!< Bit 7 /
mbed_official	76:aeb1df146756	4879	#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /!< Bit 8 /
mbed_official	76:aeb1df146756	4880	#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /!< Bit 9 /
mbed_official	76:aeb1df146756	4881	#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /!< Bit 10 /
mbed_official	76:aeb1df146756	4882	#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /!< Bit 11 /
mbed_official	76:aeb1df146756	4883	#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /!< Bit 12 /
mbed_official	76:aeb1df146756	4884	#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /!< Bit 13 /
mbed_official	76:aeb1df146756	4885	#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /!< Bit 14 /
mbed_official	76:aeb1df146756	4886	#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /!< Bit 15 /
mbed_official	76:aeb1df146756	4887
mbed_official	76:aeb1df146756	4888	/******************************************************************************/
mbed_official	76:aeb1df146756	4889	/* */
mbed_official	76:aeb1df146756	4890	/* Timers (TIM) */
mbed_official	76:aeb1df146756	4891	/* */
mbed_official	76:aeb1df146756	4892	/******************************************************************************/
mbed_official	76:aeb1df146756	4893
mbed_official	76:aeb1df146756	4894	/***************** Bit definition for TIM_CR1 register ******************/
mbed_official	76:aeb1df146756	4895	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
mbed_official	76:aeb1df146756	4896	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
mbed_official	76:aeb1df146756	4897	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
mbed_official	76:aeb1df146756	4898	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
mbed_official	76:aeb1df146756	4899	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
mbed_official	76:aeb1df146756	4900
mbed_official	76:aeb1df146756	4901	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
mbed_official	76:aeb1df146756	4902	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
mbed_official	76:aeb1df146756	4903	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
mbed_official	76:aeb1df146756	4904
mbed_official	76:aeb1df146756	4905	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
mbed_official	76:aeb1df146756	4906
mbed_official	76:aeb1df146756	4907	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
mbed_official	76:aeb1df146756	4908	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	4909	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	4910
mbed_official	76:aeb1df146756	4911	/***************** Bit definition for TIM_CR2 register ******************/
mbed_official	76:aeb1df146756	4912	#define TIM_CR2_CCDS ((uint16_t)0x0008) /!<Capture/Compare DMA Selection /
mbed_official	76:aeb1df146756	4913
mbed_official	76:aeb1df146756	4914	#define TIM_CR2_MMS ((uint16_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
mbed_official	76:aeb1df146756	4915	#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	4916	#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	4917	#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	4918
mbed_official	76:aeb1df146756	4919	#define TIM_CR2_TI1S ((uint16_t)0x0080) /!<TI1 Selection /
mbed_official	76:aeb1df146756	4920
mbed_official	76:aeb1df146756	4921	/***************** Bit definition for TIM_SMCR register *****************/
mbed_official	76:aeb1df146756	4922	#define TIM_SMCR_SMS ((uint16_t)0x0007) /!<SMS[2:0] bits (Slave mode selection) /
mbed_official	76:aeb1df146756	4923	#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /!<Bit 0 /
mbed_official	76:aeb1df146756	4924	#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /!<Bit 1 /
mbed_official	76:aeb1df146756	4925	#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /!<Bit 2 /
mbed_official	76:aeb1df146756	4926
mbed_official	76:aeb1df146756	4927	#define TIM_SMCR_OCCS ((uint16_t)0x0008) /!<OCCS bits (OCref Clear Selection) /
mbed_official	76:aeb1df146756	4928
mbed_official	76:aeb1df146756	4929	#define TIM_SMCR_TS ((uint16_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
mbed_official	76:aeb1df146756	4930	#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	4931	#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	4932	#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	4933
mbed_official	76:aeb1df146756	4934	#define TIM_SMCR_MSM ((uint16_t)0x0080) /!<Master/slave mode /
mbed_official	76:aeb1df146756	4935
mbed_official	76:aeb1df146756	4936	#define TIM_SMCR_ETF ((uint16_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
mbed_official	76:aeb1df146756	4937	#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	4938	#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	4939	#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /!<Bit 2 /
mbed_official	76:aeb1df146756	4940	#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /!<Bit 3 /
mbed_official	76:aeb1df146756	4941
mbed_official	76:aeb1df146756	4942	#define TIM_SMCR_ETPS ((uint16_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
mbed_official	76:aeb1df146756	4943	#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	4944	#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	4945
mbed_official	76:aeb1df146756	4946	#define TIM_SMCR_ECE ((uint16_t)0x4000) /!<External clock enable /
mbed_official	76:aeb1df146756	4947	#define TIM_SMCR_ETP ((uint16_t)0x8000) /!<External trigger polarity /
mbed_official	76:aeb1df146756	4948
mbed_official	76:aeb1df146756	4949	/***************** Bit definition for TIM_DIER register *****************/
mbed_official	76:aeb1df146756	4950	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
mbed_official	76:aeb1df146756	4951	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
mbed_official	76:aeb1df146756	4952	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
mbed_official	76:aeb1df146756	4953	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
mbed_official	76:aeb1df146756	4954	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
mbed_official	76:aeb1df146756	4955	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
mbed_official	76:aeb1df146756	4956	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
mbed_official	76:aeb1df146756	4957	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
mbed_official	76:aeb1df146756	4958	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
mbed_official	76:aeb1df146756	4959	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
mbed_official	76:aeb1df146756	4960	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
mbed_official	76:aeb1df146756	4961	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
mbed_official	76:aeb1df146756	4962
mbed_official	76:aeb1df146756	4963	/****************** Bit definition for TIM_SR register ******************/
mbed_official	76:aeb1df146756	4964	#define TIM_SR_UIF ((uint16_t)0x0001) /!<Update interrupt Flag /
mbed_official	76:aeb1df146756	4965	#define TIM_SR_CC1IF ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
mbed_official	76:aeb1df146756	4966	#define TIM_SR_CC2IF ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
mbed_official	76:aeb1df146756	4967	#define TIM_SR_CC3IF ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
mbed_official	76:aeb1df146756	4968	#define TIM_SR_CC4IF ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
mbed_official	76:aeb1df146756	4969	#define TIM_SR_TIF ((uint16_t)0x0040) /!<Trigger interrupt Flag /
mbed_official	76:aeb1df146756	4970	#define TIM_SR_CC1OF ((uint16_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
mbed_official	76:aeb1df146756	4971	#define TIM_SR_CC2OF ((uint16_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
mbed_official	76:aeb1df146756	4972	#define TIM_SR_CC3OF ((uint16_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
mbed_official	76:aeb1df146756	4973	#define TIM_SR_CC4OF ((uint16_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
mbed_official	76:aeb1df146756	4974
mbed_official	76:aeb1df146756	4975	/***************** Bit definition for TIM_EGR register ******************/
mbed_official	76:aeb1df146756	4976	#define TIM_EGR_UG ((uint8_t)0x01) /!<Update Generation /
mbed_official	76:aeb1df146756	4977	#define TIM_EGR_CC1G ((uint8_t)0x02) /!<Capture/Compare 1 Generation /
mbed_official	76:aeb1df146756	4978	#define TIM_EGR_CC2G ((uint8_t)0x04) /!<Capture/Compare 2 Generation /
mbed_official	76:aeb1df146756	4979	#define TIM_EGR_CC3G ((uint8_t)0x08) /!<Capture/Compare 3 Generation /
mbed_official	76:aeb1df146756	4980	#define TIM_EGR_CC4G ((uint8_t)0x10) /!<Capture/Compare 4 Generation /
mbed_official	76:aeb1df146756	4981	#define TIM_EGR_TG ((uint8_t)0x40) /!<Trigger Generation /
mbed_official	76:aeb1df146756	4982
mbed_official	76:aeb1df146756	4983	/**************** Bit definition for TIM_CCMR1 register *****************/
mbed_official	76:aeb1df146756	4984	#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
mbed_official	76:aeb1df146756	4985	#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /!<Bit 0 /
mbed_official	76:aeb1df146756	4986	#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /!<Bit 1 /
mbed_official	76:aeb1df146756	4987
mbed_official	76:aeb1df146756	4988	#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /!<Output Compare 1 Fast enable /
mbed_official	76:aeb1df146756	4989	#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /!<Output Compare 1 Preload enable /
mbed_official	76:aeb1df146756	4990
mbed_official	76:aeb1df146756	4991	#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
mbed_official	76:aeb1df146756	4992	#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	4993	#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	4994	#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	4995
mbed_official	76:aeb1df146756	4996	#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /!<Output Compare 1Clear Enable /
mbed_official	76:aeb1df146756	4997
mbed_official	76:aeb1df146756	4998	#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
mbed_official	76:aeb1df146756	4999	#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	5000	#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	5001
mbed_official	76:aeb1df146756	5002	#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /!<Output Compare 2 Fast enable /
mbed_official	76:aeb1df146756	5003	#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /!<Output Compare 2 Preload enable /
mbed_official	76:aeb1df146756	5004
mbed_official	76:aeb1df146756	5005	#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
mbed_official	76:aeb1df146756	5006	#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5007	#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5008	#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /!<Bit 2 /
mbed_official	76:aeb1df146756	5009
mbed_official	76:aeb1df146756	5010	#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /!<Output Compare 2 Clear Enable /
mbed_official	76:aeb1df146756	5011
mbed_official	76:aeb1df146756	5012	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5013
mbed_official	76:aeb1df146756	5014	#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
mbed_official	76:aeb1df146756	5015	#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
mbed_official	76:aeb1df146756	5016	#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
mbed_official	76:aeb1df146756	5017
mbed_official	76:aeb1df146756	5018	#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
mbed_official	76:aeb1df146756	5019	#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5020	#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5021	#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	5022	#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /!<Bit 3 /
mbed_official	76:aeb1df146756	5023
mbed_official	76:aeb1df146756	5024	#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
mbed_official	76:aeb1df146756	5025	#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
mbed_official	76:aeb1df146756	5026	#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
mbed_official	76:aeb1df146756	5027
mbed_official	76:aeb1df146756	5028	#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
mbed_official	76:aeb1df146756	5029	#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5030	#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5031	#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /!<Bit 2 /
mbed_official	76:aeb1df146756	5032	#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /!<Bit 3 /
mbed_official	76:aeb1df146756	5033
mbed_official	76:aeb1df146756	5034	/**************** Bit definition for TIM_CCMR2 register *****************/
mbed_official	76:aeb1df146756	5035	#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
mbed_official	76:aeb1df146756	5036	#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /!<Bit 0 /
mbed_official	76:aeb1df146756	5037	#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /!<Bit 1 /
mbed_official	76:aeb1df146756	5038
mbed_official	76:aeb1df146756	5039	#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /!<Output Compare 3 Fast enable /
mbed_official	76:aeb1df146756	5040	#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /!<Output Compare 3 Preload enable /
mbed_official	76:aeb1df146756	5041
mbed_official	76:aeb1df146756	5042	#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
mbed_official	76:aeb1df146756	5043	#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5044	#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5045	#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	5046
mbed_official	76:aeb1df146756	5047	#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /!<Output Compare 3 Clear Enable /
mbed_official	76:aeb1df146756	5048
mbed_official	76:aeb1df146756	5049	#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
mbed_official	76:aeb1df146756	5050	#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	5051	#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	5052
mbed_official	76:aeb1df146756	5053	#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /!<Output Compare 4 Fast enable /
mbed_official	76:aeb1df146756	5054	#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /!<Output Compare 4 Preload enable /
mbed_official	76:aeb1df146756	5055
mbed_official	76:aeb1df146756	5056	#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
mbed_official	76:aeb1df146756	5057	#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5058	#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5059	#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /!<Bit 2 /
mbed_official	76:aeb1df146756	5060
mbed_official	76:aeb1df146756	5061	#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /!<Output Compare 4 Clear Enable /
mbed_official	76:aeb1df146756	5062
mbed_official	76:aeb1df146756	5063	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5064
mbed_official	76:aeb1df146756	5065	#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
mbed_official	76:aeb1df146756	5066	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
mbed_official	76:aeb1df146756	5067	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
mbed_official	76:aeb1df146756	5068
mbed_official	76:aeb1df146756	5069	#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
mbed_official	76:aeb1df146756	5070	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5071	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5072	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /!<Bit 2 /
mbed_official	76:aeb1df146756	5073	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /!<Bit 3 /
mbed_official	76:aeb1df146756	5074
mbed_official	76:aeb1df146756	5075	#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
mbed_official	76:aeb1df146756	5076	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
mbed_official	76:aeb1df146756	5077	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
mbed_official	76:aeb1df146756	5078
mbed_official	76:aeb1df146756	5079	#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
mbed_official	76:aeb1df146756	5080	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5081	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5082	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /!<Bit 2 /
mbed_official	76:aeb1df146756	5083	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /!<Bit 3 /
mbed_official	76:aeb1df146756	5084
mbed_official	76:aeb1df146756	5085	/***************** Bit definition for TIM_CCER register *****************/
mbed_official	76:aeb1df146756	5086	#define TIM_CCER_CC1E ((uint16_t)0x0001) /!<Capture/Compare 1 output enable /
mbed_official	76:aeb1df146756	5087	#define TIM_CCER_CC1P ((uint16_t)0x0002) /!<Capture/Compare 1 output Polarity /
mbed_official	76:aeb1df146756	5088	#define TIM_CCER_CC1NP ((uint16_t)0x0008) /!<Capture/Compare 1 Complementary output Polarity /
mbed_official	76:aeb1df146756	5089	#define TIM_CCER_CC2E ((uint16_t)0x0010) /!<Capture/Compare 2 output enable /
mbed_official	76:aeb1df146756	5090	#define TIM_CCER_CC2P ((uint16_t)0x0020) /!<Capture/Compare 2 output Polarity /
mbed_official	76:aeb1df146756	5091	#define TIM_CCER_CC2NP ((uint16_t)0x0080) /!<Capture/Compare 2 Complementary output Polarity /
mbed_official	76:aeb1df146756	5092	#define TIM_CCER_CC3E ((uint16_t)0x0100) /!<Capture/Compare 3 output enable /
mbed_official	76:aeb1df146756	5093	#define TIM_CCER_CC3P ((uint16_t)0x0200) /!<Capture/Compare 3 output Polarity /
mbed_official	76:aeb1df146756	5094	#define TIM_CCER_CC3NP ((uint16_t)0x0800) /!<Capture/Compare 3 Complementary output Polarity /
mbed_official	76:aeb1df146756	5095	#define TIM_CCER_CC4E ((uint16_t)0x1000) /!<Capture/Compare 4 output enable /
mbed_official	76:aeb1df146756	5096	#define TIM_CCER_CC4P ((uint16_t)0x2000) /!<Capture/Compare 4 output Polarity /
mbed_official	76:aeb1df146756	5097	#define TIM_CCER_CC4NP ((uint16_t)0x8000) /!<Capture/Compare 4 Complementary output Polarity /
mbed_official	76:aeb1df146756	5098
mbed_official	76:aeb1df146756	5099	/***************** Bit definition for TIM_CNT register ******************/
mbed_official	76:aeb1df146756	5100	#define TIM_CNT_CNT ((uint16_t)0xFFFF) /!<Counter Value /
mbed_official	76:aeb1df146756	5101
mbed_official	76:aeb1df146756	5102	/***************** Bit definition for TIM_PSC register ******************/
mbed_official	76:aeb1df146756	5103	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
mbed_official	76:aeb1df146756	5104
mbed_official	76:aeb1df146756	5105	/***************** Bit definition for TIM_ARR register ******************/
mbed_official	76:aeb1df146756	5106	#define TIM_ARR_ARR ((uint16_t)0xFFFF) /!<actual auto-reload Value /
mbed_official	76:aeb1df146756	5107
mbed_official	76:aeb1df146756	5108	/***************** Bit definition for TIM_CCR1 register *****************/
mbed_official	76:aeb1df146756	5109	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
mbed_official	76:aeb1df146756	5110
mbed_official	76:aeb1df146756	5111	/***************** Bit definition for TIM_CCR2 register *****************/
mbed_official	76:aeb1df146756	5112	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
mbed_official	76:aeb1df146756	5113
mbed_official	76:aeb1df146756	5114	/***************** Bit definition for TIM_CCR3 register *****************/
mbed_official	76:aeb1df146756	5115	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
mbed_official	76:aeb1df146756	5116
mbed_official	76:aeb1df146756	5117	/***************** Bit definition for TIM_CCR4 register *****************/
mbed_official	76:aeb1df146756	5118	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
mbed_official	76:aeb1df146756	5119
mbed_official	76:aeb1df146756	5120	/***************** Bit definition for TIM_DCR register ******************/
mbed_official	76:aeb1df146756	5121	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
mbed_official	76:aeb1df146756	5122	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
mbed_official	76:aeb1df146756	5123	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
mbed_official	76:aeb1df146756	5124	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
mbed_official	76:aeb1df146756	5125	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
mbed_official	76:aeb1df146756	5126	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
mbed_official	76:aeb1df146756	5127
mbed_official	76:aeb1df146756	5128	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
mbed_official	76:aeb1df146756	5129	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
mbed_official	76:aeb1df146756	5130	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
mbed_official	76:aeb1df146756	5131	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
mbed_official	76:aeb1df146756	5132	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
mbed_official	76:aeb1df146756	5133	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
mbed_official	76:aeb1df146756	5134
mbed_official	76:aeb1df146756	5135	/***************** Bit definition for TIM_DMAR register *****************/
mbed_official	76:aeb1df146756	5136	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
mbed_official	76:aeb1df146756	5137
mbed_official	76:aeb1df146756	5138	/***************** Bit definition for TIM_OR register *******************/
mbed_official	76:aeb1df146756	5139	#define TIM_OR_TI1RMP ((uint16_t)0x0003) /!<Option register for TI1 Remapping /
mbed_official	76:aeb1df146756	5140	#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
mbed_official	76:aeb1df146756	5141	#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
mbed_official	76:aeb1df146756	5142
mbed_official	76:aeb1df146756	5143	/******************************************************************************/
mbed_official	76:aeb1df146756	5144	/* */
mbed_official	76:aeb1df146756	5145	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official	76:aeb1df146756	5146	/* */
mbed_official	76:aeb1df146756	5147	/******************************************************************************/
mbed_official	76:aeb1df146756	5148
mbed_official	76:aeb1df146756	5149	/***************** Bit definition for USART_SR register *****************/
mbed_official	76:aeb1df146756	5150	#define USART_SR_PE ((uint16_t)0x0001) /!< Parity Error /
mbed_official	76:aeb1df146756	5151	#define USART_SR_FE ((uint16_t)0x0002) /!< Framing Error /
mbed_official	76:aeb1df146756	5152	#define USART_SR_NE ((uint16_t)0x0004) /!< Noise Error Flag /
mbed_official	76:aeb1df146756	5153	#define USART_SR_ORE ((uint16_t)0x0008) /!< OverRun Error /
mbed_official	76:aeb1df146756	5154	#define USART_SR_IDLE ((uint16_t)0x0010) /!< IDLE line detected /
mbed_official	76:aeb1df146756	5155	#define USART_SR_RXNE ((uint16_t)0x0020) /!< Read Data Register Not Empty /
mbed_official	76:aeb1df146756	5156	#define USART_SR_TC ((uint16_t)0x0040) /!< Transmission Complete /
mbed_official	76:aeb1df146756	5157	#define USART_SR_TXE ((uint16_t)0x0080) /!< Transmit Data Register Empty /
mbed_official	76:aeb1df146756	5158	#define USART_SR_LBD ((uint16_t)0x0100) /!< LIN Break Detection Flag /
mbed_official	76:aeb1df146756	5159	#define USART_SR_CTS ((uint16_t)0x0200) /!< CTS Flag /
mbed_official	76:aeb1df146756	5160
mbed_official	76:aeb1df146756	5161	/***************** Bit definition for USART_DR register *****************/
mbed_official	76:aeb1df146756	5162	#define USART_DR_DR ((uint16_t)0x01FF) /!< Data value /
mbed_official	76:aeb1df146756	5163
mbed_official	76:aeb1df146756	5164	/**************** Bit definition for USART_BRR register *****************/
mbed_official	76:aeb1df146756	5165	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
mbed_official	76:aeb1df146756	5166	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
mbed_official	76:aeb1df146756	5167
mbed_official	76:aeb1df146756	5168	/**************** Bit definition for USART_CR1 register *****************/
mbed_official	76:aeb1df146756	5169	#define USART_CR1_SBK ((uint16_t)0x0001) /!< Send Break /
mbed_official	76:aeb1df146756	5170	#define USART_CR1_RWU ((uint16_t)0x0002) /!< Receiver wakeup /
mbed_official	76:aeb1df146756	5171	#define USART_CR1_RE ((uint16_t)0x0004) /!< Receiver Enable /
mbed_official	76:aeb1df146756	5172	#define USART_CR1_TE ((uint16_t)0x0008) /!< Transmitter Enable /
mbed_official	76:aeb1df146756	5173	#define USART_CR1_IDLEIE ((uint16_t)0x0010) /!< IDLE Interrupt Enable /
mbed_official	76:aeb1df146756	5174	#define USART_CR1_RXNEIE ((uint16_t)0x0020) /!< RXNE Interrupt Enable /
mbed_official	76:aeb1df146756	5175	#define USART_CR1_TCIE ((uint16_t)0x0040) /!< Transmission Complete Interrupt Enable /
mbed_official	76:aeb1df146756	5176	#define USART_CR1_TXEIE ((uint16_t)0x0080) /!< PE Interrupt Enable /
mbed_official	76:aeb1df146756	5177	#define USART_CR1_PEIE ((uint16_t)0x0100) /!< PE Interrupt Enable /
mbed_official	76:aeb1df146756	5178	#define USART_CR1_PS ((uint16_t)0x0200) /!< Parity Selection /
mbed_official	76:aeb1df146756	5179	#define USART_CR1_PCE ((uint16_t)0x0400) /!< Parity Control Enable /
mbed_official	76:aeb1df146756	5180	#define USART_CR1_WAKE ((uint16_t)0x0800) /!< Wakeup method /
mbed_official	76:aeb1df146756	5181	#define USART_CR1_M ((uint16_t)0x1000) /!< Word length /
mbed_official	76:aeb1df146756	5182	#define USART_CR1_UE ((uint16_t)0x2000) /!< USART Enable /
mbed_official	76:aeb1df146756	5183	#define USART_CR1_OVER8 ((uint16_t)0x8000) /!< Oversampling by 8-bit mode /
mbed_official	76:aeb1df146756	5184
mbed_official	76:aeb1df146756	5185	/**************** Bit definition for USART_CR2 register *****************/
mbed_official	76:aeb1df146756	5186	#define USART_CR2_ADD ((uint16_t)0x000F) /!< Address of the USART node /
mbed_official	76:aeb1df146756	5187	#define USART_CR2_LBDL ((uint16_t)0x0020) /!< LIN Break Detection Length /
mbed_official	76:aeb1df146756	5188	#define USART_CR2_LBDIE ((uint16_t)0x0040) /!< LIN Break Detection Interrupt Enable /
mbed_official	76:aeb1df146756	5189	#define USART_CR2_LBCL ((uint16_t)0x0100) /!< Last Bit Clock pulse /
mbed_official	76:aeb1df146756	5190	#define USART_CR2_CPHA ((uint16_t)0x0200) /!< Clock Phase /
mbed_official	76:aeb1df146756	5191	#define USART_CR2_CPOL ((uint16_t)0x0400) /!< Clock Polarity /
mbed_official	76:aeb1df146756	5192	#define USART_CR2_CLKEN ((uint16_t)0x0800) /!< Clock Enable /
mbed_official	76:aeb1df146756	5193
mbed_official	76:aeb1df146756	5194	#define USART_CR2_STOP ((uint16_t)0x3000) /!< STOP[1:0] bits (STOP bits) /
mbed_official	76:aeb1df146756	5195	#define USART_CR2_STOP_0 ((uint16_t)0x1000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5196	#define USART_CR2_STOP_1 ((uint16_t)0x2000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5197
mbed_official	76:aeb1df146756	5198	#define USART_CR2_LINEN ((uint16_t)0x4000) /!< LIN mode enable /
mbed_official	76:aeb1df146756	5199
mbed_official	76:aeb1df146756	5200	/**************** Bit definition for USART_CR3 register *****************/
mbed_official	76:aeb1df146756	5201	#define USART_CR3_EIE ((uint16_t)0x0001) /!< Error Interrupt Enable /
mbed_official	76:aeb1df146756	5202	#define USART_CR3_IREN ((uint16_t)0x0002) /!< IrDA mode Enable /
mbed_official	76:aeb1df146756	5203	#define USART_CR3_IRLP ((uint16_t)0x0004) /!< IrDA Low-Power /
mbed_official	76:aeb1df146756	5204	#define USART_CR3_HDSEL ((uint16_t)0x0008) /!< Half-Duplex Selection /
mbed_official	76:aeb1df146756	5205	#define USART_CR3_NACK ((uint16_t)0x0010) /!< Smartcard NACK enable /
mbed_official	76:aeb1df146756	5206	#define USART_CR3_SCEN ((uint16_t)0x0020) /!< Smartcard mode enable /
mbed_official	76:aeb1df146756	5207	#define USART_CR3_DMAR ((uint16_t)0x0040) /!< DMA Enable Receiver /
mbed_official	76:aeb1df146756	5208	#define USART_CR3_DMAT ((uint16_t)0x0080) /!< DMA Enable Transmitter /
mbed_official	76:aeb1df146756	5209	#define USART_CR3_RTSE ((uint16_t)0x0100) /!< RTS Enable /
mbed_official	76:aeb1df146756	5210	#define USART_CR3_CTSE ((uint16_t)0x0200) /!< CTS Enable /
mbed_official	76:aeb1df146756	5211	#define USART_CR3_CTSIE ((uint16_t)0x0400) /!< CTS Interrupt Enable /
mbed_official	76:aeb1df146756	5212	#define USART_CR3_ONEBIT ((uint16_t)0x0800) /!< One sample bit method enable /
mbed_official	76:aeb1df146756	5213
mbed_official	76:aeb1df146756	5214	/**************** Bit definition for USART_GTPR register ****************/
mbed_official	76:aeb1df146756	5215	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
mbed_official	76:aeb1df146756	5216	#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /!< Bit 0 /
mbed_official	76:aeb1df146756	5217	#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /!< Bit 1 /
mbed_official	76:aeb1df146756	5218	#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /!< Bit 2 /
mbed_official	76:aeb1df146756	5219	#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /!< Bit 3 /
mbed_official	76:aeb1df146756	5220	#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /!< Bit 4 /
mbed_official	76:aeb1df146756	5221	#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /!< Bit 5 /
mbed_official	76:aeb1df146756	5222	#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /!< Bit 6 /
mbed_official	76:aeb1df146756	5223	#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /!< Bit 7 /
mbed_official	76:aeb1df146756	5224
mbed_official	76:aeb1df146756	5225	#define USART_GTPR_GT ((uint16_t)0xFF00) /!< Guard time value /
mbed_official	76:aeb1df146756	5226
mbed_official	76:aeb1df146756	5227	/******************************************************************************/
mbed_official	76:aeb1df146756	5228	/* */
mbed_official	76:aeb1df146756	5229	/* Universal Serial Bus (USB) */
mbed_official	76:aeb1df146756	5230	/* */
mbed_official	76:aeb1df146756	5231	/******************************************************************************/
mbed_official	76:aeb1df146756	5232
mbed_official	76:aeb1df146756	5233	/!<Endpoint-specific registers /
mbed_official	76:aeb1df146756	5234	/***************** Bit definition for USB_EP0R register *****************/
mbed_official	76:aeb1df146756	5235	#define USB_EP0R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5236
mbed_official	76:aeb1df146756	5237	#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5238	#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5239	#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5240
mbed_official	76:aeb1df146756	5241	#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5242	#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5243	#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5244
mbed_official	76:aeb1df146756	5245	#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5246	#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5247	#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5248
mbed_official	76:aeb1df146756	5249	#define USB_EP0R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5250
mbed_official	76:aeb1df146756	5251	#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5252	#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5253	#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5254
mbed_official	76:aeb1df146756	5255	#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5256	#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5257
mbed_official	76:aeb1df146756	5258	/***************** Bit definition for USB_EP1R register *****************/
mbed_official	76:aeb1df146756	5259	#define USB_EP1R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5260
mbed_official	76:aeb1df146756	5261	#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5262	#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5263	#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5264
mbed_official	76:aeb1df146756	5265	#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5266	#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5267	#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5268
mbed_official	76:aeb1df146756	5269	#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5270	#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5271	#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5272
mbed_official	76:aeb1df146756	5273	#define USB_EP1R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5274
mbed_official	76:aeb1df146756	5275	#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5276	#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5277	#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5278
mbed_official	76:aeb1df146756	5279	#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5280	#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5281
mbed_official	76:aeb1df146756	5282	/***************** Bit definition for USB_EP2R register *****************/
mbed_official	76:aeb1df146756	5283	#define USB_EP2R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5284
mbed_official	76:aeb1df146756	5285	#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5286	#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5287	#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5288
mbed_official	76:aeb1df146756	5289	#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5290	#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5291	#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5292
mbed_official	76:aeb1df146756	5293	#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5294	#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5295	#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5296
mbed_official	76:aeb1df146756	5297	#define USB_EP2R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5298
mbed_official	76:aeb1df146756	5299	#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5300	#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5301	#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5302
mbed_official	76:aeb1df146756	5303	#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5304	#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5305
mbed_official	76:aeb1df146756	5306	/***************** Bit definition for USB_EP3R register *****************/
mbed_official	76:aeb1df146756	5307	#define USB_EP3R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5308
mbed_official	76:aeb1df146756	5309	#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5310	#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5311	#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5312
mbed_official	76:aeb1df146756	5313	#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5314	#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5315	#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5316
mbed_official	76:aeb1df146756	5317	#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5318	#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5319	#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5320
mbed_official	76:aeb1df146756	5321	#define USB_EP3R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5322
mbed_official	76:aeb1df146756	5323	#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5324	#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5325	#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5326
mbed_official	76:aeb1df146756	5327	#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5328	#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5329
mbed_official	76:aeb1df146756	5330	/***************** Bit definition for USB_EP4R register *****************/
mbed_official	76:aeb1df146756	5331	#define USB_EP4R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5332
mbed_official	76:aeb1df146756	5333	#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5334	#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5335	#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5336
mbed_official	76:aeb1df146756	5337	#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5338	#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5339	#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5340
mbed_official	76:aeb1df146756	5341	#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5342	#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5343	#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5344
mbed_official	76:aeb1df146756	5345	#define USB_EP4R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5346
mbed_official	76:aeb1df146756	5347	#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5348	#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5349	#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5350
mbed_official	76:aeb1df146756	5351	#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5352	#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5353
mbed_official	76:aeb1df146756	5354	/***************** Bit definition for USB_EP5R register *****************/
mbed_official	76:aeb1df146756	5355	#define USB_EP5R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5356
mbed_official	76:aeb1df146756	5357	#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5358	#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5359	#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5360
mbed_official	76:aeb1df146756	5361	#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5362	#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5363	#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5364
mbed_official	76:aeb1df146756	5365	#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5366	#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5367	#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5368
mbed_official	76:aeb1df146756	5369	#define USB_EP5R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5370
mbed_official	76:aeb1df146756	5371	#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5372	#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5373	#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5374
mbed_official	76:aeb1df146756	5375	#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5376	#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5377
mbed_official	76:aeb1df146756	5378	/***************** Bit definition for USB_EP6R register *****************/
mbed_official	76:aeb1df146756	5379	#define USB_EP6R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5380
mbed_official	76:aeb1df146756	5381	#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5382	#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5383	#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5384
mbed_official	76:aeb1df146756	5385	#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5386	#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5387	#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5388
mbed_official	76:aeb1df146756	5389	#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5390	#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5391	#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5392
mbed_official	76:aeb1df146756	5393	#define USB_EP6R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5394
mbed_official	76:aeb1df146756	5395	#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5396	#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5397	#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5398
mbed_official	76:aeb1df146756	5399	#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5400	#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5401
mbed_official	76:aeb1df146756	5402	/***************** Bit definition for USB_EP7R register *****************/
mbed_official	76:aeb1df146756	5403	#define USB_EP7R_EA ((uint16_t)0x000F) /!<Endpoint Address /
mbed_official	76:aeb1df146756	5404
mbed_official	76:aeb1df146756	5405	#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
mbed_official	76:aeb1df146756	5406	#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /!<Bit 0 /
mbed_official	76:aeb1df146756	5407	#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /!<Bit 1 /
mbed_official	76:aeb1df146756	5408
mbed_official	76:aeb1df146756	5409	#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /!<Data Toggle, for transmission transfers /
mbed_official	76:aeb1df146756	5410	#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /!<Correct Transfer for transmission /
mbed_official	76:aeb1df146756	5411	#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /!<Endpoint Kind /
mbed_official	76:aeb1df146756	5412
mbed_official	76:aeb1df146756	5413	#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /!<EP_TYPE[1:0] bits (Endpoint type) /
mbed_official	76:aeb1df146756	5414	#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /!<Bit 0 /
mbed_official	76:aeb1df146756	5415	#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /!<Bit 1 /
mbed_official	76:aeb1df146756	5416
mbed_official	76:aeb1df146756	5417	#define USB_EP7R_SETUP ((uint16_t)0x0800) /!<Setup transaction completed /
mbed_official	76:aeb1df146756	5418
mbed_official	76:aeb1df146756	5419	#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
mbed_official	76:aeb1df146756	5420	#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /!<Bit 0 /
mbed_official	76:aeb1df146756	5421	#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /!<Bit 1 /
mbed_official	76:aeb1df146756	5422
mbed_official	76:aeb1df146756	5423	#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /!<Data Toggle, for reception transfers /
mbed_official	76:aeb1df146756	5424	#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /!<Correct Transfer for reception /
mbed_official	76:aeb1df146756	5425
mbed_official	76:aeb1df146756	5426	/!<Common registers /
mbed_official	76:aeb1df146756	5427	/***************** Bit definition for USB_CNTR register *****************/
mbed_official	76:aeb1df146756	5428	#define USB_CNTR_FRES ((uint16_t)0x0001) /!<Force USB Reset /
mbed_official	76:aeb1df146756	5429	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!<Power down /
mbed_official	76:aeb1df146756	5430	#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /!<Low-power mode /
mbed_official	76:aeb1df146756	5431	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!<Force suspend /
mbed_official	76:aeb1df146756	5432	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!<Resume request /
mbed_official	76:aeb1df146756	5433	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!<Expected Start Of Frame Interrupt Mask /
mbed_official	76:aeb1df146756	5434	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!<Start Of Frame Interrupt Mask /
mbed_official	76:aeb1df146756	5435	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!<RESET Interrupt Mask /
mbed_official	76:aeb1df146756	5436	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!<Suspend mode Interrupt Mask /
mbed_official	76:aeb1df146756	5437	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!<Wakeup Interrupt Mask /
mbed_official	76:aeb1df146756	5438	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!<Error Interrupt Mask /
mbed_official	76:aeb1df146756	5439	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!<Packet Memory Area Over / Underrun Interrupt Mask /
mbed_official	76:aeb1df146756	5440	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!<Correct Transfer Interrupt Mask /
mbed_official	76:aeb1df146756	5441
mbed_official	76:aeb1df146756	5442	/***************** Bit definition for USB_ISTR register *****************/
mbed_official	76:aeb1df146756	5443	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!<Endpoint Identifier /
mbed_official	76:aeb1df146756	5444	#define USB_ISTR_DIR ((uint16_t)0x0010) /!<Direction of transaction /
mbed_official	76:aeb1df146756	5445	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!<Expected Start Of Frame /
mbed_official	76:aeb1df146756	5446	#define USB_ISTR_SOF ((uint16_t)0x0200) /!<Start Of Frame /
mbed_official	76:aeb1df146756	5447	#define USB_ISTR_RESET ((uint16_t)0x0400) /!<USB RESET request /
mbed_official	76:aeb1df146756	5448	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!<Suspend mode request /
mbed_official	76:aeb1df146756	5449	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!<Wake up /
mbed_official	76:aeb1df146756	5450	#define USB_ISTR_ERR ((uint16_t)0x2000) /!<Error /
mbed_official	76:aeb1df146756	5451	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!<Packet Memory Area Over / Underrun /
mbed_official	76:aeb1df146756	5452	#define USB_ISTR_CTR ((uint16_t)0x8000) /!<Correct Transfer /
mbed_official	76:aeb1df146756	5453
mbed_official	76:aeb1df146756	5454	/***************** Bit definition for USB_FNR register ******************/
mbed_official	76:aeb1df146756	5455	#define USB_FNR_FN ((uint16_t)0x07FF) /!<Frame Number /
mbed_official	76:aeb1df146756	5456	#define USB_FNR_LSOF ((uint16_t)0x1800) /!<Lost SOF /
mbed_official	76:aeb1df146756	5457	#define USB_FNR_LCK ((uint16_t)0x2000) /!<Locked /
mbed_official	76:aeb1df146756	5458	#define USB_FNR_RXDM ((uint16_t)0x4000) /!<Receive Data - Line Status /
mbed_official	76:aeb1df146756	5459	#define USB_FNR_RXDP ((uint16_t)0x8000) /!<Receive Data + Line Status /
mbed_official	76:aeb1df146756	5460
mbed_official	76:aeb1df146756	5461	/**************** Bit definition for USB_DADDR register *****************/
mbed_official	76:aeb1df146756	5462	#define USB_DADDR_ADD ((uint8_t)0x7F) /!<ADD[6:0] bits (Device Address) /
mbed_official	76:aeb1df146756	5463	#define USB_DADDR_ADD0 ((uint8_t)0x01) /!<Bit 0 /
mbed_official	76:aeb1df146756	5464	#define USB_DADDR_ADD1 ((uint8_t)0x02) /!<Bit 1 /
mbed_official	76:aeb1df146756	5465	#define USB_DADDR_ADD2 ((uint8_t)0x04) /!<Bit 2 /
mbed_official	76:aeb1df146756	5466	#define USB_DADDR_ADD3 ((uint8_t)0x08) /!<Bit 3 /
mbed_official	76:aeb1df146756	5467	#define USB_DADDR_ADD4 ((uint8_t)0x10) /!<Bit 4 /
mbed_official	76:aeb1df146756	5468	#define USB_DADDR_ADD5 ((uint8_t)0x20) /!<Bit 5 /
mbed_official	76:aeb1df146756	5469	#define USB_DADDR_ADD6 ((uint8_t)0x40) /!<Bit 6 /
mbed_official	76:aeb1df146756	5470
mbed_official	76:aeb1df146756	5471	#define USB_DADDR_EF ((uint8_t)0x80) /!<Enable Function /
mbed_official	76:aeb1df146756	5472
mbed_official	76:aeb1df146756	5473	/**************** Bit definition for USB_BTABLE register ****************/
mbed_official	76:aeb1df146756	5474	#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /!<Buffer Table /
mbed_official	76:aeb1df146756	5475
mbed_official	76:aeb1df146756	5476	/!< Buffer descriptor table /
mbed_official	76:aeb1df146756	5477	/*************** Bit definition for USB_ADDR0_TX register ***************/
mbed_official	76:aeb1df146756	5478	#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 0 /
mbed_official	76:aeb1df146756	5479
mbed_official	76:aeb1df146756	5480	/*************** Bit definition for USB_ADDR1_TX register ***************/
mbed_official	76:aeb1df146756	5481	#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 1 /
mbed_official	76:aeb1df146756	5482
mbed_official	76:aeb1df146756	5483	/*************** Bit definition for USB_ADDR2_TX register ***************/
mbed_official	76:aeb1df146756	5484	#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 2 /
mbed_official	76:aeb1df146756	5485
mbed_official	76:aeb1df146756	5486	/*************** Bit definition for USB_ADDR3_TX register ***************/
mbed_official	76:aeb1df146756	5487	#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 3 /
mbed_official	76:aeb1df146756	5488
mbed_official	76:aeb1df146756	5489	/*************** Bit definition for USB_ADDR4_TX register ***************/
mbed_official	76:aeb1df146756	5490	#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 4 /
mbed_official	76:aeb1df146756	5491
mbed_official	76:aeb1df146756	5492	/*************** Bit definition for USB_ADDR5_TX register ***************/
mbed_official	76:aeb1df146756	5493	#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 5 /
mbed_official	76:aeb1df146756	5494
mbed_official	76:aeb1df146756	5495	/*************** Bit definition for USB_ADDR6_TX register ***************/
mbed_official	76:aeb1df146756	5496	#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 6 /
mbed_official	76:aeb1df146756	5497
mbed_official	76:aeb1df146756	5498	/*************** Bit definition for USB_ADDR7_TX register ***************/
mbed_official	76:aeb1df146756	5499	#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 7 /
mbed_official	76:aeb1df146756	5500
mbed_official	76:aeb1df146756	5501	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5502
mbed_official	76:aeb1df146756	5503	/*************** Bit definition for USB_COUNT0_TX register **************/
mbed_official	76:aeb1df146756	5504	#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 0 /
mbed_official	76:aeb1df146756	5505
mbed_official	76:aeb1df146756	5506	/*************** Bit definition for USB_COUNT1_TX register **************/
mbed_official	76:aeb1df146756	5507	#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 1 /
mbed_official	76:aeb1df146756	5508
mbed_official	76:aeb1df146756	5509	/*************** Bit definition for USB_COUNT2_TX register **************/
mbed_official	76:aeb1df146756	5510	#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 2 /
mbed_official	76:aeb1df146756	5511
mbed_official	76:aeb1df146756	5512	/*************** Bit definition for USB_COUNT3_TX register **************/
mbed_official	76:aeb1df146756	5513	#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 3 /
mbed_official	76:aeb1df146756	5514
mbed_official	76:aeb1df146756	5515	/*************** Bit definition for USB_COUNT4_TX register **************/
mbed_official	76:aeb1df146756	5516	#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 4 /
mbed_official	76:aeb1df146756	5517
mbed_official	76:aeb1df146756	5518	/*************** Bit definition for USB_COUNT5_TX register **************/
mbed_official	76:aeb1df146756	5519	#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 5 /
mbed_official	76:aeb1df146756	5520
mbed_official	76:aeb1df146756	5521	/*************** Bit definition for USB_COUNT6_TX register **************/
mbed_official	76:aeb1df146756	5522	#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 6 /
mbed_official	76:aeb1df146756	5523
mbed_official	76:aeb1df146756	5524	/*************** Bit definition for USB_COUNT7_TX register **************/
mbed_official	76:aeb1df146756	5525	#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 7 /
mbed_official	76:aeb1df146756	5526
mbed_official	76:aeb1df146756	5527	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5528
mbed_official	76:aeb1df146756	5529	/************** Bit definition for USB_COUNT0_TX_0 register *************/
mbed_official	76:aeb1df146756	5530	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
mbed_official	76:aeb1df146756	5531
mbed_official	76:aeb1df146756	5532	/************** Bit definition for USB_COUNT0_TX_1 register *************/
mbed_official	76:aeb1df146756	5533	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
mbed_official	76:aeb1df146756	5534
mbed_official	76:aeb1df146756	5535	/************** Bit definition for USB_COUNT1_TX_0 register *************/
mbed_official	76:aeb1df146756	5536	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
mbed_official	76:aeb1df146756	5537
mbed_official	76:aeb1df146756	5538	/************** Bit definition for USB_COUNT1_TX_1 register *************/
mbed_official	76:aeb1df146756	5539	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
mbed_official	76:aeb1df146756	5540
mbed_official	76:aeb1df146756	5541	/************** Bit definition for USB_COUNT2_TX_0 register *************/
mbed_official	76:aeb1df146756	5542	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
mbed_official	76:aeb1df146756	5543
mbed_official	76:aeb1df146756	5544	/************** Bit definition for USB_COUNT2_TX_1 register *************/
mbed_official	76:aeb1df146756	5545	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
mbed_official	76:aeb1df146756	5546
mbed_official	76:aeb1df146756	5547	/************** Bit definition for USB_COUNT3_TX_0 register *************/
mbed_official	76:aeb1df146756	5548	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
mbed_official	76:aeb1df146756	5549
mbed_official	76:aeb1df146756	5550	/************** Bit definition for USB_COUNT3_TX_1 register *************/
mbed_official	76:aeb1df146756	5551	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
mbed_official	76:aeb1df146756	5552
mbed_official	76:aeb1df146756	5553	/************** Bit definition for USB_COUNT4_TX_0 register *************/
mbed_official	76:aeb1df146756	5554	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
mbed_official	76:aeb1df146756	5555
mbed_official	76:aeb1df146756	5556	/************** Bit definition for USB_COUNT4_TX_1 register *************/
mbed_official	76:aeb1df146756	5557	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
mbed_official	76:aeb1df146756	5558
mbed_official	76:aeb1df146756	5559	/************** Bit definition for USB_COUNT5_TX_0 register *************/
mbed_official	76:aeb1df146756	5560	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
mbed_official	76:aeb1df146756	5561
mbed_official	76:aeb1df146756	5562	/************** Bit definition for USB_COUNT5_TX_1 register *************/
mbed_official	76:aeb1df146756	5563	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
mbed_official	76:aeb1df146756	5564
mbed_official	76:aeb1df146756	5565	/************** Bit definition for USB_COUNT6_TX_0 register *************/
mbed_official	76:aeb1df146756	5566	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
mbed_official	76:aeb1df146756	5567
mbed_official	76:aeb1df146756	5568	/************** Bit definition for USB_COUNT6_TX_1 register *************/
mbed_official	76:aeb1df146756	5569	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
mbed_official	76:aeb1df146756	5570
mbed_official	76:aeb1df146756	5571	/************** Bit definition for USB_COUNT7_TX_0 register *************/
mbed_official	76:aeb1df146756	5572	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
mbed_official	76:aeb1df146756	5573
mbed_official	76:aeb1df146756	5574	/************** Bit definition for USB_COUNT7_TX_1 register *************/
mbed_official	76:aeb1df146756	5575	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
mbed_official	76:aeb1df146756	5576
mbed_official	76:aeb1df146756	5577	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5578
mbed_official	76:aeb1df146756	5579	/*************** Bit definition for USB_ADDR0_RX register ***************/
mbed_official	76:aeb1df146756	5580	#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 0 /
mbed_official	76:aeb1df146756	5581
mbed_official	76:aeb1df146756	5582	/*************** Bit definition for USB_ADDR1_RX register ***************/
mbed_official	76:aeb1df146756	5583	#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 1 /
mbed_official	76:aeb1df146756	5584
mbed_official	76:aeb1df146756	5585	/*************** Bit definition for USB_ADDR2_RX register ***************/
mbed_official	76:aeb1df146756	5586	#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 2 /
mbed_official	76:aeb1df146756	5587
mbed_official	76:aeb1df146756	5588	/*************** Bit definition for USB_ADDR3_RX register ***************/
mbed_official	76:aeb1df146756	5589	#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 3 /
mbed_official	76:aeb1df146756	5590
mbed_official	76:aeb1df146756	5591	/*************** Bit definition for USB_ADDR4_RX register ***************/
mbed_official	76:aeb1df146756	5592	#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 4 /
mbed_official	76:aeb1df146756	5593
mbed_official	76:aeb1df146756	5594	/*************** Bit definition for USB_ADDR5_RX register ***************/
mbed_official	76:aeb1df146756	5595	#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 5 /
mbed_official	76:aeb1df146756	5596
mbed_official	76:aeb1df146756	5597	/*************** Bit definition for USB_ADDR6_RX register ***************/
mbed_official	76:aeb1df146756	5598	#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 6 /
mbed_official	76:aeb1df146756	5599
mbed_official	76:aeb1df146756	5600	/*************** Bit definition for USB_ADDR7_RX register ***************/
mbed_official	76:aeb1df146756	5601	#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 7 /
mbed_official	76:aeb1df146756	5602
mbed_official	76:aeb1df146756	5603	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5604
mbed_official	76:aeb1df146756	5605	/*************** Bit definition for USB_COUNT0_RX register **************/
mbed_official	76:aeb1df146756	5606	#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5607
mbed_official	76:aeb1df146756	5608	#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5609	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5610	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5611	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5612	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5613	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5614
mbed_official	76:aeb1df146756	5615	#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5616
mbed_official	76:aeb1df146756	5617	/*************** Bit definition for USB_COUNT1_RX register **************/
mbed_official	76:aeb1df146756	5618	#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5619
mbed_official	76:aeb1df146756	5620	#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5621	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5622	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5623	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5624	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5625	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5626
mbed_official	76:aeb1df146756	5627	#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5628
mbed_official	76:aeb1df146756	5629	/*************** Bit definition for USB_COUNT2_RX register **************/
mbed_official	76:aeb1df146756	5630	#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5631
mbed_official	76:aeb1df146756	5632	#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5633	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5634	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5635	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5636	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5637	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5638
mbed_official	76:aeb1df146756	5639	#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5640
mbed_official	76:aeb1df146756	5641	/*************** Bit definition for USB_COUNT3_RX register **************/
mbed_official	76:aeb1df146756	5642	#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5643
mbed_official	76:aeb1df146756	5644	#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5645	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5646	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5647	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5648	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5649	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5650
mbed_official	76:aeb1df146756	5651	#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5652
mbed_official	76:aeb1df146756	5653	/*************** Bit definition for USB_COUNT4_RX register **************/
mbed_official	76:aeb1df146756	5654	#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5655
mbed_official	76:aeb1df146756	5656	#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5657	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5658	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5659	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5660	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5661	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5662
mbed_official	76:aeb1df146756	5663	#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5664
mbed_official	76:aeb1df146756	5665	/*************** Bit definition for USB_COUNT5_RX register **************/
mbed_official	76:aeb1df146756	5666	#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5667
mbed_official	76:aeb1df146756	5668	#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5669	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5670	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5671	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5672	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5673	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5674
mbed_official	76:aeb1df146756	5675	#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5676
mbed_official	76:aeb1df146756	5677	/*************** Bit definition for USB_COUNT6_RX register **************/
mbed_official	76:aeb1df146756	5678	#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5679
mbed_official	76:aeb1df146756	5680	#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5681	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5682	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5683	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5684	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5685	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5686
mbed_official	76:aeb1df146756	5687	#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5688
mbed_official	76:aeb1df146756	5689	/*************** Bit definition for USB_COUNT7_RX register **************/
mbed_official	76:aeb1df146756	5690	#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
mbed_official	76:aeb1df146756	5691
mbed_official	76:aeb1df146756	5692	#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
mbed_official	76:aeb1df146756	5693	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5694	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5695	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5696	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5697	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5698
mbed_official	76:aeb1df146756	5699	#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
mbed_official	76:aeb1df146756	5700
mbed_official	76:aeb1df146756	5701	/----------------------------------------------------------------------------/
mbed_official	76:aeb1df146756	5702
mbed_official	76:aeb1df146756	5703	/************** Bit definition for USB_COUNT0_RX_0 register *************/
mbed_official	76:aeb1df146756	5704	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5705
mbed_official	76:aeb1df146756	5706	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5707	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5708	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5709	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5710	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5711	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5712
mbed_official	76:aeb1df146756	5713	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5714
mbed_official	76:aeb1df146756	5715	/************** Bit definition for USB_COUNT0_RX_1 register *************/
mbed_official	76:aeb1df146756	5716	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5717
mbed_official	76:aeb1df146756	5718	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5719	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5720	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5721	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5722	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5723	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5724
mbed_official	76:aeb1df146756	5725	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5726
mbed_official	76:aeb1df146756	5727	/************** Bit definition for USB_COUNT1_RX_0 register *************/
mbed_official	76:aeb1df146756	5728	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5729
mbed_official	76:aeb1df146756	5730	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5731	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5732	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5733	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5734	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5735	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5736
mbed_official	76:aeb1df146756	5737	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5738
mbed_official	76:aeb1df146756	5739	/************** Bit definition for USB_COUNT1_RX_1 register *************/
mbed_official	76:aeb1df146756	5740	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5741
mbed_official	76:aeb1df146756	5742	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5743	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5744	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5745	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5746	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5747	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5748
mbed_official	76:aeb1df146756	5749	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5750
mbed_official	76:aeb1df146756	5751	/************** Bit definition for USB_COUNT2_RX_0 register *************/
mbed_official	76:aeb1df146756	5752	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5753
mbed_official	76:aeb1df146756	5754	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5755	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5756	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5757	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5758	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5759	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5760
mbed_official	76:aeb1df146756	5761	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5762
mbed_official	76:aeb1df146756	5763	/************** Bit definition for USB_COUNT2_RX_1 register *************/
mbed_official	76:aeb1df146756	5764	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5765
mbed_official	76:aeb1df146756	5766	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5767	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5768	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5769	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5770	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5771	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5772
mbed_official	76:aeb1df146756	5773	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5774
mbed_official	76:aeb1df146756	5775	/************** Bit definition for USB_COUNT3_RX_0 register *************/
mbed_official	76:aeb1df146756	5776	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5777
mbed_official	76:aeb1df146756	5778	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5779	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5780	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5781	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5782	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5783	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5784
mbed_official	76:aeb1df146756	5785	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5786
mbed_official	76:aeb1df146756	5787	/************** Bit definition for USB_COUNT3_RX_1 register *************/
mbed_official	76:aeb1df146756	5788	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5789
mbed_official	76:aeb1df146756	5790	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5791	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5792	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5793	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5794	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5795	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5796
mbed_official	76:aeb1df146756	5797	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5798
mbed_official	76:aeb1df146756	5799	/************** Bit definition for USB_COUNT4_RX_0 register *************/
mbed_official	76:aeb1df146756	5800	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5801
mbed_official	76:aeb1df146756	5802	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5803	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5804	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5805	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5806	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5807	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5808
mbed_official	76:aeb1df146756	5809	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5810
mbed_official	76:aeb1df146756	5811	/************** Bit definition for USB_COUNT4_RX_1 register *************/
mbed_official	76:aeb1df146756	5812	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5813
mbed_official	76:aeb1df146756	5814	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5815	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5816	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5817	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5818	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5819	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5820
mbed_official	76:aeb1df146756	5821	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5822
mbed_official	76:aeb1df146756	5823	/************** Bit definition for USB_COUNT5_RX_0 register *************/
mbed_official	76:aeb1df146756	5824	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5825
mbed_official	76:aeb1df146756	5826	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5827	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5828	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5829	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5830	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5831	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5832
mbed_official	76:aeb1df146756	5833	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5834
mbed_official	76:aeb1df146756	5835	/************** Bit definition for USB_COUNT5_RX_1 register *************/
mbed_official	76:aeb1df146756	5836	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5837
mbed_official	76:aeb1df146756	5838	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5839	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5840	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5841	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5842	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5843	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5844
mbed_official	76:aeb1df146756	5845	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5846
mbed_official	76:aeb1df146756	5847	/************* Bit definition for USB_COUNT6_RX_0 register *************/
mbed_official	76:aeb1df146756	5848	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5849
mbed_official	76:aeb1df146756	5850	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5851	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5852	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5853	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5854	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5855	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5856
mbed_official	76:aeb1df146756	5857	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5858
mbed_official	76:aeb1df146756	5859	/************** Bit definition for USB_COUNT6_RX_1 register *************/
mbed_official	76:aeb1df146756	5860	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5861
mbed_official	76:aeb1df146756	5862	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5863	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5864	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5865	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5866	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5867	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5868
mbed_official	76:aeb1df146756	5869	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5870
mbed_official	76:aeb1df146756	5871	/************* Bit definition for USB_COUNT7_RX_0 register **************/
mbed_official	76:aeb1df146756	5872	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
mbed_official	76:aeb1df146756	5873
mbed_official	76:aeb1df146756	5874	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
mbed_official	76:aeb1df146756	5875	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	76:aeb1df146756	5876	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	76:aeb1df146756	5877	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5878	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5879	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5880
mbed_official	76:aeb1df146756	5881	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
mbed_official	76:aeb1df146756	5882
mbed_official	76:aeb1df146756	5883	/************* Bit definition for USB_COUNT7_RX_1 register **************/
mbed_official	76:aeb1df146756	5884	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
mbed_official	76:aeb1df146756	5885
mbed_official	76:aeb1df146756	5886	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
mbed_official	76:aeb1df146756	5887	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	76:aeb1df146756	5888	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	76:aeb1df146756	5889	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	76:aeb1df146756	5890	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	76:aeb1df146756	5891	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	76:aeb1df146756	5892
mbed_official	76:aeb1df146756	5893	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
mbed_official	76:aeb1df146756	5894
mbed_official	76:aeb1df146756	5895	/******************************************************************************/
mbed_official	76:aeb1df146756	5896	/* */
mbed_official	76:aeb1df146756	5897	/* Window WATCHDOG (WWDG) */
mbed_official	76:aeb1df146756	5898	/* */
mbed_official	76:aeb1df146756	5899	/******************************************************************************/
mbed_official	76:aeb1df146756	5900
mbed_official	76:aeb1df146756	5901	/***************** Bit definition for WWDG_CR register ******************/
mbed_official	76:aeb1df146756	5902	#define WWDG_CR_T ((uint8_t)0x7F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
mbed_official	76:aeb1df146756	5903	#define WWDG_CR_T0 ((uint8_t)0x01) /!< Bit 0 /
mbed_official	76:aeb1df146756	5904	#define WWDG_CR_T1 ((uint8_t)0x02) /!< Bit 1 /
mbed_official	76:aeb1df146756	5905	#define WWDG_CR_T2 ((uint8_t)0x04) /!< Bit 2 /
mbed_official	76:aeb1df146756	5906	#define WWDG_CR_T3 ((uint8_t)0x08) /!< Bit 3 /
mbed_official	76:aeb1df146756	5907	#define WWDG_CR_T4 ((uint8_t)0x10) /!< Bit 4 /
mbed_official	76:aeb1df146756	5908	#define WWDG_CR_T5 ((uint8_t)0x20) /!< Bit 5 /
mbed_official	76:aeb1df146756	5909	#define WWDG_CR_T6 ((uint8_t)0x40) /!< Bit 6 /
mbed_official	76:aeb1df146756	5910
mbed_official	76:aeb1df146756	5911	#define WWDG_CR_WDGA ((uint8_t)0x80) /!< Activation bit /
mbed_official	76:aeb1df146756	5912
mbed_official	76:aeb1df146756	5913	/***************** Bit definition for WWDG_CFR register *****************/
mbed_official	76:aeb1df146756	5914	#define WWDG_CFR_W ((uint16_t)0x007F) /!< W[6:0] bits (7-bit window value) /
mbed_official	76:aeb1df146756	5915	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!< Bit 0 /
mbed_official	76:aeb1df146756	5916	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!< Bit 1 /
mbed_official	76:aeb1df146756	5917	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!< Bit 2 /
mbed_official	76:aeb1df146756	5918	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!< Bit 3 /
mbed_official	76:aeb1df146756	5919	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!< Bit 4 /
mbed_official	76:aeb1df146756	5920	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!< Bit 5 /
mbed_official	76:aeb1df146756	5921	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!< Bit 6 /
mbed_official	76:aeb1df146756	5922
mbed_official	76:aeb1df146756	5923	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!< WDGTB[1:0] bits (Timer Base) /
mbed_official	76:aeb1df146756	5924	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!< Bit 0 /
mbed_official	76:aeb1df146756	5925	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!< Bit 1 /
mbed_official	76:aeb1df146756	5926
mbed_official	76:aeb1df146756	5927	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!< Early Wakeup Interrupt /
mbed_official	76:aeb1df146756	5928
mbed_official	76:aeb1df146756	5929	/***************** Bit definition for WWDG_SR register ******************/
mbed_official	76:aeb1df146756	5930	#define WWDG_SR_EWIF ((uint8_t)0x01) /!< Early Wakeup Interrupt Flag /
mbed_official	76:aeb1df146756	5931
mbed_official	76:aeb1df146756	5932	/******************************************************************************/
mbed_official	76:aeb1df146756	5933	/* */
mbed_official	76:aeb1df146756	5934	/* SystemTick (SysTick) */
mbed_official	76:aeb1df146756	5935	/* */
mbed_official	76:aeb1df146756	5936	/******************************************************************************/
mbed_official	76:aeb1df146756	5937
mbed_official	76:aeb1df146756	5938	/*************** Bit definition for SysTick_CTRL register ***************/
mbed_official	76:aeb1df146756	5939	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
mbed_official	76:aeb1df146756	5940	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
mbed_official	76:aeb1df146756	5941	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
mbed_official	76:aeb1df146756	5942	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
mbed_official	76:aeb1df146756	5943
mbed_official	76:aeb1df146756	5944	/*************** Bit definition for SysTick_LOAD register ***************/
mbed_official	76:aeb1df146756	5945	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
mbed_official	76:aeb1df146756	5946
mbed_official	76:aeb1df146756	5947	/*************** Bit definition for SysTick_VAL register ****************/
mbed_official	76:aeb1df146756	5948	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
mbed_official	76:aeb1df146756	5949
mbed_official	76:aeb1df146756	5950	/*************** Bit definition for SysTick_CALIB register **************/
mbed_official	76:aeb1df146756	5951	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
mbed_official	76:aeb1df146756	5952	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
mbed_official	76:aeb1df146756	5953	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
mbed_official	76:aeb1df146756	5954
mbed_official	76:aeb1df146756	5955	/******************************************************************************/
mbed_official	76:aeb1df146756	5956	/* */
mbed_official	76:aeb1df146756	5957	/* Nested Vectored Interrupt Controller (NVIC) */
mbed_official	76:aeb1df146756	5958	/* */
mbed_official	76:aeb1df146756	5959	/******************************************************************************/
mbed_official	76:aeb1df146756	5960
mbed_official	76:aeb1df146756	5961	/**************** Bit definition for NVIC_ISER register *****************/
mbed_official	76:aeb1df146756	5962	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
mbed_official	76:aeb1df146756	5963	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
mbed_official	76:aeb1df146756	5964	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
mbed_official	76:aeb1df146756	5965	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
mbed_official	76:aeb1df146756	5966	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
mbed_official	76:aeb1df146756	5967	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
mbed_official	76:aeb1df146756	5968	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
mbed_official	76:aeb1df146756	5969	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
mbed_official	76:aeb1df146756	5970	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
mbed_official	76:aeb1df146756	5971	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
mbed_official	76:aeb1df146756	5972	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
mbed_official	76:aeb1df146756	5973	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
mbed_official	76:aeb1df146756	5974	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
mbed_official	76:aeb1df146756	5975	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
mbed_official	76:aeb1df146756	5976	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
mbed_official	76:aeb1df146756	5977	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
mbed_official	76:aeb1df146756	5978	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
mbed_official	76:aeb1df146756	5979	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
mbed_official	76:aeb1df146756	5980	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
mbed_official	76:aeb1df146756	5981	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
mbed_official	76:aeb1df146756	5982	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
mbed_official	76:aeb1df146756	5983	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
mbed_official	76:aeb1df146756	5984	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
mbed_official	76:aeb1df146756	5985	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
mbed_official	76:aeb1df146756	5986	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
mbed_official	76:aeb1df146756	5987	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
mbed_official	76:aeb1df146756	5988	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
mbed_official	76:aeb1df146756	5989	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
mbed_official	76:aeb1df146756	5990	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
mbed_official	76:aeb1df146756	5991	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
mbed_official	76:aeb1df146756	5992	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
mbed_official	76:aeb1df146756	5993	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
mbed_official	76:aeb1df146756	5994	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
mbed_official	76:aeb1df146756	5995
mbed_official	76:aeb1df146756	5996	/**************** Bit definition for NVIC_ICER register *****************/
mbed_official	76:aeb1df146756	5997	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
mbed_official	76:aeb1df146756	5998	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
mbed_official	76:aeb1df146756	5999	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
mbed_official	76:aeb1df146756	6000	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
mbed_official	76:aeb1df146756	6001	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
mbed_official	76:aeb1df146756	6002	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
mbed_official	76:aeb1df146756	6003	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
mbed_official	76:aeb1df146756	6004	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
mbed_official	76:aeb1df146756	6005	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
mbed_official	76:aeb1df146756	6006	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
mbed_official	76:aeb1df146756	6007	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
mbed_official	76:aeb1df146756	6008	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
mbed_official	76:aeb1df146756	6009	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
mbed_official	76:aeb1df146756	6010	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
mbed_official	76:aeb1df146756	6011	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
mbed_official	76:aeb1df146756	6012	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
mbed_official	76:aeb1df146756	6013	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
mbed_official	76:aeb1df146756	6014	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
mbed_official	76:aeb1df146756	6015	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
mbed_official	76:aeb1df146756	6016	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
mbed_official	76:aeb1df146756	6017	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
mbed_official	76:aeb1df146756	6018	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
mbed_official	76:aeb1df146756	6019	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
mbed_official	76:aeb1df146756	6020	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
mbed_official	76:aeb1df146756	6021	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
mbed_official	76:aeb1df146756	6022	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
mbed_official	76:aeb1df146756	6023	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
mbed_official	76:aeb1df146756	6024	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
mbed_official	76:aeb1df146756	6025	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
mbed_official	76:aeb1df146756	6026	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
mbed_official	76:aeb1df146756	6027	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
mbed_official	76:aeb1df146756	6028	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
mbed_official	76:aeb1df146756	6029	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
mbed_official	76:aeb1df146756	6030
mbed_official	76:aeb1df146756	6031	/**************** Bit definition for NVIC_ISPR register *****************/
mbed_official	76:aeb1df146756	6032	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
mbed_official	76:aeb1df146756	6033	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
mbed_official	76:aeb1df146756	6034	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
mbed_official	76:aeb1df146756	6035	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
mbed_official	76:aeb1df146756	6036	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
mbed_official	76:aeb1df146756	6037	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
mbed_official	76:aeb1df146756	6038	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
mbed_official	76:aeb1df146756	6039	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
mbed_official	76:aeb1df146756	6040	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
mbed_official	76:aeb1df146756	6041	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
mbed_official	76:aeb1df146756	6042	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
mbed_official	76:aeb1df146756	6043	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
mbed_official	76:aeb1df146756	6044	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
mbed_official	76:aeb1df146756	6045	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
mbed_official	76:aeb1df146756	6046	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
mbed_official	76:aeb1df146756	6047	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
mbed_official	76:aeb1df146756	6048	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
mbed_official	76:aeb1df146756	6049	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
mbed_official	76:aeb1df146756	6050	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
mbed_official	76:aeb1df146756	6051	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
mbed_official	76:aeb1df146756	6052	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
mbed_official	76:aeb1df146756	6053	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
mbed_official	76:aeb1df146756	6054	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
mbed_official	76:aeb1df146756	6055	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
mbed_official	76:aeb1df146756	6056	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
mbed_official	76:aeb1df146756	6057	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
mbed_official	76:aeb1df146756	6058	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
mbed_official	76:aeb1df146756	6059	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
mbed_official	76:aeb1df146756	6060	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
mbed_official	76:aeb1df146756	6061	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
mbed_official	76:aeb1df146756	6062	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
mbed_official	76:aeb1df146756	6063	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
mbed_official	76:aeb1df146756	6064	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
mbed_official	76:aeb1df146756	6065
mbed_official	76:aeb1df146756	6066	/**************** Bit definition for NVIC_ICPR register *****************/
mbed_official	76:aeb1df146756	6067	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
mbed_official	76:aeb1df146756	6068	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
mbed_official	76:aeb1df146756	6069	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
mbed_official	76:aeb1df146756	6070	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
mbed_official	76:aeb1df146756	6071	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
mbed_official	76:aeb1df146756	6072	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
mbed_official	76:aeb1df146756	6073	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
mbed_official	76:aeb1df146756	6074	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
mbed_official	76:aeb1df146756	6075	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
mbed_official	76:aeb1df146756	6076	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
mbed_official	76:aeb1df146756	6077	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
mbed_official	76:aeb1df146756	6078	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
mbed_official	76:aeb1df146756	6079	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
mbed_official	76:aeb1df146756	6080	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
mbed_official	76:aeb1df146756	6081	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
mbed_official	76:aeb1df146756	6082	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
mbed_official	76:aeb1df146756	6083	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
mbed_official	76:aeb1df146756	6084	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
mbed_official	76:aeb1df146756	6085	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
mbed_official	76:aeb1df146756	6086	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
mbed_official	76:aeb1df146756	6087	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
mbed_official	76:aeb1df146756	6088	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
mbed_official	76:aeb1df146756	6089	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
mbed_official	76:aeb1df146756	6090	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
mbed_official	76:aeb1df146756	6091	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
mbed_official	76:aeb1df146756	6092	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
mbed_official	76:aeb1df146756	6093	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
mbed_official	76:aeb1df146756	6094	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
mbed_official	76:aeb1df146756	6095	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
mbed_official	76:aeb1df146756	6096	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
mbed_official	76:aeb1df146756	6097	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
mbed_official	76:aeb1df146756	6098	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
mbed_official	76:aeb1df146756	6099	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
mbed_official	76:aeb1df146756	6100
mbed_official	76:aeb1df146756	6101	/**************** Bit definition for NVIC_IABR register *****************/
mbed_official	76:aeb1df146756	6102	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
mbed_official	76:aeb1df146756	6103	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
mbed_official	76:aeb1df146756	6104	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
mbed_official	76:aeb1df146756	6105	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
mbed_official	76:aeb1df146756	6106	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
mbed_official	76:aeb1df146756	6107	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
mbed_official	76:aeb1df146756	6108	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
mbed_official	76:aeb1df146756	6109	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
mbed_official	76:aeb1df146756	6110	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
mbed_official	76:aeb1df146756	6111	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
mbed_official	76:aeb1df146756	6112	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
mbed_official	76:aeb1df146756	6113	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
mbed_official	76:aeb1df146756	6114	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
mbed_official	76:aeb1df146756	6115	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
mbed_official	76:aeb1df146756	6116	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
mbed_official	76:aeb1df146756	6117	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
mbed_official	76:aeb1df146756	6118	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
mbed_official	76:aeb1df146756	6119	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
mbed_official	76:aeb1df146756	6120	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
mbed_official	76:aeb1df146756	6121	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
mbed_official	76:aeb1df146756	6122	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
mbed_official	76:aeb1df146756	6123	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
mbed_official	76:aeb1df146756	6124	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
mbed_official	76:aeb1df146756	6125	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
mbed_official	76:aeb1df146756	6126	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
mbed_official	76:aeb1df146756	6127	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
mbed_official	76:aeb1df146756	6128	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
mbed_official	76:aeb1df146756	6129	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
mbed_official	76:aeb1df146756	6130	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
mbed_official	76:aeb1df146756	6131	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
mbed_official	76:aeb1df146756	6132	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
mbed_official	76:aeb1df146756	6133	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
mbed_official	76:aeb1df146756	6134	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
mbed_official	76:aeb1df146756	6135
mbed_official	76:aeb1df146756	6136	/**************** Bit definition for NVIC_PRI0 register *****************/
mbed_official	76:aeb1df146756	6137	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
mbed_official	76:aeb1df146756	6138	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
mbed_official	76:aeb1df146756	6139	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
mbed_official	76:aeb1df146756	6140	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
mbed_official	76:aeb1df146756	6141
mbed_official	76:aeb1df146756	6142	/**************** Bit definition for NVIC_PRI1 register *****************/
mbed_official	76:aeb1df146756	6143	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
mbed_official	76:aeb1df146756	6144	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
mbed_official	76:aeb1df146756	6145	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
mbed_official	76:aeb1df146756	6146	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
mbed_official	76:aeb1df146756	6147
mbed_official	76:aeb1df146756	6148	/**************** Bit definition for NVIC_PRI2 register *****************/
mbed_official	76:aeb1df146756	6149	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
mbed_official	76:aeb1df146756	6150	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
mbed_official	76:aeb1df146756	6151	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
mbed_official	76:aeb1df146756	6152	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
mbed_official	76:aeb1df146756	6153
mbed_official	76:aeb1df146756	6154	/**************** Bit definition for NVIC_PRI3 register *****************/
mbed_official	76:aeb1df146756	6155	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
mbed_official	76:aeb1df146756	6156	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
mbed_official	76:aeb1df146756	6157	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
mbed_official	76:aeb1df146756	6158	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
mbed_official	76:aeb1df146756	6159
mbed_official	76:aeb1df146756	6160	/**************** Bit definition for NVIC_PRI4 register *****************/
mbed_official	76:aeb1df146756	6161	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
mbed_official	76:aeb1df146756	6162	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
mbed_official	76:aeb1df146756	6163	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
mbed_official	76:aeb1df146756	6164	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
mbed_official	76:aeb1df146756	6165
mbed_official	76:aeb1df146756	6166	/**************** Bit definition for NVIC_PRI5 register *****************/
mbed_official	76:aeb1df146756	6167	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
mbed_official	76:aeb1df146756	6168	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
mbed_official	76:aeb1df146756	6169	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
mbed_official	76:aeb1df146756	6170	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
mbed_official	76:aeb1df146756	6171
mbed_official	76:aeb1df146756	6172	/**************** Bit definition for NVIC_PRI6 register *****************/
mbed_official	76:aeb1df146756	6173	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
mbed_official	76:aeb1df146756	6174	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
mbed_official	76:aeb1df146756	6175	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
mbed_official	76:aeb1df146756	6176	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
mbed_official	76:aeb1df146756	6177
mbed_official	76:aeb1df146756	6178	/**************** Bit definition for NVIC_PRI7 register *****************/
mbed_official	76:aeb1df146756	6179	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
mbed_official	76:aeb1df146756	6180	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
mbed_official	76:aeb1df146756	6181	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
mbed_official	76:aeb1df146756	6182	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
mbed_official	76:aeb1df146756	6183
mbed_official	76:aeb1df146756	6184	/**************** Bit definition for SCB_CPUID register *****************/
mbed_official	76:aeb1df146756	6185	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
mbed_official	76:aeb1df146756	6186	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
mbed_official	76:aeb1df146756	6187	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
mbed_official	76:aeb1df146756	6188	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
mbed_official	76:aeb1df146756	6189	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
mbed_official	76:aeb1df146756	6190
mbed_official	76:aeb1df146756	6191	/***************** Bit definition for SCB_ICSR register *****************/
mbed_official	76:aeb1df146756	6192	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
mbed_official	76:aeb1df146756	6193	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
mbed_official	76:aeb1df146756	6194	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
mbed_official	76:aeb1df146756	6195	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
mbed_official	76:aeb1df146756	6196	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
mbed_official	76:aeb1df146756	6197	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
mbed_official	76:aeb1df146756	6198	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
mbed_official	76:aeb1df146756	6199	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
mbed_official	76:aeb1df146756	6200	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
mbed_official	76:aeb1df146756	6201	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
mbed_official	76:aeb1df146756	6202
mbed_official	76:aeb1df146756	6203	/***************** Bit definition for SCB_VTOR register *****************/
mbed_official	76:aeb1df146756	6204	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
mbed_official	76:aeb1df146756	6205	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
mbed_official	76:aeb1df146756	6206
mbed_official	76:aeb1df146756	6207	/!<************** Bit definition for SCB_AIRCR register *****************/
mbed_official	76:aeb1df146756	6208	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
mbed_official	76:aeb1df146756	6209	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
mbed_official	76:aeb1df146756	6210	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
mbed_official	76:aeb1df146756	6211
mbed_official	76:aeb1df146756	6212	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
mbed_official	76:aeb1df146756	6213	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	76:aeb1df146756	6214	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	76:aeb1df146756	6215	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	76:aeb1df146756	6216
mbed_official	76:aeb1df146756	6217	/* prority group configuration */
mbed_official	76:aeb1df146756	6218	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
mbed_official	76:aeb1df146756	6219	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
mbed_official	76:aeb1df146756	6220	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
mbed_official	76:aeb1df146756	6221	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
mbed_official	76:aeb1df146756	6222	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
mbed_official	76:aeb1df146756	6223	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
mbed_official	76:aeb1df146756	6224	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
mbed_official	76:aeb1df146756	6225	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
mbed_official	76:aeb1df146756	6226
mbed_official	76:aeb1df146756	6227	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
mbed_official	76:aeb1df146756	6228	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
mbed_official	76:aeb1df146756	6229
mbed_official	76:aeb1df146756	6230	/***************** Bit definition for SCB_SCR register ******************/
mbed_official	76:aeb1df146756	6231	#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /!< Sleep on exit bit /
mbed_official	76:aeb1df146756	6232	#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /!< Sleep deep bit /
mbed_official	76:aeb1df146756	6233	#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /!< Wake up from WFE /
mbed_official	76:aeb1df146756	6234
mbed_official	76:aeb1df146756	6235	/****************** Bit definition for SCB_CCR register *****************/
mbed_official	76:aeb1df146756	6236	#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
mbed_official	76:aeb1df146756	6237	#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
mbed_official	76:aeb1df146756	6238	#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /!< Trap for unaligned access /
mbed_official	76:aeb1df146756	6239	#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /!< Trap on Divide by 0 /
mbed_official	76:aeb1df146756	6240	#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /!< Handlers running at priority -1 and -2 /
mbed_official	76:aeb1df146756	6241	#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
mbed_official	76:aeb1df146756	6242
mbed_official	76:aeb1df146756	6243	/***************** Bit definition for SCB_SHPR register ******************/
mbed_official	76:aeb1df146756	6244	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
mbed_official	76:aeb1df146756	6245	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
mbed_official	76:aeb1df146756	6246	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
mbed_official	76:aeb1df146756	6247	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
mbed_official	76:aeb1df146756	6248
mbed_official	76:aeb1df146756	6249	/**************** Bit definition for SCB_SHCSR register *****************/
mbed_official	76:aeb1df146756	6250	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
mbed_official	76:aeb1df146756	6251	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
mbed_official	76:aeb1df146756	6252	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
mbed_official	76:aeb1df146756	6253	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
mbed_official	76:aeb1df146756	6254	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
mbed_official	76:aeb1df146756	6255	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
mbed_official	76:aeb1df146756	6256	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
mbed_official	76:aeb1df146756	6257	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
mbed_official	76:aeb1df146756	6258	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
mbed_official	76:aeb1df146756	6259	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
mbed_official	76:aeb1df146756	6260	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
mbed_official	76:aeb1df146756	6261	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
mbed_official	76:aeb1df146756	6262	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
mbed_official	76:aeb1df146756	6263	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
mbed_official	76:aeb1df146756	6264
mbed_official	76:aeb1df146756	6265	/***************** Bit definition for SCB_CFSR register *****************/
mbed_official	76:aeb1df146756	6266	/!< MFSR /
mbed_official	76:aeb1df146756	6267	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
mbed_official	76:aeb1df146756	6268	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
mbed_official	76:aeb1df146756	6269	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
mbed_official	76:aeb1df146756	6270	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
mbed_official	76:aeb1df146756	6271	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
mbed_official	76:aeb1df146756	6272	/!< BFSR /
mbed_official	76:aeb1df146756	6273	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
mbed_official	76:aeb1df146756	6274	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
mbed_official	76:aeb1df146756	6275	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
mbed_official	76:aeb1df146756	6276	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
mbed_official	76:aeb1df146756	6277	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
mbed_official	76:aeb1df146756	6278	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
mbed_official	76:aeb1df146756	6279	/!< UFSR /
mbed_official	76:aeb1df146756	6280	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to excecute an undefined instruction /
mbed_official	76:aeb1df146756	6281	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
mbed_official	76:aeb1df146756	6282	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
mbed_official	76:aeb1df146756	6283	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
mbed_official	76:aeb1df146756	6284	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
mbed_official	76:aeb1df146756	6285	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
mbed_official	76:aeb1df146756	6286
mbed_official	76:aeb1df146756	6287	/***************** Bit definition for SCB_HFSR register *****************/
mbed_official	76:aeb1df146756	6288	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occures because of vector table read on exception processing /
mbed_official	76:aeb1df146756	6289	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
mbed_official	76:aeb1df146756	6290	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
mbed_official	76:aeb1df146756	6291
mbed_official	76:aeb1df146756	6292	/***************** Bit definition for SCB_DFSR register *****************/
mbed_official	76:aeb1df146756	6293	#define SCB_DFSR_HALTED ((uint8_t)0x01) /!< Halt request flag /
mbed_official	76:aeb1df146756	6294	#define SCB_DFSR_BKPT ((uint8_t)0x02) /!< BKPT flag /
mbed_official	76:aeb1df146756	6295	#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /!< Data Watchpoint and Trace (DWT) flag /
mbed_official	76:aeb1df146756	6296	#define SCB_DFSR_VCATCH ((uint8_t)0x08) /!< Vector catch flag /
mbed_official	76:aeb1df146756	6297	#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /!< External debug request flag /
mbed_official	76:aeb1df146756	6298
mbed_official	76:aeb1df146756	6299	/***************** Bit definition for SCB_MMFAR register ****************/
mbed_official	76:aeb1df146756	6300	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
mbed_official	76:aeb1df146756	6301
mbed_official	76:aeb1df146756	6302	/***************** Bit definition for SCB_BFAR register *****************/
mbed_official	76:aeb1df146756	6303	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
mbed_official	76:aeb1df146756	6304
mbed_official	76:aeb1df146756	6305	/***************** Bit definition for SCB_afsr register *****************/
mbed_official	76:aeb1df146756	6306	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
mbed_official	76:aeb1df146756	6307	/**
mbed_official	76:aeb1df146756	6308	* @}
mbed_official	76:aeb1df146756	6309	*/
mbed_official	76:aeb1df146756	6310
mbed_official	76:aeb1df146756	6311	/**
mbed_official	76:aeb1df146756	6312	* @}
mbed_official	76:aeb1df146756	6313	*/
mbed_official	76:aeb1df146756	6314
mbed_official	76:aeb1df146756	6315	#ifdef USE_STDPERIPH_DRIVER
mbed_official	76:aeb1df146756	6316	#include "stm32l1xx_conf.h"
mbed_official	76:aeb1df146756	6317	#endif
mbed_official	76:aeb1df146756	6318
mbed_official	76:aeb1df146756	6319	/** @addtogroup Exported_macro
mbed_official	76:aeb1df146756	6320	* @{
mbed_official	76:aeb1df146756	6321	*/
mbed_official	76:aeb1df146756	6322
mbed_official	76:aeb1df146756	6323	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
mbed_official	76:aeb1df146756	6324
mbed_official	76:aeb1df146756	6325	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
mbed_official	76:aeb1df146756	6326
mbed_official	76:aeb1df146756	6327	#define READ_BIT(REG, BIT) ((REG) & (BIT))
mbed_official	76:aeb1df146756	6328
mbed_official	76:aeb1df146756	6329	#define CLEAR_REG(REG) ((REG) = (0x0))
mbed_official	76:aeb1df146756	6330
mbed_official	76:aeb1df146756	6331	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
mbed_official	76:aeb1df146756	6332
mbed_official	76:aeb1df146756	6333	#define READ_REG(REG) ((REG))
mbed_official	76:aeb1df146756	6334
mbed_official	76:aeb1df146756	6335	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
mbed_official	76:aeb1df146756	6336
mbed_official	76:aeb1df146756	6337	/**
mbed_official	76:aeb1df146756	6338	* @}
mbed_official	76:aeb1df146756	6339	*/
mbed_official	76:aeb1df146756	6340
mbed_official	76:aeb1df146756	6341	#ifdef __cplusplus
mbed_official	76:aeb1df146756	6342	}
mbed_official	76:aeb1df146756	6343	#endif
mbed_official	76:aeb1df146756	6344
mbed_official	76:aeb1df146756	6345	#endif /* __STM32L1XX_H */
mbed_official	76:aeb1df146756	6346
mbed_official	76:aeb1df146756	6347	/**
mbed_official	76:aeb1df146756	6348	* @}
mbed_official	76:aeb1df146756	6349	*/
mbed_official	76:aeb1df146756	6350
mbed_official	76:aeb1df146756	6351	/**
mbed_official	76:aeb1df146756	6352	* @}
mbed_official	76:aeb1df146756	6353	*/
mbed_official	76:aeb1df146756	6354
mbed_official	76:aeb1df146756	6355	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2014
Imports:	301
Forks:	0
Commits:	115
Dependents:	0
Dependencies:	0
Followers:	15
Issues:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx.h@76:aeb1df146756, 2014-01-27 (annotated)

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