mbed-F401 - mbed library with additional peripherals for ST F…

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Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

UART2 : PA_3 rx, PA_2 tx
UART3 : PC_7 rx, PC_6 tx
I2C2 : PB_3 SDA, PB_10 SCL
I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_rcc.c@76:aeb1df146756, 2014-01-27 (annotated)

Committer:: mbed_official
Date:: Mon Jan 27 14:30:07 2014 +0000
Revision:: 76:aeb1df146756
Child:: 106:ced8cbb51063

Synchronized with git revision a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd



Full URL: https://github.com/mbedmicro/mbed/commit/a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd/



Add NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	76:aeb1df146756	1	/**
mbed_official	76:aeb1df146756	2	******************************************************************************
mbed_official	76:aeb1df146756	3	* @file stm32f0xx_rcc.c
mbed_official	76:aeb1df146756	4	* @author MCD Application Team
mbed_official	76:aeb1df146756	5	* @version V1.3.0
mbed_official	76:aeb1df146756	6	* @date 16-January-2014
mbed_official	76:aeb1df146756	7	* @brief This file provides firmware functions to manage the following
mbed_official	76:aeb1df146756	8	* functionalities of the Reset and clock control (RCC) peripheral:
mbed_official	76:aeb1df146756	9	* + Internal/external clocks, PLL, CSS and MCO configuration
mbed_official	76:aeb1df146756	10	* + System, AHB and APB busses clocks configuration
mbed_official	76:aeb1df146756	11	* + Peripheral clocks configuration
mbed_official	76:aeb1df146756	12	* + Interrupts and flags management
mbed_official	76:aeb1df146756	13	*
mbed_official	76:aeb1df146756	14	@verbatim
mbed_official	76:aeb1df146756	15
mbed_official	76:aeb1df146756	16	===============================================================================
mbed_official	76:aeb1df146756	17	##### RCC specific features #####
mbed_official	76:aeb1df146756	18	===============================================================================
mbed_official	76:aeb1df146756	19	[..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
mbed_official	76:aeb1df146756	20	all peripherals are off except internal SRAM, Flash and SWD.
mbed_official	76:aeb1df146756	21	(#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official	76:aeb1df146756	22	all peripherals mapped on these busses are running at HSI speed.
mbed_official	76:aeb1df146756	23	(#) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official	76:aeb1df146756	24	(#) All GPIOs are in input floating state, except the SWD pins which
mbed_official	76:aeb1df146756	25	are assigned to be used for debug purpose.
mbed_official	76:aeb1df146756	26	[..] Once the device started from reset, the user application has to:
mbed_official	76:aeb1df146756	27	(#) Configure the clock source to be used to drive the System clock
mbed_official	76:aeb1df146756	28	(if the application needs higher frequency/performance)
mbed_official	76:aeb1df146756	29	(#) Configure the System clock frequency and Flash settings
mbed_official	76:aeb1df146756	30	(#) Configure the AHB and APB busses prescalers
mbed_official	76:aeb1df146756	31	(#) Enable the clock for the peripheral(s) to be used
mbed_official	76:aeb1df146756	32	(#) Configure the clock source(s) for peripherals which clocks are not
mbed_official	76:aeb1df146756	33	derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
mbed_official	76:aeb1df146756	34
mbed_official	76:aeb1df146756	35	@endverbatim
mbed_official	76:aeb1df146756	36
mbed_official	76:aeb1df146756	37	******************************************************************************
mbed_official	76:aeb1df146756	38	* @attention
mbed_official	76:aeb1df146756	39	*
mbed_official	76:aeb1df146756	40	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official	76:aeb1df146756	41	*
mbed_official	76:aeb1df146756	42	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official	76:aeb1df146756	43	* You may not use this file except in compliance with the License.
mbed_official	76:aeb1df146756	44	* You may obtain a copy of the License at:
mbed_official	76:aeb1df146756	45	*
mbed_official	76:aeb1df146756	46	* http://www.st.com/software_license_agreement_liberty_v2
mbed_official	76:aeb1df146756	47	*
mbed_official	76:aeb1df146756	48	* Unless required by applicable law or agreed to in writing, software
mbed_official	76:aeb1df146756	49	* distributed under the License is distributed on an "AS IS" BASIS,
mbed_official	76:aeb1df146756	50	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official	76:aeb1df146756	51	* See the License for the specific language governing permissions and
mbed_official	76:aeb1df146756	52	* limitations under the License.
mbed_official	76:aeb1df146756	53	*
mbed_official	76:aeb1df146756	54	******************************************************************************
mbed_official	76:aeb1df146756	55	*/
mbed_official	76:aeb1df146756	56
mbed_official	76:aeb1df146756	57	/* Includes ------------------------------------------------------------------*/
mbed_official	76:aeb1df146756	58	#include "stm32f0xx_rcc.h"
mbed_official	76:aeb1df146756	59
mbed_official	76:aeb1df146756	60	/** @addtogroup STM32F0xx_StdPeriph_Driver
mbed_official	76:aeb1df146756	61	* @{
mbed_official	76:aeb1df146756	62	*/
mbed_official	76:aeb1df146756	63
mbed_official	76:aeb1df146756	64	/** @defgroup RCC
mbed_official	76:aeb1df146756	65	* @brief RCC driver modules
mbed_official	76:aeb1df146756	66	* @{
mbed_official	76:aeb1df146756	67	*/
mbed_official	76:aeb1df146756	68
mbed_official	76:aeb1df146756	69	/* Private typedef -----------------------------------------------------------*/
mbed_official	76:aeb1df146756	70	/* Private define ------------------------------------------------------------*/
mbed_official	76:aeb1df146756	71
mbed_official	76:aeb1df146756	72	/* ---------------------- RCC registers mask -------------------------------- */
mbed_official	76:aeb1df146756	73	/* RCC Flag Mask */
mbed_official	76:aeb1df146756	74	#define FLAG_MASK ((uint8_t)0x1F)
mbed_official	76:aeb1df146756	75
mbed_official	76:aeb1df146756	76	/* CR register byte 2 (Bits[23:16]) base address */
mbed_official	76:aeb1df146756	77	#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
mbed_official	76:aeb1df146756	78
mbed_official	76:aeb1df146756	79	/* CFGR register byte 3 (Bits[31:23]) base address */
mbed_official	76:aeb1df146756	80	#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
mbed_official	76:aeb1df146756	81
mbed_official	76:aeb1df146756	82	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	76:aeb1df146756	83	#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
mbed_official	76:aeb1df146756	84
mbed_official	76:aeb1df146756	85	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	76:aeb1df146756	86	#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
mbed_official	76:aeb1df146756	87
mbed_official	76:aeb1df146756	88	/* Private macro -------------------------------------------------------------*/
mbed_official	76:aeb1df146756	89	/* Private variables ---------------------------------------------------------*/
mbed_official	76:aeb1df146756	90	static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	76:aeb1df146756	91
mbed_official	76:aeb1df146756	92	/* Private function prototypes -----------------------------------------------*/
mbed_official	76:aeb1df146756	93	/* Private functions ---------------------------------------------------------*/
mbed_official	76:aeb1df146756	94
mbed_official	76:aeb1df146756	95	/** @defgroup RCC_Private_Functions
mbed_official	76:aeb1df146756	96	* @{
mbed_official	76:aeb1df146756	97	*/
mbed_official	76:aeb1df146756	98
mbed_official	76:aeb1df146756	99	/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official	76:aeb1df146756	100	* @brief Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official	76:aeb1df146756	101	*
mbed_official	76:aeb1df146756	102	@verbatim
mbed_official	76:aeb1df146756	103	===============================================================================
mbed_official	76:aeb1df146756	104	##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
mbed_official	76:aeb1df146756	105	===============================================================================
mbed_official	76:aeb1df146756	106	[..] This section provides functions allowing to configure the internal/external clocks,
mbed_official	76:aeb1df146756	107	PLL, CSS and MCO.
mbed_official	76:aeb1df146756	108	(#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
mbed_official	76:aeb1df146756	109	or through the PLL as System clock source.
mbed_official	76:aeb1df146756	110	The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
mbed_official	76:aeb1df146756	111	(#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
mbed_official	76:aeb1df146756	112	the ADC peripheral.
mbed_official	76:aeb1df146756	113	(#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
mbed_official	76:aeb1df146756	114	clock source.
mbed_official	76:aeb1df146756	115	(#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
mbed_official	76:aeb1df146756	116	through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official	76:aeb1df146756	117	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official	76:aeb1df146756	118	LSE can be used also to clock the USART and CEC peripherals.
mbed_official	76:aeb1df146756	119	(#) PLL (clocked by HSI or HSE), for System clock.
mbed_official	76:aeb1df146756	120	(#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
mbed_official	76:aeb1df146756	121	(HSE used directly or through PLL as System clock source), the System clock
mbed_official	76:aeb1df146756	122	is automatically switched to HSI and an interrupt is generated if enabled.
mbed_official	76:aeb1df146756	123	The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
mbed_official	76:aeb1df146756	124	exception vector.
mbed_official	76:aeb1df146756	125	(#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
mbed_official	76:aeb1df146756	126	HSE, LSE or PLL (divided by 2) clock on PA8 pin.
mbed_official	76:aeb1df146756	127
mbed_official	76:aeb1df146756	128	@endverbatim
mbed_official	76:aeb1df146756	129	* @{
mbed_official	76:aeb1df146756	130	*/
mbed_official	76:aeb1df146756	131
mbed_official	76:aeb1df146756	132	/**
mbed_official	76:aeb1df146756	133	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	76:aeb1df146756	134	* @note The default reset state of the clock configuration is given below:
mbed_official	76:aeb1df146756	135	* @note HSI ON and used as system clock source
mbed_official	76:aeb1df146756	136	* @note HSI14, HSE and PLL OFF
mbed_official	76:aeb1df146756	137	* @note AHB, APB prescaler set to 1.
mbed_official	76:aeb1df146756	138	* @note CSS and MCO OFF
mbed_official	76:aeb1df146756	139	* @note All interrupts disabled
mbed_official	76:aeb1df146756	140	* @note However, this function doesn't modify the configuration of the
mbed_official	76:aeb1df146756	141	* @note Peripheral clocks
mbed_official	76:aeb1df146756	142	* @note LSI, LSE and RTC clocks
mbed_official	76:aeb1df146756	143	* @param None
mbed_official	76:aeb1df146756	144	* @retval None
mbed_official	76:aeb1df146756	145	*/
mbed_official	76:aeb1df146756	146	void RCC_DeInit(void)
mbed_official	76:aeb1df146756	147	{
mbed_official	76:aeb1df146756	148	/* Set HSION bit */
mbed_official	76:aeb1df146756	149	RCC->CR \|= (uint32_t)0x00000001;
mbed_official	76:aeb1df146756	150
mbed_official	76:aeb1df146756	151	#if defined (STM32F051)
mbed_official	76:aeb1df146756	152	/* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
mbed_official	76:aeb1df146756	153	RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official	76:aeb1df146756	154	#else
mbed_official	76:aeb1df146756	155	/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official	76:aeb1df146756	156	RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official	76:aeb1df146756	157	#endif /* STM32F051 */
mbed_official	76:aeb1df146756	158
mbed_official	76:aeb1df146756	159	/* Reset HSEON, CSSON and PLLON bits */
mbed_official	76:aeb1df146756	160	RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official	76:aeb1df146756	161
mbed_official	76:aeb1df146756	162	/* Reset HSEBYP bit */
mbed_official	76:aeb1df146756	163	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	76:aeb1df146756	164
mbed_official	76:aeb1df146756	165	/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official	76:aeb1df146756	166	RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official	76:aeb1df146756	167
mbed_official	76:aeb1df146756	168	/* Reset PREDIV1[3:0] bits */
mbed_official	76:aeb1df146756	169	RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official	76:aeb1df146756	170
mbed_official	76:aeb1df146756	171	/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
mbed_official	76:aeb1df146756	172	RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
mbed_official	76:aeb1df146756	173
mbed_official	76:aeb1df146756	174	/* Reset HSI14 bit */
mbed_official	76:aeb1df146756	175	RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official	76:aeb1df146756	176
mbed_official	76:aeb1df146756	177	/* Disable all interrupts */
mbed_official	76:aeb1df146756	178	RCC->CIR = 0x00000000;
mbed_official	76:aeb1df146756	179	}
mbed_official	76:aeb1df146756	180
mbed_official	76:aeb1df146756	181	/**
mbed_official	76:aeb1df146756	182	* @brief Configures the External High Speed oscillator (HSE).
mbed_official	76:aeb1df146756	183	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	76:aeb1df146756	184	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	76:aeb1df146756	185	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	76:aeb1df146756	186	* @note HSE state can not be changed if it is used directly or through the
mbed_official	76:aeb1df146756	187	* PLL as system clock. In this case, you have to select another source
mbed_official	76:aeb1df146756	188	* of the system clock then change the HSE state (ex. disable it).
mbed_official	76:aeb1df146756	189	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	190	* @note This function resets the CSSON bit, so if the Clock security system(CSS)
mbed_official	76:aeb1df146756	191	* was previously enabled you have to enable it again after calling this
mbed_official	76:aeb1df146756	192	* function.
mbed_official	76:aeb1df146756	193	* @param RCC_HSE: specifies the new state of the HSE.
mbed_official	76:aeb1df146756	194	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	195	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	76:aeb1df146756	196	* 6 HSE oscillator clock cycles.
mbed_official	76:aeb1df146756	197	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	76:aeb1df146756	198	* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official	76:aeb1df146756	199	* @retval None
mbed_official	76:aeb1df146756	200	*/
mbed_official	76:aeb1df146756	201	void RCC_HSEConfig(uint8_t RCC_HSE)
mbed_official	76:aeb1df146756	202	{
mbed_official	76:aeb1df146756	203	/* Check the parameters */
mbed_official	76:aeb1df146756	204	assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official	76:aeb1df146756	205
mbed_official	76:aeb1df146756	206	/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official	76:aeb1df146756	207	(__IO uint8_t ) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
mbed_official	76:aeb1df146756	208
mbed_official	76:aeb1df146756	209	/* Set the new HSE configuration -------------------------------------------*/
mbed_official	76:aeb1df146756	210	(__IO uint8_t ) CR_BYTE2_ADDRESS = RCC_HSE;
mbed_official	76:aeb1df146756	211
mbed_official	76:aeb1df146756	212	}
mbed_official	76:aeb1df146756	213
mbed_official	76:aeb1df146756	214	/**
mbed_official	76:aeb1df146756	215	* @brief Waits for HSE start-up.
mbed_official	76:aeb1df146756	216	* @note This function waits on HSERDY flag to be set and return SUCCESS if
mbed_official	76:aeb1df146756	217	* this flag is set, otherwise returns ERROR if the timeout is reached
mbed_official	76:aeb1df146756	218	* and this flag is not set. The timeout value is defined by the constant
mbed_official	76:aeb1df146756	219	* HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
mbed_official	76:aeb1df146756	220	* on the HSE crystal used in your application.
mbed_official	76:aeb1df146756	221	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	222	* @param None
mbed_official	76:aeb1df146756	223	* @retval An ErrorStatus enumeration value:
mbed_official	76:aeb1df146756	224	* - SUCCESS: HSE oscillator is stable and ready to use
mbed_official	76:aeb1df146756	225	* - ERROR: HSE oscillator not yet ready
mbed_official	76:aeb1df146756	226	*/
mbed_official	76:aeb1df146756	227	ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official	76:aeb1df146756	228	{
mbed_official	76:aeb1df146756	229	__IO uint32_t StartUpCounter = 0;
mbed_official	76:aeb1df146756	230	ErrorStatus status = ERROR;
mbed_official	76:aeb1df146756	231	FlagStatus HSEStatus = RESET;
mbed_official	76:aeb1df146756	232
mbed_official	76:aeb1df146756	233	/* Wait till HSE is ready and if timeout is reached exit */
mbed_official	76:aeb1df146756	234	do
mbed_official	76:aeb1df146756	235	{
mbed_official	76:aeb1df146756	236	HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official	76:aeb1df146756	237	StartUpCounter++;
mbed_official	76:aeb1df146756	238	} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official	76:aeb1df146756	239
mbed_official	76:aeb1df146756	240	if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official	76:aeb1df146756	241	{
mbed_official	76:aeb1df146756	242	status = SUCCESS;
mbed_official	76:aeb1df146756	243	}
mbed_official	76:aeb1df146756	244	else
mbed_official	76:aeb1df146756	245	{
mbed_official	76:aeb1df146756	246	status = ERROR;
mbed_official	76:aeb1df146756	247	}
mbed_official	76:aeb1df146756	248	return (status);
mbed_official	76:aeb1df146756	249	}
mbed_official	76:aeb1df146756	250
mbed_official	76:aeb1df146756	251	/**
mbed_official	76:aeb1df146756	252	* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official	76:aeb1df146756	253	* @note The calibration is used to compensate for the variations in voltage
mbed_official	76:aeb1df146756	254	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	76:aeb1df146756	255	* Refer to the Application Note AN4067 for more details on how to
mbed_official	76:aeb1df146756	256	* calibrate the HSI.
mbed_official	76:aeb1df146756	257	* @param HSICalibrationValue: specifies the HSI calibration trimming value.
mbed_official	76:aeb1df146756	258	* This parameter must be a number between 0 and 0x1F.
mbed_official	76:aeb1df146756	259	* @retval None
mbed_official	76:aeb1df146756	260	*/
mbed_official	76:aeb1df146756	261	void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official	76:aeb1df146756	262	{
mbed_official	76:aeb1df146756	263	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	264
mbed_official	76:aeb1df146756	265	/* Check the parameters */
mbed_official	76:aeb1df146756	266	assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official	76:aeb1df146756	267
mbed_official	76:aeb1df146756	268	tmpreg = RCC->CR;
mbed_official	76:aeb1df146756	269
mbed_official	76:aeb1df146756	270	/* Clear HSITRIM[4:0] bits */
mbed_official	76:aeb1df146756	271	tmpreg &= ~RCC_CR_HSITRIM;
mbed_official	76:aeb1df146756	272
mbed_official	76:aeb1df146756	273	/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official	76:aeb1df146756	274	tmpreg \|= (uint32_t)HSICalibrationValue << 3;
mbed_official	76:aeb1df146756	275
mbed_official	76:aeb1df146756	276	/* Store the new value */
mbed_official	76:aeb1df146756	277	RCC->CR = tmpreg;
mbed_official	76:aeb1df146756	278	}
mbed_official	76:aeb1df146756	279
mbed_official	76:aeb1df146756	280	/**
mbed_official	76:aeb1df146756	281	* @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official	76:aeb1df146756	282	* @note After enabling the HSI, the application software should wait on
mbed_official	76:aeb1df146756	283	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	76:aeb1df146756	284	* be used to clock the PLL and/or system clock.
mbed_official	76:aeb1df146756	285	* @note HSI can not be stopped if it is used directly or through the PLL
mbed_official	76:aeb1df146756	286	* as system clock. In this case, you have to select another source
mbed_official	76:aeb1df146756	287	* of the system clock then stop the HSI.
mbed_official	76:aeb1df146756	288	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	289	* @param NewState: new state of the HSI.
mbed_official	76:aeb1df146756	290	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	291	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	76:aeb1df146756	292	* clock cycles.
mbed_official	76:aeb1df146756	293	* @retval None
mbed_official	76:aeb1df146756	294	*/
mbed_official	76:aeb1df146756	295	void RCC_HSICmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	296	{
mbed_official	76:aeb1df146756	297	/* Check the parameters */
mbed_official	76:aeb1df146756	298	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	299
mbed_official	76:aeb1df146756	300	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	301	{
mbed_official	76:aeb1df146756	302	RCC->CR \|= RCC_CR_HSION;
mbed_official	76:aeb1df146756	303	}
mbed_official	76:aeb1df146756	304	else
mbed_official	76:aeb1df146756	305	{
mbed_official	76:aeb1df146756	306	RCC->CR &= ~RCC_CR_HSION;
mbed_official	76:aeb1df146756	307	}
mbed_official	76:aeb1df146756	308	}
mbed_official	76:aeb1df146756	309
mbed_official	76:aeb1df146756	310	/**
mbed_official	76:aeb1df146756	311	* @brief Adjusts the Internal High Speed oscillator for ADC (HSI14)
mbed_official	76:aeb1df146756	312	* calibration value.
mbed_official	76:aeb1df146756	313	* @note The calibration is used to compensate for the variations in voltage
mbed_official	76:aeb1df146756	314	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	76:aeb1df146756	315	* Refer to the Application Note AN4067 for more details on how to
mbed_official	76:aeb1df146756	316	* calibrate the HSI14.
mbed_official	76:aeb1df146756	317	* @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
mbed_official	76:aeb1df146756	318	* This parameter must be a number between 0 and 0x1F.
mbed_official	76:aeb1df146756	319	* @retval None
mbed_official	76:aeb1df146756	320	*/
mbed_official	76:aeb1df146756	321	void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
mbed_official	76:aeb1df146756	322	{
mbed_official	76:aeb1df146756	323	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	324
mbed_official	76:aeb1df146756	325	/* Check the parameters */
mbed_official	76:aeb1df146756	326	assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
mbed_official	76:aeb1df146756	327
mbed_official	76:aeb1df146756	328	tmpreg = RCC->CR2;
mbed_official	76:aeb1df146756	329
mbed_official	76:aeb1df146756	330	/* Clear HSI14TRIM[4:0] bits */
mbed_official	76:aeb1df146756	331	tmpreg &= ~RCC_CR2_HSI14TRIM;
mbed_official	76:aeb1df146756	332
mbed_official	76:aeb1df146756	333	/* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
mbed_official	76:aeb1df146756	334	tmpreg \|= (uint32_t)HSI14CalibrationValue << 3;
mbed_official	76:aeb1df146756	335
mbed_official	76:aeb1df146756	336	/* Store the new value */
mbed_official	76:aeb1df146756	337	RCC->CR2 = tmpreg;
mbed_official	76:aeb1df146756	338	}
mbed_official	76:aeb1df146756	339
mbed_official	76:aeb1df146756	340	/**
mbed_official	76:aeb1df146756	341	* @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).
mbed_official	76:aeb1df146756	342	* @note After enabling the HSI14, the application software should wait on
mbed_official	76:aeb1df146756	343	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	76:aeb1df146756	344	* be used to clock the ADC.
mbed_official	76:aeb1df146756	345	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	346	* @param NewState: new state of the HSI14.
mbed_official	76:aeb1df146756	347	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	348	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
mbed_official	76:aeb1df146756	349	* clock cycles.
mbed_official	76:aeb1df146756	350	* @retval None
mbed_official	76:aeb1df146756	351	*/
mbed_official	76:aeb1df146756	352	void RCC_HSI14Cmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	353	{
mbed_official	76:aeb1df146756	354	/* Check the parameters */
mbed_official	76:aeb1df146756	355	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	356
mbed_official	76:aeb1df146756	357	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	358	{
mbed_official	76:aeb1df146756	359	RCC->CR2 \|= RCC_CR2_HSI14ON;
mbed_official	76:aeb1df146756	360	}
mbed_official	76:aeb1df146756	361	else
mbed_official	76:aeb1df146756	362	{
mbed_official	76:aeb1df146756	363	RCC->CR2 &= ~RCC_CR2_HSI14ON;
mbed_official	76:aeb1df146756	364	}
mbed_official	76:aeb1df146756	365	}
mbed_official	76:aeb1df146756	366
mbed_official	76:aeb1df146756	367	/**
mbed_official	76:aeb1df146756	368	* @brief Enables or disables the Internal High Speed oscillator request from ADC.
mbed_official	76:aeb1df146756	369	* @param NewState: new state of the HSI14 ADC request.
mbed_official	76:aeb1df146756	370	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	371	* @retval None
mbed_official	76:aeb1df146756	372	*/
mbed_official	76:aeb1df146756	373	void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	374	{
mbed_official	76:aeb1df146756	375	/* Check the parameters */
mbed_official	76:aeb1df146756	376	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	377
mbed_official	76:aeb1df146756	378	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	379	{
mbed_official	76:aeb1df146756	380	RCC->CR2 &= ~RCC_CR2_HSI14DIS;
mbed_official	76:aeb1df146756	381	}
mbed_official	76:aeb1df146756	382	else
mbed_official	76:aeb1df146756	383	{
mbed_official	76:aeb1df146756	384	RCC->CR2 \|= RCC_CR2_HSI14DIS;
mbed_official	76:aeb1df146756	385	}
mbed_official	76:aeb1df146756	386	}
mbed_official	76:aeb1df146756	387
mbed_official	76:aeb1df146756	388	/**
mbed_official	76:aeb1df146756	389	* @brief Configures the External Low Speed oscillator (LSE).
mbed_official	76:aeb1df146756	390	* @note As the LSE is in the Backup domain and write access is denied to this
mbed_official	76:aeb1df146756	391	* domain after reset, you have to enable write access using
mbed_official	76:aeb1df146756	392	* PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
mbed_official	76:aeb1df146756	393	* (to be done once after reset).
mbed_official	76:aeb1df146756	394	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
mbed_official	76:aeb1df146756	395	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	76:aeb1df146756	396	* is stable and can be used to clock the RTC.
mbed_official	76:aeb1df146756	397	* @param RCC_LSE: specifies the new state of the LSE.
mbed_official	76:aeb1df146756	398	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	399	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	76:aeb1df146756	400	* 6 LSE oscillator clock cycles.
mbed_official	76:aeb1df146756	401	* @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official	76:aeb1df146756	402	* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official	76:aeb1df146756	403	* @retval None
mbed_official	76:aeb1df146756	404	*/
mbed_official	76:aeb1df146756	405	void RCC_LSEConfig(uint32_t RCC_LSE)
mbed_official	76:aeb1df146756	406	{
mbed_official	76:aeb1df146756	407	/* Check the parameters */
mbed_official	76:aeb1df146756	408	assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official	76:aeb1df146756	409
mbed_official	76:aeb1df146756	410	/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official	76:aeb1df146756	411	/* Reset LSEON bit */
mbed_official	76:aeb1df146756	412	RCC->BDCR &= ~(RCC_BDCR_LSEON);
mbed_official	76:aeb1df146756	413
mbed_official	76:aeb1df146756	414	/* Reset LSEBYP bit */
mbed_official	76:aeb1df146756	415	RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
mbed_official	76:aeb1df146756	416
mbed_official	76:aeb1df146756	417	/* Configure LSE */
mbed_official	76:aeb1df146756	418	RCC->BDCR \|= RCC_LSE;
mbed_official	76:aeb1df146756	419	}
mbed_official	76:aeb1df146756	420
mbed_official	76:aeb1df146756	421	/**
mbed_official	76:aeb1df146756	422	* @brief Configures the External Low Speed oscillator (LSE) drive capability.
mbed_official	76:aeb1df146756	423	* @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
mbed_official	76:aeb1df146756	424	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	425	* @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
mbed_official	76:aeb1df146756	426	* @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
mbed_official	76:aeb1df146756	427	* @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
mbed_official	76:aeb1df146756	428	* @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
mbed_official	76:aeb1df146756	429	* @retval None
mbed_official	76:aeb1df146756	430	*/
mbed_official	76:aeb1df146756	431	void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
mbed_official	76:aeb1df146756	432	{
mbed_official	76:aeb1df146756	433	/* Check the parameters */
mbed_official	76:aeb1df146756	434	assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
mbed_official	76:aeb1df146756	435
mbed_official	76:aeb1df146756	436	/* Clear LSEDRV[1:0] bits */
mbed_official	76:aeb1df146756	437	RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
mbed_official	76:aeb1df146756	438
mbed_official	76:aeb1df146756	439	/* Set the LSE Drive */
mbed_official	76:aeb1df146756	440	RCC->BDCR \|= RCC_LSEDrive;
mbed_official	76:aeb1df146756	441	}
mbed_official	76:aeb1df146756	442
mbed_official	76:aeb1df146756	443	/**
mbed_official	76:aeb1df146756	444	* @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official	76:aeb1df146756	445	* @note After enabling the LSI, the application software should wait on
mbed_official	76:aeb1df146756	446	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	76:aeb1df146756	447	* be used to clock the IWDG and/or the RTC.
mbed_official	76:aeb1df146756	448	* @note LSI can not be disabled if the IWDG is running.
mbed_official	76:aeb1df146756	449	* @param NewState: new state of the LSI.
mbed_official	76:aeb1df146756	450	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	451	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	76:aeb1df146756	452	* clock cycles.
mbed_official	76:aeb1df146756	453	* @retval None
mbed_official	76:aeb1df146756	454	*/
mbed_official	76:aeb1df146756	455	void RCC_LSICmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	456	{
mbed_official	76:aeb1df146756	457	/* Check the parameters */
mbed_official	76:aeb1df146756	458	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	459
mbed_official	76:aeb1df146756	460	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	461	{
mbed_official	76:aeb1df146756	462	RCC->CSR \|= RCC_CSR_LSION;
mbed_official	76:aeb1df146756	463	}
mbed_official	76:aeb1df146756	464	else
mbed_official	76:aeb1df146756	465	{
mbed_official	76:aeb1df146756	466	RCC->CSR &= ~RCC_CSR_LSION;
mbed_official	76:aeb1df146756	467	}
mbed_official	76:aeb1df146756	468	}
mbed_official	76:aeb1df146756	469
mbed_official	76:aeb1df146756	470	/**
mbed_official	76:aeb1df146756	471	* @brief Configures the PLL clock source and multiplication factor.
mbed_official	76:aeb1df146756	472	* @note This function must be used only when the PLL is disabled.
mbed_official	76:aeb1df146756	473	*
mbed_official	76:aeb1df146756	474	* @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official	76:aeb1df146756	475	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	476	* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
mbed_official	76:aeb1df146756	477	* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
mbed_official	76:aeb1df146756	478	* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	479	* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	480	* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
mbed_official	76:aeb1df146756	481	* PLL source).
mbed_official	76:aeb1df146756	482	*
mbed_official	76:aeb1df146756	483	* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
mbed_official	76:aeb1df146756	484	* This parameter can be RCC_PLLMul_x where x:[2,16]
mbed_official	76:aeb1df146756	485	*
mbed_official	76:aeb1df146756	486	* @retval None
mbed_official	76:aeb1df146756	487	*/
mbed_official	76:aeb1df146756	488	void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
mbed_official	76:aeb1df146756	489	{
mbed_official	76:aeb1df146756	490	/* Check the parameters */
mbed_official	76:aeb1df146756	491	assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official	76:aeb1df146756	492	assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official	76:aeb1df146756	493
mbed_official	76:aeb1df146756	494	/* Clear PLL Source [16] and Multiplier [21:18] bits */
mbed_official	76:aeb1df146756	495	RCC->CFGR &= ~(RCC_CFGR_PLLMULL \| RCC_CFGR_PLLSRC);
mbed_official	76:aeb1df146756	496
mbed_official	76:aeb1df146756	497	/* Set the PLL Source and Multiplier */
mbed_official	76:aeb1df146756	498	RCC->CFGR \|= (uint32_t)(RCC_PLLSource \| RCC_PLLMul);
mbed_official	76:aeb1df146756	499	}
mbed_official	76:aeb1df146756	500
mbed_official	76:aeb1df146756	501	/**
mbed_official	76:aeb1df146756	502	* @brief Enables or disables the PLL.
mbed_official	76:aeb1df146756	503	* @note After enabling the PLL, the application software should wait on
mbed_official	76:aeb1df146756	504	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	76:aeb1df146756	505	* be used as system clock source.
mbed_official	76:aeb1df146756	506	* @note The PLL can not be disabled if it is used as system clock source
mbed_official	76:aeb1df146756	507	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	508	* @param NewState: new state of the PLL.
mbed_official	76:aeb1df146756	509	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	510	* @retval None
mbed_official	76:aeb1df146756	511	*/
mbed_official	76:aeb1df146756	512	void RCC_PLLCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	513	{
mbed_official	76:aeb1df146756	514	/* Check the parameters */
mbed_official	76:aeb1df146756	515	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	516
mbed_official	76:aeb1df146756	517	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	518	{
mbed_official	76:aeb1df146756	519	RCC->CR \|= RCC_CR_PLLON;
mbed_official	76:aeb1df146756	520	}
mbed_official	76:aeb1df146756	521	else
mbed_official	76:aeb1df146756	522	{
mbed_official	76:aeb1df146756	523	RCC->CR &= ~RCC_CR_PLLON;
mbed_official	76:aeb1df146756	524	}
mbed_official	76:aeb1df146756	525	}
mbed_official	76:aeb1df146756	526
mbed_official	76:aeb1df146756	527	/**
mbed_official	76:aeb1df146756	528	* @brief Enables or disables the Internal High Speed oscillator for USB (HSI48).
mbed_official	76:aeb1df146756	529	* This function is only applicable for STM32F072 devices.
mbed_official	76:aeb1df146756	530	* @note After enabling the HSI48, the application software should wait on
mbed_official	76:aeb1df146756	531	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
mbed_official	76:aeb1df146756	532	* be used to clock the USB.
mbed_official	76:aeb1df146756	533	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	76:aeb1df146756	534	* @param NewState: new state of the HSI48.
mbed_official	76:aeb1df146756	535	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	536	* @retval None
mbed_official	76:aeb1df146756	537	*/
mbed_official	76:aeb1df146756	538	void RCC_HSI48Cmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	539	{
mbed_official	76:aeb1df146756	540	/* Check the parameters */
mbed_official	76:aeb1df146756	541	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	542
mbed_official	76:aeb1df146756	543	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	544	{
mbed_official	76:aeb1df146756	545	RCC->CR2 \|= RCC_CR2_HSI48ON;
mbed_official	76:aeb1df146756	546	}
mbed_official	76:aeb1df146756	547	else
mbed_official	76:aeb1df146756	548	{
mbed_official	76:aeb1df146756	549	RCC->CR2 &= ~RCC_CR2_HSI48ON;
mbed_official	76:aeb1df146756	550	}
mbed_official	76:aeb1df146756	551	}
mbed_official	76:aeb1df146756	552
mbed_official	76:aeb1df146756	553	/**
mbed_official	76:aeb1df146756	554	* @brief Configures the PREDIV1 division factor.
mbed_official	76:aeb1df146756	555	* @note This function must be used only when the PLL is disabled.
mbed_official	76:aeb1df146756	556	* @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
mbed_official	76:aeb1df146756	557	* This parameter can be RCC_PREDIV1_Divx where x:[1,16]
mbed_official	76:aeb1df146756	558	* @retval None
mbed_official	76:aeb1df146756	559	*/
mbed_official	76:aeb1df146756	560	void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
mbed_official	76:aeb1df146756	561	{
mbed_official	76:aeb1df146756	562	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	563
mbed_official	76:aeb1df146756	564	/* Check the parameters */
mbed_official	76:aeb1df146756	565	assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
mbed_official	76:aeb1df146756	566
mbed_official	76:aeb1df146756	567	tmpreg = RCC->CFGR2;
mbed_official	76:aeb1df146756	568	/* Clear PREDIV1[3:0] bits */
mbed_official	76:aeb1df146756	569	tmpreg &= ~(RCC_CFGR2_PREDIV1);
mbed_official	76:aeb1df146756	570	/* Set the PREDIV1 division factor */
mbed_official	76:aeb1df146756	571	tmpreg \|= RCC_PREDIV1_Div;
mbed_official	76:aeb1df146756	572	/* Store the new value */
mbed_official	76:aeb1df146756	573	RCC->CFGR2 = tmpreg;
mbed_official	76:aeb1df146756	574	}
mbed_official	76:aeb1df146756	575
mbed_official	76:aeb1df146756	576	/**
mbed_official	76:aeb1df146756	577	* @brief Enables or disables the Clock Security System.
mbed_official	76:aeb1df146756	578	* @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official	76:aeb1df146756	579	* is automatically disabled and an interrupt is generated to inform the
mbed_official	76:aeb1df146756	580	* software about the failure (Clock Security System Interrupt, CSSI),
mbed_official	76:aeb1df146756	581	* allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official	76:aeb1df146756	582	* the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
mbed_official	76:aeb1df146756	583	* @param NewState: new state of the Clock Security System.
mbed_official	76:aeb1df146756	584	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	585	* @retval None
mbed_official	76:aeb1df146756	586	*/
mbed_official	76:aeb1df146756	587	void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	588	{
mbed_official	76:aeb1df146756	589	/* Check the parameters */
mbed_official	76:aeb1df146756	590	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	591
mbed_official	76:aeb1df146756	592	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	593	{
mbed_official	76:aeb1df146756	594	RCC->CR \|= RCC_CR_CSSON;
mbed_official	76:aeb1df146756	595	}
mbed_official	76:aeb1df146756	596	else
mbed_official	76:aeb1df146756	597	{
mbed_official	76:aeb1df146756	598	RCC->CR &= ~RCC_CR_CSSON;
mbed_official	76:aeb1df146756	599	}
mbed_official	76:aeb1df146756	600	}
mbed_official	76:aeb1df146756	601
mbed_official	76:aeb1df146756	602	#ifdef STM32F051
mbed_official	76:aeb1df146756	603	/**
mbed_official	76:aeb1df146756	604	* @brief Selects the clock source to output on MCO pin (PA8).
mbed_official	76:aeb1df146756	605	* @note PA8 should be configured in alternate function mode.
mbed_official	76:aeb1df146756	606	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	76:aeb1df146756	607	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	608	* @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official	76:aeb1df146756	609	* @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official	76:aeb1df146756	610	* @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official	76:aeb1df146756	611	* @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official	76:aeb1df146756	612	* @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official	76:aeb1df146756	613	* @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official	76:aeb1df146756	614	* @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official	76:aeb1df146756	615	* @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official	76:aeb1df146756	616	* @retval None
mbed_official	76:aeb1df146756	617	*/
mbed_official	76:aeb1df146756	618	void RCC_MCOConfig(uint8_t RCC_MCOSource)
mbed_official	76:aeb1df146756	619	{
mbed_official	76:aeb1df146756	620	/* Check the parameters */
mbed_official	76:aeb1df146756	621	assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official	76:aeb1df146756	622
mbed_official	76:aeb1df146756	623	/* Select MCO clock source and prescaler */
mbed_official	76:aeb1df146756	624	(__IO uint8_t ) CFGR_BYTE3_ADDRESS = RCC_MCOSource;
mbed_official	76:aeb1df146756	625	}
mbed_official	76:aeb1df146756	626	#else
mbed_official	76:aeb1df146756	627
mbed_official	76:aeb1df146756	628	/**
mbed_official	76:aeb1df146756	629	* @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
mbed_official	76:aeb1df146756	630	* prescsaler.
mbed_official	76:aeb1df146756	631	* @note PA8 should be configured in alternate function mode.
mbed_official	76:aeb1df146756	632	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	76:aeb1df146756	633	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	634	* @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official	76:aeb1df146756	635	* @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official	76:aeb1df146756	636	* @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official	76:aeb1df146756	637	* @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official	76:aeb1df146756	638	* @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official	76:aeb1df146756	639	* @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official	76:aeb1df146756	640	* @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official	76:aeb1df146756	641	* @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official	76:aeb1df146756	642	* @arg RCC_MCOSource_PLLCLK: PLL clock selected.
mbed_official	76:aeb1df146756	643	* @arg RCC_MCOSource_HSI48: HSI48 clock selected.
mbed_official	76:aeb1df146756	644	* @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
mbed_official	76:aeb1df146756	645	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	646	* @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
mbed_official	76:aeb1df146756	647	* @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
mbed_official	76:aeb1df146756	648	* @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
mbed_official	76:aeb1df146756	649	* @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
mbed_official	76:aeb1df146756	650	* @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
mbed_official	76:aeb1df146756	651	* @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
mbed_official	76:aeb1df146756	652	* @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
mbed_official	76:aeb1df146756	653	* @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
mbed_official	76:aeb1df146756	654	* @retval None
mbed_official	76:aeb1df146756	655	*/
mbed_official	76:aeb1df146756	656	void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
mbed_official	76:aeb1df146756	657	{
mbed_official	76:aeb1df146756	658	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	659
mbed_official	76:aeb1df146756	660	/* Check the parameters */
mbed_official	76:aeb1df146756	661	assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official	76:aeb1df146756	662	assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
mbed_official	76:aeb1df146756	663
mbed_official	76:aeb1df146756	664	/* Get CFGR value */
mbed_official	76:aeb1df146756	665	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	666	/* Clear MCOPRE[2:0] bits */
mbed_official	76:aeb1df146756	667	tmpreg &= ~(RCC_CFGR_MCO_PRE \| RCC_CFGR_MCO \| RCC_CFGR_PLLNODIV);
mbed_official	76:aeb1df146756	668	/* Set the RCC_MCOSource and RCC_MCOPrescaler */
mbed_official	76:aeb1df146756	669	tmpreg \|= (RCC_MCOPrescaler \| ((uint32_t)RCC_MCOSource<<24));
mbed_official	76:aeb1df146756	670	/* Store the new value */
mbed_official	76:aeb1df146756	671	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	672	}
mbed_official	76:aeb1df146756	673	#endif /* STM32F072 */
mbed_official	76:aeb1df146756	674
mbed_official	76:aeb1df146756	675	/**
mbed_official	76:aeb1df146756	676	* @}
mbed_official	76:aeb1df146756	677	*/
mbed_official	76:aeb1df146756	678
mbed_official	76:aeb1df146756	679	/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
mbed_official	76:aeb1df146756	680	* @brief System, AHB and APB busses clocks configuration functions
mbed_official	76:aeb1df146756	681	*
mbed_official	76:aeb1df146756	682	@verbatim
mbed_official	76:aeb1df146756	683	===============================================================================
mbed_official	76:aeb1df146756	684	##### System, AHB and APB busses clocks configuration functions #####
mbed_official	76:aeb1df146756	685	===============================================================================
mbed_official	76:aeb1df146756	686
mbed_official	76:aeb1df146756	687	[..] This section provide functions allowing to configure the System, AHB and
mbed_official	76:aeb1df146756	688	APB busses clocks.
mbed_official	76:aeb1df146756	689	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official	76:aeb1df146756	690	HSE and PLL.
mbed_official	76:aeb1df146756	691	The AHB clock (HCLK) is derived from System clock through configurable prescaler
mbed_official	76:aeb1df146756	692	and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
mbed_official	76:aeb1df146756	693	and APB (PCLK) clocks are derived from AHB clock through
mbed_official	76:aeb1df146756	694	configurable prescalers and used to clock the peripherals mapped on these busses.
mbed_official	76:aeb1df146756	695	You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
mbed_official	76:aeb1df146756	696
mbed_official	76:aeb1df146756	697	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official	76:aeb1df146756	698	(+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
mbed_official	76:aeb1df146756	699	programmable prescaler: 2 or 4).
mbed_official	76:aeb1df146756	700	(+@) The CEC clock which is derived from LSE or HSI divided by 244.
mbed_official	76:aeb1df146756	701	(+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
mbed_official	76:aeb1df146756	702	(+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
mbed_official	76:aeb1df146756	703	(+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
mbed_official	76:aeb1df146756	704	divided by a programmable prescaler).
mbed_official	76:aeb1df146756	705	The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
mbed_official	76:aeb1df146756	706	clock frequency.
mbed_official	76:aeb1df146756	707	(+@) IWDG clock which is always the LSI clock.
mbed_official	76:aeb1df146756	708
mbed_official	76:aeb1df146756	709	(#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
mbed_official	76:aeb1df146756	710	Depending on the maximum frequency, the FLASH wait states (WS) should be
mbed_official	76:aeb1df146756	711	adapted accordingly:
mbed_official	76:aeb1df146756	712	+--------------------------------------------- +
mbed_official	76:aeb1df146756	713	\| Wait states \| HCLK clock frequency (MHz) \|
mbed_official	76:aeb1df146756	714	\|---------------\|------------------------------\|
mbed_official	76:aeb1df146756	715	\|0WS(1CPU cycle)\| 0 < HCLK <= 24 \|
mbed_official	76:aeb1df146756	716	\|---------------\|------------------------------\|
mbed_official	76:aeb1df146756	717	\|1WS(2CPU cycle)\| 24 < HCLK <= 48 \|
mbed_official	76:aeb1df146756	718	+----------------------------------------------+
mbed_official	76:aeb1df146756	719
mbed_official	76:aeb1df146756	720	(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
mbed_official	76:aeb1df146756	721	prefetch is disabled.
mbed_official	76:aeb1df146756	722
mbed_official	76:aeb1df146756	723	[..] It is recommended to use the following software sequences to tune the number
mbed_official	76:aeb1df146756	724	of wait states needed to access the Flash memory with the CPU frequency (HCLK).
mbed_official	76:aeb1df146756	725	(+) Increasing the CPU frequency
mbed_official	76:aeb1df146756	726	(++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
mbed_official	76:aeb1df146756	727	function
mbed_official	76:aeb1df146756	728	(++) Check that Flash Prefetch buffer activation is taken into account by
mbed_official	76:aeb1df146756	729	reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
mbed_official	76:aeb1df146756	730	(++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
mbed_official	76:aeb1df146756	731	(++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official	76:aeb1df146756	732	(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official	76:aeb1df146756	733	(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official	76:aeb1df146756	734	(++) Check that the new CPU clock source is taken into account by reading
mbed_official	76:aeb1df146756	735	the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official	76:aeb1df146756	736	(+) Decreasing the CPU frequency
mbed_official	76:aeb1df146756	737	(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official	76:aeb1df146756	738	(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official	76:aeb1df146756	739	(++) Check that the new CPU clock source is taken into account by reading
mbed_official	76:aeb1df146756	740	the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official	76:aeb1df146756	741	(++) Program the new number of WS, using "FLASH_SetLatency()" function
mbed_official	76:aeb1df146756	742	(++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official	76:aeb1df146756	743	(++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
mbed_official	76:aeb1df146756	744	function
mbed_official	76:aeb1df146756	745	(++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
mbed_official	76:aeb1df146756	746	using the FLASH_GetPrefetchBufferStatus() function.
mbed_official	76:aeb1df146756	747
mbed_official	76:aeb1df146756	748	@endverbatim
mbed_official	76:aeb1df146756	749	* @{
mbed_official	76:aeb1df146756	750	*/
mbed_official	76:aeb1df146756	751
mbed_official	76:aeb1df146756	752	/**
mbed_official	76:aeb1df146756	753	* @brief Configures the system clock (SYSCLK).
mbed_official	76:aeb1df146756	754	* @note The HSI is used (enabled by hardware) as system clock source after
mbed_official	76:aeb1df146756	755	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official	76:aeb1df146756	756	* of failure of the HSE used directly or indirectly as system clock
mbed_official	76:aeb1df146756	757	* (if the Clock Security System CSS is enabled).
mbed_official	76:aeb1df146756	758	* @note A switch from one clock source to another occurs only if the target
mbed_official	76:aeb1df146756	759	* clock source is ready (clock stable after startup delay or PLL locked).
mbed_official	76:aeb1df146756	760	* If a clock source which is not yet ready is selected, the switch will
mbed_official	76:aeb1df146756	761	* occur when the clock source will be ready.
mbed_official	76:aeb1df146756	762	* You can use RCC_GetSYSCLKSource() function to know which clock is
mbed_official	76:aeb1df146756	763	* currently used as system clock source.
mbed_official	76:aeb1df146756	764	* @param RCC_SYSCLKSource: specifies the clock source used as system clock source
mbed_official	76:aeb1df146756	765	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	766	* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
mbed_official	76:aeb1df146756	767	* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
mbed_official	76:aeb1df146756	768	* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
mbed_official	76:aeb1df146756	769	* @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	770	* @retval None
mbed_official	76:aeb1df146756	771	*/
mbed_official	76:aeb1df146756	772	void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official	76:aeb1df146756	773	{
mbed_official	76:aeb1df146756	774	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	775
mbed_official	76:aeb1df146756	776	/* Check the parameters */
mbed_official	76:aeb1df146756	777	assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official	76:aeb1df146756	778
mbed_official	76:aeb1df146756	779	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	780
mbed_official	76:aeb1df146756	781	/* Clear SW[1:0] bits */
mbed_official	76:aeb1df146756	782	tmpreg &= ~RCC_CFGR_SW;
mbed_official	76:aeb1df146756	783
mbed_official	76:aeb1df146756	784	/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official	76:aeb1df146756	785	tmpreg \|= RCC_SYSCLKSource;
mbed_official	76:aeb1df146756	786
mbed_official	76:aeb1df146756	787	/* Store the new value */
mbed_official	76:aeb1df146756	788	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	789	}
mbed_official	76:aeb1df146756	790
mbed_official	76:aeb1df146756	791	/**
mbed_official	76:aeb1df146756	792	* @brief Returns the clock source used as system clock.
mbed_official	76:aeb1df146756	793	* @param None
mbed_official	76:aeb1df146756	794	* @retval The clock source used as system clock. The returned value can be one
mbed_official	76:aeb1df146756	795	* of the following values:
mbed_official	76:aeb1df146756	796	* - 0x00: HSI used as system clock
mbed_official	76:aeb1df146756	797	* - 0x04: HSE used as system clock
mbed_official	76:aeb1df146756	798	* - 0x08: PLL used as system clock
mbed_official	76:aeb1df146756	799	* - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	800	*/
mbed_official	76:aeb1df146756	801	uint8_t RCC_GetSYSCLKSource(void)
mbed_official	76:aeb1df146756	802	{
mbed_official	76:aeb1df146756	803	return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
mbed_official	76:aeb1df146756	804	}
mbed_official	76:aeb1df146756	805
mbed_official	76:aeb1df146756	806	/**
mbed_official	76:aeb1df146756	807	* @brief Configures the AHB clock (HCLK).
mbed_official	76:aeb1df146756	808	* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official	76:aeb1df146756	809	* the system clock (SYSCLK).
mbed_official	76:aeb1df146756	810	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	811	* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official	76:aeb1df146756	812	* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official	76:aeb1df146756	813	* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official	76:aeb1df146756	814	* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official	76:aeb1df146756	815	* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official	76:aeb1df146756	816	* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official	76:aeb1df146756	817	* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official	76:aeb1df146756	818	* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official	76:aeb1df146756	819	* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official	76:aeb1df146756	820	* @retval None
mbed_official	76:aeb1df146756	821	*/
mbed_official	76:aeb1df146756	822	void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official	76:aeb1df146756	823	{
mbed_official	76:aeb1df146756	824	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	825
mbed_official	76:aeb1df146756	826	/* Check the parameters */
mbed_official	76:aeb1df146756	827	assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official	76:aeb1df146756	828
mbed_official	76:aeb1df146756	829	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	830
mbed_official	76:aeb1df146756	831	/* Clear HPRE[3:0] bits */
mbed_official	76:aeb1df146756	832	tmpreg &= ~RCC_CFGR_HPRE;
mbed_official	76:aeb1df146756	833
mbed_official	76:aeb1df146756	834	/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official	76:aeb1df146756	835	tmpreg \|= RCC_SYSCLK;
mbed_official	76:aeb1df146756	836
mbed_official	76:aeb1df146756	837	/* Store the new value */
mbed_official	76:aeb1df146756	838	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	839	}
mbed_official	76:aeb1df146756	840
mbed_official	76:aeb1df146756	841	/**
mbed_official	76:aeb1df146756	842	* @brief Configures the APB clock (PCLK).
mbed_official	76:aeb1df146756	843	* @param RCC_HCLK: defines the APB clock divider. This clock is derived from
mbed_official	76:aeb1df146756	844	* the AHB clock (HCLK).
mbed_official	76:aeb1df146756	845	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	846	* @arg RCC_HCLK_Div1: APB clock = HCLK
mbed_official	76:aeb1df146756	847	* @arg RCC_HCLK_Div2: APB clock = HCLK/2
mbed_official	76:aeb1df146756	848	* @arg RCC_HCLK_Div4: APB clock = HCLK/4
mbed_official	76:aeb1df146756	849	* @arg RCC_HCLK_Div8: APB clock = HCLK/8
mbed_official	76:aeb1df146756	850	* @arg RCC_HCLK_Div16: APB clock = HCLK/16
mbed_official	76:aeb1df146756	851	* @retval None
mbed_official	76:aeb1df146756	852	*/
mbed_official	76:aeb1df146756	853	void RCC_PCLKConfig(uint32_t RCC_HCLK)
mbed_official	76:aeb1df146756	854	{
mbed_official	76:aeb1df146756	855	uint32_t tmpreg = 0;
mbed_official	76:aeb1df146756	856
mbed_official	76:aeb1df146756	857	/* Check the parameters */
mbed_official	76:aeb1df146756	858	assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official	76:aeb1df146756	859
mbed_official	76:aeb1df146756	860	tmpreg = RCC->CFGR;
mbed_official	76:aeb1df146756	861
mbed_official	76:aeb1df146756	862	/* Clear PPRE[2:0] bits */
mbed_official	76:aeb1df146756	863	tmpreg &= ~RCC_CFGR_PPRE;
mbed_official	76:aeb1df146756	864
mbed_official	76:aeb1df146756	865	/* Set PPRE[2:0] bits according to RCC_HCLK value */
mbed_official	76:aeb1df146756	866	tmpreg \|= RCC_HCLK;
mbed_official	76:aeb1df146756	867
mbed_official	76:aeb1df146756	868	/* Store the new value */
mbed_official	76:aeb1df146756	869	RCC->CFGR = tmpreg;
mbed_official	76:aeb1df146756	870	}
mbed_official	76:aeb1df146756	871
mbed_official	76:aeb1df146756	872	/**
mbed_official	76:aeb1df146756	873	* @brief Configures the ADC clock (ADCCLK).
mbed_official	76:aeb1df146756	874	* @note This function is obsolete.
mbed_official	76:aeb1df146756	875	* For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
mbed_official	76:aeb1df146756	876	* @param RCC_ADCCLK: defines the ADC clock source. This clock is derived
mbed_official	76:aeb1df146756	877	* from the HSI14 or APB clock (PCLK).
mbed_official	76:aeb1df146756	878	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	879	* @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
mbed_official	76:aeb1df146756	880	* @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
mbed_official	76:aeb1df146756	881	* @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
mbed_official	76:aeb1df146756	882	* @retval None
mbed_official	76:aeb1df146756	883	*/
mbed_official	76:aeb1df146756	884	void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
mbed_official	76:aeb1df146756	885	{
mbed_official	76:aeb1df146756	886	/* Check the parameters */
mbed_official	76:aeb1df146756	887	assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
mbed_official	76:aeb1df146756	888
mbed_official	76:aeb1df146756	889	/* Clear ADCPRE bit */
mbed_official	76:aeb1df146756	890	RCC->CFGR &= ~RCC_CFGR_ADCPRE;
mbed_official	76:aeb1df146756	891	/* Set ADCPRE bits according to RCC_PCLK value */
mbed_official	76:aeb1df146756	892	RCC->CFGR \|= RCC_ADCCLK & 0xFFFF;
mbed_official	76:aeb1df146756	893
mbed_official	76:aeb1df146756	894	/* Clear ADCSW bit */
mbed_official	76:aeb1df146756	895	RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
mbed_official	76:aeb1df146756	896	/* Set ADCSW bits according to RCC_ADCCLK value */
mbed_official	76:aeb1df146756	897	RCC->CFGR3 \|= RCC_ADCCLK >> 16;
mbed_official	76:aeb1df146756	898	}
mbed_official	76:aeb1df146756	899
mbed_official	76:aeb1df146756	900	/**
mbed_official	76:aeb1df146756	901	* @brief Configures the CEC clock (CECCLK).
mbed_official	76:aeb1df146756	902	* @param RCC_CECCLK: defines the CEC clock source. This clock is derived
mbed_official	76:aeb1df146756	903	* from the HSI or LSE clock.
mbed_official	76:aeb1df146756	904	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	905	* @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
mbed_official	76:aeb1df146756	906	* @arg RCC_CECCLK_LSE: CEC clock = LSE
mbed_official	76:aeb1df146756	907	* @retval None
mbed_official	76:aeb1df146756	908	*/
mbed_official	76:aeb1df146756	909	void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
mbed_official	76:aeb1df146756	910	{
mbed_official	76:aeb1df146756	911	/* Check the parameters */
mbed_official	76:aeb1df146756	912	assert_param(IS_RCC_CECCLK(RCC_CECCLK));
mbed_official	76:aeb1df146756	913
mbed_official	76:aeb1df146756	914	/* Clear CECSW bit */
mbed_official	76:aeb1df146756	915	RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
mbed_official	76:aeb1df146756	916	/* Set CECSW bits according to RCC_CECCLK value */
mbed_official	76:aeb1df146756	917	RCC->CFGR3 \|= RCC_CECCLK;
mbed_official	76:aeb1df146756	918	}
mbed_official	76:aeb1df146756	919
mbed_official	76:aeb1df146756	920	/**
mbed_official	76:aeb1df146756	921	* @brief Configures the I2C1 clock (I2C1CLK).
mbed_official	76:aeb1df146756	922	* @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
mbed_official	76:aeb1df146756	923	* from the HSI or System clock.
mbed_official	76:aeb1df146756	924	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	925	* @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
mbed_official	76:aeb1df146756	926	* @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
mbed_official	76:aeb1df146756	927	* @retval None
mbed_official	76:aeb1df146756	928	*/
mbed_official	76:aeb1df146756	929	void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
mbed_official	76:aeb1df146756	930	{
mbed_official	76:aeb1df146756	931	/* Check the parameters */
mbed_official	76:aeb1df146756	932	assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
mbed_official	76:aeb1df146756	933
mbed_official	76:aeb1df146756	934	/* Clear I2CSW bit */
mbed_official	76:aeb1df146756	935	RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
mbed_official	76:aeb1df146756	936	/* Set I2CSW bits according to RCC_I2CCLK value */
mbed_official	76:aeb1df146756	937	RCC->CFGR3 \|= RCC_I2CCLK;
mbed_official	76:aeb1df146756	938	}
mbed_official	76:aeb1df146756	939
mbed_official	76:aeb1df146756	940	/**
mbed_official	76:aeb1df146756	941	* @brief Configures the USART1 clock (USART1CLK).
mbed_official	76:aeb1df146756	942	* @param RCC_USARTCLK: defines the USART clock source. This clock is derived
mbed_official	76:aeb1df146756	943	* from the HSI or System clock.
mbed_official	76:aeb1df146756	944	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	945	* @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
mbed_official	76:aeb1df146756	946	* @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
mbed_official	76:aeb1df146756	947	* @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
mbed_official	76:aeb1df146756	948	* @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
mbed_official	76:aeb1df146756	949	* @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	950	* @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	951	* @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	952	* @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	953	* @retval None
mbed_official	76:aeb1df146756	954	*/
mbed_official	76:aeb1df146756	955	void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
mbed_official	76:aeb1df146756	956	{
mbed_official	76:aeb1df146756	957	uint32_t tmp = 0;
mbed_official	76:aeb1df146756	958
mbed_official	76:aeb1df146756	959	/* Check the parameters */
mbed_official	76:aeb1df146756	960	assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
mbed_official	76:aeb1df146756	961
mbed_official	76:aeb1df146756	962	/* Get USART index */
mbed_official	76:aeb1df146756	963	tmp = (RCC_USARTCLK >> 28);
mbed_official	76:aeb1df146756	964
mbed_official	76:aeb1df146756	965	/* Clear USARTSW[1:0] bit */
mbed_official	76:aeb1df146756	966	if (tmp == (uint32_t)0x00000001)
mbed_official	76:aeb1df146756	967	{
mbed_official	76:aeb1df146756	968	/* Clear USART1SW[1:0] bit */
mbed_official	76:aeb1df146756	969	RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
mbed_official	76:aeb1df146756	970	}
mbed_official	76:aeb1df146756	971	else
mbed_official	76:aeb1df146756	972	{
mbed_official	76:aeb1df146756	973	/* Clear USART2SW[1:0] bit */
mbed_official	76:aeb1df146756	974	RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
mbed_official	76:aeb1df146756	975	}
mbed_official	76:aeb1df146756	976
mbed_official	76:aeb1df146756	977	/* Set USARTxSW bits according to RCC_USARTCLK value */
mbed_official	76:aeb1df146756	978	RCC->CFGR3 \|= RCC_USARTCLK;
mbed_official	76:aeb1df146756	979	}
mbed_official	76:aeb1df146756	980
mbed_official	76:aeb1df146756	981	/**
mbed_official	76:aeb1df146756	982	* @brief Configures the USB clock (USBCLK).
mbed_official	76:aeb1df146756	983	* This function is only applicable for STM32F072 devices.
mbed_official	76:aeb1df146756	984	* @param RCC_USBCLK: defines the USB clock source. This clock is derived
mbed_official	76:aeb1df146756	985	* from the HSI48 or system clock.
mbed_official	76:aeb1df146756	986	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	987	* @arg RCC_USBCLK_HSI48: USB clock = HSI48
mbed_official	76:aeb1df146756	988	* @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
mbed_official	76:aeb1df146756	989	* @retval None
mbed_official	76:aeb1df146756	990	*/
mbed_official	76:aeb1df146756	991	void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
mbed_official	76:aeb1df146756	992	{
mbed_official	76:aeb1df146756	993	/* Check the parameters */
mbed_official	76:aeb1df146756	994	assert_param(IS_RCC_USBCLK(RCC_USBCLK));
mbed_official	76:aeb1df146756	995
mbed_official	76:aeb1df146756	996	/* Clear USBSW bit */
mbed_official	76:aeb1df146756	997	RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
mbed_official	76:aeb1df146756	998	/* Set USBSW bits according to RCC_USBCLK value */
mbed_official	76:aeb1df146756	999	RCC->CFGR3 \|= RCC_USBCLK;
mbed_official	76:aeb1df146756	1000	}
mbed_official	76:aeb1df146756	1001
mbed_official	76:aeb1df146756	1002	/**
mbed_official	76:aeb1df146756	1003	* @brief Returns the frequencies of the System, AHB and APB busses clocks.
mbed_official	76:aeb1df146756	1004	* @note The frequency returned by this function is not the real frequency
mbed_official	76:aeb1df146756	1005	* in the chip. It is calculated based on the predefined constant and
mbed_official	76:aeb1df146756	1006	* the source selected by RCC_SYSCLKConfig():
mbed_official	76:aeb1df146756	1007	*
mbed_official	76:aeb1df146756	1008	* @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
mbed_official	76:aeb1df146756	1009	*
mbed_official	76:aeb1df146756	1010	* @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
mbed_official	76:aeb1df146756	1011	*
mbed_official	76:aeb1df146756	1012	* @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
mbed_official	76:aeb1df146756	1013	* or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official	76:aeb1df146756	1014	*
mbed_official	76:aeb1df146756	1015	* @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
mbed_official	76:aeb1df146756	1016	*
mbed_official	76:aeb1df146756	1017	* @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official	76:aeb1df146756	1018	* 8 MHz) but the real value may vary depending on the variations
mbed_official	76:aeb1df146756	1019	* in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
mbed_official	76:aeb1df146756	1020	*
mbed_official	76:aeb1df146756	1021	* @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official	76:aeb1df146756	1022	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	76:aeb1df146756	1023	* frequency of the crystal used. Otherwise, this function may
mbed_official	76:aeb1df146756	1024	* return wrong result.
mbed_official	76:aeb1df146756	1025	*
mbed_official	76:aeb1df146756	1026	* @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value
mbed_official	76:aeb1df146756	1027	* 48 MHz) but the real value may vary depending on the variations
mbed_official	76:aeb1df146756	1028	* in voltage and temperature.
mbed_official	76:aeb1df146756	1029	*
mbed_official	76:aeb1df146756	1030	* @note The result of this function could be not correct when using fractional
mbed_official	76:aeb1df146756	1031	* value for HSE crystal.
mbed_official	76:aeb1df146756	1032	*
mbed_official	76:aeb1df146756	1033	* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official	76:aeb1df146756	1034	* the clocks frequencies.
mbed_official	76:aeb1df146756	1035	*
mbed_official	76:aeb1df146756	1036	* @note This function can be used by the user application to compute the
mbed_official	76:aeb1df146756	1037	* baudrate for the communication peripherals or configure other parameters.
mbed_official	76:aeb1df146756	1038	* @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function
mbed_official	76:aeb1df146756	1039	* must be called to update the structure's field. Otherwise, any
mbed_official	76:aeb1df146756	1040	* configuration based on this function will be incorrect.
mbed_official	76:aeb1df146756	1041	*
mbed_official	76:aeb1df146756	1042	* @retval None
mbed_official	76:aeb1df146756	1043	*/
mbed_official	76:aeb1df146756	1044	void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official	76:aeb1df146756	1045	{
mbed_official	76:aeb1df146756	1046	uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
mbed_official	76:aeb1df146756	1047
mbed_official	76:aeb1df146756	1048	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	76:aeb1df146756	1049	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	76:aeb1df146756	1050
mbed_official	76:aeb1df146756	1051	switch (tmp)
mbed_official	76:aeb1df146756	1052	{
mbed_official	76:aeb1df146756	1053	case 0x00: /* HSI used as system clock */
mbed_official	76:aeb1df146756	1054	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	1055	break;
mbed_official	76:aeb1df146756	1056	case 0x04: /* HSE used as system clock */
mbed_official	76:aeb1df146756	1057	RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official	76:aeb1df146756	1058	break;
mbed_official	76:aeb1df146756	1059	case 0x08: /* PLL used as system clock */
mbed_official	76:aeb1df146756	1060	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	76:aeb1df146756	1061	pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official	76:aeb1df146756	1062	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	76:aeb1df146756	1063	pllmull = ( pllmull >> 18) + 2;
mbed_official	76:aeb1df146756	1064
mbed_official	76:aeb1df146756	1065	if (pllsource == 0x00)
mbed_official	76:aeb1df146756	1066	{
mbed_official	76:aeb1df146756	1067	/* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official	76:aeb1df146756	1068	pllclk = (HSI_VALUE >> 1) * pllmull;
mbed_official	76:aeb1df146756	1069	}
mbed_official	76:aeb1df146756	1070	else
mbed_official	76:aeb1df146756	1071	{
mbed_official	76:aeb1df146756	1072	prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official	76:aeb1df146756	1073	/* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official	76:aeb1df146756	1074	pllclk = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official	76:aeb1df146756	1075	}
mbed_official	76:aeb1df146756	1076	RCC_Clocks->SYSCLK_Frequency = pllclk;
mbed_official	76:aeb1df146756	1077	break;
mbed_official	76:aeb1df146756	1078	case 0x0C: /* HSI48 used as system clock */
mbed_official	76:aeb1df146756	1079	RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
mbed_official	76:aeb1df146756	1080	break;
mbed_official	76:aeb1df146756	1081	default: /* HSI used as system clock */
mbed_official	76:aeb1df146756	1082	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	1083	break;
mbed_official	76:aeb1df146756	1084	}
mbed_official	76:aeb1df146756	1085	/* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
mbed_official	76:aeb1df146756	1086	/* Get HCLK prescaler */
mbed_official	76:aeb1df146756	1087	tmp = RCC->CFGR & RCC_CFGR_HPRE;
mbed_official	76:aeb1df146756	1088	tmp = tmp >> 4;
mbed_official	76:aeb1df146756	1089	presc = APBAHBPrescTable[tmp];
mbed_official	76:aeb1df146756	1090	/* HCLK clock frequency */
mbed_official	76:aeb1df146756	1091	RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
mbed_official	76:aeb1df146756	1092
mbed_official	76:aeb1df146756	1093	/* Get PCLK prescaler */
mbed_official	76:aeb1df146756	1094	tmp = RCC->CFGR & RCC_CFGR_PPRE;
mbed_official	76:aeb1df146756	1095	tmp = tmp >> 8;
mbed_official	76:aeb1df146756	1096	presc = APBAHBPrescTable[tmp];
mbed_official	76:aeb1df146756	1097	/* PCLK clock frequency */
mbed_official	76:aeb1df146756	1098	RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official	76:aeb1df146756	1099
mbed_official	76:aeb1df146756	1100	/* ADCCLK clock frequency */
mbed_official	76:aeb1df146756	1101	if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
mbed_official	76:aeb1df146756	1102	{
mbed_official	76:aeb1df146756	1103	/* ADC Clock is HSI14 Osc. */
mbed_official	76:aeb1df146756	1104	RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
mbed_official	76:aeb1df146756	1105	}
mbed_official	76:aeb1df146756	1106	else
mbed_official	76:aeb1df146756	1107	{
mbed_official	76:aeb1df146756	1108	if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
mbed_official	76:aeb1df146756	1109	{
mbed_official	76:aeb1df146756	1110	/* ADC Clock is derived from PCLK/2 */
mbed_official	76:aeb1df146756	1111	RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
mbed_official	76:aeb1df146756	1112	}
mbed_official	76:aeb1df146756	1113	else
mbed_official	76:aeb1df146756	1114	{
mbed_official	76:aeb1df146756	1115	/* ADC Clock is derived from PCLK/4 */
mbed_official	76:aeb1df146756	1116	RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
mbed_official	76:aeb1df146756	1117	}
mbed_official	76:aeb1df146756	1118
mbed_official	76:aeb1df146756	1119	}
mbed_official	76:aeb1df146756	1120
mbed_official	76:aeb1df146756	1121	/* CECCLK clock frequency */
mbed_official	76:aeb1df146756	1122	if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
mbed_official	76:aeb1df146756	1123	{
mbed_official	76:aeb1df146756	1124	/* CEC Clock is HSI/244 */
mbed_official	76:aeb1df146756	1125	RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
mbed_official	76:aeb1df146756	1126	}
mbed_official	76:aeb1df146756	1127	else
mbed_official	76:aeb1df146756	1128	{
mbed_official	76:aeb1df146756	1129	/* CECC Clock is LSE Osc. */
mbed_official	76:aeb1df146756	1130	RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
mbed_official	76:aeb1df146756	1131	}
mbed_official	76:aeb1df146756	1132
mbed_official	76:aeb1df146756	1133	/* I2C1CLK clock frequency */
mbed_official	76:aeb1df146756	1134	if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
mbed_official	76:aeb1df146756	1135	{
mbed_official	76:aeb1df146756	1136	/* I2C1 Clock is HSI Osc. */
mbed_official	76:aeb1df146756	1137	RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	1138	}
mbed_official	76:aeb1df146756	1139	else
mbed_official	76:aeb1df146756	1140	{
mbed_official	76:aeb1df146756	1141	/* I2C1 Clock is System Clock */
mbed_official	76:aeb1df146756	1142	RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official	76:aeb1df146756	1143	}
mbed_official	76:aeb1df146756	1144
mbed_official	76:aeb1df146756	1145	/* USART1CLK clock frequency */
mbed_official	76:aeb1df146756	1146	if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
mbed_official	76:aeb1df146756	1147	{
mbed_official	76:aeb1df146756	1148	/* USART1 Clock is PCLK */
mbed_official	76:aeb1df146756	1149	RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
mbed_official	76:aeb1df146756	1150	}
mbed_official	76:aeb1df146756	1151	else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
mbed_official	76:aeb1df146756	1152	{
mbed_official	76:aeb1df146756	1153	/* USART1 Clock is System Clock */
mbed_official	76:aeb1df146756	1154	RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official	76:aeb1df146756	1155	}
mbed_official	76:aeb1df146756	1156	else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
mbed_official	76:aeb1df146756	1157	{
mbed_official	76:aeb1df146756	1158	/* USART1 Clock is LSE Osc. */
mbed_official	76:aeb1df146756	1159	RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
mbed_official	76:aeb1df146756	1160	}
mbed_official	76:aeb1df146756	1161	else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
mbed_official	76:aeb1df146756	1162	{
mbed_official	76:aeb1df146756	1163	/* USART1 Clock is HSI Osc. */
mbed_official	76:aeb1df146756	1164	RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	1165	}
mbed_official	76:aeb1df146756	1166
mbed_official	76:aeb1df146756	1167	/* USART2CLK clock frequency */
mbed_official	76:aeb1df146756	1168	if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
mbed_official	76:aeb1df146756	1169	{
mbed_official	76:aeb1df146756	1170	/* USART Clock is PCLK */
mbed_official	76:aeb1df146756	1171	RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
mbed_official	76:aeb1df146756	1172	}
mbed_official	76:aeb1df146756	1173	else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
mbed_official	76:aeb1df146756	1174	{
mbed_official	76:aeb1df146756	1175	/* USART Clock is System Clock */
mbed_official	76:aeb1df146756	1176	RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official	76:aeb1df146756	1177	}
mbed_official	76:aeb1df146756	1178	else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
mbed_official	76:aeb1df146756	1179	{
mbed_official	76:aeb1df146756	1180	/* USART Clock is LSE Osc. */
mbed_official	76:aeb1df146756	1181	RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
mbed_official	76:aeb1df146756	1182	}
mbed_official	76:aeb1df146756	1183	else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
mbed_official	76:aeb1df146756	1184	{
mbed_official	76:aeb1df146756	1185	/* USART Clock is HSI Osc. */
mbed_official	76:aeb1df146756	1186	RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
mbed_official	76:aeb1df146756	1187	}
mbed_official	76:aeb1df146756	1188
mbed_official	76:aeb1df146756	1189	/* USBCLK clock frequency */
mbed_official	76:aeb1df146756	1190	if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
mbed_official	76:aeb1df146756	1191	{
mbed_official	76:aeb1df146756	1192	/* USB Clock is HSI48 */
mbed_official	76:aeb1df146756	1193	RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
mbed_official	76:aeb1df146756	1194	}
mbed_official	76:aeb1df146756	1195	else
mbed_official	76:aeb1df146756	1196	{
mbed_official	76:aeb1df146756	1197	/* USB Clock is PLL clock */
mbed_official	76:aeb1df146756	1198	RCC_Clocks->USBCLK_Frequency = pllclk;
mbed_official	76:aeb1df146756	1199	}
mbed_official	76:aeb1df146756	1200	}
mbed_official	76:aeb1df146756	1201
mbed_official	76:aeb1df146756	1202	/**
mbed_official	76:aeb1df146756	1203	* @}
mbed_official	76:aeb1df146756	1204	*/
mbed_official	76:aeb1df146756	1205
mbed_official	76:aeb1df146756	1206	/** @defgroup RCC_Group3 Peripheral clocks configuration functions
mbed_official	76:aeb1df146756	1207	* @brief Peripheral clocks configuration functions
mbed_official	76:aeb1df146756	1208	*
mbed_official	76:aeb1df146756	1209	@verbatim
mbed_official	76:aeb1df146756	1210	===============================================================================
mbed_official	76:aeb1df146756	1211	#####Peripheral clocks configuration functions #####
mbed_official	76:aeb1df146756	1212	===============================================================================
mbed_official	76:aeb1df146756	1213
mbed_official	76:aeb1df146756	1214	[..] This section provide functions allowing to configure the Peripheral clocks.
mbed_official	76:aeb1df146756	1215	(#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE
mbed_official	76:aeb1df146756	1216	divided by 32).
mbed_official	76:aeb1df146756	1217	(#) After restart from Reset or wakeup from STANDBY, all peripherals are off
mbed_official	76:aeb1df146756	1218	except internal SRAM, Flash and SWD. Before to start using a peripheral you
mbed_official	76:aeb1df146756	1219	have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
mbed_official	76:aeb1df146756	1220	RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
mbed_official	76:aeb1df146756	1221	(#) To reset the peripherals configuration (to the default state after device reset)
mbed_official	76:aeb1df146756	1222	you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
mbed_official	76:aeb1df146756	1223	RCC_APB1PeriphResetCmd() functions.
mbed_official	76:aeb1df146756	1224
mbed_official	76:aeb1df146756	1225	@endverbatim
mbed_official	76:aeb1df146756	1226	* @{
mbed_official	76:aeb1df146756	1227	*/
mbed_official	76:aeb1df146756	1228
mbed_official	76:aeb1df146756	1229	/**
mbed_official	76:aeb1df146756	1230	* @brief Configures the RTC clock (RTCCLK).
mbed_official	76:aeb1df146756	1231	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	76:aeb1df146756	1232	* access is denied to this domain after reset, you have to enable write
mbed_official	76:aeb1df146756	1233	* access using PWR_BackupAccessCmd(ENABLE) function before to configure
mbed_official	76:aeb1df146756	1234	* the RTC clock source (to be done once after reset).
mbed_official	76:aeb1df146756	1235	* @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official	76:aeb1df146756	1236	* is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
mbed_official	76:aeb1df146756	1237	*
mbed_official	76:aeb1df146756	1238	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	76:aeb1df146756	1239	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1240	* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official	76:aeb1df146756	1241	* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official	76:aeb1df146756	1242	* @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
mbed_official	76:aeb1df146756	1243	*
mbed_official	76:aeb1df146756	1244	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	76:aeb1df146756	1245	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	76:aeb1df146756	1246	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	76:aeb1df146756	1247	* cannot be used in STOP and STANDBY modes.
mbed_official	76:aeb1df146756	1248	*
mbed_official	76:aeb1df146756	1249	* @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
mbed_official	76:aeb1df146756	1250	* RTC clock source).
mbed_official	76:aeb1df146756	1251	*
mbed_official	76:aeb1df146756	1252	* @retval None
mbed_official	76:aeb1df146756	1253	*/
mbed_official	76:aeb1df146756	1254	void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official	76:aeb1df146756	1255	{
mbed_official	76:aeb1df146756	1256	/* Check the parameters */
mbed_official	76:aeb1df146756	1257	assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official	76:aeb1df146756	1258
mbed_official	76:aeb1df146756	1259	/* Select the RTC clock source */
mbed_official	76:aeb1df146756	1260	RCC->BDCR \|= RCC_RTCCLKSource;
mbed_official	76:aeb1df146756	1261	}
mbed_official	76:aeb1df146756	1262
mbed_official	76:aeb1df146756	1263	/**
mbed_official	76:aeb1df146756	1264	* @brief Enables or disables the RTC clock.
mbed_official	76:aeb1df146756	1265	* @note This function must be used only after the RTC clock source was selected
mbed_official	76:aeb1df146756	1266	* using the RCC_RTCCLKConfig function.
mbed_official	76:aeb1df146756	1267	* @param NewState: new state of the RTC clock.
mbed_official	76:aeb1df146756	1268	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1269	* @retval None
mbed_official	76:aeb1df146756	1270	*/
mbed_official	76:aeb1df146756	1271	void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	1272	{
mbed_official	76:aeb1df146756	1273	/* Check the parameters */
mbed_official	76:aeb1df146756	1274	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1275
mbed_official	76:aeb1df146756	1276	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1277	{
mbed_official	76:aeb1df146756	1278	RCC->BDCR \|= RCC_BDCR_RTCEN;
mbed_official	76:aeb1df146756	1279	}
mbed_official	76:aeb1df146756	1280	else
mbed_official	76:aeb1df146756	1281	{
mbed_official	76:aeb1df146756	1282	RCC->BDCR &= ~RCC_BDCR_RTCEN;
mbed_official	76:aeb1df146756	1283	}
mbed_official	76:aeb1df146756	1284	}
mbed_official	76:aeb1df146756	1285
mbed_official	76:aeb1df146756	1286	/**
mbed_official	76:aeb1df146756	1287	* @brief Forces or releases the Backup domain reset.
mbed_official	76:aeb1df146756	1288	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	76:aeb1df146756	1289	* and the RTC clock source selection in RCC_BDCR register.
mbed_official	76:aeb1df146756	1290	* @param NewState: new state of the Backup domain reset.
mbed_official	76:aeb1df146756	1291	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1292	* @retval None
mbed_official	76:aeb1df146756	1293	*/
mbed_official	76:aeb1df146756	1294	void RCC_BackupResetCmd(FunctionalState NewState)
mbed_official	76:aeb1df146756	1295	{
mbed_official	76:aeb1df146756	1296	/* Check the parameters */
mbed_official	76:aeb1df146756	1297	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1298
mbed_official	76:aeb1df146756	1299	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1300	{
mbed_official	76:aeb1df146756	1301	RCC->BDCR \|= RCC_BDCR_BDRST;
mbed_official	76:aeb1df146756	1302	}
mbed_official	76:aeb1df146756	1303	else
mbed_official	76:aeb1df146756	1304	{
mbed_official	76:aeb1df146756	1305	RCC->BDCR &= ~RCC_BDCR_BDRST;
mbed_official	76:aeb1df146756	1306	}
mbed_official	76:aeb1df146756	1307	}
mbed_official	76:aeb1df146756	1308
mbed_official	76:aeb1df146756	1309	/**
mbed_official	76:aeb1df146756	1310	* @brief Enables or disables the AHB peripheral clock.
mbed_official	76:aeb1df146756	1311	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1312	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1313	* using it.
mbed_official	76:aeb1df146756	1314	* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official	76:aeb1df146756	1315	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1316	* @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official	76:aeb1df146756	1317	* @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official	76:aeb1df146756	1318	* @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official	76:aeb1df146756	1319	* @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official	76:aeb1df146756	1320	* @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1321	* @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official	76:aeb1df146756	1322	* @arg RCC_AHBPeriph_TS: TS clock
mbed_official	76:aeb1df146756	1323	* @arg RCC_AHBPeriph_CRC: CRC clock
mbed_official	76:aeb1df146756	1324	* @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
mbed_official	76:aeb1df146756	1325	* @arg RCC_AHBPeriph_SRAM: SRAM clock
mbed_official	76:aeb1df146756	1326	* @arg RCC_AHBPeriph_DMA1: DMA1 clock
mbed_official	76:aeb1df146756	1327	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1328	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1329	* @retval None
mbed_official	76:aeb1df146756	1330	*/
mbed_official	76:aeb1df146756	1331	void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1332	{
mbed_official	76:aeb1df146756	1333	/* Check the parameters */
mbed_official	76:aeb1df146756	1334	assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official	76:aeb1df146756	1335	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1336
mbed_official	76:aeb1df146756	1337	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1338	{
mbed_official	76:aeb1df146756	1339	RCC->AHBENR \|= RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1340	}
mbed_official	76:aeb1df146756	1341	else
mbed_official	76:aeb1df146756	1342	{
mbed_official	76:aeb1df146756	1343	RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1344	}
mbed_official	76:aeb1df146756	1345	}
mbed_official	76:aeb1df146756	1346
mbed_official	76:aeb1df146756	1347	/**
mbed_official	76:aeb1df146756	1348	* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official	76:aeb1df146756	1349	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1350	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1351	* using it.
mbed_official	76:aeb1df146756	1352	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1353	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1354	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official	76:aeb1df146756	1355	* @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official	76:aeb1df146756	1356	* @arg RCC_APB2Periph_TIM1: TIM1 clock
mbed_official	76:aeb1df146756	1357	* @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official	76:aeb1df146756	1358	* @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official	76:aeb1df146756	1359	* @arg RCC_APB2Periph_TIM15: TIM15 clock
mbed_official	76:aeb1df146756	1360	* @arg RCC_APB2Periph_TIM16: TIM16 clock
mbed_official	76:aeb1df146756	1361	* @arg RCC_APB2Periph_TIM17: TIM17 clock
mbed_official	76:aeb1df146756	1362	* @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
mbed_official	76:aeb1df146756	1363	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1364	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1365	* @retval None
mbed_official	76:aeb1df146756	1366	*/
mbed_official	76:aeb1df146756	1367	void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1368	{
mbed_official	76:aeb1df146756	1369	/* Check the parameters */
mbed_official	76:aeb1df146756	1370	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	76:aeb1df146756	1371	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1372
mbed_official	76:aeb1df146756	1373	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1374	{
mbed_official	76:aeb1df146756	1375	RCC->APB2ENR \|= RCC_APB2Periph;
mbed_official	76:aeb1df146756	1376	}
mbed_official	76:aeb1df146756	1377	else
mbed_official	76:aeb1df146756	1378	{
mbed_official	76:aeb1df146756	1379	RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official	76:aeb1df146756	1380	}
mbed_official	76:aeb1df146756	1381	}
mbed_official	76:aeb1df146756	1382
mbed_official	76:aeb1df146756	1383	/**
mbed_official	76:aeb1df146756	1384	* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official	76:aeb1df146756	1385	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	76:aeb1df146756	1386	* is disabled and the application software has to enable this clock before
mbed_official	76:aeb1df146756	1387	* using it.
mbed_official	76:aeb1df146756	1388	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official	76:aeb1df146756	1389	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1390	* @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
mbed_official	76:aeb1df146756	1391	* @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official	76:aeb1df146756	1392	* @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official	76:aeb1df146756	1393	* @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1394	* @arg RCC_APB1Periph_TIM14: TIM14 clock
mbed_official	76:aeb1df146756	1395	* @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official	76:aeb1df146756	1396	* @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official	76:aeb1df146756	1397	* @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official	76:aeb1df146756	1398	* @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1399	* @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1400	* @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official	76:aeb1df146756	1401	* @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official	76:aeb1df146756	1402	* @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices
mbed_official	76:aeb1df146756	1403	* @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices
mbed_official	76:aeb1df146756	1404	* @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices
mbed_official	76:aeb1df146756	1405	* @arg RCC_APB1Periph_PWR: PWR clock
mbed_official	76:aeb1df146756	1406	* @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official	76:aeb1df146756	1407	* @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices
mbed_official	76:aeb1df146756	1408	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1409	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1410	* @retval None
mbed_official	76:aeb1df146756	1411	*/
mbed_official	76:aeb1df146756	1412	void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1413	{
mbed_official	76:aeb1df146756	1414	/* Check the parameters */
mbed_official	76:aeb1df146756	1415	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	76:aeb1df146756	1416	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1417
mbed_official	76:aeb1df146756	1418	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1419	{
mbed_official	76:aeb1df146756	1420	RCC->APB1ENR \|= RCC_APB1Periph;
mbed_official	76:aeb1df146756	1421	}
mbed_official	76:aeb1df146756	1422	else
mbed_official	76:aeb1df146756	1423	{
mbed_official	76:aeb1df146756	1424	RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official	76:aeb1df146756	1425	}
mbed_official	76:aeb1df146756	1426	}
mbed_official	76:aeb1df146756	1427
mbed_official	76:aeb1df146756	1428	/**
mbed_official	76:aeb1df146756	1429	* @brief Forces or releases AHB peripheral reset.
mbed_official	76:aeb1df146756	1430	* @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official	76:aeb1df146756	1431	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1432	* @arg RCC_AHBPeriph_GPIOA: GPIOA clock
mbed_official	76:aeb1df146756	1433	* @arg RCC_AHBPeriph_GPIOB: GPIOB clock
mbed_official	76:aeb1df146756	1434	* @arg RCC_AHBPeriph_GPIOC: GPIOC clock
mbed_official	76:aeb1df146756	1435	* @arg RCC_AHBPeriph_GPIOD: GPIOD clock
mbed_official	76:aeb1df146756	1436	* @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1437	* @arg RCC_AHBPeriph_GPIOF: GPIOF clock
mbed_official	76:aeb1df146756	1438	* @arg RCC_AHBPeriph_TS: TS clock
mbed_official	76:aeb1df146756	1439	* @param NewState: new state of the specified peripheral reset.
mbed_official	76:aeb1df146756	1440	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1441	* @retval None
mbed_official	76:aeb1df146756	1442	*/
mbed_official	76:aeb1df146756	1443	void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1444	{
mbed_official	76:aeb1df146756	1445	/* Check the parameters */
mbed_official	76:aeb1df146756	1446	assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
mbed_official	76:aeb1df146756	1447	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1448
mbed_official	76:aeb1df146756	1449	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1450	{
mbed_official	76:aeb1df146756	1451	RCC->AHBRSTR \|= RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1452	}
mbed_official	76:aeb1df146756	1453	else
mbed_official	76:aeb1df146756	1454	{
mbed_official	76:aeb1df146756	1455	RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official	76:aeb1df146756	1456	}
mbed_official	76:aeb1df146756	1457	}
mbed_official	76:aeb1df146756	1458
mbed_official	76:aeb1df146756	1459	/**
mbed_official	76:aeb1df146756	1460	* @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official	76:aeb1df146756	1461	* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official	76:aeb1df146756	1462	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1463	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
mbed_official	76:aeb1df146756	1464	* @arg RCC_APB2Periph_ADC1: ADC1 clock
mbed_official	76:aeb1df146756	1465	* @arg RCC_APB2Periph_TIM1: TIM1 clock
mbed_official	76:aeb1df146756	1466	* @arg RCC_APB2Periph_SPI1: SPI1 clock
mbed_official	76:aeb1df146756	1467	* @arg RCC_APB2Periph_USART1: USART1 clock
mbed_official	76:aeb1df146756	1468	* @arg RCC_APB2Periph_TIM15: TIM15 clock
mbed_official	76:aeb1df146756	1469	* @arg RCC_APB2Periph_TIM16: TIM16 clock
mbed_official	76:aeb1df146756	1470	* @arg RCC_APB2Periph_TIM17: TIM17 clock
mbed_official	76:aeb1df146756	1471	* @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
mbed_official	76:aeb1df146756	1472	* @param NewState: new state of the specified peripheral reset.
mbed_official	76:aeb1df146756	1473	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1474	* @retval None
mbed_official	76:aeb1df146756	1475	*/
mbed_official	76:aeb1df146756	1476	void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1477	{
mbed_official	76:aeb1df146756	1478	/* Check the parameters */
mbed_official	76:aeb1df146756	1479	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official	76:aeb1df146756	1480	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1481
mbed_official	76:aeb1df146756	1482	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1483	{
mbed_official	76:aeb1df146756	1484	RCC->APB2RSTR \|= RCC_APB2Periph;
mbed_official	76:aeb1df146756	1485	}
mbed_official	76:aeb1df146756	1486	else
mbed_official	76:aeb1df146756	1487	{
mbed_official	76:aeb1df146756	1488	RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official	76:aeb1df146756	1489	}
mbed_official	76:aeb1df146756	1490	}
mbed_official	76:aeb1df146756	1491
mbed_official	76:aeb1df146756	1492	/**
mbed_official	76:aeb1df146756	1493	* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official	76:aeb1df146756	1494	* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official	76:aeb1df146756	1495	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1496	* @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
mbed_official	76:aeb1df146756	1497	* @arg RCC_APB1Periph_TIM3: TIM3 clock
mbed_official	76:aeb1df146756	1498	* @arg RCC_APB1Periph_TIM6: TIM6 clock
mbed_official	76:aeb1df146756	1499	* @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1500	* @arg RCC_APB1Periph_TIM14: TIM14 clock
mbed_official	76:aeb1df146756	1501	* @arg RCC_APB1Periph_WWDG: WWDG clock
mbed_official	76:aeb1df146756	1502	* @arg RCC_APB1Periph_SPI2: SPI2 clock
mbed_official	76:aeb1df146756	1503	* @arg RCC_APB1Periph_USART2: USART2 clock
mbed_official	76:aeb1df146756	1504	* @arg RCC_APB1Periph_USART3: USART3 clock
mbed_official	76:aeb1df146756	1505	* @arg RCC_APB1Periph_USART4: USART4 clock
mbed_official	76:aeb1df146756	1506	* @arg RCC_APB1Periph_I2C1: I2C1 clock
mbed_official	76:aeb1df146756	1507	* @arg RCC_APB1Periph_I2C2: I2C2 clock
mbed_official	76:aeb1df146756	1508	* @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1509	* @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1510	* @arg RCC_APB1Periph_CRS: CRS clock, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1511	* @arg RCC_APB1Periph_PWR: PWR clock
mbed_official	76:aeb1df146756	1512	* @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official	76:aeb1df146756	1513	* @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051 and STM32F072 devices
mbed_official	76:aeb1df146756	1514	* @param NewState: new state of the specified peripheral clock.
mbed_official	76:aeb1df146756	1515	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1516	* @retval None
mbed_official	76:aeb1df146756	1517	*/
mbed_official	76:aeb1df146756	1518	void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official	76:aeb1df146756	1519	{
mbed_official	76:aeb1df146756	1520	/* Check the parameters */
mbed_official	76:aeb1df146756	1521	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official	76:aeb1df146756	1522	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1523
mbed_official	76:aeb1df146756	1524	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1525	{
mbed_official	76:aeb1df146756	1526	RCC->APB1RSTR \|= RCC_APB1Periph;
mbed_official	76:aeb1df146756	1527	}
mbed_official	76:aeb1df146756	1528	else
mbed_official	76:aeb1df146756	1529	{
mbed_official	76:aeb1df146756	1530	RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official	76:aeb1df146756	1531	}
mbed_official	76:aeb1df146756	1532	}
mbed_official	76:aeb1df146756	1533
mbed_official	76:aeb1df146756	1534	/**
mbed_official	76:aeb1df146756	1535	* @}
mbed_official	76:aeb1df146756	1536	*/
mbed_official	76:aeb1df146756	1537
mbed_official	76:aeb1df146756	1538	/** @defgroup RCC_Group4 Interrupts and flags management functions
mbed_official	76:aeb1df146756	1539	* @brief Interrupts and flags management functions
mbed_official	76:aeb1df146756	1540	*
mbed_official	76:aeb1df146756	1541	@verbatim
mbed_official	76:aeb1df146756	1542	===============================================================================
mbed_official	76:aeb1df146756	1543	##### Interrupts and flags management functions #####
mbed_official	76:aeb1df146756	1544	===============================================================================
mbed_official	76:aeb1df146756	1545	@endverbatim
mbed_official	76:aeb1df146756	1546	* @{
mbed_official	76:aeb1df146756	1547	*/
mbed_official	76:aeb1df146756	1548
mbed_official	76:aeb1df146756	1549	/**
mbed_official	76:aeb1df146756	1550	* @brief Enables or disables the specified RCC interrupts.
mbed_official	76:aeb1df146756	1551	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	76:aeb1df146756	1552	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	76:aeb1df146756	1553	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	76:aeb1df146756	1554	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	76:aeb1df146756	1555	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	76:aeb1df146756	1556	* pending bit is cleared.
mbed_official	76:aeb1df146756	1557	* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official	76:aeb1df146756	1558	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1559	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1560	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1561	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1562	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1563	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1564	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official	76:aeb1df146756	1565	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1566	* @param NewState: new state of the specified RCC interrupts.
mbed_official	76:aeb1df146756	1567	* This parameter can be: ENABLE or DISABLE.
mbed_official	76:aeb1df146756	1568	* @retval None
mbed_official	76:aeb1df146756	1569	*/
mbed_official	76:aeb1df146756	1570	void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official	76:aeb1df146756	1571	{
mbed_official	76:aeb1df146756	1572	/* Check the parameters */
mbed_official	76:aeb1df146756	1573	assert_param(IS_RCC_IT(RCC_IT));
mbed_official	76:aeb1df146756	1574	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	76:aeb1df146756	1575
mbed_official	76:aeb1df146756	1576	if (NewState != DISABLE)
mbed_official	76:aeb1df146756	1577	{
mbed_official	76:aeb1df146756	1578	/* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
mbed_official	76:aeb1df146756	1579	(__IO uint8_t ) CIR_BYTE1_ADDRESS \|= RCC_IT;
mbed_official	76:aeb1df146756	1580	}
mbed_official	76:aeb1df146756	1581	else
mbed_official	76:aeb1df146756	1582	{
mbed_official	76:aeb1df146756	1583	/* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
mbed_official	76:aeb1df146756	1584	(__IO uint8_t ) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official	76:aeb1df146756	1585	}
mbed_official	76:aeb1df146756	1586	}
mbed_official	76:aeb1df146756	1587
mbed_official	76:aeb1df146756	1588	/**
mbed_official	76:aeb1df146756	1589	* @brief Checks whether the specified RCC flag is set or not.
mbed_official	76:aeb1df146756	1590	* @param RCC_FLAG: specifies the flag to check.
mbed_official	76:aeb1df146756	1591	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1592	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	76:aeb1df146756	1593	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	76:aeb1df146756	1594	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	76:aeb1df146756	1595	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	76:aeb1df146756	1596	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	76:aeb1df146756	1597	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official	76:aeb1df146756	1598	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	76:aeb1df146756	1599	* @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset
mbed_official	76:aeb1df146756	1600	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	76:aeb1df146756	1601	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	76:aeb1df146756	1602	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	76:aeb1df146756	1603	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	76:aeb1df146756	1604	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	76:aeb1df146756	1605	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
mbed_official	76:aeb1df146756	1606	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1607	* @retval The new state of RCC_FLAG (SET or RESET).
mbed_official	76:aeb1df146756	1608	*/
mbed_official	76:aeb1df146756	1609	FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official	76:aeb1df146756	1610	{
mbed_official	76:aeb1df146756	1611	uint32_t tmp = 0;
mbed_official	76:aeb1df146756	1612	uint32_t statusreg = 0;
mbed_official	76:aeb1df146756	1613	FlagStatus bitstatus = RESET;
mbed_official	76:aeb1df146756	1614
mbed_official	76:aeb1df146756	1615	/* Check the parameters */
mbed_official	76:aeb1df146756	1616	assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official	76:aeb1df146756	1617
mbed_official	76:aeb1df146756	1618	/* Get the RCC register index */
mbed_official	76:aeb1df146756	1619	tmp = RCC_FLAG >> 5;
mbed_official	76:aeb1df146756	1620
mbed_official	76:aeb1df146756	1621	if (tmp == 0) /* The flag to check is in CR register */
mbed_official	76:aeb1df146756	1622	{
mbed_official	76:aeb1df146756	1623	statusreg = RCC->CR;
mbed_official	76:aeb1df146756	1624	}
mbed_official	76:aeb1df146756	1625	else if (tmp == 1) /* The flag to check is in BDCR register */
mbed_official	76:aeb1df146756	1626	{
mbed_official	76:aeb1df146756	1627	statusreg = RCC->BDCR;
mbed_official	76:aeb1df146756	1628	}
mbed_official	76:aeb1df146756	1629	else if (tmp == 2) /* The flag to check is in CSR register */
mbed_official	76:aeb1df146756	1630	{
mbed_official	76:aeb1df146756	1631	statusreg = RCC->CSR;
mbed_official	76:aeb1df146756	1632	}
mbed_official	76:aeb1df146756	1633	else /* The flag to check is in CR2 register */
mbed_official	76:aeb1df146756	1634	{
mbed_official	76:aeb1df146756	1635	statusreg = RCC->CR2;
mbed_official	76:aeb1df146756	1636	}
mbed_official	76:aeb1df146756	1637
mbed_official	76:aeb1df146756	1638	/* Get the flag position */
mbed_official	76:aeb1df146756	1639	tmp = RCC_FLAG & FLAG_MASK;
mbed_official	76:aeb1df146756	1640
mbed_official	76:aeb1df146756	1641	if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official	76:aeb1df146756	1642	{
mbed_official	76:aeb1df146756	1643	bitstatus = SET;
mbed_official	76:aeb1df146756	1644	}
mbed_official	76:aeb1df146756	1645	else
mbed_official	76:aeb1df146756	1646	{
mbed_official	76:aeb1df146756	1647	bitstatus = RESET;
mbed_official	76:aeb1df146756	1648	}
mbed_official	76:aeb1df146756	1649	/* Return the flag status */
mbed_official	76:aeb1df146756	1650	return bitstatus;
mbed_official	76:aeb1df146756	1651	}
mbed_official	76:aeb1df146756	1652
mbed_official	76:aeb1df146756	1653	/**
mbed_official	76:aeb1df146756	1654	* @brief Clears the RCC reset flags.
mbed_official	76:aeb1df146756	1655	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
mbed_official	76:aeb1df146756	1656	* RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
mbed_official	76:aeb1df146756	1657	* RCC_FLAG_LPWRRST.
mbed_official	76:aeb1df146756	1658	* @param None
mbed_official	76:aeb1df146756	1659	* @retval None
mbed_official	76:aeb1df146756	1660	*/
mbed_official	76:aeb1df146756	1661	void RCC_ClearFlag(void)
mbed_official	76:aeb1df146756	1662	{
mbed_official	76:aeb1df146756	1663	/* Set RMVF bit to clear the reset flags */
mbed_official	76:aeb1df146756	1664	RCC->CSR \|= RCC_CSR_RMVF;
mbed_official	76:aeb1df146756	1665	}
mbed_official	76:aeb1df146756	1666
mbed_official	76:aeb1df146756	1667	/**
mbed_official	76:aeb1df146756	1668	* @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official	76:aeb1df146756	1669	* @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official	76:aeb1df146756	1670	* This parameter can be one of the following values:
mbed_official	76:aeb1df146756	1671	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1672	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1673	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1674	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1675	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1676	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official	76:aeb1df146756	1677	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1678	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	76:aeb1df146756	1679	* @retval The new state of RCC_IT (SET or RESET).
mbed_official	76:aeb1df146756	1680	*/
mbed_official	76:aeb1df146756	1681	ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official	76:aeb1df146756	1682	{
mbed_official	76:aeb1df146756	1683	ITStatus bitstatus = RESET;
mbed_official	76:aeb1df146756	1684
mbed_official	76:aeb1df146756	1685	/* Check the parameters */
mbed_official	76:aeb1df146756	1686	assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official	76:aeb1df146756	1687
mbed_official	76:aeb1df146756	1688	/* Check the status of the specified RCC interrupt */
mbed_official	76:aeb1df146756	1689	if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official	76:aeb1df146756	1690	{
mbed_official	76:aeb1df146756	1691	bitstatus = SET;
mbed_official	76:aeb1df146756	1692	}
mbed_official	76:aeb1df146756	1693	else
mbed_official	76:aeb1df146756	1694	{
mbed_official	76:aeb1df146756	1695	bitstatus = RESET;
mbed_official	76:aeb1df146756	1696	}
mbed_official	76:aeb1df146756	1697	/* Return the RCC_IT status */
mbed_official	76:aeb1df146756	1698	return bitstatus;
mbed_official	76:aeb1df146756	1699	}
mbed_official	76:aeb1df146756	1700
mbed_official	76:aeb1df146756	1701	/**
mbed_official	76:aeb1df146756	1702	* @brief Clears the RCC's interrupt pending bits.
mbed_official	76:aeb1df146756	1703	* @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official	76:aeb1df146756	1704	* This parameter can be any combination of the following values:
mbed_official	76:aeb1df146756	1705	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	76:aeb1df146756	1706	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	76:aeb1df146756	1707	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	76:aeb1df146756	1708	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	76:aeb1df146756	1709	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	76:aeb1df146756	1710	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
mbed_official	76:aeb1df146756	1711	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
mbed_official	76:aeb1df146756	1712	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	76:aeb1df146756	1713	* @retval None
mbed_official	76:aeb1df146756	1714	*/
mbed_official	76:aeb1df146756	1715	void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official	76:aeb1df146756	1716	{
mbed_official	76:aeb1df146756	1717	/* Check the parameters */
mbed_official	76:aeb1df146756	1718	assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official	76:aeb1df146756	1719
mbed_official	76:aeb1df146756	1720	/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official	76:aeb1df146756	1721	pending bits */
mbed_official	76:aeb1df146756	1722	(__IO uint8_t ) CIR_BYTE2_ADDRESS = RCC_IT;
mbed_official	76:aeb1df146756	1723	}
mbed_official	76:aeb1df146756	1724
mbed_official	76:aeb1df146756	1725	/**
mbed_official	76:aeb1df146756	1726	* @}
mbed_official	76:aeb1df146756	1727	*/
mbed_official	76:aeb1df146756	1728
mbed_official	76:aeb1df146756	1729	/**
mbed_official	76:aeb1df146756	1730	* @}
mbed_official	76:aeb1df146756	1731	*/
mbed_official	76:aeb1df146756	1732
mbed_official	76:aeb1df146756	1733	/**
mbed_official	76:aeb1df146756	1734	* @}
mbed_official	76:aeb1df146756	1735	*/
mbed_official	76:aeb1df146756	1736
mbed_official	76:aeb1df146756	1737	/**
mbed_official	76:aeb1df146756	1738	* @}
mbed_official	76:aeb1df146756	1739	*/
mbed_official	76:aeb1df146756	1740
mbed_official	76:aeb1df146756	1741	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2014
Imports:	301
Forks:	0
Commits:	115
Dependents:	0
Dependencies:	0
Followers:	15
Issues:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_rcc.c@76:aeb1df146756, 2014-01-27 (annotated)

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