Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

  • UART2 : PA_3 rx, PA_2 tx
  • UART3 : PC_7 rx, PC_6 tx
  • I2C2 : PB_3 SDA, PB_10 SCL
  • I2C3 : PB_4 SDA, PA_8 SCL

targets/hal/TARGET_Freescale/TARGET_K20D5M/us_ticker.c@68:41613245dfd7, 2013-12-26 (annotated)

Committer:
mbed_official
Date:
Thu Dec 26 13:00:06 2013 +0000
Revision:
68:41613245dfd7
Child:
73:299c67215126
Synchronized with git revision fba199a9c4445231b0f38e1e113c118182635546



Full URL: https://github.com/mbedmicro/mbed/commit/fba199a9c4445231b0f38e1e113c118182635546/



target K20D5M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 68:41613245dfd7 1 /* mbed Microcontroller Library
mbed_official 68:41613245dfd7 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 68:41613245dfd7 3 *
mbed_official 68:41613245dfd7 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 68:41613245dfd7 5 * you may not use this file except in compliance with the License.
mbed_official 68:41613245dfd7 6 * You may obtain a copy of the License at
mbed_official 68:41613245dfd7 7 *
mbed_official 68:41613245dfd7 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 68:41613245dfd7 9 *
mbed_official 68:41613245dfd7 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 68:41613245dfd7 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 68:41613245dfd7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 68:41613245dfd7 13 * See the License for the specific language governing permissions and
mbed_official 68:41613245dfd7 14 * limitations under the License.
mbed_official 68:41613245dfd7 15 */
mbed_official 68:41613245dfd7 16 #include <stddef.h>
mbed_official 68:41613245dfd7 17 #include "us_ticker_api.h"
mbed_official 68:41613245dfd7 18 #include "PeripheralNames.h"
mbed_official 68:41613245dfd7 19
mbed_official 68:41613245dfd7 20 static void pit_init(void);
mbed_official 68:41613245dfd7 21 static void lptmr_init(void);
mbed_official 68:41613245dfd7 22
mbed_official 68:41613245dfd7 23 static int us_ticker_inited = 0;
mbed_official 68:41613245dfd7 24
mbed_official 68:41613245dfd7 25 void us_ticker_init(void) {
mbed_official 68:41613245dfd7 26 if (us_ticker_inited)
mbed_official 68:41613245dfd7 27 return;
mbed_official 68:41613245dfd7 28 us_ticker_inited = 1;
mbed_official 68:41613245dfd7 29
mbed_official 68:41613245dfd7 30 pit_init();
mbed_official 68:41613245dfd7 31 lptmr_init();
mbed_official 68:41613245dfd7 32 }
mbed_official 68:41613245dfd7 33
mbed_official 68:41613245dfd7 34 static uint32_t pit_us_ticker_counter = 0;
mbed_official 68:41613245dfd7 35
mbed_official 68:41613245dfd7 36 void pit0_isr(void) {
mbed_official 68:41613245dfd7 37 pit_us_ticker_counter++;
mbed_official 68:41613245dfd7 38 PIT->CHANNEL[0].LDVAL = 48; // 1us
mbed_official 68:41613245dfd7 39 PIT->CHANNEL[0].TFLG = 1;
mbed_official 68:41613245dfd7 40 }
mbed_official 68:41613245dfd7 41
mbed_official 68:41613245dfd7 42 /******************************************************************************
mbed_official 68:41613245dfd7 43 * Timer for us timing.
mbed_official 68:41613245dfd7 44 ******************************************************************************/
mbed_official 68:41613245dfd7 45 static void pit_init(void) {
mbed_official 68:41613245dfd7 46 SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
mbed_official 68:41613245dfd7 47 PIT->MCR = 0; // Enable PIT
mbed_official 68:41613245dfd7 48
mbed_official 68:41613245dfd7 49 PIT->CHANNEL[0].LDVAL = 48; // 1us
mbed_official 68:41613245dfd7 50 PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TIE_MASK;
mbed_official 68:41613245dfd7 51 PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
mbed_official 68:41613245dfd7 52
mbed_official 68:41613245dfd7 53 NVIC_SetVector(PIT0_IRQn, (uint32_t)pit0_isr);
mbed_official 68:41613245dfd7 54 NVIC_EnableIRQ(PIT0_IRQn);
mbed_official 68:41613245dfd7 55 }
mbed_official 68:41613245dfd7 56
mbed_official 68:41613245dfd7 57 uint32_t us_ticker_read() {
mbed_official 68:41613245dfd7 58 if (!us_ticker_inited)
mbed_official 68:41613245dfd7 59 us_ticker_init();
mbed_official 68:41613245dfd7 60
mbed_official 68:41613245dfd7 61 return pit_us_ticker_counter;
mbed_official 68:41613245dfd7 62 }
mbed_official 68:41613245dfd7 63
mbed_official 68:41613245dfd7 64 /******************************************************************************
mbed_official 68:41613245dfd7 65 * Timer Event
mbed_official 68:41613245dfd7 66 *
mbed_official 68:41613245dfd7 67 * It schedules interrupts at given (32bit)us interval of time.
mbed_official 68:41613245dfd7 68 * It is implemented used the 16bit Low Power Timer that remains powered in all
mbed_official 68:41613245dfd7 69 * power modes.
mbed_official 68:41613245dfd7 70 ******************************************************************************/
mbed_official 68:41613245dfd7 71 static void lptmr_isr(void);
mbed_official 68:41613245dfd7 72
mbed_official 68:41613245dfd7 73 static void lptmr_init(void) {
mbed_official 68:41613245dfd7 74 /* Clock the timer */
mbed_official 68:41613245dfd7 75 SIM->SCGC5 |= SIM_SCGC5_LPTIMER_MASK;
mbed_official 68:41613245dfd7 76
mbed_official 68:41613245dfd7 77 /* Reset */
mbed_official 68:41613245dfd7 78 LPTMR0->CSR = 0;
mbed_official 68:41613245dfd7 79
mbed_official 68:41613245dfd7 80 /* Set interrupt handler */
mbed_official 68:41613245dfd7 81 NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
mbed_official 68:41613245dfd7 82 NVIC_EnableIRQ(LPTimer_IRQn);
mbed_official 68:41613245dfd7 83
mbed_official 68:41613245dfd7 84 /* Clock at (1)MHz -> (1)tick/us */
mbed_official 68:41613245dfd7 85 OSC0->CR |= OSC_CR_ERCLKEN_MASK;
mbed_official 68:41613245dfd7 86 LPTMR0->PSR = 0;
mbed_official 68:41613245dfd7 87 LPTMR0->PSR |= LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
mbed_official 68:41613245dfd7 88 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
mbed_official 68:41613245dfd7 89 }
mbed_official 68:41613245dfd7 90
mbed_official 68:41613245dfd7 91 void us_ticker_disable_interrupt(void) {
mbed_official 68:41613245dfd7 92 LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
mbed_official 68:41613245dfd7 93 }
mbed_official 68:41613245dfd7 94
mbed_official 68:41613245dfd7 95 void us_ticker_clear_interrupt(void) {
mbed_official 68:41613245dfd7 96 // we already clear interrupt in lptmr_isr
mbed_official 68:41613245dfd7 97 }
mbed_official 68:41613245dfd7 98
mbed_official 68:41613245dfd7 99 static uint32_t us_ticker_int_counter = 0;
mbed_official 68:41613245dfd7 100 static uint16_t us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 101
mbed_official 68:41613245dfd7 102 static void lptmr_set(unsigned short count) {
mbed_official 68:41613245dfd7 103 /* Reset */
mbed_official 68:41613245dfd7 104 LPTMR0->CSR = 0;
mbed_official 68:41613245dfd7 105
mbed_official 68:41613245dfd7 106 /* Set the compare register */
mbed_official 68:41613245dfd7 107 LPTMR0->CMR = count;
mbed_official 68:41613245dfd7 108
mbed_official 68:41613245dfd7 109 /* Enable interrupt */
mbed_official 68:41613245dfd7 110 LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
mbed_official 68:41613245dfd7 111
mbed_official 68:41613245dfd7 112 /* Start the timer */
mbed_official 68:41613245dfd7 113 LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
mbed_official 68:41613245dfd7 114 }
mbed_official 68:41613245dfd7 115
mbed_official 68:41613245dfd7 116 static void lptmr_isr(void) {
mbed_official 68:41613245dfd7 117 // write 1 to TCF to clear the LPT timer compare flag
mbed_official 68:41613245dfd7 118 LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
mbed_official 68:41613245dfd7 119
mbed_official 68:41613245dfd7 120 if (us_ticker_int_counter > 0) {
mbed_official 68:41613245dfd7 121 lptmr_set(0xFFFF);
mbed_official 68:41613245dfd7 122 us_ticker_int_counter--;
mbed_official 68:41613245dfd7 123
mbed_official 68:41613245dfd7 124 } else {
mbed_official 68:41613245dfd7 125 if (us_ticker_int_remainder > 0) {
mbed_official 68:41613245dfd7 126 lptmr_set(us_ticker_int_remainder);
mbed_official 68:41613245dfd7 127 us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 128
mbed_official 68:41613245dfd7 129 } else {
mbed_official 68:41613245dfd7 130 // This function is going to disable the interrupts if there are
mbed_official 68:41613245dfd7 131 // no other events in the queue
mbed_official 68:41613245dfd7 132 us_ticker_irq_handler();
mbed_official 68:41613245dfd7 133 }
mbed_official 68:41613245dfd7 134 }
mbed_official 68:41613245dfd7 135 }
mbed_official 68:41613245dfd7 136
mbed_official 68:41613245dfd7 137 void us_ticker_set_interrupt(unsigned int timestamp) {
mbed_official 68:41613245dfd7 138 int delta = (int)(timestamp - us_ticker_read());
mbed_official 68:41613245dfd7 139 if (delta <= 0) {
mbed_official 68:41613245dfd7 140 // This event was in the past:
mbed_official 68:41613245dfd7 141 us_ticker_irq_handler();
mbed_official 68:41613245dfd7 142 return;
mbed_official 68:41613245dfd7 143 }
mbed_official 68:41613245dfd7 144
mbed_official 68:41613245dfd7 145 us_ticker_int_counter = (uint32_t)(delta >> 16);
mbed_official 68:41613245dfd7 146 us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
mbed_official 68:41613245dfd7 147 if (us_ticker_int_counter > 0) {
mbed_official 68:41613245dfd7 148 lptmr_set(0xFFFF);
mbed_official 68:41613245dfd7 149 us_ticker_int_counter--;
mbed_official 68:41613245dfd7 150 } else {
mbed_official 68:41613245dfd7 151 lptmr_set(us_ticker_int_remainder);
mbed_official 68:41613245dfd7 152 us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 153 }
mbed_official 68:41613245dfd7 154 }