Peter Drescher / ST_L152_32MHZ

Lib to change the clock speed of the ST Nucleo L152RE board to 32 MHz.

The ST Nucleo L152 board is running on 16 MHz out of the box. To speed up the cpu to the maximum 32MHz speed we have to change the clock setting. Simply add the lib and : 

         #include "ST_L152_32MHZ.h"
        L152_init32 myinit(0);   // use the internal oscillator

in front of your program. This should be the first line in main to ensure the frequency is changed before other objects are initialised.

This frequency is generated out of the internal RC oscillator. The frequency is not so stable like a crystal. The PLL is switched to 96MHz to enable the use of the USB interface.

If you need a more precise timing source, you have to add a external crystal.

/media/uploads/dreschpe/oszillator.jpg

You need : X3 8MHz crystal , C33 and C34 18pF 0603 , R35 and R37 have to be short with a small piece of wire.

         #include "ST_L152_32MHZ.h"
        L152_init32 myinit(1);   // use external crystal oscillator

ST_L152_32MHZ.cpp@1:bdeac50afe1a, 2014-03-11 (annotated)

Committer:
dreschpe
Date:
Tue Mar 11 21:03:03 2014 +0000
Revision:
1:bdeac50afe1a
Parent:
0:84e23a19e37d
Child:
2:9e2ba1d93567
change result type to enum

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 1:bdeac50afe1a 1 /* mbed library for the ST NUCLEO board L152RE
dreschpe 1:bdeac50afe1a 2 * to change the CPU clock to 32 MHz
dreschpe 1:bdeac50afe1a 3 * A pll clock of 96 MHz is used to enable USB
dreschpe 1:bdeac50afe1a 4 *
dreschpe 1:bdeac50afe1a 5 * Copyright (c) 2014 Peter Drescher - DC2PD
dreschpe 1:bdeac50afe1a 6 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 1:bdeac50afe1a 7 *
dreschpe 1:bdeac50afe1a 8 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
dreschpe 1:bdeac50afe1a 9 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
dreschpe 1:bdeac50afe1a 10 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
dreschpe 1:bdeac50afe1a 11 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
dreschpe 1:bdeac50afe1a 12 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
dreschpe 1:bdeac50afe1a 13 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
dreschpe 1:bdeac50afe1a 14 * THE SOFTWARE.
dreschpe 1:bdeac50afe1a 15 */
dreschpe 1:bdeac50afe1a 16
dreschpe 0:84e23a19e37d 17 #include "stm32l1xx.h"
dreschpe 0:84e23a19e37d 18 #include "stm32l1xx_flash.h"
dreschpe 0:84e23a19e37d 19 #include "stm32l1xx_rcc.h"
dreschpe 0:84e23a19e37d 20 #include "ST_L152_32MHZ.h"
dreschpe 0:84e23a19e37d 21
dreschpe 1:bdeac50afe1a 22 // only the constructor
dreschpe 0:84e23a19e37d 23 L152_init32::L152_init32(unsigned int external){
dreschpe 1:bdeac50afe1a 24 Status = setup_clock_32MHZ(external);
dreschpe 0:84e23a19e37d 25 }
dreschpe 0:84e23a19e37d 26
dreschpe 0:84e23a19e37d 27 #define PLL_STARTUP_TIMEOUT 0x5000
dreschpe 0:84e23a19e37d 28
dreschpe 1:bdeac50afe1a 29 ClockStatus L152_init32::setup_clock_32MHZ(int external)
dreschpe 0:84e23a19e37d 30 {
dreschpe 0:84e23a19e37d 31 uint32_t PLLStartUpCounter = 0,PLLStatus = 0,error;
dreschpe 0:84e23a19e37d 32
dreschpe 0:84e23a19e37d 33 if(external == 0) { // internal Oscillator
dreschpe 0:84e23a19e37d 34 RCC_PLLConfig(RCC_PLLSource_HSI,RCC_PLLMul_6,RCC_PLLDiv_3); // setup pll to 96MHz to use USB
dreschpe 0:84e23a19e37d 35 } else {
dreschpe 0:84e23a19e37d 36 RCC_HSEConfig(RCC_HSE_ON); // start external crystal osc.
dreschpe 0:84e23a19e37d 37 error = RCC_WaitForHSEStartUp();
dreschpe 0:84e23a19e37d 38 if(error == ERROR ) { // no external crystal
dreschpe 1:bdeac50afe1a 39 return(EXT_ERR);
dreschpe 0:84e23a19e37d 40 }
dreschpe 0:84e23a19e37d 41 RCC_PLLConfig(RCC_PLLSource_HSE,RCC_PLLMul_12,RCC_PLLDiv_3); // setup pll to 96MHz to use USB
dreschpe 0:84e23a19e37d 42 }
dreschpe 0:84e23a19e37d 43 RCC_PLLCmd(ENABLE); // switch on pll
dreschpe 0:84e23a19e37d 44 do {
dreschpe 0:84e23a19e37d 45 PLLStatus = RCC->CR & RCC_CR_PLLRDY;
dreschpe 0:84e23a19e37d 46 } while((PLLStatus == 0) && (PLLStartUpCounter < PLL_STARTUP_TIMEOUT)); // wait for pll
dreschpe 0:84e23a19e37d 47 if(PLLStatus == 0) {
dreschpe 1:bdeac50afe1a 48 return(PLL_ERR);
dreschpe 0:84e23a19e37d 49 }
dreschpe 0:84e23a19e37d 50 FLASH_SetLatency(FLASH_Latency_1);
dreschpe 0:84e23a19e37d 51 FLASH_PrefetchBufferCmd(ENABLE);
dreschpe 0:84e23a19e37d 52 FLASH_ReadAccess64Cmd(ENABLE);
dreschpe 0:84e23a19e37d 53 RCC_HCLKConfig(RCC_SYSCLK_Div2);
dreschpe 0:84e23a19e37d 54 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); // switch to 32 MHz clock
dreschpe 0:84e23a19e37d 55 SystemCoreClockUpdate(); // update SystemCoreClock var
dreschpe 1:bdeac50afe1a 56 return(OK);
dreschpe 0:84e23a19e37d 57 }