Peter Drescher
Library to control a QVGA TFT connected to SPI. You can use printf to print text The lib can handle different fonts, draw lines, circles, rect and bmp
SPI_TFT.cpp@12:b2dd49f04d5d, 2012-04-07 (annotated)
- Committer:
- dreschpe
- Date:
- Sat Apr 07 16:05:39 2012 +0000
- Revision:
- 12:b2dd49f04d5d
- Parent:
- 11:3cfa9bb9b070
- Child:
- 13:d525819cb601
Use DMA and direct access to SPI register to speed up to 6 times.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| dreschpe | 4:e1e45f8a7664 | 1 | /* mbed library for 240*320 pixel display TFT based on HX8347D LCD Controller |
| dreschpe | 4:e1e45f8a7664 | 2 | * Copyright (c) 2011 Peter Drescher - DC2PD |
| dreschpe | 4:e1e45f8a7664 | 3 | * |
| dreschpe | 4:e1e45f8a7664 | 4 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| dreschpe | 4:e1e45f8a7664 | 5 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| dreschpe | 4:e1e45f8a7664 | 6 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| dreschpe | 4:e1e45f8a7664 | 7 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| dreschpe | 4:e1e45f8a7664 | 8 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| dreschpe | 4:e1e45f8a7664 | 9 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| dreschpe | 4:e1e45f8a7664 | 10 | * THE SOFTWARE. |
| dreschpe | 4:e1e45f8a7664 | 11 | */ |
| dreschpe | 12:b2dd49f04d5d | 12 | |
| dreschpe | 12:b2dd49f04d5d | 13 | |
| dreschpe | 12:b2dd49f04d5d | 14 | // fix bmp padding for Bitmap function |
| dreschpe | 12:b2dd49f04d5d | 15 | // speed up pixel |
| dreschpe | 10:1e868317ff49 | 16 | // 30.12.11 fix cls |
| dreschpe | 12:b2dd49f04d5d | 17 | // 11.03.12 use DMA to speed up |
| dreschpe | 12:b2dd49f04d5d | 18 | // 15.03.12 use SSEL for TFT CS to enable DMA Register writes |
| dreschpe | 12:b2dd49f04d5d | 19 | // 06.04.12 fix SSEL CS problem |
| dreschpe | 12:b2dd49f04d5d | 20 | // 06.04.12 use direct access to the spi register to speed up the library. |
| dreschpe | 6:fc33e4a5713e | 21 | |
| dreschpe | 4:e1e45f8a7664 | 22 | |
| dreschpe | 4:e1e45f8a7664 | 23 | #include "SPI_TFT.h" |
| dreschpe | 4:e1e45f8a7664 | 24 | #include "mbed.h" |
| dreschpe | 4:e1e45f8a7664 | 25 | |
| dreschpe | 4:e1e45f8a7664 | 26 | |
| dreschpe | 4:e1e45f8a7664 | 27 | #define BPP 16 // Bits per pixel |
| dreschpe | 4:e1e45f8a7664 | 28 | |
| dreschpe | 12:b2dd49f04d5d | 29 | |
| dreschpe | 12:b2dd49f04d5d | 30 | //extern Serial pc; |
| dreschpe | 12:b2dd49f04d5d | 31 | //extern DigitalOut xx; // debug !! |
| dreschpe | 4:e1e45f8a7664 | 32 | |
| dreschpe | 4:e1e45f8a7664 | 33 | SPI_TFT::SPI_TFT(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, const char *name) |
| dreschpe | 12:b2dd49f04d5d | 34 | : _spi(mosi, miso, sclk), _reset(reset),GraphicsDisplay(name) { |
| dreschpe | 4:e1e45f8a7664 | 35 | tft_reset(); |
| dreschpe | 4:e1e45f8a7664 | 36 | orientation = 0; |
| dreschpe | 4:e1e45f8a7664 | 37 | char_x = 0; |
| dreschpe | 12:b2dd49f04d5d | 38 | if (mosi == p11 || mosi == P0_18) spi_port = 0; // we must know the used SPI port to setup the DMA |
| dreschpe | 12:b2dd49f04d5d | 39 | else spi_port = 1; |
| dreschpe | 4:e1e45f8a7664 | 40 | } |
| dreschpe | 4:e1e45f8a7664 | 41 | |
| dreschpe | 4:e1e45f8a7664 | 42 | int SPI_TFT::width() { |
| dreschpe | 4:e1e45f8a7664 | 43 | if (orientation == 0 || orientation == 2) return 240; |
| dreschpe | 4:e1e45f8a7664 | 44 | else return 320; |
| dreschpe | 4:e1e45f8a7664 | 45 | } |
| dreschpe | 4:e1e45f8a7664 | 46 | |
| dreschpe | 4:e1e45f8a7664 | 47 | |
| dreschpe | 4:e1e45f8a7664 | 48 | int SPI_TFT::height() { |
| dreschpe | 4:e1e45f8a7664 | 49 | if (orientation == 0 || orientation == 2) return 320; |
| dreschpe | 4:e1e45f8a7664 | 50 | else return 240; |
| dreschpe | 4:e1e45f8a7664 | 51 | } |
| dreschpe | 4:e1e45f8a7664 | 52 | |
| dreschpe | 4:e1e45f8a7664 | 53 | |
| dreschpe | 4:e1e45f8a7664 | 54 | void SPI_TFT::set_orientation(unsigned int o) { |
| dreschpe | 4:e1e45f8a7664 | 55 | orientation = o; |
| dreschpe | 4:e1e45f8a7664 | 56 | switch (orientation) { |
| dreschpe | 4:e1e45f8a7664 | 57 | case 0: |
| dreschpe | 12:b2dd49f04d5d | 58 | wr_reg(0x16, 0x08); |
| dreschpe | 4:e1e45f8a7664 | 59 | break; |
| dreschpe | 4:e1e45f8a7664 | 60 | case 1: |
| dreschpe | 12:b2dd49f04d5d | 61 | wr_reg(0x16, 0x68); |
| dreschpe | 4:e1e45f8a7664 | 62 | break; |
| dreschpe | 4:e1e45f8a7664 | 63 | case 2: |
| dreschpe | 12:b2dd49f04d5d | 64 | wr_reg(0x16, 0xC8); |
| dreschpe | 4:e1e45f8a7664 | 65 | break; |
| dreschpe | 4:e1e45f8a7664 | 66 | case 3: |
| dreschpe | 12:b2dd49f04d5d | 67 | wr_reg(0x16, 0xA8); |
| dreschpe | 4:e1e45f8a7664 | 68 | break; |
| dreschpe | 4:e1e45f8a7664 | 69 | } |
| dreschpe | 12:b2dd49f04d5d | 70 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 71 | } |
| dreschpe | 4:e1e45f8a7664 | 72 | |
| dreschpe | 4:e1e45f8a7664 | 73 | |
| dreschpe | 12:b2dd49f04d5d | 74 | // write command to tft register |
| dreschpe | 4:e1e45f8a7664 | 75 | |
| dreschpe | 12:b2dd49f04d5d | 76 | void SPI_TFT::wr_cmd(unsigned char cmd) { |
| dreschpe | 12:b2dd49f04d5d | 77 | unsigned short spi_d; |
| dreschpe | 12:b2dd49f04d5d | 78 | spi_d = 0x7000 | cmd ; |
| dreschpe | 12:b2dd49f04d5d | 79 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 80 | LPC_SSP0->DR = spi_d; |
| dreschpe | 12:b2dd49f04d5d | 81 | // we have to wait for SPI IDLE to get SSEL (CS) back to high |
| dreschpe | 12:b2dd49f04d5d | 82 | do { |
| dreschpe | 12:b2dd49f04d5d | 83 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle |
| dreschpe | 12:b2dd49f04d5d | 84 | } else { |
| dreschpe | 12:b2dd49f04d5d | 85 | LPC_SSP1->DR = spi_d; |
| dreschpe | 12:b2dd49f04d5d | 86 | do { |
| dreschpe | 12:b2dd49f04d5d | 87 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle |
| dreschpe | 12:b2dd49f04d5d | 88 | } |
| dreschpe | 4:e1e45f8a7664 | 89 | |
| dreschpe | 4:e1e45f8a7664 | 90 | } |
| dreschpe | 4:e1e45f8a7664 | 91 | |
| dreschpe | 4:e1e45f8a7664 | 92 | |
| dreschpe | 4:e1e45f8a7664 | 93 | |
| dreschpe | 12:b2dd49f04d5d | 94 | void SPI_TFT::wr_dat(unsigned char dat) { |
| dreschpe | 12:b2dd49f04d5d | 95 | unsigned short spi_d; |
| dreschpe | 12:b2dd49f04d5d | 96 | spi_d = 0x7200 | dat; |
| dreschpe | 12:b2dd49f04d5d | 97 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 98 | LPC_SSP0->DR = spi_d; |
| dreschpe | 12:b2dd49f04d5d | 99 | // we have to wait for SPI IDLE to get SSEL (CS) back to high |
| dreschpe | 12:b2dd49f04d5d | 100 | do { |
| dreschpe | 12:b2dd49f04d5d | 101 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle |
| dreschpe | 12:b2dd49f04d5d | 102 | } else { |
| dreschpe | 12:b2dd49f04d5d | 103 | LPC_SSP1->DR = spi_d; |
| dreschpe | 12:b2dd49f04d5d | 104 | do { |
| dreschpe | 12:b2dd49f04d5d | 105 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle |
| dreschpe | 12:b2dd49f04d5d | 106 | } |
| dreschpe | 4:e1e45f8a7664 | 107 | } |
| dreschpe | 4:e1e45f8a7664 | 108 | |
| dreschpe | 4:e1e45f8a7664 | 109 | |
| dreschpe | 4:e1e45f8a7664 | 110 | |
| dreschpe | 12:b2dd49f04d5d | 111 | // the HX8347-D controller do not use the MISO (SDO) Signal. |
| dreschpe | 12:b2dd49f04d5d | 112 | // The controller use the MOSI signal bidirectional. |
| dreschpe | 12:b2dd49f04d5d | 113 | // To read from the controller we have to make some bit banging |
| dreschpe | 12:b2dd49f04d5d | 114 | |
| dreschpe | 12:b2dd49f04d5d | 115 | unsigned short SPI_TFT::rd_dat (void) { |
| dreschpe | 12:b2dd49f04d5d | 116 | unsigned short val = 0; |
| dreschpe | 12:b2dd49f04d5d | 117 | |
| dreschpe | 12:b2dd49f04d5d | 118 | //val = _spi.write(0x73ff); /* Dummy read 1 */ |
| dreschpe | 12:b2dd49f04d5d | 119 | //val = _spi.write(0x0000); /* Read D8..D15 */ |
| dreschpe | 12:b2dd49f04d5d | 120 | return (val); |
| dreschpe | 12:b2dd49f04d5d | 121 | } |
| dreschpe | 12:b2dd49f04d5d | 122 | |
| dreschpe | 12:b2dd49f04d5d | 123 | void SPI_TFT::wr_reg (unsigned char reg, unsigned char val) { |
| dreschpe | 12:b2dd49f04d5d | 124 | wr_cmd(reg); |
| dreschpe | 12:b2dd49f04d5d | 125 | wr_dat(val); |
| dreschpe | 12:b2dd49f04d5d | 126 | } |
| dreschpe | 12:b2dd49f04d5d | 127 | |
| dreschpe | 4:e1e45f8a7664 | 128 | unsigned short SPI_TFT::rd_reg (unsigned char reg) { |
| dreschpe | 4:e1e45f8a7664 | 129 | wr_cmd(reg); |
| dreschpe | 4:e1e45f8a7664 | 130 | return(rd_dat()); |
| dreschpe | 4:e1e45f8a7664 | 131 | } |
| dreschpe | 4:e1e45f8a7664 | 132 | |
| dreschpe | 4:e1e45f8a7664 | 133 | void SPI_TFT::tft_reset() { |
| dreschpe | 4:e1e45f8a7664 | 134 | static unsigned short driverCode; |
| dreschpe | 12:b2dd49f04d5d | 135 | _spi.format(16,3); // 16 bit spi mode 3 |
| dreschpe | 12:b2dd49f04d5d | 136 | _spi.frequency(48000000); // 48 Mhz SPI clock |
| dreschpe | 12:b2dd49f04d5d | 137 | _reset = 0; // display reset |
| dreschpe | 12:b2dd49f04d5d | 138 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 139 | // Set up SSEL0 for CS |
| dreschpe | 12:b2dd49f04d5d | 140 | LPC_PINCON->PINSEL1 |= (1UL << 1); |
| dreschpe | 12:b2dd49f04d5d | 141 | } else { |
| dreschpe | 12:b2dd49f04d5d | 142 | // Set up SSEL1 |
| dreschpe | 12:b2dd49f04d5d | 143 | LPC_PINCON->PINSEL0 |= (1UL << 13); |
| dreschpe | 12:b2dd49f04d5d | 144 | } |
| dreschpe | 4:e1e45f8a7664 | 145 | wait_us(50); |
| dreschpe | 4:e1e45f8a7664 | 146 | _reset = 1; // end reset |
| dreschpe | 4:e1e45f8a7664 | 147 | wait_ms(5); |
| dreschpe | 4:e1e45f8a7664 | 148 | |
| dreschpe | 4:e1e45f8a7664 | 149 | /* Start Initial Sequence ----------------------------------------------------*/ |
| dreschpe | 12:b2dd49f04d5d | 150 | wr_reg(0xEA, 0x00); /* Reset Power Control 1 */ |
| dreschpe | 12:b2dd49f04d5d | 151 | wr_reg(0xEB, 0x20); /* Power Control 2 */ |
| dreschpe | 12:b2dd49f04d5d | 152 | wr_reg(0xEC, 0x0C); /* Power Control 3 */ |
| dreschpe | 12:b2dd49f04d5d | 153 | wr_reg(0xED, 0xC4); /* Power Control 4 */ |
| dreschpe | 12:b2dd49f04d5d | 154 | wr_reg(0xE8, 0x40); /* Source OPON_N */ |
| dreschpe | 12:b2dd49f04d5d | 155 | wr_reg(0xE9, 0x38); /* Source OPON_I */ |
| dreschpe | 12:b2dd49f04d5d | 156 | wr_reg(0xF1, 0x01); /* */ |
| dreschpe | 12:b2dd49f04d5d | 157 | wr_reg(0xF2, 0x10); /* */ |
| dreschpe | 12:b2dd49f04d5d | 158 | wr_reg(0x27, 0xA3); /* Display Control 2 */ |
| dreschpe | 4:e1e45f8a7664 | 159 | |
| dreschpe | 4:e1e45f8a7664 | 160 | /* Power On sequence ---------------------------------------------------------*/ |
| dreschpe | 12:b2dd49f04d5d | 161 | wr_reg(0x1B, 0x1B); /* Power Control 2 */ |
| dreschpe | 12:b2dd49f04d5d | 162 | wr_reg(0x1A, 0x01); /* Power Control 1 */ |
| dreschpe | 12:b2dd49f04d5d | 163 | wr_reg(0x24, 0x2F); /* Vcom Control 2 */ |
| dreschpe | 12:b2dd49f04d5d | 164 | wr_reg(0x25, 0x57); /* Vcom Control 3 */ |
| dreschpe | 12:b2dd49f04d5d | 165 | wr_reg(0x23, 0x8D); /* Vcom Control 1 */ |
| dreschpe | 4:e1e45f8a7664 | 166 | |
| dreschpe | 4:e1e45f8a7664 | 167 | /* Gamma settings -----------------------------------------------------------*/ |
| dreschpe | 4:e1e45f8a7664 | 168 | wr_reg(0x40,0x00); // |
| dreschpe | 4:e1e45f8a7664 | 169 | wr_reg(0x41,0x00); // |
| dreschpe | 4:e1e45f8a7664 | 170 | wr_reg(0x42,0x01); // |
| dreschpe | 4:e1e45f8a7664 | 171 | wr_reg(0x43,0x13); // |
| dreschpe | 4:e1e45f8a7664 | 172 | wr_reg(0x44,0x10); // |
| dreschpe | 4:e1e45f8a7664 | 173 | wr_reg(0x45,0x26); // |
| dreschpe | 4:e1e45f8a7664 | 174 | wr_reg(0x46,0x08); // |
| dreschpe | 4:e1e45f8a7664 | 175 | wr_reg(0x47,0x51); // |
| dreschpe | 4:e1e45f8a7664 | 176 | wr_reg(0x48,0x02); // |
| dreschpe | 4:e1e45f8a7664 | 177 | wr_reg(0x49,0x12); // |
| dreschpe | 4:e1e45f8a7664 | 178 | wr_reg(0x4A,0x18); // |
| dreschpe | 4:e1e45f8a7664 | 179 | wr_reg(0x4B,0x19); // |
| dreschpe | 4:e1e45f8a7664 | 180 | wr_reg(0x4C,0x14); // |
| dreschpe | 4:e1e45f8a7664 | 181 | wr_reg(0x50,0x19); // |
| dreschpe | 4:e1e45f8a7664 | 182 | wr_reg(0x51,0x2F); // |
| dreschpe | 4:e1e45f8a7664 | 183 | wr_reg(0x52,0x2C); // |
| dreschpe | 4:e1e45f8a7664 | 184 | wr_reg(0x53,0x3E); // |
| dreschpe | 4:e1e45f8a7664 | 185 | wr_reg(0x54,0x3F); // |
| dreschpe | 4:e1e45f8a7664 | 186 | wr_reg(0x55,0x3F); // |
| dreschpe | 4:e1e45f8a7664 | 187 | wr_reg(0x56,0x2E); // |
| dreschpe | 4:e1e45f8a7664 | 188 | wr_reg(0x57,0x77); // |
| dreschpe | 4:e1e45f8a7664 | 189 | wr_reg(0x58,0x0B); // |
| dreschpe | 4:e1e45f8a7664 | 190 | wr_reg(0x59,0x06); // |
| dreschpe | 4:e1e45f8a7664 | 191 | wr_reg(0x5A,0x07); // |
| dreschpe | 4:e1e45f8a7664 | 192 | wr_reg(0x5B,0x0D); // |
| dreschpe | 4:e1e45f8a7664 | 193 | wr_reg(0x5C,0x1D); // |
| dreschpe | 4:e1e45f8a7664 | 194 | wr_reg(0x5D,0xCC); // |
| dreschpe | 4:e1e45f8a7664 | 195 | |
| dreschpe | 4:e1e45f8a7664 | 196 | /* Power + Osc ---------------------------------------------------------------*/ |
| dreschpe | 4:e1e45f8a7664 | 197 | wr_reg(0x18, 0x0036); /* OSC Control 1 */ |
| dreschpe | 4:e1e45f8a7664 | 198 | wr_reg(0x19, 0x0001); /* OSC Control 2 */ |
| dreschpe | 4:e1e45f8a7664 | 199 | wr_reg(0x01, 0x0000); /* Display Mode Control */ |
| dreschpe | 4:e1e45f8a7664 | 200 | wr_reg(0x1F, 0x0088); /* Power Control 6 */ |
| dreschpe | 4:e1e45f8a7664 | 201 | wait_ms(5); /* Delay 5 ms */ |
| dreschpe | 4:e1e45f8a7664 | 202 | wr_reg(0x1F, 0x0080); /* Power Control 6 */ |
| dreschpe | 4:e1e45f8a7664 | 203 | wait_ms(5); /* Delay 5 ms */ |
| dreschpe | 4:e1e45f8a7664 | 204 | wr_reg(0x1F, 0x0090); /* Power Control 6 */ |
| dreschpe | 4:e1e45f8a7664 | 205 | wait_ms(5); /* Delay 5 ms */ |
| dreschpe | 4:e1e45f8a7664 | 206 | wr_reg(0x1F, 0x00D0); /* Power Control 6 */ |
| dreschpe | 4:e1e45f8a7664 | 207 | wait_ms(5); /* Delay 5 ms */ |
| dreschpe | 4:e1e45f8a7664 | 208 | |
| dreschpe | 4:e1e45f8a7664 | 209 | wr_reg(0x17, 0x0005); /* Colmod 16Bit/Pixel */ |
| dreschpe | 4:e1e45f8a7664 | 210 | |
| dreschpe | 4:e1e45f8a7664 | 211 | wr_reg(0x36, 0x0000); /* Panel Characteristic */ |
| dreschpe | 4:e1e45f8a7664 | 212 | wr_reg(0x28, 0x0038); /* Display Control 3 */ |
| dreschpe | 4:e1e45f8a7664 | 213 | wait_ms(40); |
| dreschpe | 4:e1e45f8a7664 | 214 | wr_reg(0x28, 0x003C); /* Display Control 3 */ |
| dreschpe | 4:e1e45f8a7664 | 215 | switch (orientation) { |
| dreschpe | 4:e1e45f8a7664 | 216 | case 0: |
| dreschpe | 4:e1e45f8a7664 | 217 | wr_reg(0x16, 0x0008); |
| dreschpe | 4:e1e45f8a7664 | 218 | break; |
| dreschpe | 4:e1e45f8a7664 | 219 | case 1: |
| dreschpe | 4:e1e45f8a7664 | 220 | wr_reg(0x16, 0x0068); |
| dreschpe | 4:e1e45f8a7664 | 221 | break; |
| dreschpe | 4:e1e45f8a7664 | 222 | case 2: |
| dreschpe | 4:e1e45f8a7664 | 223 | wr_reg(0x16, 0x00C8); |
| dreschpe | 4:e1e45f8a7664 | 224 | break; |
| dreschpe | 4:e1e45f8a7664 | 225 | case 3: |
| dreschpe | 4:e1e45f8a7664 | 226 | wr_reg(0x16, 0x00A8); |
| dreschpe | 4:e1e45f8a7664 | 227 | break; |
| dreschpe | 4:e1e45f8a7664 | 228 | } |
| dreschpe | 4:e1e45f8a7664 | 229 | |
| dreschpe | 12:b2dd49f04d5d | 230 | // setup DMA channel 0 |
| dreschpe | 12:b2dd49f04d5d | 231 | // Power up the GPDMA. |
| dreschpe | 12:b2dd49f04d5d | 232 | LPC_SC->PCONP |= (1UL << 29); |
| dreschpe | 12:b2dd49f04d5d | 233 | LPC_GPDMA->DMACConfig = 1; // enable DMA controller |
| dreschpe | 12:b2dd49f04d5d | 234 | // Reset the Interrupt status |
| dreschpe | 12:b2dd49f04d5d | 235 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 236 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 237 | LPC_GPDMACH0->DMACCLLI = 0; |
| dreschpe | 12:b2dd49f04d5d | 238 | |
| dreschpe | 4:e1e45f8a7664 | 239 | WindowMax (); |
| dreschpe | 4:e1e45f8a7664 | 240 | } |
| dreschpe | 4:e1e45f8a7664 | 241 | |
| dreschpe | 4:e1e45f8a7664 | 242 | |
| dreschpe | 4:e1e45f8a7664 | 243 | |
| dreschpe | 4:e1e45f8a7664 | 244 | |
| dreschpe | 4:e1e45f8a7664 | 245 | void SPI_TFT::pixel(int x, int y, int color) { |
| dreschpe | 12:b2dd49f04d5d | 246 | unsigned char u,l; |
| dreschpe | 4:e1e45f8a7664 | 247 | wr_reg(0x03, (x >> 0)); |
| dreschpe | 4:e1e45f8a7664 | 248 | wr_reg(0x02, (x >> 8)); |
| dreschpe | 4:e1e45f8a7664 | 249 | wr_reg(0x07, (y >> 0)); |
| dreschpe | 4:e1e45f8a7664 | 250 | wr_reg(0x06, (y >> 8)); |
| dreschpe | 4:e1e45f8a7664 | 251 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 252 | u = color >> 8; |
| dreschpe | 12:b2dd49f04d5d | 253 | l = color & 0xff; |
| dreschpe | 12:b2dd49f04d5d | 254 | |
| dreschpe | 12:b2dd49f04d5d | 255 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 256 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 257 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 258 | LPC_SSP0->DR = u; // high byte |
| dreschpe | 12:b2dd49f04d5d | 259 | LPC_SSP0->DR = l; // low byte |
| dreschpe | 12:b2dd49f04d5d | 260 | LPC_SSP0->CR0 |= 0x08UL; // set back to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 261 | // we have to wait for SPI IDLE to get SSEL (CS) back to high |
| dreschpe | 12:b2dd49f04d5d | 262 | do { |
| dreschpe | 12:b2dd49f04d5d | 263 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle |
| dreschpe | 12:b2dd49f04d5d | 264 | } else { |
| dreschpe | 12:b2dd49f04d5d | 265 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 266 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 267 | LPC_SSP1->DR = u; |
| dreschpe | 12:b2dd49f04d5d | 268 | LPC_SSP1->DR = l; |
| dreschpe | 12:b2dd49f04d5d | 269 | LPC_SSP1->CR0 |= 0x08UL; // set back to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 270 | // we have to wait for SPI IDLE to get SSEL (CS) back to high |
| dreschpe | 12:b2dd49f04d5d | 271 | do { |
| dreschpe | 12:b2dd49f04d5d | 272 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle |
| dreschpe | 12:b2dd49f04d5d | 273 | } |
| dreschpe | 4:e1e45f8a7664 | 274 | } |
| dreschpe | 4:e1e45f8a7664 | 275 | |
| dreschpe | 4:e1e45f8a7664 | 276 | |
| dreschpe | 4:e1e45f8a7664 | 277 | void SPI_TFT::window (unsigned int x, unsigned int y, unsigned int w, unsigned int h) { |
| dreschpe | 12:b2dd49f04d5d | 278 | wr_reg(0x03, x ); |
| dreschpe | 4:e1e45f8a7664 | 279 | wr_reg(0x02, (x >> 8)); |
| dreschpe | 12:b2dd49f04d5d | 280 | wr_reg(0x05, x+w-1 ); |
| dreschpe | 4:e1e45f8a7664 | 281 | wr_reg(0x04, (x+w-1 >> 8)); |
| dreschpe | 12:b2dd49f04d5d | 282 | wr_reg(0x07, y ); |
| dreschpe | 4:e1e45f8a7664 | 283 | wr_reg(0x06, ( y >> 8)); |
| dreschpe | 12:b2dd49f04d5d | 284 | wr_reg(0x09, ( y+h-1 )); |
| dreschpe | 4:e1e45f8a7664 | 285 | wr_reg(0x08, ( y+h-1 >> 8)); |
| dreschpe | 4:e1e45f8a7664 | 286 | } |
| dreschpe | 4:e1e45f8a7664 | 287 | |
| dreschpe | 4:e1e45f8a7664 | 288 | |
| dreschpe | 4:e1e45f8a7664 | 289 | void SPI_TFT::WindowMax (void) { |
| dreschpe | 4:e1e45f8a7664 | 290 | window (0, 0, width(), height()); |
| dreschpe | 4:e1e45f8a7664 | 291 | } |
| dreschpe | 4:e1e45f8a7664 | 292 | |
| dreschpe | 4:e1e45f8a7664 | 293 | |
| dreschpe | 4:e1e45f8a7664 | 294 | void SPI_TFT::cls (void) { |
| dreschpe | 12:b2dd49f04d5d | 295 | //unsigned int i |
| dreschpe | 12:b2dd49f04d5d | 296 | |
| dreschpe | 12:b2dd49f04d5d | 297 | int pixel = ( width() * height()); |
| dreschpe | 12:b2dd49f04d5d | 298 | int dma_count; |
| dreschpe | 12:b2dd49f04d5d | 299 | int color = _background; |
| dreschpe | 10:1e868317ff49 | 300 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 301 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 302 | |
| dreschpe | 12:b2dd49f04d5d | 303 | // The SSEL signal is held low until the spi FIFO is emty. |
| dreschpe | 12:b2dd49f04d5d | 304 | // We have to lower the SPI clock for the 8 bit start to get the spi running |
| dreschpe | 12:b2dd49f04d5d | 305 | // until the next data word |
| dreschpe | 12:b2dd49f04d5d | 306 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color; |
| dreschpe | 12:b2dd49f04d5d | 307 | |
| dreschpe | 12:b2dd49f04d5d | 308 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 309 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 310 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 311 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 312 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 313 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 slow down to prevent a fifo emty |
| dreschpe | 12:b2dd49f04d5d | 314 | LPC_SSP0->DR = 0x72; // start byte |
| dreschpe | 12:b2dd49f04d5d | 315 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 316 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 317 | } else { |
| dreschpe | 12:b2dd49f04d5d | 318 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 319 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 320 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 321 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 322 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 323 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 324 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 325 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 326 | } |
| dreschpe | 12:b2dd49f04d5d | 327 | |
| dreschpe | 12:b2dd49f04d5d | 328 | // start DMA |
| dreschpe | 12:b2dd49f04d5d | 329 | do { |
| dreschpe | 12:b2dd49f04d5d | 330 | if (pixel > 4095) { |
| dreschpe | 12:b2dd49f04d5d | 331 | dma_count = 4095; |
| dreschpe | 12:b2dd49f04d5d | 332 | pixel = pixel - 4095; |
| dreschpe | 12:b2dd49f04d5d | 333 | } else { |
| dreschpe | 12:b2dd49f04d5d | 334 | dma_count = pixel; |
| dreschpe | 12:b2dd49f04d5d | 335 | pixel = 0; |
| dreschpe | 12:b2dd49f04d5d | 336 | } |
| dreschpe | 12:b2dd49f04d5d | 337 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 338 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 339 | LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 340 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 341 | LPC_GPDMA->DMACSoftSReq = 0x1; // DMA request |
| dreschpe | 12:b2dd49f04d5d | 342 | |
| dreschpe | 12:b2dd49f04d5d | 343 | do { |
| dreschpe | 12:b2dd49f04d5d | 344 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 345 | |
| dreschpe | 12:b2dd49f04d5d | 346 | } while (pixel > 0); |
| dreschpe | 12:b2dd49f04d5d | 347 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 348 | do { |
| dreschpe | 12:b2dd49f04d5d | 349 | } while ((0x0010 & LPC_SSP0->SR) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 350 | /* disable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 351 | LPC_SSP0->DMACR = 0x0; |
| dreschpe | 12:b2dd49f04d5d | 352 | } else { |
| dreschpe | 12:b2dd49f04d5d | 353 | do { |
| dreschpe | 12:b2dd49f04d5d | 354 | } while ((0x0010 & LPC_SSP1->SR) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 355 | /* disable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 356 | LPC_SSP1->DMACR = 0x0; |
| dreschpe | 12:b2dd49f04d5d | 357 | } |
| dreschpe | 12:b2dd49f04d5d | 358 | |
| dreschpe | 4:e1e45f8a7664 | 359 | } |
| dreschpe | 4:e1e45f8a7664 | 360 | |
| dreschpe | 4:e1e45f8a7664 | 361 | |
| dreschpe | 4:e1e45f8a7664 | 362 | void SPI_TFT::circle(int x0, int y0, int r, int color) { |
| dreschpe | 4:e1e45f8a7664 | 363 | |
| dreschpe | 4:e1e45f8a7664 | 364 | int draw_x0, draw_y0; |
| dreschpe | 4:e1e45f8a7664 | 365 | int draw_x1, draw_y1; |
| dreschpe | 4:e1e45f8a7664 | 366 | int draw_x2, draw_y2; |
| dreschpe | 4:e1e45f8a7664 | 367 | int draw_x3, draw_y3; |
| dreschpe | 4:e1e45f8a7664 | 368 | int draw_x4, draw_y4; |
| dreschpe | 4:e1e45f8a7664 | 369 | int draw_x5, draw_y5; |
| dreschpe | 4:e1e45f8a7664 | 370 | int draw_x6, draw_y6; |
| dreschpe | 4:e1e45f8a7664 | 371 | int draw_x7, draw_y7; |
| dreschpe | 4:e1e45f8a7664 | 372 | int xx, yy; |
| dreschpe | 4:e1e45f8a7664 | 373 | int di; |
| dreschpe | 9:9dc5dfdda734 | 374 | //WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 375 | if (r == 0) { /* no radius */ |
| dreschpe | 4:e1e45f8a7664 | 376 | return; |
| dreschpe | 4:e1e45f8a7664 | 377 | } |
| dreschpe | 4:e1e45f8a7664 | 378 | |
| dreschpe | 4:e1e45f8a7664 | 379 | draw_x0 = draw_x1 = x0; |
| dreschpe | 4:e1e45f8a7664 | 380 | draw_y0 = draw_y1 = y0 + r; |
| dreschpe | 4:e1e45f8a7664 | 381 | if (draw_y0 < height()) { |
| dreschpe | 4:e1e45f8a7664 | 382 | pixel(draw_x0, draw_y0, color); /* 90 degree */ |
| dreschpe | 4:e1e45f8a7664 | 383 | } |
| dreschpe | 4:e1e45f8a7664 | 384 | |
| dreschpe | 4:e1e45f8a7664 | 385 | draw_x2 = draw_x3 = x0; |
| dreschpe | 4:e1e45f8a7664 | 386 | draw_y2 = draw_y3 = y0 - r; |
| dreschpe | 4:e1e45f8a7664 | 387 | if (draw_y2 >= 0) { |
| dreschpe | 4:e1e45f8a7664 | 388 | pixel(draw_x2, draw_y2, color); /* 270 degree */ |
| dreschpe | 4:e1e45f8a7664 | 389 | } |
| dreschpe | 4:e1e45f8a7664 | 390 | |
| dreschpe | 4:e1e45f8a7664 | 391 | draw_x4 = draw_x6 = x0 + r; |
| dreschpe | 4:e1e45f8a7664 | 392 | draw_y4 = draw_y6 = y0; |
| dreschpe | 4:e1e45f8a7664 | 393 | if (draw_x4 < width()) { |
| dreschpe | 4:e1e45f8a7664 | 394 | pixel(draw_x4, draw_y4, color); /* 0 degree */ |
| dreschpe | 4:e1e45f8a7664 | 395 | } |
| dreschpe | 4:e1e45f8a7664 | 396 | |
| dreschpe | 4:e1e45f8a7664 | 397 | draw_x5 = draw_x7 = x0 - r; |
| dreschpe | 4:e1e45f8a7664 | 398 | draw_y5 = draw_y7 = y0; |
| dreschpe | 4:e1e45f8a7664 | 399 | if (draw_x5>=0) { |
| dreschpe | 4:e1e45f8a7664 | 400 | pixel(draw_x5, draw_y5, color); /* 180 degree */ |
| dreschpe | 4:e1e45f8a7664 | 401 | } |
| dreschpe | 4:e1e45f8a7664 | 402 | |
| dreschpe | 4:e1e45f8a7664 | 403 | if (r == 1) { |
| dreschpe | 4:e1e45f8a7664 | 404 | return; |
| dreschpe | 4:e1e45f8a7664 | 405 | } |
| dreschpe | 4:e1e45f8a7664 | 406 | |
| dreschpe | 4:e1e45f8a7664 | 407 | di = 3 - 2*r; |
| dreschpe | 4:e1e45f8a7664 | 408 | xx = 0; |
| dreschpe | 4:e1e45f8a7664 | 409 | yy = r; |
| dreschpe | 4:e1e45f8a7664 | 410 | while (xx < yy) { |
| dreschpe | 4:e1e45f8a7664 | 411 | |
| dreschpe | 4:e1e45f8a7664 | 412 | if (di < 0) { |
| dreschpe | 4:e1e45f8a7664 | 413 | di += 4*xx + 6; |
| dreschpe | 4:e1e45f8a7664 | 414 | } else { |
| dreschpe | 4:e1e45f8a7664 | 415 | di += 4*(xx - yy) + 10; |
| dreschpe | 4:e1e45f8a7664 | 416 | yy--; |
| dreschpe | 4:e1e45f8a7664 | 417 | draw_y0--; |
| dreschpe | 4:e1e45f8a7664 | 418 | draw_y1--; |
| dreschpe | 4:e1e45f8a7664 | 419 | draw_y2++; |
| dreschpe | 4:e1e45f8a7664 | 420 | draw_y3++; |
| dreschpe | 4:e1e45f8a7664 | 421 | draw_x4--; |
| dreschpe | 4:e1e45f8a7664 | 422 | draw_x5++; |
| dreschpe | 4:e1e45f8a7664 | 423 | draw_x6--; |
| dreschpe | 4:e1e45f8a7664 | 424 | draw_x7++; |
| dreschpe | 4:e1e45f8a7664 | 425 | } |
| dreschpe | 4:e1e45f8a7664 | 426 | xx++; |
| dreschpe | 4:e1e45f8a7664 | 427 | draw_x0++; |
| dreschpe | 4:e1e45f8a7664 | 428 | draw_x1--; |
| dreschpe | 4:e1e45f8a7664 | 429 | draw_x2++; |
| dreschpe | 4:e1e45f8a7664 | 430 | draw_x3--; |
| dreschpe | 4:e1e45f8a7664 | 431 | draw_y4++; |
| dreschpe | 4:e1e45f8a7664 | 432 | draw_y5++; |
| dreschpe | 4:e1e45f8a7664 | 433 | draw_y6--; |
| dreschpe | 4:e1e45f8a7664 | 434 | draw_y7--; |
| dreschpe | 4:e1e45f8a7664 | 435 | |
| dreschpe | 4:e1e45f8a7664 | 436 | if ( (draw_x0 <= width()) && (draw_y0>=0) ) { |
| dreschpe | 4:e1e45f8a7664 | 437 | pixel(draw_x0, draw_y0, color); |
| dreschpe | 4:e1e45f8a7664 | 438 | } |
| dreschpe | 4:e1e45f8a7664 | 439 | |
| dreschpe | 4:e1e45f8a7664 | 440 | if ( (draw_x1 >= 0) && (draw_y1 >= 0) ) { |
| dreschpe | 4:e1e45f8a7664 | 441 | pixel(draw_x1, draw_y1, color); |
| dreschpe | 4:e1e45f8a7664 | 442 | } |
| dreschpe | 4:e1e45f8a7664 | 443 | |
| dreschpe | 4:e1e45f8a7664 | 444 | if ( (draw_x2 <= width()) && (draw_y2 <= height()) ) { |
| dreschpe | 4:e1e45f8a7664 | 445 | pixel(draw_x2, draw_y2, color); |
| dreschpe | 4:e1e45f8a7664 | 446 | } |
| dreschpe | 4:e1e45f8a7664 | 447 | |
| dreschpe | 4:e1e45f8a7664 | 448 | if ( (draw_x3 >=0 ) && (draw_y3 <= height()) ) { |
| dreschpe | 4:e1e45f8a7664 | 449 | pixel(draw_x3, draw_y3, color); |
| dreschpe | 4:e1e45f8a7664 | 450 | } |
| dreschpe | 4:e1e45f8a7664 | 451 | |
| dreschpe | 4:e1e45f8a7664 | 452 | if ( (draw_x4 <= width()) && (draw_y4 >= 0) ) { |
| dreschpe | 4:e1e45f8a7664 | 453 | pixel(draw_x4, draw_y4, color); |
| dreschpe | 4:e1e45f8a7664 | 454 | } |
| dreschpe | 4:e1e45f8a7664 | 455 | |
| dreschpe | 4:e1e45f8a7664 | 456 | if ( (draw_x5 >= 0) && (draw_y5 >= 0) ) { |
| dreschpe | 4:e1e45f8a7664 | 457 | pixel(draw_x5, draw_y5, color); |
| dreschpe | 4:e1e45f8a7664 | 458 | } |
| dreschpe | 4:e1e45f8a7664 | 459 | if ( (draw_x6 <=width()) && (draw_y6 <= height()) ) { |
| dreschpe | 4:e1e45f8a7664 | 460 | pixel(draw_x6, draw_y6, color); |
| dreschpe | 4:e1e45f8a7664 | 461 | } |
| dreschpe | 4:e1e45f8a7664 | 462 | if ( (draw_x7 >= 0) && (draw_y7 <= height()) ) { |
| dreschpe | 4:e1e45f8a7664 | 463 | pixel(draw_x7, draw_y7, color); |
| dreschpe | 4:e1e45f8a7664 | 464 | } |
| dreschpe | 4:e1e45f8a7664 | 465 | } |
| dreschpe | 4:e1e45f8a7664 | 466 | return; |
| dreschpe | 4:e1e45f8a7664 | 467 | } |
| dreschpe | 4:e1e45f8a7664 | 468 | |
| dreschpe | 5:2db1b8070d94 | 469 | void SPI_TFT::fillcircle(int x, int y, int r, int color) { |
| dreschpe | 4:e1e45f8a7664 | 470 | int i; |
| dreschpe | 5:2db1b8070d94 | 471 | for (i = 0; i <= r; i++) |
| dreschpe | 4:e1e45f8a7664 | 472 | circle(x,y,i,color); |
| dreschpe | 4:e1e45f8a7664 | 473 | } |
| dreschpe | 4:e1e45f8a7664 | 474 | |
| dreschpe | 4:e1e45f8a7664 | 475 | |
| dreschpe | 4:e1e45f8a7664 | 476 | |
| dreschpe | 4:e1e45f8a7664 | 477 | void SPI_TFT::hline(int x0, int x1, int y, int color) { |
| dreschpe | 4:e1e45f8a7664 | 478 | int w; |
| dreschpe | 4:e1e45f8a7664 | 479 | w = x1 - x0 + 1; |
| dreschpe | 4:e1e45f8a7664 | 480 | window(x0,y,w,1); |
| dreschpe | 4:e1e45f8a7664 | 481 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 482 | |
| dreschpe | 12:b2dd49f04d5d | 483 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 484 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 485 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 486 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 487 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 488 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 489 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 490 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 491 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 492 | } else { |
| dreschpe | 12:b2dd49f04d5d | 493 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 494 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 495 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 496 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 497 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 498 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 499 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 500 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 4:e1e45f8a7664 | 501 | } |
| dreschpe | 12:b2dd49f04d5d | 502 | |
| dreschpe | 12:b2dd49f04d5d | 503 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 504 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 505 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color; |
| dreschpe | 12:b2dd49f04d5d | 506 | LPC_GPDMACH0->DMACCControl = w | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 507 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 508 | LPC_GPDMA->DMACSoftSReq = 0x1; // start DMA |
| dreschpe | 12:b2dd49f04d5d | 509 | do { |
| dreschpe | 12:b2dd49f04d5d | 510 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 511 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 512 | do { |
| dreschpe | 12:b2dd49f04d5d | 513 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 514 | } else { |
| dreschpe | 12:b2dd49f04d5d | 515 | do { |
| dreschpe | 12:b2dd49f04d5d | 516 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 517 | } |
| dreschpe | 9:9dc5dfdda734 | 518 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 519 | return; |
| dreschpe | 4:e1e45f8a7664 | 520 | } |
| dreschpe | 4:e1e45f8a7664 | 521 | |
| dreschpe | 4:e1e45f8a7664 | 522 | void SPI_TFT::vline(int x, int y0, int y1, int color) { |
| dreschpe | 4:e1e45f8a7664 | 523 | int h; |
| dreschpe | 4:e1e45f8a7664 | 524 | h = y1 - y0 + 1; |
| dreschpe | 4:e1e45f8a7664 | 525 | window(x,y0,1,h); |
| dreschpe | 4:e1e45f8a7664 | 526 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 527 | |
| dreschpe | 12:b2dd49f04d5d | 528 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 529 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 530 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 531 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 532 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 533 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 534 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 535 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 536 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 537 | } else { |
| dreschpe | 12:b2dd49f04d5d | 538 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 539 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 540 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 541 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 542 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 543 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 544 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 545 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 4:e1e45f8a7664 | 546 | } |
| dreschpe | 12:b2dd49f04d5d | 547 | |
| dreschpe | 12:b2dd49f04d5d | 548 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 549 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 550 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color; |
| dreschpe | 12:b2dd49f04d5d | 551 | LPC_GPDMACH0->DMACCControl = h | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 552 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 553 | LPC_GPDMA->DMACSoftSReq = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 554 | do { |
| dreschpe | 12:b2dd49f04d5d | 555 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 556 | |
| dreschpe | 12:b2dd49f04d5d | 557 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 558 | do { |
| dreschpe | 12:b2dd49f04d5d | 559 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 560 | } else { |
| dreschpe | 12:b2dd49f04d5d | 561 | do { |
| dreschpe | 12:b2dd49f04d5d | 562 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 563 | } |
| dreschpe | 9:9dc5dfdda734 | 564 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 565 | return; |
| dreschpe | 4:e1e45f8a7664 | 566 | } |
| dreschpe | 4:e1e45f8a7664 | 567 | |
| dreschpe | 4:e1e45f8a7664 | 568 | |
| dreschpe | 4:e1e45f8a7664 | 569 | |
| dreschpe | 4:e1e45f8a7664 | 570 | void SPI_TFT::line(int x0, int y0, int x1, int y1, int color) { |
| dreschpe | 9:9dc5dfdda734 | 571 | //WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 572 | int dx = 0, dy = 0; |
| dreschpe | 4:e1e45f8a7664 | 573 | int dx_sym = 0, dy_sym = 0; |
| dreschpe | 4:e1e45f8a7664 | 574 | int dx_x2 = 0, dy_x2 = 0; |
| dreschpe | 4:e1e45f8a7664 | 575 | int di = 0; |
| dreschpe | 4:e1e45f8a7664 | 576 | |
| dreschpe | 4:e1e45f8a7664 | 577 | dx = x1-x0; |
| dreschpe | 4:e1e45f8a7664 | 578 | dy = y1-y0; |
| dreschpe | 4:e1e45f8a7664 | 579 | |
| dreschpe | 4:e1e45f8a7664 | 580 | if (dx == 0) { /* vertical line */ |
| dreschpe | 4:e1e45f8a7664 | 581 | if (y1 > y0) vline(x0,y0,y1,color); |
| dreschpe | 4:e1e45f8a7664 | 582 | else vline(x0,y1,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 583 | return; |
| dreschpe | 4:e1e45f8a7664 | 584 | } |
| dreschpe | 4:e1e45f8a7664 | 585 | |
| dreschpe | 4:e1e45f8a7664 | 586 | if (dx > 0) { |
| dreschpe | 4:e1e45f8a7664 | 587 | dx_sym = 1; |
| dreschpe | 4:e1e45f8a7664 | 588 | } else { |
| dreschpe | 4:e1e45f8a7664 | 589 | dx_sym = -1; |
| dreschpe | 4:e1e45f8a7664 | 590 | } |
| dreschpe | 4:e1e45f8a7664 | 591 | if (dy == 0) { /* horizontal line */ |
| dreschpe | 4:e1e45f8a7664 | 592 | if (x1 > x0) hline(x0,x1,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 593 | else hline(x1,x0,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 594 | return; |
| dreschpe | 4:e1e45f8a7664 | 595 | } |
| dreschpe | 4:e1e45f8a7664 | 596 | |
| dreschpe | 4:e1e45f8a7664 | 597 | if (dy > 0) { |
| dreschpe | 4:e1e45f8a7664 | 598 | dy_sym = 1; |
| dreschpe | 4:e1e45f8a7664 | 599 | } else { |
| dreschpe | 4:e1e45f8a7664 | 600 | dy_sym = -1; |
| dreschpe | 4:e1e45f8a7664 | 601 | } |
| dreschpe | 4:e1e45f8a7664 | 602 | |
| dreschpe | 4:e1e45f8a7664 | 603 | dx = dx_sym*dx; |
| dreschpe | 4:e1e45f8a7664 | 604 | dy = dy_sym*dy; |
| dreschpe | 4:e1e45f8a7664 | 605 | |
| dreschpe | 4:e1e45f8a7664 | 606 | dx_x2 = dx*2; |
| dreschpe | 4:e1e45f8a7664 | 607 | dy_x2 = dy*2; |
| dreschpe | 4:e1e45f8a7664 | 608 | |
| dreschpe | 4:e1e45f8a7664 | 609 | if (dx >= dy) { |
| dreschpe | 4:e1e45f8a7664 | 610 | di = dy_x2 - dx; |
| dreschpe | 4:e1e45f8a7664 | 611 | while (x0 != x1) { |
| dreschpe | 4:e1e45f8a7664 | 612 | |
| dreschpe | 4:e1e45f8a7664 | 613 | pixel(x0, y0, color); |
| dreschpe | 4:e1e45f8a7664 | 614 | x0 += dx_sym; |
| dreschpe | 4:e1e45f8a7664 | 615 | if (di<0) { |
| dreschpe | 4:e1e45f8a7664 | 616 | di += dy_x2; |
| dreschpe | 4:e1e45f8a7664 | 617 | } else { |
| dreschpe | 4:e1e45f8a7664 | 618 | di += dy_x2 - dx_x2; |
| dreschpe | 4:e1e45f8a7664 | 619 | y0 += dy_sym; |
| dreschpe | 4:e1e45f8a7664 | 620 | } |
| dreschpe | 4:e1e45f8a7664 | 621 | } |
| dreschpe | 4:e1e45f8a7664 | 622 | pixel(x0, y0, color); |
| dreschpe | 4:e1e45f8a7664 | 623 | } else { |
| dreschpe | 4:e1e45f8a7664 | 624 | di = dx_x2 - dy; |
| dreschpe | 4:e1e45f8a7664 | 625 | while (y0 != y1) { |
| dreschpe | 4:e1e45f8a7664 | 626 | pixel(x0, y0, color); |
| dreschpe | 4:e1e45f8a7664 | 627 | y0 += dy_sym; |
| dreschpe | 4:e1e45f8a7664 | 628 | if (di < 0) { |
| dreschpe | 4:e1e45f8a7664 | 629 | di += dx_x2; |
| dreschpe | 4:e1e45f8a7664 | 630 | } else { |
| dreschpe | 4:e1e45f8a7664 | 631 | di += dx_x2 - dy_x2; |
| dreschpe | 4:e1e45f8a7664 | 632 | x0 += dx_sym; |
| dreschpe | 4:e1e45f8a7664 | 633 | } |
| dreschpe | 4:e1e45f8a7664 | 634 | } |
| dreschpe | 4:e1e45f8a7664 | 635 | pixel(x0, y0, color); |
| dreschpe | 4:e1e45f8a7664 | 636 | } |
| dreschpe | 4:e1e45f8a7664 | 637 | return; |
| dreschpe | 4:e1e45f8a7664 | 638 | } |
| dreschpe | 4:e1e45f8a7664 | 639 | |
| dreschpe | 4:e1e45f8a7664 | 640 | |
| dreschpe | 4:e1e45f8a7664 | 641 | void SPI_TFT::rect(int x0, int y0, int x1, int y1, int color) { |
| dreschpe | 4:e1e45f8a7664 | 642 | |
| dreschpe | 4:e1e45f8a7664 | 643 | if (x1 > x0) hline(x0,x1,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 644 | else hline(x1,x0,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 645 | |
| dreschpe | 4:e1e45f8a7664 | 646 | if (y1 > y0) vline(x0,y0,y1,color); |
| dreschpe | 4:e1e45f8a7664 | 647 | else vline(x0,y1,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 648 | |
| dreschpe | 4:e1e45f8a7664 | 649 | if (x1 > x0) hline(x0,x1,y1,color); |
| dreschpe | 4:e1e45f8a7664 | 650 | else hline(x1,x0,y1,color); |
| dreschpe | 4:e1e45f8a7664 | 651 | |
| dreschpe | 4:e1e45f8a7664 | 652 | if (y1 > y0) vline(x1,y0,y1,color); |
| dreschpe | 4:e1e45f8a7664 | 653 | else vline(x1,y1,y0,color); |
| dreschpe | 4:e1e45f8a7664 | 654 | |
| dreschpe | 4:e1e45f8a7664 | 655 | return; |
| dreschpe | 4:e1e45f8a7664 | 656 | } |
| dreschpe | 4:e1e45f8a7664 | 657 | |
| dreschpe | 4:e1e45f8a7664 | 658 | |
| dreschpe | 4:e1e45f8a7664 | 659 | |
| dreschpe | 4:e1e45f8a7664 | 660 | void SPI_TFT::fillrect(int x0, int y0, int x1, int y1, int color) { |
| dreschpe | 4:e1e45f8a7664 | 661 | |
| dreschpe | 4:e1e45f8a7664 | 662 | int h = y1 - y0 + 1; |
| dreschpe | 4:e1e45f8a7664 | 663 | int w = x1 - x0 + 1; |
| dreschpe | 4:e1e45f8a7664 | 664 | int pixel = h * w; |
| dreschpe | 12:b2dd49f04d5d | 665 | int dma_count; |
| dreschpe | 4:e1e45f8a7664 | 666 | window(x0,y0,w,h); |
| dreschpe | 4:e1e45f8a7664 | 667 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 668 | |
| dreschpe | 12:b2dd49f04d5d | 669 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 670 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 671 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 672 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 673 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 674 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 675 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 676 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 677 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 678 | } else { |
| dreschpe | 12:b2dd49f04d5d | 679 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 680 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 681 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 682 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 683 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 684 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 685 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 686 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 4:e1e45f8a7664 | 687 | } |
| dreschpe | 12:b2dd49f04d5d | 688 | |
| dreschpe | 12:b2dd49f04d5d | 689 | do { |
| dreschpe | 12:b2dd49f04d5d | 690 | if (pixel > 4095) { |
| dreschpe | 12:b2dd49f04d5d | 691 | dma_count = 4095; |
| dreschpe | 12:b2dd49f04d5d | 692 | pixel = pixel - 4095; |
| dreschpe | 12:b2dd49f04d5d | 693 | } else { |
| dreschpe | 12:b2dd49f04d5d | 694 | dma_count = pixel; |
| dreschpe | 12:b2dd49f04d5d | 695 | pixel = 0; |
| dreschpe | 12:b2dd49f04d5d | 696 | } |
| dreschpe | 12:b2dd49f04d5d | 697 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 698 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 699 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color; |
| dreschpe | 12:b2dd49f04d5d | 700 | LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 701 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 702 | LPC_GPDMA->DMACSoftSReq = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 703 | do { |
| dreschpe | 12:b2dd49f04d5d | 704 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 705 | |
| dreschpe | 12:b2dd49f04d5d | 706 | } while (pixel > 0); |
| dreschpe | 12:b2dd49f04d5d | 707 | |
| dreschpe | 12:b2dd49f04d5d | 708 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 709 | do { |
| dreschpe | 12:b2dd49f04d5d | 710 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 711 | } else { |
| dreschpe | 12:b2dd49f04d5d | 712 | do { |
| dreschpe | 12:b2dd49f04d5d | 713 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 714 | } |
| dreschpe | 12:b2dd49f04d5d | 715 | |
| dreschpe | 9:9dc5dfdda734 | 716 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 717 | return; |
| dreschpe | 4:e1e45f8a7664 | 718 | } |
| dreschpe | 4:e1e45f8a7664 | 719 | |
| dreschpe | 4:e1e45f8a7664 | 720 | |
| dreschpe | 6:fc33e4a5713e | 721 | void SPI_TFT::locate(int x, int y) { |
| dreschpe | 6:fc33e4a5713e | 722 | char_x = x; |
| dreschpe | 6:fc33e4a5713e | 723 | char_y = y; |
| dreschpe | 4:e1e45f8a7664 | 724 | } |
| dreschpe | 4:e1e45f8a7664 | 725 | |
| dreschpe | 4:e1e45f8a7664 | 726 | |
| dreschpe | 4:e1e45f8a7664 | 727 | |
| dreschpe | 4:e1e45f8a7664 | 728 | int SPI_TFT::columns() { |
| dreschpe | 4:e1e45f8a7664 | 729 | return width() / font[1]; |
| dreschpe | 4:e1e45f8a7664 | 730 | } |
| dreschpe | 4:e1e45f8a7664 | 731 | |
| dreschpe | 4:e1e45f8a7664 | 732 | |
| dreschpe | 4:e1e45f8a7664 | 733 | |
| dreschpe | 4:e1e45f8a7664 | 734 | int SPI_TFT::rows() { |
| dreschpe | 4:e1e45f8a7664 | 735 | return height() / font[2]; |
| dreschpe | 4:e1e45f8a7664 | 736 | } |
| dreschpe | 4:e1e45f8a7664 | 737 | |
| dreschpe | 4:e1e45f8a7664 | 738 | |
| dreschpe | 4:e1e45f8a7664 | 739 | |
| dreschpe | 4:e1e45f8a7664 | 740 | int SPI_TFT::_putc(int value) { |
| dreschpe | 6:fc33e4a5713e | 741 | if (value == '\n') { // new line |
| dreschpe | 4:e1e45f8a7664 | 742 | char_x = 0; |
| dreschpe | 6:fc33e4a5713e | 743 | char_y = char_y + font[2]; |
| dreschpe | 6:fc33e4a5713e | 744 | if (char_y >= height() - font[2]) { |
| dreschpe | 6:fc33e4a5713e | 745 | char_y = 0; |
| dreschpe | 4:e1e45f8a7664 | 746 | } |
| dreschpe | 4:e1e45f8a7664 | 747 | } else { |
| dreschpe | 6:fc33e4a5713e | 748 | character(char_x, char_y, value); |
| dreschpe | 12:b2dd49f04d5d | 749 | } |
| dreschpe | 4:e1e45f8a7664 | 750 | return value; |
| dreschpe | 4:e1e45f8a7664 | 751 | } |
| dreschpe | 4:e1e45f8a7664 | 752 | |
| dreschpe | 4:e1e45f8a7664 | 753 | |
| dreschpe | 4:e1e45f8a7664 | 754 | |
| dreschpe | 4:e1e45f8a7664 | 755 | |
| dreschpe | 6:fc33e4a5713e | 756 | void SPI_TFT::character(int x, int y, int c) { |
| dreschpe | 12:b2dd49f04d5d | 757 | unsigned int hor,vert,offset,bpl,j,i,b,p; |
| dreschpe | 4:e1e45f8a7664 | 758 | unsigned char* zeichen; |
| dreschpe | 4:e1e45f8a7664 | 759 | unsigned char z,w; |
| dreschpe | 12:b2dd49f04d5d | 760 | unsigned int pixel; |
| dreschpe | 12:b2dd49f04d5d | 761 | unsigned int dma_count,dma_off; |
| dreschpe | 12:b2dd49f04d5d | 762 | uint16_t *buffer; |
| dreschpe | 4:e1e45f8a7664 | 763 | |
| dreschpe | 4:e1e45f8a7664 | 764 | if ((c < 31) || (c > 127)) return; // test char range |
| dreschpe | 4:e1e45f8a7664 | 765 | |
| dreschpe | 4:e1e45f8a7664 | 766 | // read font parameter from start of array |
| dreschpe | 4:e1e45f8a7664 | 767 | offset = font[0]; // bytes / char |
| dreschpe | 4:e1e45f8a7664 | 768 | hor = font[1]; // get hor size of font |
| dreschpe | 4:e1e45f8a7664 | 769 | vert = font[2]; // get vert size of font |
| dreschpe | 4:e1e45f8a7664 | 770 | bpl = font[3]; // bytes per line |
| dreschpe | 4:e1e45f8a7664 | 771 | |
| dreschpe | 4:e1e45f8a7664 | 772 | if (char_x + hor > width()) { |
| dreschpe | 4:e1e45f8a7664 | 773 | char_x = 0; |
| dreschpe | 6:fc33e4a5713e | 774 | char_y = char_y + vert; |
| dreschpe | 12:b2dd49f04d5d | 775 | if (char_y >= height() - font[2]) { |
| dreschpe | 6:fc33e4a5713e | 776 | char_y = 0; |
| dreschpe | 4:e1e45f8a7664 | 777 | } |
| dreschpe | 4:e1e45f8a7664 | 778 | } |
| dreschpe | 6:fc33e4a5713e | 779 | window(char_x, char_y,hor,vert); // char box |
| dreschpe | 4:e1e45f8a7664 | 780 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 781 | |
| dreschpe | 12:b2dd49f04d5d | 782 | pixel = hor * vert; // calculate buffer size |
| dreschpe | 12:b2dd49f04d5d | 783 | |
| dreschpe | 12:b2dd49f04d5d | 784 | buffer = (uint16_t *) malloc (2*pixel); // we need a buffer for the 16 bit |
| dreschpe | 12:b2dd49f04d5d | 785 | if (buffer == NULL) { |
| dreschpe | 12:b2dd49f04d5d | 786 | //led = 1; |
| dreschpe | 12:b2dd49f04d5d | 787 | //pc.printf("Malloc error !\n\r"); |
| dreschpe | 12:b2dd49f04d5d | 788 | return; // error no memory |
| dreschpe | 12:b2dd49f04d5d | 789 | } |
| dreschpe | 12:b2dd49f04d5d | 790 | |
| dreschpe | 4:e1e45f8a7664 | 791 | zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap |
| dreschpe | 4:e1e45f8a7664 | 792 | w = zeichen[0]; // width of actual char |
| dreschpe | 12:b2dd49f04d5d | 793 | p = 0; |
| dreschpe | 12:b2dd49f04d5d | 794 | // construct the char into the buffer |
| dreschpe | 4:e1e45f8a7664 | 795 | for (j=0; j<vert; j++) { // vert line |
| dreschpe | 4:e1e45f8a7664 | 796 | for (i=0; i<hor; i++) { // horz line |
| dreschpe | 4:e1e45f8a7664 | 797 | z = zeichen[bpl * i + ((j & 0xF8) >> 3)+1]; |
| dreschpe | 4:e1e45f8a7664 | 798 | b = 1 << (j & 0x07); |
| dreschpe | 4:e1e45f8a7664 | 799 | if (( z & b ) == 0x00) { |
| dreschpe | 12:b2dd49f04d5d | 800 | buffer[p] = _background; |
| dreschpe | 4:e1e45f8a7664 | 801 | } else { |
| dreschpe | 12:b2dd49f04d5d | 802 | buffer[p] = _foreground; |
| dreschpe | 4:e1e45f8a7664 | 803 | } |
| dreschpe | 12:b2dd49f04d5d | 804 | p++; |
| dreschpe | 4:e1e45f8a7664 | 805 | } |
| dreschpe | 4:e1e45f8a7664 | 806 | } |
| dreschpe | 12:b2dd49f04d5d | 807 | |
| dreschpe | 12:b2dd49f04d5d | 808 | |
| dreschpe | 12:b2dd49f04d5d | 809 | // copy the buffer with DMA SPI to display |
| dreschpe | 12:b2dd49f04d5d | 810 | dma_off = 0; // offset for DMA transfer |
| dreschpe | 12:b2dd49f04d5d | 811 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 812 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 813 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 814 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 815 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 816 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 817 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 818 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 819 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 820 | } else { |
| dreschpe | 12:b2dd49f04d5d | 821 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 822 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 823 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 824 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 825 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 826 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 827 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 828 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 829 | } |
| dreschpe | 12:b2dd49f04d5d | 830 | |
| dreschpe | 12:b2dd49f04d5d | 831 | // start DMA |
| dreschpe | 12:b2dd49f04d5d | 832 | do { |
| dreschpe | 12:b2dd49f04d5d | 833 | if (pixel > 4095) { // this is a giant font ! |
| dreschpe | 12:b2dd49f04d5d | 834 | dma_count = 4095; |
| dreschpe | 12:b2dd49f04d5d | 835 | pixel = pixel - 4095; |
| dreschpe | 12:b2dd49f04d5d | 836 | } else { |
| dreschpe | 12:b2dd49f04d5d | 837 | dma_count = pixel; |
| dreschpe | 12:b2dd49f04d5d | 838 | pixel = 0; |
| dreschpe | 12:b2dd49f04d5d | 839 | } |
| dreschpe | 12:b2dd49f04d5d | 840 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 841 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 842 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t) (buffer + dma_off); |
| dreschpe | 12:b2dd49f04d5d | 843 | LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 844 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 845 | LPC_GPDMA->DMACSoftSReq = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 846 | do { |
| dreschpe | 12:b2dd49f04d5d | 847 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 848 | dma_off = dma_off + dma_count; |
| dreschpe | 12:b2dd49f04d5d | 849 | } while (pixel > 0); |
| dreschpe | 12:b2dd49f04d5d | 850 | |
| dreschpe | 12:b2dd49f04d5d | 851 | free ((uint16_t *) buffer); |
| dreschpe | 12:b2dd49f04d5d | 852 | |
| dreschpe | 12:b2dd49f04d5d | 853 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 854 | do { |
| dreschpe | 12:b2dd49f04d5d | 855 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle |
| dreschpe | 12:b2dd49f04d5d | 856 | /* disable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 857 | LPC_SSP0->DMACR = 0x0; |
| dreschpe | 12:b2dd49f04d5d | 858 | } else { |
| dreschpe | 12:b2dd49f04d5d | 859 | do { |
| dreschpe | 12:b2dd49f04d5d | 860 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle |
| dreschpe | 12:b2dd49f04d5d | 861 | /* disable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 862 | LPC_SSP1->DMACR = 0x0; |
| dreschpe | 12:b2dd49f04d5d | 863 | } |
| dreschpe | 12:b2dd49f04d5d | 864 | |
| dreschpe | 9:9dc5dfdda734 | 865 | WindowMax(); |
| dreschpe | 4:e1e45f8a7664 | 866 | if ((w + 2) < hor) { // x offset to next char |
| dreschpe | 4:e1e45f8a7664 | 867 | char_x += w + 2; |
| dreschpe | 4:e1e45f8a7664 | 868 | } else char_x += hor; |
| dreschpe | 12:b2dd49f04d5d | 869 | |
| dreschpe | 4:e1e45f8a7664 | 870 | } |
| dreschpe | 4:e1e45f8a7664 | 871 | |
| dreschpe | 4:e1e45f8a7664 | 872 | |
| dreschpe | 4:e1e45f8a7664 | 873 | void SPI_TFT::set_font(unsigned char* f) { |
| dreschpe | 4:e1e45f8a7664 | 874 | font = f; |
| dreschpe | 4:e1e45f8a7664 | 875 | } |
| dreschpe | 4:e1e45f8a7664 | 876 | |
| dreschpe | 4:e1e45f8a7664 | 877 | |
| dreschpe | 4:e1e45f8a7664 | 878 | |
| dreschpe | 4:e1e45f8a7664 | 879 | void SPI_TFT::Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap) { |
| dreschpe | 12:b2dd49f04d5d | 880 | unsigned int j; |
| dreschpe | 12:b2dd49f04d5d | 881 | int padd; |
| dreschpe | 4:e1e45f8a7664 | 882 | unsigned short *bitmap_ptr = (unsigned short *)bitmap; |
| dreschpe | 12:b2dd49f04d5d | 883 | // the lines are padded to multiple of 4 bytes in a bitmap |
| dreschpe | 6:fc33e4a5713e | 884 | padd = -1; |
| dreschpe | 6:fc33e4a5713e | 885 | do { |
| dreschpe | 6:fc33e4a5713e | 886 | padd ++; |
| dreschpe | 6:fc33e4a5713e | 887 | } while (2*(w + padd)%4 != 0); |
| dreschpe | 4:e1e45f8a7664 | 888 | window(x, y, w, h); |
| dreschpe | 4:e1e45f8a7664 | 889 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 890 | |
| dreschpe | 12:b2dd49f04d5d | 891 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 892 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 893 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 894 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 895 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 896 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 897 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 898 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 899 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 900 | } else { |
| dreschpe | 12:b2dd49f04d5d | 901 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 902 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 903 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 904 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 905 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 906 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 907 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 908 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 909 | } |
| dreschpe | 6:fc33e4a5713e | 910 | bitmap_ptr += ((h - 1)* (w + padd)); |
| dreschpe | 4:e1e45f8a7664 | 911 | for (j = 0; j < h; j++) { //Lines |
| dreschpe | 12:b2dd49f04d5d | 912 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 913 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 914 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)bitmap_ptr; |
| dreschpe | 12:b2dd49f04d5d | 915 | LPC_GPDMACH0->DMACCControl = w | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 916 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 917 | LPC_GPDMA->DMACSoftSReq = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 918 | do { |
| dreschpe | 12:b2dd49f04d5d | 919 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 920 | |
| dreschpe | 12:b2dd49f04d5d | 921 | bitmap_ptr -= w; |
| dreschpe | 6:fc33e4a5713e | 922 | bitmap_ptr -= padd; |
| dreschpe | 4:e1e45f8a7664 | 923 | } |
| dreschpe | 12:b2dd49f04d5d | 924 | |
| dreschpe | 12:b2dd49f04d5d | 925 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 926 | do { |
| dreschpe | 12:b2dd49f04d5d | 927 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 928 | } else { |
| dreschpe | 12:b2dd49f04d5d | 929 | do { |
| dreschpe | 12:b2dd49f04d5d | 930 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 931 | } |
| dreschpe | 12:b2dd49f04d5d | 932 | |
| dreschpe | 9:9dc5dfdda734 | 933 | WindowMax(); |
| dreschpe | 5:2db1b8070d94 | 934 | } |
| dreschpe | 5:2db1b8070d94 | 935 | |
| dreschpe | 5:2db1b8070d94 | 936 | |
| dreschpe | 5:2db1b8070d94 | 937 | int SPI_TFT::BMP_16(unsigned int x, unsigned int y, const char *Name_BMP) { |
| dreschpe | 5:2db1b8070d94 | 938 | |
| dreschpe | 5:2db1b8070d94 | 939 | #define OffsetPixelWidth 18 |
| dreschpe | 5:2db1b8070d94 | 940 | #define OffsetPixelHeigh 22 |
| dreschpe | 5:2db1b8070d94 | 941 | #define OffsetFileSize 34 |
| dreschpe | 5:2db1b8070d94 | 942 | #define OffsetPixData 10 |
| dreschpe | 5:2db1b8070d94 | 943 | #define OffsetBPP 28 |
| dreschpe | 5:2db1b8070d94 | 944 | |
| dreschpe | 5:2db1b8070d94 | 945 | char filename[50]; |
| dreschpe | 5:2db1b8070d94 | 946 | unsigned char BMP_Header[54]; |
| dreschpe | 5:2db1b8070d94 | 947 | unsigned short BPP_t; |
| dreschpe | 5:2db1b8070d94 | 948 | unsigned int PixelWidth,PixelHeigh,start_data; |
| dreschpe | 5:2db1b8070d94 | 949 | unsigned int i,off; |
| dreschpe | 5:2db1b8070d94 | 950 | int padd,j; |
| dreschpe | 5:2db1b8070d94 | 951 | unsigned short *line; |
| dreschpe | 5:2db1b8070d94 | 952 | |
| dreschpe | 5:2db1b8070d94 | 953 | // get the filename |
| dreschpe | 5:2db1b8070d94 | 954 | LocalFileSystem local("local"); |
| dreschpe | 5:2db1b8070d94 | 955 | sprintf(&filename[0],"/local/"); |
| dreschpe | 5:2db1b8070d94 | 956 | i=7; |
| dreschpe | 5:2db1b8070d94 | 957 | while (*Name_BMP!='\0') { |
| dreschpe | 5:2db1b8070d94 | 958 | filename[i++]=*Name_BMP++; |
| dreschpe | 5:2db1b8070d94 | 959 | } |
| dreschpe | 12:b2dd49f04d5d | 960 | |
| dreschpe | 12:b2dd49f04d5d | 961 | fprintf(stderr, "filename : %s \n\r",filename); |
| dreschpe | 12:b2dd49f04d5d | 962 | |
| dreschpe | 12:b2dd49f04d5d | 963 | |
| dreschpe | 5:2db1b8070d94 | 964 | FILE *Image = fopen((const char *)&filename[0], "r"); // open the bmp file |
| dreschpe | 5:2db1b8070d94 | 965 | if (!Image) { |
| dreschpe | 5:2db1b8070d94 | 966 | return(0); // error file not found ! |
| dreschpe | 5:2db1b8070d94 | 967 | } |
| dreschpe | 5:2db1b8070d94 | 968 | |
| dreschpe | 5:2db1b8070d94 | 969 | fread(&BMP_Header[0],1,54,Image); // get the BMP Header |
| dreschpe | 5:2db1b8070d94 | 970 | |
| dreschpe | 5:2db1b8070d94 | 971 | if (BMP_Header[0] != 0x42 || BMP_Header[1] != 0x4D) { // check magic byte |
| dreschpe | 5:2db1b8070d94 | 972 | fclose(Image); |
| dreschpe | 5:2db1b8070d94 | 973 | return(-1); // error no BMP file |
| dreschpe | 5:2db1b8070d94 | 974 | } |
| dreschpe | 5:2db1b8070d94 | 975 | |
| dreschpe | 5:2db1b8070d94 | 976 | BPP_t = BMP_Header[OffsetBPP] + (BMP_Header[OffsetBPP + 1] << 8); |
| dreschpe | 5:2db1b8070d94 | 977 | if (BPP_t != 0x0010) { |
| dreschpe | 5:2db1b8070d94 | 978 | fclose(Image); |
| dreschpe | 5:2db1b8070d94 | 979 | return(-2); // error no 16 bit BMP |
| dreschpe | 5:2db1b8070d94 | 980 | } |
| dreschpe | 5:2db1b8070d94 | 981 | |
| dreschpe | 5:2db1b8070d94 | 982 | PixelHeigh = BMP_Header[OffsetPixelHeigh] + (BMP_Header[OffsetPixelHeigh + 1] << 8) + (BMP_Header[OffsetPixelHeigh + 2] << 16) + (BMP_Header[OffsetPixelHeigh + 3] << 24); |
| dreschpe | 5:2db1b8070d94 | 983 | PixelWidth = BMP_Header[OffsetPixelWidth] + (BMP_Header[OffsetPixelWidth + 1] << 8) + (BMP_Header[OffsetPixelWidth + 2] << 16) + (BMP_Header[OffsetPixelWidth + 3] << 24); |
| dreschpe | 5:2db1b8070d94 | 984 | if (PixelHeigh > height() + y || PixelWidth > width() + x) { |
| dreschpe | 5:2db1b8070d94 | 985 | fclose(Image); |
| dreschpe | 5:2db1b8070d94 | 986 | return(-3); // to big |
| dreschpe | 5:2db1b8070d94 | 987 | } |
| dreschpe | 5:2db1b8070d94 | 988 | |
| dreschpe | 5:2db1b8070d94 | 989 | start_data = BMP_Header[OffsetPixData] + (BMP_Header[OffsetPixData + 1] << 8) + (BMP_Header[OffsetPixData + 2] << 16) + (BMP_Header[OffsetPixData + 3] << 24); |
| dreschpe | 5:2db1b8070d94 | 990 | |
| dreschpe | 12:b2dd49f04d5d | 991 | |
| dreschpe | 12:b2dd49f04d5d | 992 | line = (unsigned short *) malloc (2 * PixelWidth); // we need a buffer for a line |
| dreschpe | 5:2db1b8070d94 | 993 | if (line == NULL) { |
| dreschpe | 5:2db1b8070d94 | 994 | return(-4); // error no memory |
| dreschpe | 5:2db1b8070d94 | 995 | } |
| dreschpe | 5:2db1b8070d94 | 996 | |
| dreschpe | 12:b2dd49f04d5d | 997 | // the bmp lines are padded to multiple of 4 bytes |
| dreschpe | 5:2db1b8070d94 | 998 | padd = -1; |
| dreschpe | 5:2db1b8070d94 | 999 | do { |
| dreschpe | 5:2db1b8070d94 | 1000 | padd ++; |
| dreschpe | 5:2db1b8070d94 | 1001 | } while ((PixelWidth * 2 + padd)%4 != 0); |
| dreschpe | 5:2db1b8070d94 | 1002 | |
| dreschpe | 12:b2dd49f04d5d | 1003 | window(x, y,PixelWidth+1,PixelHeigh); |
| dreschpe | 5:2db1b8070d94 | 1004 | wr_cmd(0x22); |
| dreschpe | 12:b2dd49f04d5d | 1005 | |
| dreschpe | 5:2db1b8070d94 | 1006 | for (j = PixelHeigh - 1; j >= 0; j--) { //Lines bottom up |
| dreschpe | 5:2db1b8070d94 | 1007 | off = j * (PixelWidth * 2 + padd) + start_data; // start of line |
| dreschpe | 5:2db1b8070d94 | 1008 | fseek(Image, off ,SEEK_SET); |
| dreschpe | 5:2db1b8070d94 | 1009 | fread(line,1,PixelWidth * 2,Image); // read a line - slow ! |
| dreschpe | 12:b2dd49f04d5d | 1010 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 1011 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0 |
| dreschpe | 12:b2dd49f04d5d | 1012 | /* Enable SSP0 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 1013 | LPC_SSP0->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 1014 | LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 1015 | LPC_SSP0->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 1016 | LPC_SSP0->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 1017 | LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 1018 | LPC_SSP0->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 1019 | } else { |
| dreschpe | 12:b2dd49f04d5d | 1020 | LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1 |
| dreschpe | 12:b2dd49f04d5d | 1021 | /* Enable SSP1 for DMA. */ |
| dreschpe | 12:b2dd49f04d5d | 1022 | LPC_SSP1->DMACR = 0x2; |
| dreschpe | 12:b2dd49f04d5d | 1023 | LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit |
| dreschpe | 12:b2dd49f04d5d | 1024 | LPC_SSP1->CR0 |= 0x300UL; // clock div / 4 |
| dreschpe | 12:b2dd49f04d5d | 1025 | LPC_SSP1->DR = 0x72; // start Data |
| dreschpe | 12:b2dd49f04d5d | 1026 | LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit |
| dreschpe | 12:b2dd49f04d5d | 1027 | LPC_SSP1->CR0 &= ~(0x300UL); // reset clock div |
| dreschpe | 12:b2dd49f04d5d | 1028 | } |
| dreschpe | 12:b2dd49f04d5d | 1029 | |
| dreschpe | 12:b2dd49f04d5d | 1030 | LPC_GPDMA->DMACIntTCClear = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 1031 | LPC_GPDMA->DMACIntErrClr = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 1032 | LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)line; |
| dreschpe | 12:b2dd49f04d5d | 1033 | LPC_GPDMACH0->DMACCControl = PixelWidth | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt |
| dreschpe | 12:b2dd49f04d5d | 1034 | LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ; |
| dreschpe | 12:b2dd49f04d5d | 1035 | LPC_GPDMA->DMACSoftSReq = 0x1; |
| dreschpe | 12:b2dd49f04d5d | 1036 | do { |
| dreschpe | 12:b2dd49f04d5d | 1037 | } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running |
| dreschpe | 12:b2dd49f04d5d | 1038 | |
| dreschpe | 5:2db1b8070d94 | 1039 | } |
| dreschpe | 12:b2dd49f04d5d | 1040 | |
| dreschpe | 12:b2dd49f04d5d | 1041 | if (spi_port == 0) { // TFT on SSP0 |
| dreschpe | 12:b2dd49f04d5d | 1042 | do { |
| dreschpe | 12:b2dd49f04d5d | 1043 | } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 1044 | } else { |
| dreschpe | 12:b2dd49f04d5d | 1045 | do { |
| dreschpe | 12:b2dd49f04d5d | 1046 | } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty |
| dreschpe | 12:b2dd49f04d5d | 1047 | } |
| dreschpe | 12:b2dd49f04d5d | 1048 | |
| dreschpe | 5:2db1b8070d94 | 1049 | free (line); |
| dreschpe | 5:2db1b8070d94 | 1050 | fclose(Image); |
| dreschpe | 9:9dc5dfdda734 | 1051 | WindowMax(); |
| dreschpe | 5:2db1b8070d94 | 1052 | return(1); |
| dreschpe | 4:e1e45f8a7664 | 1053 | } |