dhivya gopal / Mbed 2 deprecated TFT_sdcard

sd card and tft

Dependencies:   MMA8451Q SDFileSystem SPI_TFT_ILI9341 TFT_fonts mbed

Fork of TFT_test_frdm-kl25z by Motoo Tanaka

SPI_STMPE610.cpp@3:955860740bd0, 2014-11-25 (annotated)

Committer:
dhivya12
Date:
Tue Nov 25 09:13:55 2014 +0000
Revision:
3:955860740bd0
Parent:
0:6b8a2d4c88b3 
tft and sd card

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:6b8a2d4c88b3 1 /* mbed SPI_STMPE610.cpp to test adafruit 2.8" TFT LCD shiled w Touchscreen
Rhyme 0:6b8a2d4c88b3 2 * Copyright (c) 2014 Motoo Tanaka @ Design Methodology Lab
Rhyme 0:6b8a2d4c88b3 3 *
Rhyme 0:6b8a2d4c88b3 4 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Rhyme 0:6b8a2d4c88b3 5 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Rhyme 0:6b8a2d4c88b3 6 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Rhyme 0:6b8a2d4c88b3 7 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Rhyme 0:6b8a2d4c88b3 8 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Rhyme 0:6b8a2d4c88b3 9 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Rhyme 0:6b8a2d4c88b3 10 * THE SOFTWARE.
Rhyme 0:6b8a2d4c88b3 11 */
Rhyme 0:6b8a2d4c88b3 12 /*
Rhyme 0:6b8a2d4c88b3 13 * Note: Since the interrupt siganl of the shield was not connected
Rhyme 0:6b8a2d4c88b3 14 * to an interrupt pin on my frdm-kl25z, I just used polling mode.
Rhyme 0:6b8a2d4c88b3 15 */
Rhyme 0:6b8a2d4c88b3 16
Rhyme 0:6b8a2d4c88b3 17 #include "SPI_STMPE610.h"
Rhyme 0:6b8a2d4c88b3 18
Rhyme 0:6b8a2d4c88b3 19 /* some definitions here */
Rhyme 0:6b8a2d4c88b3 20 #define REG_CHIP_ID 0x00
Rhyme 0:6b8a2d4c88b3 21 #define REG_CHIP_ID_MSB 0x00
Rhyme 0:6b8a2d4c88b3 22 #define REG_CHIP_ID_LSB 0x01
Rhyme 0:6b8a2d4c88b3 23
Rhyme 0:6b8a2d4c88b3 24 #define REG_ID_VER 0x02
Rhyme 0:6b8a2d4c88b3 25 #define REG_SYS_CTRL1 0x03
Rhyme 0:6b8a2d4c88b3 26 #define REG_SYS_CTRL1_RESET 0x02
Rhyme 0:6b8a2d4c88b3 27
Rhyme 0:6b8a2d4c88b3 28 #define REG_SYS_CTRL2 0x04
Rhyme 0:6b8a2d4c88b3 29 #define REG_SPI_CFG 0x08
Rhyme 0:6b8a2d4c88b3 30 #define REG_INT_CTRL 0x09
Rhyme 0:6b8a2d4c88b3 31 #define REG_INT_CTRL_POL_HIGH 0x04
Rhyme 0:6b8a2d4c88b3 32 #define REG_INT_CTRL_POL_LOW 0x00
Rhyme 0:6b8a2d4c88b3 33 #define REG_INT_CTRL_EDGE 0x02
Rhyme 0:6b8a2d4c88b3 34 #define REG_INT_CTRL_LEVEL 0x00
Rhyme 0:6b8a2d4c88b3 35 #define REG_INT_CTRL_ENABLE 0x01
Rhyme 0:6b8a2d4c88b3 36 #define REG_INT_CTRL_DISABLE 0x00
Rhyme 0:6b8a2d4c88b3 37
Rhyme 0:6b8a2d4c88b3 38 #define REG_INT_EN 0x0A
Rhyme 0:6b8a2d4c88b3 39 #define REG_INT_EN_TOUCHDET 0x01
Rhyme 0:6b8a2d4c88b3 40 #define REG_INT_EN_FIFOTH 0x02
Rhyme 0:6b8a2d4c88b3 41 #define REG_INT_EN_FIFOOF 0x04
Rhyme 0:6b8a2d4c88b3 42 #define REG_INT_EN_FIFOFULL 0x08
Rhyme 0:6b8a2d4c88b3 43 #define REG_INT_EN_FIFOEMPTY 0x10
Rhyme 0:6b8a2d4c88b3 44 #define REG_INT_EN_ADC 0x40
Rhyme 0:6b8a2d4c88b3 45
Rhyme 0:6b8a2d4c88b3 46 #define REG_INT_STA 0x0B
Rhyme 0:6b8a2d4c88b3 47 #define REG_INT_STA_TOUCHDET 0x01
Rhyme 0:6b8a2d4c88b3 48
Rhyme 0:6b8a2d4c88b3 49 #define REG_GPIO_EN 0x0C
Rhyme 0:6b8a2d4c88b3 50 #define REG_GPIO_INT_STA 0x0D
Rhyme 0:6b8a2d4c88b3 51 #define REG_ADC_INT_EN 0x0E
Rhyme 0:6b8a2d4c88b3 52 #define REG_ADC_INT_STA 0x0F
Rhyme 0:6b8a2d4c88b3 53 #define REG_GPIO_SET_PIN 0x10
Rhyme 0:6b8a2d4c88b3 54 #define REG_GPIO_CLR_PIN 0x11
Rhyme 0:6b8a2d4c88b3 55 #define REG_GPIO_MP_STA 0x12
Rhyme 0:6b8a2d4c88b3 56 #define REG_GPIO_DIR 0x13
Rhyme 0:6b8a2d4c88b3 57 #define REG_GPIO_ED 0x14
Rhyme 0:6b8a2d4c88b3 58 #define REG_GPIO_RE 0x15
Rhyme 0:6b8a2d4c88b3 59 #define REG_GPIO_FE 0x16
Rhyme 0:6b8a2d4c88b3 60 #define REG_GPIO_AF 0x17
Rhyme 0:6b8a2d4c88b3 61 #define REG_ADC_CTRL1 0x20
Rhyme 0:6b8a2d4c88b3 62 #define REG_ADC_CTRL1_12BIT 0x08
Rhyme 0:6b8a2d4c88b3 63 #define REG_ADC_CTRL1_10BIT 0x00
Rhyme 0:6b8a2d4c88b3 64
Rhyme 0:6b8a2d4c88b3 65 #define REG_ADC_CTRL2 0x21
Rhyme 0:6b8a2d4c88b3 66 #define REG_ADC_CTRL2_1_625MHZ 0x00
Rhyme 0:6b8a2d4c88b3 67 #define REG_ADC_CTRL2_3_25MHZ 0x01
Rhyme 0:6b8a2d4c88b3 68 #define REG_ADC_CTRL2_6_5MHZ 0x02
Rhyme 0:6b8a2d4c88b3 69
Rhyme 0:6b8a2d4c88b3 70 #define REG_ADC_CAPT 0x22
Rhyme 0:6b8a2d4c88b3 71 #define REG_ADC_DATA_CH0 0x30
Rhyme 0:6b8a2d4c88b3 72 #define REG_ADC_DATA_CH1 0x32
Rhyme 0:6b8a2d4c88b3 73 #define REG_ADC_DATA_CH4 0x38
Rhyme 0:6b8a2d4c88b3 74 #define REG_ADC_DATA_CH5 0x3A
Rhyme 0:6b8a2d4c88b3 75 #define REG_ADC_DATA_CH6 0x3C
Rhyme 0:6b8a2d4c88b3 76 #define REG_ADC_DATA_CH7 0x3E
Rhyme 0:6b8a2d4c88b3 77 #define REG_TSC_CTRL 0x40
Rhyme 0:6b8a2d4c88b3 78 #define REG_TSC_CTRL_EN 0x01
Rhyme 0:6b8a2d4c88b3 79 #define REG_TSC_CTRL_XYZ 0x00
Rhyme 0:6b8a2d4c88b3 80 #define REG_TSC_CTRL_XY 0x02
Rhyme 0:6b8a2d4c88b3 81
Rhyme 0:6b8a2d4c88b3 82 #define REG_TSC_CFG 0x41
Rhyme 0:6b8a2d4c88b3 83 #define REG_TSC_CFG_1SAMPLE 0x00
Rhyme 0:6b8a2d4c88b3 84 #define REG_TSC_CFG_2SAMPLE 0x40
Rhyme 0:6b8a2d4c88b3 85 #define REG_TSC_CFG_4SAMPLE 0x80
Rhyme 0:6b8a2d4c88b3 86 #define REG_TSC_CFG_8SAMPLE 0xC0
Rhyme 0:6b8a2d4c88b3 87 #define REG_TSC_CFG_DELAY_10US 0x00
Rhyme 0:6b8a2d4c88b3 88 #define REG_TSC_CFG_DELAY_50US 0x08
Rhyme 0:6b8a2d4c88b3 89 #define REG_TSC_CFG_DELAY_100US 0x10
Rhyme 0:6b8a2d4c88b3 90 #define REG_TSC_CFG_DELAY_500US 0x18
Rhyme 0:6b8a2d4c88b3 91 #define REG_TSC_CFG_DELAY_1MS 0x20
Rhyme 0:6b8a2d4c88b3 92 #define REG_TSC_CFG_DELAY_5MS 0x28
Rhyme 0:6b8a2d4c88b3 93 #define REG_TSC_CFG_DELAY_10MS 0x30
Rhyme 0:6b8a2d4c88b3 94 #define REG_TSC_CFG_DELAY_50MS 0x38
Rhyme 0:6b8a2d4c88b3 95 #define REG_TSC_CFG_SETTLE_10US 0x00
Rhyme 0:6b8a2d4c88b3 96 #define REG_TSC_CFG_SETTLE_100US 0x01
Rhyme 0:6b8a2d4c88b3 97 #define REG_TSC_CFG_SETTLE_500US 0x02
Rhyme 0:6b8a2d4c88b3 98 #define REG_TSC_CFG_SETTLE_1MS 0x03
Rhyme 0:6b8a2d4c88b3 99 #define REG_TSC_CFG_SETTLE_5MS 0x04
Rhyme 0:6b8a2d4c88b3 100 #define REG_TSC_CFG_SETTLE_10MS 0x05
Rhyme 0:6b8a2d4c88b3 101 #define REG_TSC_CFG_SETTLE_50MS 0x06
Rhyme 0:6b8a2d4c88b3 102 #define REG_TSC_CFG_SETTLE_100MS 0x07
Rhyme 0:6b8a2d4c88b3 103
Rhyme 0:6b8a2d4c88b3 104 #define REG_WDW_TR_X 0x42
Rhyme 0:6b8a2d4c88b3 105 #define REG_WDW_TR_Y 0x44
Rhyme 0:6b8a2d4c88b3 106 #define REG_WDW_BL_X 0x46
Rhyme 0:6b8a2d4c88b3 107 #define REG_WDW_BL_Y 0x48
Rhyme 0:6b8a2d4c88b3 108 #define REG_FIFO_TH 0x4A
Rhyme 0:6b8a2d4c88b3 109 #define REG_FIFO_STA 0x4B
Rhyme 0:6b8a2d4c88b3 110 #define REG_FIFO_SIZE 0x4C
Rhyme 0:6b8a2d4c88b3 111 #define REG_TSC_DATA_X 0x4D
Rhyme 0:6b8a2d4c88b3 112 #define REG_TSC_DATA_Y 0x4F
Rhyme 0:6b8a2d4c88b3 113 #define REG_TSC_DATA_Z 0x51
Rhyme 0:6b8a2d4c88b3 114 #define REG_TSC_DATA_XYZ 0x52
Rhyme 0:6b8a2d4c88b3 115 #define REG_TSC_FRACT_XYZ 0x56
Rhyme 0:6b8a2d4c88b3 116 #define REG_TSC_DATA 0x57
Rhyme 0:6b8a2d4c88b3 117 #define REG_TSC_I_DRIVE 0x58
Rhyme 0:6b8a2d4c88b3 118 #define REG_TSC_SHIELD 0x59
Rhyme 0:6b8a2d4c88b3 119
Rhyme 0:6b8a2d4c88b3 120 SPI_STMPE610::SPI_STMPE610(PinName mosi, PinName miso, PinName sclk, PinName cs) :
Rhyme 0:6b8a2d4c88b3 121 m_spi(mosi, miso, sclk), m_cs(cs) {
Rhyme 0:6b8a2d4c88b3 122 // activate the peripheral
Rhyme 0:6b8a2d4c88b3 123 m_cs = 0 ;
Rhyme 0:6b8a2d4c88b3 124 _mode = 0 ;
Rhyme 0:6b8a2d4c88b3 125 m_spi.frequency(1000000) ;
Rhyme 0:6b8a2d4c88b3 126 m_spi.format(8, 0) ;
Rhyme 0:6b8a2d4c88b3 127 write8(REG_SYS_CTRL1, REG_SYS_CTRL1_RESET) ;
Rhyme 0:6b8a2d4c88b3 128 wait(0.1) ;
Rhyme 0:6b8a2d4c88b3 129 write8(REG_SYS_CTRL2, 0x00) ; // turn on clocks
Rhyme 0:6b8a2d4c88b3 130 write8(REG_TSC_CFG,
Rhyme 0:6b8a2d4c88b3 131 REG_TSC_CFG_4SAMPLE
Rhyme 0:6b8a2d4c88b3 132 | REG_TSC_CFG_DELAY_100US
Rhyme 0:6b8a2d4c88b3 133 | REG_TSC_CFG_SETTLE_1MS ) ;
Rhyme 0:6b8a2d4c88b3 134
Rhyme 0:6b8a2d4c88b3 135 write8(REG_TSC_CTRL, REG_TSC_CTRL_XYZ | REG_TSC_CTRL_EN) ;
Rhyme 0:6b8a2d4c88b3 136 m_cs = 1 ;
Rhyme 0:6b8a2d4c88b3 137 }
Rhyme 0:6b8a2d4c88b3 138
Rhyme 0:6b8a2d4c88b3 139 SPI_STMPE610::~SPI_STMPE610() { }
Rhyme 0:6b8a2d4c88b3 140
Rhyme 0:6b8a2d4c88b3 141 void SPI_STMPE610::readRegs(int addr, uint8_t * data, int len) {
Rhyme 0:6b8a2d4c88b3 142 m_cs = 0 ;
Rhyme 0:6b8a2d4c88b3 143
Rhyme 0:6b8a2d4c88b3 144 for (int i = 0 ; i < len ; i++ ) {
Rhyme 0:6b8a2d4c88b3 145 m_spi.write((addr+i)|0x80) ; // spacify address to read
Rhyme 0:6b8a2d4c88b3 146 data[i] = m_spi.write((addr+i)|0x80) ;
Rhyme 0:6b8a2d4c88b3 147 }
Rhyme 0:6b8a2d4c88b3 148 m_spi.write(0x00) ; // to terminate read mode
Rhyme 0:6b8a2d4c88b3 149 m_cs = 1 ;
Rhyme 0:6b8a2d4c88b3 150 }
Rhyme 0:6b8a2d4c88b3 151
Rhyme 0:6b8a2d4c88b3 152 void SPI_STMPE610::writeRegs(uint8_t * data, int len) {
Rhyme 0:6b8a2d4c88b3 153 m_cs = 0 ;
Rhyme 0:6b8a2d4c88b3 154 for (int i = 0 ; i < len ; i++ ) {
Rhyme 0:6b8a2d4c88b3 155 m_spi.write(data[i]) ;
Rhyme 0:6b8a2d4c88b3 156 }
Rhyme 0:6b8a2d4c88b3 157 m_cs = 1 ;
Rhyme 0:6b8a2d4c88b3 158 }
Rhyme 0:6b8a2d4c88b3 159
Rhyme 0:6b8a2d4c88b3 160 void SPI_STMPE610::write8(int addr, uint8_t data8)
Rhyme 0:6b8a2d4c88b3 161 {
Rhyme 0:6b8a2d4c88b3 162 uint8_t data[2] ;
Rhyme 0:6b8a2d4c88b3 163 data[0] = addr ;
Rhyme 0:6b8a2d4c88b3 164 data[1] = data8 ;
Rhyme 0:6b8a2d4c88b3 165 writeRegs(data, 2) ;
Rhyme 0:6b8a2d4c88b3 166 }
Rhyme 0:6b8a2d4c88b3 167
Rhyme 0:6b8a2d4c88b3 168 uint8_t SPI_STMPE610::read8(int addr)
Rhyme 0:6b8a2d4c88b3 169 {
Rhyme 0:6b8a2d4c88b3 170 uint8_t data[1] ;
Rhyme 0:6b8a2d4c88b3 171 readRegs(addr, data, 1) ;
Rhyme 0:6b8a2d4c88b3 172 return( data[0] ) ;
Rhyme 0:6b8a2d4c88b3 173 }
Rhyme 0:6b8a2d4c88b3 174
Rhyme 0:6b8a2d4c88b3 175 void SPI_STMPE610::write16(int addr, uint16_t data16)
Rhyme 0:6b8a2d4c88b3 176 {
Rhyme 0:6b8a2d4c88b3 177 uint8_t data[3] ;
Rhyme 0:6b8a2d4c88b3 178 data[0] = addr ;
Rhyme 0:6b8a2d4c88b3 179 data[1] = (data16 >> 8) & 0xFF ;
Rhyme 0:6b8a2d4c88b3 180 data[2] = data16 & 0xFF ;
Rhyme 0:6b8a2d4c88b3 181 writeRegs(data, 3) ;
Rhyme 0:6b8a2d4c88b3 182 }
Rhyme 0:6b8a2d4c88b3 183
Rhyme 0:6b8a2d4c88b3 184 uint16_t SPI_STMPE610::read16(int addr)
Rhyme 0:6b8a2d4c88b3 185 {
Rhyme 0:6b8a2d4c88b3 186 uint8_t data[2] ;
Rhyme 0:6b8a2d4c88b3 187 uint16_t value = 0 ;
Rhyme 0:6b8a2d4c88b3 188 readRegs(addr, data, 2) ;
Rhyme 0:6b8a2d4c88b3 189 value = (data[0] << 8) | data[1] ;
Rhyme 0:6b8a2d4c88b3 190 return( value ) ;
Rhyme 0:6b8a2d4c88b3 191 }
Rhyme 0:6b8a2d4c88b3 192
Rhyme 0:6b8a2d4c88b3 193 int SPI_STMPE610::getRAWPoint(uint16_t *x, uint16_t *y, uint16_t *z)
Rhyme 0:6b8a2d4c88b3 194 {
Rhyme 0:6b8a2d4c88b3 195 uint8_t data[8], touched = 0 ;
Rhyme 0:6b8a2d4c88b3 196 data[0] = REG_TSC_CTRL ;
Rhyme 0:6b8a2d4c88b3 197 data[1] = REG_TSC_CTRL_EN ;
Rhyme 0:6b8a2d4c88b3 198 writeRegs(data, 2) ;
Rhyme 0:6b8a2d4c88b3 199 wait(0.01) ;
Rhyme 0:6b8a2d4c88b3 200
Rhyme 0:6b8a2d4c88b3 201 readRegs(REG_TSC_CTRL, data, 1) ;
Rhyme 0:6b8a2d4c88b3 202 touched = data[0] & 0x80 ;
Rhyme 0:6b8a2d4c88b3 203 if (touched) { //Touch Detected
Rhyme 0:6b8a2d4c88b3 204 readRegs(REG_TSC_DATA_X, data,5) ;
Rhyme 0:6b8a2d4c88b3 205 *x = (data[0] << 8) | data[1] ;
Rhyme 0:6b8a2d4c88b3 206 *y = (data[2] << 8) | data[3] ;
Rhyme 0:6b8a2d4c88b3 207 *z = data[4] ;
Rhyme 0:6b8a2d4c88b3 208 } else {
Rhyme 0:6b8a2d4c88b3 209 *x = 0 ;
Rhyme 0:6b8a2d4c88b3 210 *y = 0 ;
Rhyme 0:6b8a2d4c88b3 211 *z = 0 ;
Rhyme 0:6b8a2d4c88b3 212 }
Rhyme 0:6b8a2d4c88b3 213
Rhyme 0:6b8a2d4c88b3 214 data[0] = 0x4B ;
Rhyme 0:6b8a2d4c88b3 215 data[1] = 0x01 ;
Rhyme 0:6b8a2d4c88b3 216 writeRegs(data, 2) ; // clear FIFO
Rhyme 0:6b8a2d4c88b3 217
Rhyme 0:6b8a2d4c88b3 218 data[0] = REG_TSC_CTRL ;
Rhyme 0:6b8a2d4c88b3 219 data[1] = 0x00 ; // disable TSC
Rhyme 0:6b8a2d4c88b3 220 writeRegs(data, 2) ;
Rhyme 0:6b8a2d4c88b3 221
Rhyme 0:6b8a2d4c88b3 222 return( touched & (*x || *y || *z)) ;
Rhyme 0:6b8a2d4c88b3 223 }