Daniel Worrall / Mbed 2 deprecated Recorder

Record audio data to a .wav file, complete with header, using the TLV320 CODEC and I2S port

Dependencies:   mbed

USBHostLite/usbhost_lpc17xx.c@0:e7efc8468066, 2011-08-05 (annotated)

Committer:
d_worrall
Date:
Fri Aug 05 15:00:51 2011 +0000
Revision:
0:e7efc8468066
version 2.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
d_worrall 0:e7efc8468066 1 /*
d_worrall 0:e7efc8468066 2 **************************************************************************************************************
d_worrall 0:e7efc8468066 3 * NXP USB Host Stack
d_worrall 0:e7efc8468066 4 *
d_worrall 0:e7efc8468066 5 * (c) Copyright 2008, NXP SemiConductors
d_worrall 0:e7efc8468066 6 * (c) Copyright 2008, OnChip Technologies LLC
d_worrall 0:e7efc8468066 7 * All Rights Reserved
d_worrall 0:e7efc8468066 8 *
d_worrall 0:e7efc8468066 9 * www.nxp.com
d_worrall 0:e7efc8468066 10 * www.onchiptech.com
d_worrall 0:e7efc8468066 11 *
d_worrall 0:e7efc8468066 12 * File : usbhost_lpc17xx.c
d_worrall 0:e7efc8468066 13 * Programmer(s) : Ravikanth.P
d_worrall 0:e7efc8468066 14 * Version :
d_worrall 0:e7efc8468066 15 *
d_worrall 0:e7efc8468066 16 **************************************************************************************************************
d_worrall 0:e7efc8468066 17 */
d_worrall 0:e7efc8468066 18
d_worrall 0:e7efc8468066 19 /*
d_worrall 0:e7efc8468066 20 **************************************************************************************************************
d_worrall 0:e7efc8468066 21 * INCLUDE HEADER FILES
d_worrall 0:e7efc8468066 22 **************************************************************************************************************
d_worrall 0:e7efc8468066 23 */
d_worrall 0:e7efc8468066 24
d_worrall 0:e7efc8468066 25 #include "usbhost_lpc17xx.h"
d_worrall 0:e7efc8468066 26
d_worrall 0:e7efc8468066 27 /*
d_worrall 0:e7efc8468066 28 **************************************************************************************************************
d_worrall 0:e7efc8468066 29 * GLOBAL VARIABLES
d_worrall 0:e7efc8468066 30 **************************************************************************************************************
d_worrall 0:e7efc8468066 31 */
d_worrall 0:e7efc8468066 32 int gUSBConnected;
d_worrall 0:e7efc8468066 33
d_worrall 0:e7efc8468066 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
d_worrall 0:e7efc8468066 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
d_worrall 0:e7efc8468066 36 volatile USB_INT08U HOST_TDControlStatus = 0;
d_worrall 0:e7efc8468066 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
d_worrall 0:e7efc8468066 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
d_worrall 0:e7efc8468066 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
d_worrall 0:e7efc8468066 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
d_worrall 0:e7efc8468066 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
d_worrall 0:e7efc8468066 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
d_worrall 0:e7efc8468066 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
d_worrall 0:e7efc8468066 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
d_worrall 0:e7efc8468066 45
d_worrall 0:e7efc8468066 46 // USB host structures
d_worrall 0:e7efc8468066 47 // AHB SRAM block 1
d_worrall 0:e7efc8468066 48 #define HOSTBASEADDR 0x2007C000
d_worrall 0:e7efc8468066 49 // reserve memory for the linker
d_worrall 0:e7efc8468066 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
d_worrall 0:e7efc8468066 51 /*
d_worrall 0:e7efc8468066 52 **************************************************************************************************************
d_worrall 0:e7efc8468066 53 * DELAY IN MILLI SECONDS
d_worrall 0:e7efc8468066 54 *
d_worrall 0:e7efc8468066 55 * Description: This function provides a delay in milli seconds
d_worrall 0:e7efc8468066 56 *
d_worrall 0:e7efc8468066 57 * Arguments : delay The delay required
d_worrall 0:e7efc8468066 58 *
d_worrall 0:e7efc8468066 59 * Returns : None
d_worrall 0:e7efc8468066 60 *
d_worrall 0:e7efc8468066 61 **************************************************************************************************************
d_worrall 0:e7efc8468066 62 */
d_worrall 0:e7efc8468066 63
d_worrall 0:e7efc8468066 64 void Host_DelayMS (USB_INT32U delay)
d_worrall 0:e7efc8468066 65 {
d_worrall 0:e7efc8468066 66 volatile USB_INT32U i;
d_worrall 0:e7efc8468066 67
d_worrall 0:e7efc8468066 68
d_worrall 0:e7efc8468066 69 for (i = 0; i < delay; i++) {
d_worrall 0:e7efc8468066 70 Host_DelayUS(1000);
d_worrall 0:e7efc8468066 71 }
d_worrall 0:e7efc8468066 72 }
d_worrall 0:e7efc8468066 73
d_worrall 0:e7efc8468066 74 /*
d_worrall 0:e7efc8468066 75 **************************************************************************************************************
d_worrall 0:e7efc8468066 76 * DELAY IN MICRO SECONDS
d_worrall 0:e7efc8468066 77 *
d_worrall 0:e7efc8468066 78 * Description: This function provides a delay in micro seconds
d_worrall 0:e7efc8468066 79 *
d_worrall 0:e7efc8468066 80 * Arguments : delay The delay required
d_worrall 0:e7efc8468066 81 *
d_worrall 0:e7efc8468066 82 * Returns : None
d_worrall 0:e7efc8468066 83 *
d_worrall 0:e7efc8468066 84 **************************************************************************************************************
d_worrall 0:e7efc8468066 85 */
d_worrall 0:e7efc8468066 86
d_worrall 0:e7efc8468066 87 void Host_DelayUS (USB_INT32U delay)
d_worrall 0:e7efc8468066 88 {
d_worrall 0:e7efc8468066 89 volatile USB_INT32U i;
d_worrall 0:e7efc8468066 90
d_worrall 0:e7efc8468066 91
d_worrall 0:e7efc8468066 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
d_worrall 0:e7efc8468066 93 ;
d_worrall 0:e7efc8468066 94 }
d_worrall 0:e7efc8468066 95 }
d_worrall 0:e7efc8468066 96
d_worrall 0:e7efc8468066 97 // bits of the USB/OTG clock control register
d_worrall 0:e7efc8468066 98 #define HOST_CLK_EN (1<<0)
d_worrall 0:e7efc8468066 99 #define DEV_CLK_EN (1<<1)
d_worrall 0:e7efc8468066 100 #define PORTSEL_CLK_EN (1<<3)
d_worrall 0:e7efc8468066 101 #define AHB_CLK_EN (1<<4)
d_worrall 0:e7efc8468066 102
d_worrall 0:e7efc8468066 103 // bits of the USB/OTG clock status register
d_worrall 0:e7efc8468066 104 #define HOST_CLK_ON (1<<0)
d_worrall 0:e7efc8468066 105 #define DEV_CLK_ON (1<<1)
d_worrall 0:e7efc8468066 106 #define PORTSEL_CLK_ON (1<<3)
d_worrall 0:e7efc8468066 107 #define AHB_CLK_ON (1<<4)
d_worrall 0:e7efc8468066 108
d_worrall 0:e7efc8468066 109 // we need host clock, OTG/portsel clock and AHB clock
d_worrall 0:e7efc8468066 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
d_worrall 0:e7efc8468066 111
d_worrall 0:e7efc8468066 112 /*
d_worrall 0:e7efc8468066 113 **************************************************************************************************************
d_worrall 0:e7efc8468066 114 * INITIALIZE THE HOST CONTROLLER
d_worrall 0:e7efc8468066 115 *
d_worrall 0:e7efc8468066 116 * Description: This function initializes lpc17xx host controller
d_worrall 0:e7efc8468066 117 *
d_worrall 0:e7efc8468066 118 * Arguments : None
d_worrall 0:e7efc8468066 119 *
d_worrall 0:e7efc8468066 120 * Returns :
d_worrall 0:e7efc8468066 121 *
d_worrall 0:e7efc8468066 122 **************************************************************************************************************
d_worrall 0:e7efc8468066 123 */
d_worrall 0:e7efc8468066 124 void Host_Init (void)
d_worrall 0:e7efc8468066 125 {
d_worrall 0:e7efc8468066 126 PRINT_Log("In Host_Init\n");
d_worrall 0:e7efc8468066 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
d_worrall 0:e7efc8468066 128
d_worrall 0:e7efc8468066 129 // turn on power for USB
d_worrall 0:e7efc8468066 130 LPC_SC->PCONP |= (1UL<<31);
d_worrall 0:e7efc8468066 131 // Enable USB host clock, port selection and AHB clock
d_worrall 0:e7efc8468066 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
d_worrall 0:e7efc8468066 133 // Wait for clocks to become available
d_worrall 0:e7efc8468066 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
d_worrall 0:e7efc8468066 135 ;
d_worrall 0:e7efc8468066 136
d_worrall 0:e7efc8468066 137 // it seems the bits[0:1] mean the following
d_worrall 0:e7efc8468066 138 // 0: U1=device, U2=host
d_worrall 0:e7efc8468066 139 // 1: U1=host, U2=host
d_worrall 0:e7efc8468066 140 // 2: reserved
d_worrall 0:e7efc8468066 141 // 3: U1=host, U2=device
d_worrall 0:e7efc8468066 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
d_worrall 0:e7efc8468066 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
d_worrall 0:e7efc8468066 144 LPC_USB->OTGStCtrl |= 1;
d_worrall 0:e7efc8468066 145
d_worrall 0:e7efc8468066 146 // now that we've configured the ports, we can turn off the portsel clock
d_worrall 0:e7efc8468066 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
d_worrall 0:e7efc8468066 148
d_worrall 0:e7efc8468066 149 // power pins are not connected on mbed, so we can skip them
d_worrall 0:e7efc8468066 150 /* P1[18] = USB_UP_LED, 01 */
d_worrall 0:e7efc8468066 151 /* P1[19] = /USB_PPWR, 10 */
d_worrall 0:e7efc8468066 152 /* P1[22] = USB_PWRD, 10 */
d_worrall 0:e7efc8468066 153 /* P1[27] = /USB_OVRCR, 10 */
d_worrall 0:e7efc8468066 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
d_worrall 0:e7efc8468066 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
d_worrall 0:e7efc8468066 156 */
d_worrall 0:e7efc8468066 157
d_worrall 0:e7efc8468066 158 // configure USB D+/D- pins
d_worrall 0:e7efc8468066 159 /* P0[29] = USB_D+, 01 */
d_worrall 0:e7efc8468066 160 /* P0[30] = USB_D-, 01 */
d_worrall 0:e7efc8468066 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
d_worrall 0:e7efc8468066 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
d_worrall 0:e7efc8468066 163
d_worrall 0:e7efc8468066 164 PRINT_Log("Initializing Host Stack\n");
d_worrall 0:e7efc8468066 165
d_worrall 0:e7efc8468066 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
d_worrall 0:e7efc8468066 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
d_worrall 0:e7efc8468066 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
d_worrall 0:e7efc8468066 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
d_worrall 0:e7efc8468066 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
d_worrall 0:e7efc8468066 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
d_worrall 0:e7efc8468066 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
d_worrall 0:e7efc8468066 173
d_worrall 0:e7efc8468066 174 /* Initialize all the TDs, EDs and HCCA to 0 */
d_worrall 0:e7efc8468066 175 Host_EDInit(EDCtrl);
d_worrall 0:e7efc8468066 176 Host_EDInit(EDBulkIn);
d_worrall 0:e7efc8468066 177 Host_EDInit(EDBulkOut);
d_worrall 0:e7efc8468066 178 Host_TDInit(TDHead);
d_worrall 0:e7efc8468066 179 Host_TDInit(TDTail);
d_worrall 0:e7efc8468066 180 Host_HCCAInit(Hcca);
d_worrall 0:e7efc8468066 181
d_worrall 0:e7efc8468066 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
d_worrall 0:e7efc8468066 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
d_worrall 0:e7efc8468066 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
d_worrall 0:e7efc8468066 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
d_worrall 0:e7efc8468066 186
d_worrall 0:e7efc8468066 187 /* SOFTWARE RESET */
d_worrall 0:e7efc8468066 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
d_worrall 0:e7efc8468066 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
d_worrall 0:e7efc8468066 190
d_worrall 0:e7efc8468066 191 /* Put HC in operational state */
d_worrall 0:e7efc8468066 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
d_worrall 0:e7efc8468066 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
d_worrall 0:e7efc8468066 194
d_worrall 0:e7efc8468066 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
d_worrall 0:e7efc8468066 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
d_worrall 0:e7efc8468066 197
d_worrall 0:e7efc8468066 198
d_worrall 0:e7efc8468066 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
d_worrall 0:e7efc8468066 200 OR_INTR_ENABLE_WDH |
d_worrall 0:e7efc8468066 201 OR_INTR_ENABLE_RHSC;
d_worrall 0:e7efc8468066 202
d_worrall 0:e7efc8468066 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
d_worrall 0:e7efc8468066 204 /* Enable the USB Interrupt */
d_worrall 0:e7efc8468066 205 NVIC_EnableIRQ(USB_IRQn);
d_worrall 0:e7efc8468066 206 PRINT_Log("Host Initialized\n");
d_worrall 0:e7efc8468066 207 }
d_worrall 0:e7efc8468066 208
d_worrall 0:e7efc8468066 209 /*
d_worrall 0:e7efc8468066 210 **************************************************************************************************************
d_worrall 0:e7efc8468066 211 * INTERRUPT SERVICE ROUTINE
d_worrall 0:e7efc8468066 212 *
d_worrall 0:e7efc8468066 213 * Description: This function services the interrupt caused by host controller
d_worrall 0:e7efc8468066 214 *
d_worrall 0:e7efc8468066 215 * Arguments : None
d_worrall 0:e7efc8468066 216 *
d_worrall 0:e7efc8468066 217 * Returns : None
d_worrall 0:e7efc8468066 218 *
d_worrall 0:e7efc8468066 219 **************************************************************************************************************
d_worrall 0:e7efc8468066 220 */
d_worrall 0:e7efc8468066 221
d_worrall 0:e7efc8468066 222 void USB_IRQHandler (void) __irq
d_worrall 0:e7efc8468066 223 {
d_worrall 0:e7efc8468066 224 USB_INT32U int_status;
d_worrall 0:e7efc8468066 225 USB_INT32U ie_status;
d_worrall 0:e7efc8468066 226
d_worrall 0:e7efc8468066 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
d_worrall 0:e7efc8468066 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
d_worrall 0:e7efc8468066 229
d_worrall 0:e7efc8468066 230 if (!(int_status & ie_status)) {
d_worrall 0:e7efc8468066 231 return;
d_worrall 0:e7efc8468066 232 } else {
d_worrall 0:e7efc8468066 233
d_worrall 0:e7efc8468066 234 int_status = int_status & ie_status;
d_worrall 0:e7efc8468066 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
d_worrall 0:e7efc8468066 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
d_worrall 0:e7efc8468066 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
d_worrall 0:e7efc8468066 238 /*
d_worrall 0:e7efc8468066 239 * When DRWE is on, Connect Status Change
d_worrall 0:e7efc8468066 240 * means a remote wakeup event.
d_worrall 0:e7efc8468066 241 */
d_worrall 0:e7efc8468066 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
d_worrall 0:e7efc8468066 243 }
d_worrall 0:e7efc8468066 244 else {
d_worrall 0:e7efc8468066 245 /*
d_worrall 0:e7efc8468066 246 * When DRWE is off, Connect Status Change
d_worrall 0:e7efc8468066 247 * is NOT a remote wakeup event
d_worrall 0:e7efc8468066 248 */
d_worrall 0:e7efc8468066 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
d_worrall 0:e7efc8468066 250 if (!gUSBConnected) {
d_worrall 0:e7efc8468066 251 HOST_TDControlStatus = 0;
d_worrall 0:e7efc8468066 252 HOST_WdhIntr = 0;
d_worrall 0:e7efc8468066 253 HOST_RhscIntr = 1;
d_worrall 0:e7efc8468066 254 gUSBConnected = 1;
d_worrall 0:e7efc8468066 255 }
d_worrall 0:e7efc8468066 256 else
d_worrall 0:e7efc8468066 257 PRINT_Log("Spurious status change (connected)?\n");
d_worrall 0:e7efc8468066 258 } else {
d_worrall 0:e7efc8468066 259 if (gUSBConnected) {
d_worrall 0:e7efc8468066 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
d_worrall 0:e7efc8468066 261 HOST_RhscIntr = 0;
d_worrall 0:e7efc8468066 262 gUSBConnected = 0;
d_worrall 0:e7efc8468066 263 }
d_worrall 0:e7efc8468066 264 else
d_worrall 0:e7efc8468066 265 PRINT_Log("Spurious status change (disconnected)?\n");
d_worrall 0:e7efc8468066 266 }
d_worrall 0:e7efc8468066 267 }
d_worrall 0:e7efc8468066 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
d_worrall 0:e7efc8468066 269 }
d_worrall 0:e7efc8468066 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
d_worrall 0:e7efc8468066 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
d_worrall 0:e7efc8468066 272 }
d_worrall 0:e7efc8468066 273 }
d_worrall 0:e7efc8468066 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
d_worrall 0:e7efc8468066 275 HOST_WdhIntr = 1;
d_worrall 0:e7efc8468066 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
d_worrall 0:e7efc8468066 277 }
d_worrall 0:e7efc8468066 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
d_worrall 0:e7efc8468066 279 }
d_worrall 0:e7efc8468066 280 return;
d_worrall 0:e7efc8468066 281 }
d_worrall 0:e7efc8468066 282
d_worrall 0:e7efc8468066 283 /*
d_worrall 0:e7efc8468066 284 **************************************************************************************************************
d_worrall 0:e7efc8468066 285 * PROCESS TRANSFER DESCRIPTOR
d_worrall 0:e7efc8468066 286 *
d_worrall 0:e7efc8468066 287 * Description: This function processes the transfer descriptor
d_worrall 0:e7efc8468066 288 *
d_worrall 0:e7efc8468066 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
d_worrall 0:e7efc8468066 290 * token SETUP, IN, OUT
d_worrall 0:e7efc8468066 291 * buffer Current Buffer Pointer of the transfer descriptor
d_worrall 0:e7efc8468066 292 * buffer_len Length of the buffer
d_worrall 0:e7efc8468066 293 *
d_worrall 0:e7efc8468066 294 * Returns : OK if TD submission is successful
d_worrall 0:e7efc8468066 295 * ERROR if TD submission fails
d_worrall 0:e7efc8468066 296 *
d_worrall 0:e7efc8468066 297 **************************************************************************************************************
d_worrall 0:e7efc8468066 298 */
d_worrall 0:e7efc8468066 299
d_worrall 0:e7efc8468066 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
d_worrall 0:e7efc8468066 301 volatile USB_INT32U token,
d_worrall 0:e7efc8468066 302 volatile USB_INT08U *buffer,
d_worrall 0:e7efc8468066 303 USB_INT32U buffer_len)
d_worrall 0:e7efc8468066 304 {
d_worrall 0:e7efc8468066 305 volatile USB_INT32U td_toggle;
d_worrall 0:e7efc8468066 306
d_worrall 0:e7efc8468066 307
d_worrall 0:e7efc8468066 308 if (ed == EDCtrl) {
d_worrall 0:e7efc8468066 309 if (token == TD_SETUP) {
d_worrall 0:e7efc8468066 310 td_toggle = TD_TOGGLE_0;
d_worrall 0:e7efc8468066 311 } else {
d_worrall 0:e7efc8468066 312 td_toggle = TD_TOGGLE_1;
d_worrall 0:e7efc8468066 313 }
d_worrall 0:e7efc8468066 314 } else {
d_worrall 0:e7efc8468066 315 td_toggle = 0;
d_worrall 0:e7efc8468066 316 }
d_worrall 0:e7efc8468066 317 TDHead->Control = (TD_ROUNDING |
d_worrall 0:e7efc8468066 318 token |
d_worrall 0:e7efc8468066 319 TD_DELAY_INT(0) |
d_worrall 0:e7efc8468066 320 td_toggle |
d_worrall 0:e7efc8468066 321 TD_CC);
d_worrall 0:e7efc8468066 322 TDTail->Control = 0;
d_worrall 0:e7efc8468066 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
d_worrall 0:e7efc8468066 324 TDTail->CurrBufPtr = 0;
d_worrall 0:e7efc8468066 325 TDHead->Next = (USB_INT32U) TDTail;
d_worrall 0:e7efc8468066 326 TDTail->Next = 0;
d_worrall 0:e7efc8468066 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
d_worrall 0:e7efc8468066 328 TDTail->BufEnd = 0;
d_worrall 0:e7efc8468066 329
d_worrall 0:e7efc8468066 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
d_worrall 0:e7efc8468066 331 ed->TailTd = (USB_INT32U)TDTail;
d_worrall 0:e7efc8468066 332 ed->Next = 0;
d_worrall 0:e7efc8468066 333
d_worrall 0:e7efc8468066 334 if (ed == EDCtrl) {
d_worrall 0:e7efc8468066 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
d_worrall 0:e7efc8468066 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
d_worrall 0:e7efc8468066 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
d_worrall 0:e7efc8468066 338 } else {
d_worrall 0:e7efc8468066 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
d_worrall 0:e7efc8468066 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
d_worrall 0:e7efc8468066 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
d_worrall 0:e7efc8468066 342 }
d_worrall 0:e7efc8468066 343
d_worrall 0:e7efc8468066 344 Host_WDHWait();
d_worrall 0:e7efc8468066 345
d_worrall 0:e7efc8468066 346 // if (!(TDHead->Control & 0xF0000000)) {
d_worrall 0:e7efc8468066 347 if (!HOST_TDControlStatus) {
d_worrall 0:e7efc8468066 348 return (OK);
d_worrall 0:e7efc8468066 349 } else {
d_worrall 0:e7efc8468066 350 return (ERR_TD_FAIL);
d_worrall 0:e7efc8468066 351 }
d_worrall 0:e7efc8468066 352 }
d_worrall 0:e7efc8468066 353
d_worrall 0:e7efc8468066 354 /*
d_worrall 0:e7efc8468066 355 **************************************************************************************************************
d_worrall 0:e7efc8468066 356 * ENUMERATE THE DEVICE
d_worrall 0:e7efc8468066 357 *
d_worrall 0:e7efc8468066 358 * Description: This function is used to enumerate the device connected
d_worrall 0:e7efc8468066 359 *
d_worrall 0:e7efc8468066 360 * Arguments : None
d_worrall 0:e7efc8468066 361 *
d_worrall 0:e7efc8468066 362 * Returns : None
d_worrall 0:e7efc8468066 363 *
d_worrall 0:e7efc8468066 364 **************************************************************************************************************
d_worrall 0:e7efc8468066 365 */
d_worrall 0:e7efc8468066 366
d_worrall 0:e7efc8468066 367 USB_INT32S Host_EnumDev (void)
d_worrall 0:e7efc8468066 368 {
d_worrall 0:e7efc8468066 369 USB_INT32S rc;
d_worrall 0:e7efc8468066 370
d_worrall 0:e7efc8468066 371 PRINT_Log("Connect a Mass Storage device\n");
d_worrall 0:e7efc8468066 372 while (!HOST_RhscIntr)
d_worrall 0:e7efc8468066 373 __WFI();
d_worrall 0:e7efc8468066 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
d_worrall 0:e7efc8468066 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
d_worrall 0:e7efc8468066 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
d_worrall 0:e7efc8468066 377 __WFI(); // Wait for port reset to complete...
d_worrall 0:e7efc8468066 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
d_worrall 0:e7efc8468066 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
d_worrall 0:e7efc8468066 380
d_worrall 0:e7efc8468066 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
d_worrall 0:e7efc8468066 382 /* Read first 8 bytes of device desc */
d_worrall 0:e7efc8468066 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
d_worrall 0:e7efc8468066 384 if (rc != OK) {
d_worrall 0:e7efc8468066 385 PRINT_Err(rc);
d_worrall 0:e7efc8468066 386 return (rc);
d_worrall 0:e7efc8468066 387 }
d_worrall 0:e7efc8468066 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
d_worrall 0:e7efc8468066 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
d_worrall 0:e7efc8468066 390 if (rc != OK) {
d_worrall 0:e7efc8468066 391 PRINT_Err(rc);
d_worrall 0:e7efc8468066 392 return (rc);
d_worrall 0:e7efc8468066 393 }
d_worrall 0:e7efc8468066 394 Host_DelayMS(2);
d_worrall 0:e7efc8468066 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
d_worrall 0:e7efc8468066 396 /* Get the configuration descriptor */
d_worrall 0:e7efc8468066 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
d_worrall 0:e7efc8468066 398 if (rc != OK) {
d_worrall 0:e7efc8468066 399 PRINT_Err(rc);
d_worrall 0:e7efc8468066 400 return (rc);
d_worrall 0:e7efc8468066 401 }
d_worrall 0:e7efc8468066 402 /* Get the first configuration data */
d_worrall 0:e7efc8468066 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
d_worrall 0:e7efc8468066 404 if (rc != OK) {
d_worrall 0:e7efc8468066 405 PRINT_Err(rc);
d_worrall 0:e7efc8468066 406 return (rc);
d_worrall 0:e7efc8468066 407 }
d_worrall 0:e7efc8468066 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
d_worrall 0:e7efc8468066 409 if (rc != OK) {
d_worrall 0:e7efc8468066 410 PRINT_Err(rc);
d_worrall 0:e7efc8468066 411 return (rc);
d_worrall 0:e7efc8468066 412 }
d_worrall 0:e7efc8468066 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
d_worrall 0:e7efc8468066 414 if (rc != OK) {
d_worrall 0:e7efc8468066 415 PRINT_Err(rc);
d_worrall 0:e7efc8468066 416 }
d_worrall 0:e7efc8468066 417 Host_DelayMS(100); /* Some devices may require this delay */
d_worrall 0:e7efc8468066 418 return (rc);
d_worrall 0:e7efc8468066 419 }
d_worrall 0:e7efc8468066 420
d_worrall 0:e7efc8468066 421 /*
d_worrall 0:e7efc8468066 422 **************************************************************************************************************
d_worrall 0:e7efc8468066 423 * RECEIVE THE CONTROL INFORMATION
d_worrall 0:e7efc8468066 424 *
d_worrall 0:e7efc8468066 425 * Description: This function is used to receive the control information
d_worrall 0:e7efc8468066 426 *
d_worrall 0:e7efc8468066 427 * Arguments : bm_request_type
d_worrall 0:e7efc8468066 428 * b_request
d_worrall 0:e7efc8468066 429 * w_value
d_worrall 0:e7efc8468066 430 * w_index
d_worrall 0:e7efc8468066 431 * w_length
d_worrall 0:e7efc8468066 432 * buffer
d_worrall 0:e7efc8468066 433 *
d_worrall 0:e7efc8468066 434 * Returns : OK if Success
d_worrall 0:e7efc8468066 435 * ERROR if Failed
d_worrall 0:e7efc8468066 436 *
d_worrall 0:e7efc8468066 437 **************************************************************************************************************
d_worrall 0:e7efc8468066 438 */
d_worrall 0:e7efc8468066 439
d_worrall 0:e7efc8468066 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
d_worrall 0:e7efc8468066 441 USB_INT08U b_request,
d_worrall 0:e7efc8468066 442 USB_INT16U w_value,
d_worrall 0:e7efc8468066 443 USB_INT16U w_index,
d_worrall 0:e7efc8468066 444 USB_INT16U w_length,
d_worrall 0:e7efc8468066 445 volatile USB_INT08U *buffer)
d_worrall 0:e7efc8468066 446 {
d_worrall 0:e7efc8468066 447 USB_INT32S rc;
d_worrall 0:e7efc8468066 448
d_worrall 0:e7efc8468066 449
d_worrall 0:e7efc8468066 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
d_worrall 0:e7efc8468066 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
d_worrall 0:e7efc8468066 452 if (rc == OK) {
d_worrall 0:e7efc8468066 453 if (w_length) {
d_worrall 0:e7efc8468066 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
d_worrall 0:e7efc8468066 455 }
d_worrall 0:e7efc8468066 456 if (rc == OK) {
d_worrall 0:e7efc8468066 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
d_worrall 0:e7efc8468066 458 }
d_worrall 0:e7efc8468066 459 }
d_worrall 0:e7efc8468066 460 return (rc);
d_worrall 0:e7efc8468066 461 }
d_worrall 0:e7efc8468066 462
d_worrall 0:e7efc8468066 463 /*
d_worrall 0:e7efc8468066 464 **************************************************************************************************************
d_worrall 0:e7efc8468066 465 * SEND THE CONTROL INFORMATION
d_worrall 0:e7efc8468066 466 *
d_worrall 0:e7efc8468066 467 * Description: This function is used to send the control information
d_worrall 0:e7efc8468066 468 *
d_worrall 0:e7efc8468066 469 * Arguments : None
d_worrall 0:e7efc8468066 470 *
d_worrall 0:e7efc8468066 471 * Returns : OK if Success
d_worrall 0:e7efc8468066 472 * ERR_INVALID_BOOTSIG if Failed
d_worrall 0:e7efc8468066 473 *
d_worrall 0:e7efc8468066 474 **************************************************************************************************************
d_worrall 0:e7efc8468066 475 */
d_worrall 0:e7efc8468066 476
d_worrall 0:e7efc8468066 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
d_worrall 0:e7efc8468066 478 USB_INT08U b_request,
d_worrall 0:e7efc8468066 479 USB_INT16U w_value,
d_worrall 0:e7efc8468066 480 USB_INT16U w_index,
d_worrall 0:e7efc8468066 481 USB_INT16U w_length,
d_worrall 0:e7efc8468066 482 volatile USB_INT08U *buffer)
d_worrall 0:e7efc8468066 483 {
d_worrall 0:e7efc8468066 484 USB_INT32S rc;
d_worrall 0:e7efc8468066 485
d_worrall 0:e7efc8468066 486
d_worrall 0:e7efc8468066 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
d_worrall 0:e7efc8468066 488
d_worrall 0:e7efc8468066 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
d_worrall 0:e7efc8468066 490 if (rc == OK) {
d_worrall 0:e7efc8468066 491 if (w_length) {
d_worrall 0:e7efc8468066 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
d_worrall 0:e7efc8468066 493 }
d_worrall 0:e7efc8468066 494 if (rc == OK) {
d_worrall 0:e7efc8468066 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
d_worrall 0:e7efc8468066 496 }
d_worrall 0:e7efc8468066 497 }
d_worrall 0:e7efc8468066 498 return (rc);
d_worrall 0:e7efc8468066 499 }
d_worrall 0:e7efc8468066 500
d_worrall 0:e7efc8468066 501 /*
d_worrall 0:e7efc8468066 502 **************************************************************************************************************
d_worrall 0:e7efc8468066 503 * FILL SETUP PACKET
d_worrall 0:e7efc8468066 504 *
d_worrall 0:e7efc8468066 505 * Description: This function is used to fill the setup packet
d_worrall 0:e7efc8468066 506 *
d_worrall 0:e7efc8468066 507 * Arguments : None
d_worrall 0:e7efc8468066 508 *
d_worrall 0:e7efc8468066 509 * Returns : OK if Success
d_worrall 0:e7efc8468066 510 * ERR_INVALID_BOOTSIG if Failed
d_worrall 0:e7efc8468066 511 *
d_worrall 0:e7efc8468066 512 **************************************************************************************************************
d_worrall 0:e7efc8468066 513 */
d_worrall 0:e7efc8468066 514
d_worrall 0:e7efc8468066 515 void Host_FillSetup (USB_INT08U bm_request_type,
d_worrall 0:e7efc8468066 516 USB_INT08U b_request,
d_worrall 0:e7efc8468066 517 USB_INT16U w_value,
d_worrall 0:e7efc8468066 518 USB_INT16U w_index,
d_worrall 0:e7efc8468066 519 USB_INT16U w_length)
d_worrall 0:e7efc8468066 520 {
d_worrall 0:e7efc8468066 521 int i;
d_worrall 0:e7efc8468066 522 for (i=0;i<w_length;i++)
d_worrall 0:e7efc8468066 523 TDBuffer[i] = 0;
d_worrall 0:e7efc8468066 524
d_worrall 0:e7efc8468066 525 TDBuffer[0] = bm_request_type;
d_worrall 0:e7efc8468066 526 TDBuffer[1] = b_request;
d_worrall 0:e7efc8468066 527 WriteLE16U(&TDBuffer[2], w_value);
d_worrall 0:e7efc8468066 528 WriteLE16U(&TDBuffer[4], w_index);
d_worrall 0:e7efc8468066 529 WriteLE16U(&TDBuffer[6], w_length);
d_worrall 0:e7efc8468066 530 }
d_worrall 0:e7efc8468066 531
d_worrall 0:e7efc8468066 532
d_worrall 0:e7efc8468066 533
d_worrall 0:e7efc8468066 534 /*
d_worrall 0:e7efc8468066 535 **************************************************************************************************************
d_worrall 0:e7efc8468066 536 * INITIALIZE THE TRANSFER DESCRIPTOR
d_worrall 0:e7efc8468066 537 *
d_worrall 0:e7efc8468066 538 * Description: This function initializes transfer descriptor
d_worrall 0:e7efc8468066 539 *
d_worrall 0:e7efc8468066 540 * Arguments : Pointer to TD structure
d_worrall 0:e7efc8468066 541 *
d_worrall 0:e7efc8468066 542 * Returns : None
d_worrall 0:e7efc8468066 543 *
d_worrall 0:e7efc8468066 544 **************************************************************************************************************
d_worrall 0:e7efc8468066 545 */
d_worrall 0:e7efc8468066 546
d_worrall 0:e7efc8468066 547 void Host_TDInit (volatile HCTD *td)
d_worrall 0:e7efc8468066 548 {
d_worrall 0:e7efc8468066 549
d_worrall 0:e7efc8468066 550 td->Control = 0;
d_worrall 0:e7efc8468066 551 td->CurrBufPtr = 0;
d_worrall 0:e7efc8468066 552 td->Next = 0;
d_worrall 0:e7efc8468066 553 td->BufEnd = 0;
d_worrall 0:e7efc8468066 554 }
d_worrall 0:e7efc8468066 555
d_worrall 0:e7efc8468066 556 /*
d_worrall 0:e7efc8468066 557 **************************************************************************************************************
d_worrall 0:e7efc8468066 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
d_worrall 0:e7efc8468066 559 *
d_worrall 0:e7efc8468066 560 * Description: This function initializes endpoint descriptor
d_worrall 0:e7efc8468066 561 *
d_worrall 0:e7efc8468066 562 * Arguments : Pointer to ED strcuture
d_worrall 0:e7efc8468066 563 *
d_worrall 0:e7efc8468066 564 * Returns : None
d_worrall 0:e7efc8468066 565 *
d_worrall 0:e7efc8468066 566 **************************************************************************************************************
d_worrall 0:e7efc8468066 567 */
d_worrall 0:e7efc8468066 568
d_worrall 0:e7efc8468066 569 void Host_EDInit (volatile HCED *ed)
d_worrall 0:e7efc8468066 570 {
d_worrall 0:e7efc8468066 571
d_worrall 0:e7efc8468066 572 ed->Control = 0;
d_worrall 0:e7efc8468066 573 ed->TailTd = 0;
d_worrall 0:e7efc8468066 574 ed->HeadTd = 0;
d_worrall 0:e7efc8468066 575 ed->Next = 0;
d_worrall 0:e7efc8468066 576 }
d_worrall 0:e7efc8468066 577
d_worrall 0:e7efc8468066 578 /*
d_worrall 0:e7efc8468066 579 **************************************************************************************************************
d_worrall 0:e7efc8468066 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
d_worrall 0:e7efc8468066 581 *
d_worrall 0:e7efc8468066 582 * Description: This function initializes host controller communications area
d_worrall 0:e7efc8468066 583 *
d_worrall 0:e7efc8468066 584 * Arguments : Pointer to HCCA
d_worrall 0:e7efc8468066 585 *
d_worrall 0:e7efc8468066 586 * Returns :
d_worrall 0:e7efc8468066 587 *
d_worrall 0:e7efc8468066 588 **************************************************************************************************************
d_worrall 0:e7efc8468066 589 */
d_worrall 0:e7efc8468066 590
d_worrall 0:e7efc8468066 591 void Host_HCCAInit (volatile HCCA *hcca)
d_worrall 0:e7efc8468066 592 {
d_worrall 0:e7efc8468066 593 USB_INT32U i;
d_worrall 0:e7efc8468066 594
d_worrall 0:e7efc8468066 595
d_worrall 0:e7efc8468066 596 for (i = 0; i < 32; i++) {
d_worrall 0:e7efc8468066 597
d_worrall 0:e7efc8468066 598 hcca->IntTable[i] = 0;
d_worrall 0:e7efc8468066 599 hcca->FrameNumber = 0;
d_worrall 0:e7efc8468066 600 hcca->DoneHead = 0;
d_worrall 0:e7efc8468066 601 }
d_worrall 0:e7efc8468066 602
d_worrall 0:e7efc8468066 603 }
d_worrall 0:e7efc8468066 604
d_worrall 0:e7efc8468066 605 /*
d_worrall 0:e7efc8468066 606 **************************************************************************************************************
d_worrall 0:e7efc8468066 607 * WAIT FOR WDH INTERRUPT
d_worrall 0:e7efc8468066 608 *
d_worrall 0:e7efc8468066 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
d_worrall 0:e7efc8468066 610 *
d_worrall 0:e7efc8468066 611 * Arguments : None
d_worrall 0:e7efc8468066 612 *
d_worrall 0:e7efc8468066 613 * Returns : None
d_worrall 0:e7efc8468066 614 *
d_worrall 0:e7efc8468066 615 **************************************************************************************************************
d_worrall 0:e7efc8468066 616 */
d_worrall 0:e7efc8468066 617
d_worrall 0:e7efc8468066 618 void Host_WDHWait (void)
d_worrall 0:e7efc8468066 619 {
d_worrall 0:e7efc8468066 620 while (!HOST_WdhIntr)
d_worrall 0:e7efc8468066 621 __WFI();
d_worrall 0:e7efc8468066 622
d_worrall 0:e7efc8468066 623 HOST_WdhIntr = 0;
d_worrall 0:e7efc8468066 624 }
d_worrall 0:e7efc8468066 625
d_worrall 0:e7efc8468066 626 /*
d_worrall 0:e7efc8468066 627 **************************************************************************************************************
d_worrall 0:e7efc8468066 628 * READ LE 32U
d_worrall 0:e7efc8468066 629 *
d_worrall 0:e7efc8468066 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
d_worrall 0:e7efc8468066 631 * containing little endian processor
d_worrall 0:e7efc8468066 632 *
d_worrall 0:e7efc8468066 633 * Arguments : pmem Pointer to the character buffer
d_worrall 0:e7efc8468066 634 *
d_worrall 0:e7efc8468066 635 * Returns : val Unsigned integer
d_worrall 0:e7efc8468066 636 *
d_worrall 0:e7efc8468066 637 **************************************************************************************************************
d_worrall 0:e7efc8468066 638 */
d_worrall 0:e7efc8468066 639
d_worrall 0:e7efc8468066 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
d_worrall 0:e7efc8468066 641 {
d_worrall 0:e7efc8468066 642 USB_INT32U val = *(USB_INT32U*)pmem;
d_worrall 0:e7efc8468066 643 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 644 return __REV(val);
d_worrall 0:e7efc8468066 645 #else
d_worrall 0:e7efc8468066 646 return val;
d_worrall 0:e7efc8468066 647 #endif
d_worrall 0:e7efc8468066 648 }
d_worrall 0:e7efc8468066 649
d_worrall 0:e7efc8468066 650 /*
d_worrall 0:e7efc8468066 651 **************************************************************************************************************
d_worrall 0:e7efc8468066 652 * WRITE LE 32U
d_worrall 0:e7efc8468066 653 *
d_worrall 0:e7efc8468066 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
d_worrall 0:e7efc8468066 655 * containing little endian processor.
d_worrall 0:e7efc8468066 656 *
d_worrall 0:e7efc8468066 657 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 658 * val Integer value to be placed in the charecter buffer
d_worrall 0:e7efc8468066 659 *
d_worrall 0:e7efc8468066 660 * Returns : None
d_worrall 0:e7efc8468066 661 *
d_worrall 0:e7efc8468066 662 **************************************************************************************************************
d_worrall 0:e7efc8468066 663 */
d_worrall 0:e7efc8468066 664
d_worrall 0:e7efc8468066 665 void WriteLE32U (volatile USB_INT08U *pmem,
d_worrall 0:e7efc8468066 666 USB_INT32U val)
d_worrall 0:e7efc8468066 667 {
d_worrall 0:e7efc8468066 668 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 669 *(USB_INT32U*)pmem = __REV(val);
d_worrall 0:e7efc8468066 670 #else
d_worrall 0:e7efc8468066 671 *(USB_INT32U*)pmem = val;
d_worrall 0:e7efc8468066 672 #endif
d_worrall 0:e7efc8468066 673 }
d_worrall 0:e7efc8468066 674
d_worrall 0:e7efc8468066 675 /*
d_worrall 0:e7efc8468066 676 **************************************************************************************************************
d_worrall 0:e7efc8468066 677 * READ LE 16U
d_worrall 0:e7efc8468066 678 *
d_worrall 0:e7efc8468066 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
d_worrall 0:e7efc8468066 680 * containing little endian processor
d_worrall 0:e7efc8468066 681 *
d_worrall 0:e7efc8468066 682 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 683 *
d_worrall 0:e7efc8468066 684 * Returns : val Unsigned short integer
d_worrall 0:e7efc8468066 685 *
d_worrall 0:e7efc8468066 686 **************************************************************************************************************
d_worrall 0:e7efc8468066 687 */
d_worrall 0:e7efc8468066 688
d_worrall 0:e7efc8468066 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
d_worrall 0:e7efc8468066 690 {
d_worrall 0:e7efc8468066 691 USB_INT16U val = *(USB_INT16U*)pmem;
d_worrall 0:e7efc8468066 692 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 693 return __REV16(val);
d_worrall 0:e7efc8468066 694 #else
d_worrall 0:e7efc8468066 695 return val;
d_worrall 0:e7efc8468066 696 #endif
d_worrall 0:e7efc8468066 697 }
d_worrall 0:e7efc8468066 698
d_worrall 0:e7efc8468066 699 /*
d_worrall 0:e7efc8468066 700 **************************************************************************************************************
d_worrall 0:e7efc8468066 701 * WRITE LE 16U
d_worrall 0:e7efc8468066 702 *
d_worrall 0:e7efc8468066 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
d_worrall 0:e7efc8468066 704 * platform containing little endian processor
d_worrall 0:e7efc8468066 705 *
d_worrall 0:e7efc8468066 706 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 707 * val Value to be placed in the charecter buffer
d_worrall 0:e7efc8468066 708 *
d_worrall 0:e7efc8468066 709 * Returns : None
d_worrall 0:e7efc8468066 710 *
d_worrall 0:e7efc8468066 711 **************************************************************************************************************
d_worrall 0:e7efc8468066 712 */
d_worrall 0:e7efc8468066 713
d_worrall 0:e7efc8468066 714 void WriteLE16U (volatile USB_INT08U *pmem,
d_worrall 0:e7efc8468066 715 USB_INT16U val)
d_worrall 0:e7efc8468066 716 {
d_worrall 0:e7efc8468066 717 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
d_worrall 0:e7efc8468066 719 #else
d_worrall 0:e7efc8468066 720 *(USB_INT16U*)pmem = val;
d_worrall 0:e7efc8468066 721 #endif
d_worrall 0:e7efc8468066 722 }
d_worrall 0:e7efc8468066 723
d_worrall 0:e7efc8468066 724 /*
d_worrall 0:e7efc8468066 725 **************************************************************************************************************
d_worrall 0:e7efc8468066 726 * READ BE 32U
d_worrall 0:e7efc8468066 727 *
d_worrall 0:e7efc8468066 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
d_worrall 0:e7efc8468066 729 * containing big endian processor
d_worrall 0:e7efc8468066 730 *
d_worrall 0:e7efc8468066 731 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 732 *
d_worrall 0:e7efc8468066 733 * Returns : val Unsigned integer
d_worrall 0:e7efc8468066 734 *
d_worrall 0:e7efc8468066 735 **************************************************************************************************************
d_worrall 0:e7efc8468066 736 */
d_worrall 0:e7efc8468066 737
d_worrall 0:e7efc8468066 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
d_worrall 0:e7efc8468066 739 {
d_worrall 0:e7efc8468066 740 USB_INT32U val = *(USB_INT32U*)pmem;
d_worrall 0:e7efc8468066 741 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 742 return val;
d_worrall 0:e7efc8468066 743 #else
d_worrall 0:e7efc8468066 744 return __REV(val);
d_worrall 0:e7efc8468066 745 #endif
d_worrall 0:e7efc8468066 746 }
d_worrall 0:e7efc8468066 747
d_worrall 0:e7efc8468066 748 /*
d_worrall 0:e7efc8468066 749 **************************************************************************************************************
d_worrall 0:e7efc8468066 750 * WRITE BE 32U
d_worrall 0:e7efc8468066 751 *
d_worrall 0:e7efc8468066 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
d_worrall 0:e7efc8468066 753 * containing big endian processor
d_worrall 0:e7efc8468066 754 *
d_worrall 0:e7efc8468066 755 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 756 * val Value to be placed in the charecter buffer
d_worrall 0:e7efc8468066 757 *
d_worrall 0:e7efc8468066 758 * Returns : None
d_worrall 0:e7efc8468066 759 *
d_worrall 0:e7efc8468066 760 **************************************************************************************************************
d_worrall 0:e7efc8468066 761 */
d_worrall 0:e7efc8468066 762
d_worrall 0:e7efc8468066 763 void WriteBE32U (volatile USB_INT08U *pmem,
d_worrall 0:e7efc8468066 764 USB_INT32U val)
d_worrall 0:e7efc8468066 765 {
d_worrall 0:e7efc8468066 766 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 767 *(USB_INT32U*)pmem = val;
d_worrall 0:e7efc8468066 768 #else
d_worrall 0:e7efc8468066 769 *(USB_INT32U*)pmem = __REV(val);
d_worrall 0:e7efc8468066 770 #endif
d_worrall 0:e7efc8468066 771 }
d_worrall 0:e7efc8468066 772
d_worrall 0:e7efc8468066 773 /*
d_worrall 0:e7efc8468066 774 **************************************************************************************************************
d_worrall 0:e7efc8468066 775 * READ BE 16U
d_worrall 0:e7efc8468066 776 *
d_worrall 0:e7efc8468066 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
d_worrall 0:e7efc8468066 778 * containing big endian processor
d_worrall 0:e7efc8468066 779 *
d_worrall 0:e7efc8468066 780 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 781 *
d_worrall 0:e7efc8468066 782 * Returns : val Unsigned short integer
d_worrall 0:e7efc8468066 783 *
d_worrall 0:e7efc8468066 784 **************************************************************************************************************
d_worrall 0:e7efc8468066 785 */
d_worrall 0:e7efc8468066 786
d_worrall 0:e7efc8468066 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
d_worrall 0:e7efc8468066 788 {
d_worrall 0:e7efc8468066 789 USB_INT16U val = *(USB_INT16U*)pmem;
d_worrall 0:e7efc8468066 790 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 791 return val;
d_worrall 0:e7efc8468066 792 #else
d_worrall 0:e7efc8468066 793 return __REV16(val);
d_worrall 0:e7efc8468066 794 #endif
d_worrall 0:e7efc8468066 795 }
d_worrall 0:e7efc8468066 796
d_worrall 0:e7efc8468066 797 /*
d_worrall 0:e7efc8468066 798 **************************************************************************************************************
d_worrall 0:e7efc8468066 799 * WRITE BE 16U
d_worrall 0:e7efc8468066 800 *
d_worrall 0:e7efc8468066 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
d_worrall 0:e7efc8468066 802 * platform containing big endian processor
d_worrall 0:e7efc8468066 803 *
d_worrall 0:e7efc8468066 804 * Arguments : pmem Pointer to the charecter buffer
d_worrall 0:e7efc8468066 805 * val Value to be placed in the charecter buffer
d_worrall 0:e7efc8468066 806 *
d_worrall 0:e7efc8468066 807 * Returns : None
d_worrall 0:e7efc8468066 808 *
d_worrall 0:e7efc8468066 809 **************************************************************************************************************
d_worrall 0:e7efc8468066 810 */
d_worrall 0:e7efc8468066 811
d_worrall 0:e7efc8468066 812 void WriteBE16U (volatile USB_INT08U *pmem,
d_worrall 0:e7efc8468066 813 USB_INT16U val)
d_worrall 0:e7efc8468066 814 {
d_worrall 0:e7efc8468066 815 #ifdef __BIG_ENDIAN
d_worrall 0:e7efc8468066 816 *(USB_INT16U*)pmem = val;
d_worrall 0:e7efc8468066 817 #else
d_worrall 0:e7efc8468066 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
d_worrall 0:e7efc8468066 819 #endif
d_worrall 0:e7efc8468066 820 }