An example program showing how to run the LPC11U24 without a crystal

Dependencies:   mbed

Committer:
chris
Date:
Thu Sep 20 12:17:46 2012 +0000
Revision:
1:0ad292799828
Parent:
0:00bd9bd5755f
Removed white space;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
chris 0:00bd9bd5755f 1 #include "mbed.h"
chris 0:00bd9bd5755f 2
chris 0:00bd9bd5755f 3 DigitalOut myled(LED1);
chris 0:00bd9bd5755f 4
chris 0:00bd9bd5755f 5 extern int stdio_retargeting_module;
chris 0:00bd9bd5755f 6
chris 0:00bd9bd5755f 7 /**
chris 0:00bd9bd5755f 8 * Initialize the system
chris 0:00bd9bd5755f 9 *
chris 0:00bd9bd5755f 10 * @param none
chris 0:00bd9bd5755f 11 * @return none
chris 0:00bd9bd5755f 12 *
chris 0:00bd9bd5755f 13 * @brief Setup the microcontroller system.
chris 0:00bd9bd5755f 14 * Initialize the System.
chris 0:00bd9bd5755f 15 */
chris 0:00bd9bd5755f 16 extern "C" void $Sub$$SystemInit (void)
chris 0:00bd9bd5755f 17 {
chris 0:00bd9bd5755f 18
chris 0:00bd9bd5755f 19 // select the PLL input
chris 0:00bd9bd5755f 20 LPC_SYSCON->SYSPLLCLKSEL = 0x0; // Select PLL Input source 0=IRC, 1=OSC
chris 0:00bd9bd5755f 21 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
chris 0:00bd9bd5755f 22 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
chris 0:00bd9bd5755f 23 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
chris 0:00bd9bd5755f 24 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
chris 0:00bd9bd5755f 25
chris 0:00bd9bd5755f 26 // Power up the system PLL
chris 0:00bd9bd5755f 27 LPC_SYSCON->SYSPLLCTRL = 0x00000023;
chris 0:00bd9bd5755f 28 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
chris 0:00bd9bd5755f 29 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
chris 0:00bd9bd5755f 30
chris 0:00bd9bd5755f 31 // Select the main clock source
chris 0:00bd9bd5755f 32 LPC_SYSCON->MAINCLKSEL = 0x3; // Select main Clock source, 0=IRC, 1=PLLin, 2=WDO, 3=PLLout
chris 0:00bd9bd5755f 33 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
chris 0:00bd9bd5755f 34 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
chris 0:00bd9bd5755f 35 LPC_SYSCON->MAINCLKUEN = 0x01;
chris 0:00bd9bd5755f 36 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
chris 0:00bd9bd5755f 37
chris 0:00bd9bd5755f 38 LPC_SYSCON->SYSAHBCLKDIV = 0x00000001;
chris 0:00bd9bd5755f 39
chris 0:00bd9bd5755f 40 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
chris 0:00bd9bd5755f 41 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
chris 0:00bd9bd5755f 42 LPC_SYSCON->USBPLLCLKSEL = 0x0; // 0=IRC, 1=System clock, only good for low speed
chris 0:00bd9bd5755f 43 LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
chris 0:00bd9bd5755f 44 LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
chris 0:00bd9bd5755f 45 LPC_SYSCON->USBPLLCLKUEN = 0x01;
chris 0:00bd9bd5755f 46
chris 0:00bd9bd5755f 47 while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
chris 0:00bd9bd5755f 48 LPC_SYSCON->USBPLLCTRL = 0x00000023;
chris 0:00bd9bd5755f 49
chris 0:00bd9bd5755f 50 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
chris 0:00bd9bd5755f 51 LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
chris 0:00bd9bd5755f 52
chris 0:00bd9bd5755f 53 LPC_SYSCON->USBCLKSEL = 0x00000000; /* Select USB Clock */
chris 0:00bd9bd5755f 54 LPC_SYSCON->USBCLKDIV = 0x00000001; /* Set USB clock divider */
chris 0:00bd9bd5755f 55
chris 0:00bd9bd5755f 56 /* System clock to the IOCON needs to be enabled or
chris 0:00bd9bd5755f 57 most of the I/O related peripherals won't work. */
chris 0:00bd9bd5755f 58 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
chris 0:00bd9bd5755f 59 stdio_retargeting_module = 1;
chris 0:00bd9bd5755f 60
chris 0:00bd9bd5755f 61 }
chris 0:00bd9bd5755f 62
chris 0:00bd9bd5755f 63
chris 0:00bd9bd5755f 64 int main()
chris 0:00bd9bd5755f 65 {
chris 0:00bd9bd5755f 66 while(1) {
chris 0:00bd9bd5755f 67 myled = 1;
chris 0:00bd9bd5755f 68 wait(0.25);
chris 0:00bd9bd5755f 69 myled = 0;
chris 0:00bd9bd5755f 70 wait(0.25);
chris 0:00bd9bd5755f 71 }
chris 0:00bd9bd5755f 72 }