Dependencies:   mbed

Committer:
chris
Date:
Sat Mar 13 17:19:08 2010 +0000
Revision:
0:144fed3d9420

        

Who changed what in which revision?

UserRevisionLine numberNew contents of line
chris 0:144fed3d9420 1 /*
chris 0:144fed3d9420 2 **************************************************************************************************************
chris 0:144fed3d9420 3 * NXP USB Host Stack
chris 0:144fed3d9420 4 *
chris 0:144fed3d9420 5 * (c) Copyright 2008, NXP SemiConductors
chris 0:144fed3d9420 6 * (c) Copyright 2008, OnChip Technologies LLC
chris 0:144fed3d9420 7 * All Rights Reserved
chris 0:144fed3d9420 8 *
chris 0:144fed3d9420 9 * www.nxp.com
chris 0:144fed3d9420 10 * www.onchiptech.com
chris 0:144fed3d9420 11 *
chris 0:144fed3d9420 12 * File : usbhost_lpc17xx.h
chris 0:144fed3d9420 13 * Programmer(s) : Ravikanth.P
chris 0:144fed3d9420 14 * Version :
chris 0:144fed3d9420 15 *
chris 0:144fed3d9420 16 **************************************************************************************************************
chris 0:144fed3d9420 17 */
chris 0:144fed3d9420 18
chris 0:144fed3d9420 19 #ifndef USBHOST_LPC17xx_H
chris 0:144fed3d9420 20 #define USBHOST_LPC17xx_H
chris 0:144fed3d9420 21
chris 0:144fed3d9420 22 /*
chris 0:144fed3d9420 23 **************************************************************************************************************
chris 0:144fed3d9420 24 * INCLUDE HEADER FILES
chris 0:144fed3d9420 25 **************************************************************************************************************
chris 0:144fed3d9420 26 */
chris 0:144fed3d9420 27
chris 0:144fed3d9420 28 #include "usbhost_inc.h"
chris 0:144fed3d9420 29
chris 0:144fed3d9420 30 /*
chris 0:144fed3d9420 31 **************************************************************************************************************
chris 0:144fed3d9420 32 * PRINT CONFIGURATION
chris 0:144fed3d9420 33 **************************************************************************************************************
chris 0:144fed3d9420 34 */
chris 0:144fed3d9420 35
chris 0:144fed3d9420 36 #define PRINT_ENABLE 1
chris 0:144fed3d9420 37
chris 0:144fed3d9420 38 #if PRINT_ENABLE
chris 0:144fed3d9420 39 #define PRINT_Log(...) printf(__VA_ARGS__)
chris 0:144fed3d9420 40 #define PRINT_Err(rc) printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
chris 0:144fed3d9420 41
chris 0:144fed3d9420 42 #else
chris 0:144fed3d9420 43 #define PRINT_Log(...) do {} while(0)
chris 0:144fed3d9420 44 #define PRINT_Err(rc) do {} while(0)
chris 0:144fed3d9420 45
chris 0:144fed3d9420 46 #endif
chris 0:144fed3d9420 47
chris 0:144fed3d9420 48 /*
chris 0:144fed3d9420 49 **************************************************************************************************************
chris 0:144fed3d9420 50 * GENERAL DEFINITIONS
chris 0:144fed3d9420 51 **************************************************************************************************************
chris 0:144fed3d9420 52 */
chris 0:144fed3d9420 53
chris 0:144fed3d9420 54 #define DESC_LENGTH(x) x[0]
chris 0:144fed3d9420 55 #define DESC_TYPE(x) x[1]
chris 0:144fed3d9420 56
chris 0:144fed3d9420 57
chris 0:144fed3d9420 58 #define HOST_GET_DESCRIPTOR(descType, descIndex, data, length) \
chris 0:144fed3d9420 59 Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR, \
chris 0:144fed3d9420 60 (descType << 8)|(descIndex), 0, length, data)
chris 0:144fed3d9420 61
chris 0:144fed3d9420 62 #define HOST_SET_ADDRESS(new_addr) \
chris 0:144fed3d9420 63 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS, \
chris 0:144fed3d9420 64 new_addr, 0, 0, NULL)
chris 0:144fed3d9420 65
chris 0:144fed3d9420 66 #define USBH_SET_CONFIGURATION(configNum) \
chris 0:144fed3d9420 67 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
chris 0:144fed3d9420 68 configNum, 0, 0, NULL)
chris 0:144fed3d9420 69
chris 0:144fed3d9420 70 #define USBH_SET_INTERFACE(ifNum, altNum) \
chris 0:144fed3d9420 71 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE, \
chris 0:144fed3d9420 72 altNum, ifNum, 0, NULL)
chris 0:144fed3d9420 73
chris 0:144fed3d9420 74 /*
chris 0:144fed3d9420 75 **************************************************************************************************************
chris 0:144fed3d9420 76 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
chris 0:144fed3d9420 77 **************************************************************************************************************
chris 0:144fed3d9420 78 */
chris 0:144fed3d9420 79
chris 0:144fed3d9420 80 /* ------------------ HcControl Register --------------------- */
chris 0:144fed3d9420 81 #define OR_CONTROL_CLE 0x00000010
chris 0:144fed3d9420 82 #define OR_CONTROL_BLE 0x00000020
chris 0:144fed3d9420 83 #define OR_CONTROL_HCFS 0x000000C0
chris 0:144fed3d9420 84 #define OR_CONTROL_HC_OPER 0x00000080
chris 0:144fed3d9420 85 /* ----------------- HcCommandStatus Register ----------------- */
chris 0:144fed3d9420 86 #define OR_CMD_STATUS_HCR 0x00000001
chris 0:144fed3d9420 87 #define OR_CMD_STATUS_CLF 0x00000002
chris 0:144fed3d9420 88 #define OR_CMD_STATUS_BLF 0x00000004
chris 0:144fed3d9420 89 /* --------------- HcInterruptStatus Register ----------------- */
chris 0:144fed3d9420 90 #define OR_INTR_STATUS_WDH 0x00000002
chris 0:144fed3d9420 91 #define OR_INTR_STATUS_RHSC 0x00000040
chris 0:144fed3d9420 92 /* --------------- HcInterruptEnable Register ----------------- */
chris 0:144fed3d9420 93 #define OR_INTR_ENABLE_WDH 0x00000002
chris 0:144fed3d9420 94 #define OR_INTR_ENABLE_RHSC 0x00000040
chris 0:144fed3d9420 95 #define OR_INTR_ENABLE_MIE 0x80000000
chris 0:144fed3d9420 96 /* ---------------- HcRhDescriptorA Register ------------------ */
chris 0:144fed3d9420 97 #define OR_RH_STATUS_LPSC 0x00010000
chris 0:144fed3d9420 98 #define OR_RH_STATUS_DRWE 0x00008000
chris 0:144fed3d9420 99 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
chris 0:144fed3d9420 100 #define OR_RH_PORT_CCS 0x00000001
chris 0:144fed3d9420 101 #define OR_RH_PORT_PRS 0x00000010
chris 0:144fed3d9420 102 #define OR_RH_PORT_CSC 0x00010000
chris 0:144fed3d9420 103 #define OR_RH_PORT_PRSC 0x00100000
chris 0:144fed3d9420 104
chris 0:144fed3d9420 105
chris 0:144fed3d9420 106 /*
chris 0:144fed3d9420 107 **************************************************************************************************************
chris 0:144fed3d9420 108 * FRAME INTERVAL
chris 0:144fed3d9420 109 **************************************************************************************************************
chris 0:144fed3d9420 110 */
chris 0:144fed3d9420 111
chris 0:144fed3d9420 112 #define FI 0x2EDF /* 12000 bits per frame (-1) */
chris 0:144fed3d9420 113 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
chris 0:144fed3d9420 114
chris 0:144fed3d9420 115 /*
chris 0:144fed3d9420 116 **************************************************************************************************************
chris 0:144fed3d9420 117 * TRANSFER DESCRIPTOR CONTROL FIELDS
chris 0:144fed3d9420 118 **************************************************************************************************************
chris 0:144fed3d9420 119 */
chris 0:144fed3d9420 120
chris 0:144fed3d9420 121 #define TD_ROUNDING (USB_INT32U) (0x00040000) /* Buffer Rounding */
chris 0:144fed3d9420 122 #define TD_SETUP (USB_INT32U)(0) /* Direction of Setup Packet */
chris 0:144fed3d9420 123 #define TD_IN (USB_INT32U)(0x00100000) /* Direction In */
chris 0:144fed3d9420 124 #define TD_OUT (USB_INT32U)(0x00080000) /* Direction Out */
chris 0:144fed3d9420 125 #define TD_DELAY_INT(x) (USB_INT32U)((x) << 21) /* Delay Interrupt */
chris 0:144fed3d9420 126 #define TD_TOGGLE_0 (USB_INT32U)(0x02000000) /* Toggle 0 */
chris 0:144fed3d9420 127 #define TD_TOGGLE_1 (USB_INT32U)(0x03000000) /* Toggle 1 */
chris 0:144fed3d9420 128 #define TD_CC (USB_INT32U)(0xF0000000) /* Completion Code */
chris 0:144fed3d9420 129
chris 0:144fed3d9420 130 /*
chris 0:144fed3d9420 131 **************************************************************************************************************
chris 0:144fed3d9420 132 * USB STANDARD REQUEST DEFINITIONS
chris 0:144fed3d9420 133 **************************************************************************************************************
chris 0:144fed3d9420 134 */
chris 0:144fed3d9420 135
chris 0:144fed3d9420 136 #define USB_DESCRIPTOR_TYPE_DEVICE 1
chris 0:144fed3d9420 137 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
chris 0:144fed3d9420 138 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
chris 0:144fed3d9420 139 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
chris 0:144fed3d9420 140 /* ----------- Control RequestType Fields ----------- */
chris 0:144fed3d9420 141 #define USB_DEVICE_TO_HOST 0x80
chris 0:144fed3d9420 142 #define USB_HOST_TO_DEVICE 0x00
chris 0:144fed3d9420 143 #define USB_REQUEST_TYPE_CLASS 0x20
chris 0:144fed3d9420 144 #define USB_RECIPIENT_DEVICE 0x00
chris 0:144fed3d9420 145 #define USB_RECIPIENT_INTERFACE 0x01
chris 0:144fed3d9420 146 /* -------------- USB Standard Requests -------------- */
chris 0:144fed3d9420 147 #define SET_ADDRESS 5
chris 0:144fed3d9420 148 #define GET_DESCRIPTOR 6
chris 0:144fed3d9420 149 #define SET_CONFIGURATION 9
chris 0:144fed3d9420 150 #define SET_INTERFACE 11
chris 0:144fed3d9420 151
chris 0:144fed3d9420 152 /*
chris 0:144fed3d9420 153 **************************************************************************************************************
chris 0:144fed3d9420 154 * TYPE DEFINITIONS
chris 0:144fed3d9420 155 **************************************************************************************************************
chris 0:144fed3d9420 156 */
chris 0:144fed3d9420 157
chris 0:144fed3d9420 158 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
chris 0:144fed3d9420 159 volatile USB_INT32U Control; /* Endpoint descriptor control */
chris 0:144fed3d9420 160 volatile USB_INT32U TailTd; /* Physical address of tail in Transfer descriptor list */
chris 0:144fed3d9420 161 volatile USB_INT32U HeadTd; /* Physcial address of head in Transfer descriptor list */
chris 0:144fed3d9420 162 volatile USB_INT32U Next; /* Physical address of next Endpoint descriptor */
chris 0:144fed3d9420 163 } HCED;
chris 0:144fed3d9420 164
chris 0:144fed3d9420 165 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
chris 0:144fed3d9420 166 volatile USB_INT32U Control; /* Transfer descriptor control */
chris 0:144fed3d9420 167 volatile USB_INT32U CurrBufPtr; /* Physical address of current buffer pointer */
chris 0:144fed3d9420 168 volatile USB_INT32U Next; /* Physical pointer to next Transfer Descriptor */
chris 0:144fed3d9420 169 volatile USB_INT32U BufEnd; /* Physical address of end of buffer */
chris 0:144fed3d9420 170 } HCTD;
chris 0:144fed3d9420 171
chris 0:144fed3d9420 172 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
chris 0:144fed3d9420 173 volatile USB_INT32U IntTable[32]; /* Interrupt Table */
chris 0:144fed3d9420 174 volatile USB_INT32U FrameNumber; /* Frame Number */
chris 0:144fed3d9420 175 volatile USB_INT32U DoneHead; /* Done Head */
chris 0:144fed3d9420 176 volatile USB_INT08U Reserved[116]; /* Reserved for future use */
chris 0:144fed3d9420 177 volatile USB_INT08U Unknown[4]; /* Unused */
chris 0:144fed3d9420 178 } HCCA;
chris 0:144fed3d9420 179
chris 0:144fed3d9420 180 /*
chris 0:144fed3d9420 181 **************************************************************************************************************
chris 0:144fed3d9420 182 * EXTERN DECLARATIONS
chris 0:144fed3d9420 183 **************************************************************************************************************
chris 0:144fed3d9420 184 */
chris 0:144fed3d9420 185
chris 0:144fed3d9420 186 extern volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
chris 0:144fed3d9420 187 extern volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
chris 0:144fed3d9420 188 extern volatile HCTD *TDHead; /* Head transfer descriptor structure */
chris 0:144fed3d9420 189 extern volatile HCTD *TDTail; /* Tail transfer descriptor structure */
chris 0:144fed3d9420 190 extern volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
chris 0:144fed3d9420 191
chris 0:144fed3d9420 192 /*
chris 0:144fed3d9420 193 **************************************************************************************************************
chris 0:144fed3d9420 194 * FUNCTION PROTOTYPES
chris 0:144fed3d9420 195 **************************************************************************************************************
chris 0:144fed3d9420 196 */
chris 0:144fed3d9420 197
chris 0:144fed3d9420 198 void Host_Init (void);
chris 0:144fed3d9420 199
chris 0:144fed3d9420 200 extern "C" void USB_IRQHandler(void) __irq;
chris 0:144fed3d9420 201
chris 0:144fed3d9420 202 USB_INT32S Host_EnumDev (void);
chris 0:144fed3d9420 203
chris 0:144fed3d9420 204 USB_INT32S Host_ProcessTD(volatile HCED *ed,
chris 0:144fed3d9420 205 volatile USB_INT32U token,
chris 0:144fed3d9420 206 volatile USB_INT08U *buffer,
chris 0:144fed3d9420 207 USB_INT32U buffer_len);
chris 0:144fed3d9420 208
chris 0:144fed3d9420 209 void Host_DelayUS ( USB_INT32U delay);
chris 0:144fed3d9420 210 void Host_DelayMS ( USB_INT32U delay);
chris 0:144fed3d9420 211
chris 0:144fed3d9420 212
chris 0:144fed3d9420 213 void Host_TDInit (volatile HCTD *td);
chris 0:144fed3d9420 214 void Host_EDInit (volatile HCED *ed);
chris 0:144fed3d9420 215 void Host_HCCAInit (volatile HCCA *hcca);
chris 0:144fed3d9420 216
chris 0:144fed3d9420 217 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
chris 0:144fed3d9420 218 USB_INT08U b_request,
chris 0:144fed3d9420 219 USB_INT16U w_value,
chris 0:144fed3d9420 220 USB_INT16U w_index,
chris 0:144fed3d9420 221 USB_INT16U w_length,
chris 0:144fed3d9420 222 volatile USB_INT08U *buffer);
chris 0:144fed3d9420 223
chris 0:144fed3d9420 224 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
chris 0:144fed3d9420 225 USB_INT08U b_request,
chris 0:144fed3d9420 226 USB_INT16U w_value,
chris 0:144fed3d9420 227 USB_INT16U w_index,
chris 0:144fed3d9420 228 USB_INT16U w_length,
chris 0:144fed3d9420 229 volatile USB_INT08U *buffer);
chris 0:144fed3d9420 230
chris 0:144fed3d9420 231 void Host_FillSetup( USB_INT08U bm_request_type,
chris 0:144fed3d9420 232 USB_INT08U b_request,
chris 0:144fed3d9420 233 USB_INT16U w_value,
chris 0:144fed3d9420 234 USB_INT16U w_index,
chris 0:144fed3d9420 235 USB_INT16U w_length);
chris 0:144fed3d9420 236
chris 0:144fed3d9420 237
chris 0:144fed3d9420 238 void Host_WDHWait (void);
chris 0:144fed3d9420 239
chris 0:144fed3d9420 240
chris 0:144fed3d9420 241 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem);
chris 0:144fed3d9420 242 void WriteLE32U (volatile USB_INT08U *pmem,
chris 0:144fed3d9420 243 USB_INT32U val);
chris 0:144fed3d9420 244 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem);
chris 0:144fed3d9420 245 void WriteLE16U (volatile USB_INT08U *pmem,
chris 0:144fed3d9420 246 USB_INT16U val);
chris 0:144fed3d9420 247 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem);
chris 0:144fed3d9420 248 void WriteBE32U (volatile USB_INT08U *pmem,
chris 0:144fed3d9420 249 USB_INT32U val);
chris 0:144fed3d9420 250 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem);
chris 0:144fed3d9420 251 void WriteBE16U (volatile USB_INT08U *pmem,
chris 0:144fed3d9420 252 USB_INT16U val);
chris 0:144fed3d9420 253
chris 0:144fed3d9420 254 #endif