Anand Tamariya / mbed

Support for MSP430 launchpad.

Fork of mbed by mbed official

KL25Z/core_cmFunc.h@60:3d0ef94e36ec, 2013-02-19 (annotated)

Committer:
emilmont
Date:
Tue Feb 19 10:00:15 2013 +0000
Revision:
60:3d0ef94e36ec
Add Freescale FRDM-KL25Z

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 60:3d0ef94e36ec 1 /**************************************************************************//**
emilmont 60:3d0ef94e36ec 2 * @file core_cmFunc.h
emilmont 60:3d0ef94e36ec 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 60:3d0ef94e36ec 4 * @version V3.02
emilmont 60:3d0ef94e36ec 5 * @date 24. May 2012
emilmont 60:3d0ef94e36ec 6 *
emilmont 60:3d0ef94e36ec 7 * @note
emilmont 60:3d0ef94e36ec 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 60:3d0ef94e36ec 9 *
emilmont 60:3d0ef94e36ec 10 * @par
emilmont 60:3d0ef94e36ec 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 60:3d0ef94e36ec 12 * processor based microcontrollers. This file can be freely distributed
emilmont 60:3d0ef94e36ec 13 * within development tools that are supporting such ARM based processors.
emilmont 60:3d0ef94e36ec 14 *
emilmont 60:3d0ef94e36ec 15 * @par
emilmont 60:3d0ef94e36ec 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 60:3d0ef94e36ec 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 60:3d0ef94e36ec 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 60:3d0ef94e36ec 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 60:3d0ef94e36ec 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 60:3d0ef94e36ec 21 *
emilmont 60:3d0ef94e36ec 22 ******************************************************************************/
emilmont 60:3d0ef94e36ec 23
emilmont 60:3d0ef94e36ec 24 #ifndef __CORE_CMFUNC_H
emilmont 60:3d0ef94e36ec 25 #define __CORE_CMFUNC_H
emilmont 60:3d0ef94e36ec 26
emilmont 60:3d0ef94e36ec 27
emilmont 60:3d0ef94e36ec 28 /* ########################### Core Function Access ########################### */
emilmont 60:3d0ef94e36ec 29 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 60:3d0ef94e36ec 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 60:3d0ef94e36ec 31 @{
emilmont 60:3d0ef94e36ec 32 */
emilmont 60:3d0ef94e36ec 33
emilmont 60:3d0ef94e36ec 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 60:3d0ef94e36ec 35 /* ARM armcc specific functions */
emilmont 60:3d0ef94e36ec 36
emilmont 60:3d0ef94e36ec 37 #if (__ARMCC_VERSION < 400677)
emilmont 60:3d0ef94e36ec 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 60:3d0ef94e36ec 39 #endif
emilmont 60:3d0ef94e36ec 40
emilmont 60:3d0ef94e36ec 41 /* intrinsic void __enable_irq(); */
emilmont 60:3d0ef94e36ec 42 /* intrinsic void __disable_irq(); */
emilmont 60:3d0ef94e36ec 43
emilmont 60:3d0ef94e36ec 44 /** \brief Get Control Register
emilmont 60:3d0ef94e36ec 45
emilmont 60:3d0ef94e36ec 46 This function returns the content of the Control Register.
emilmont 60:3d0ef94e36ec 47
emilmont 60:3d0ef94e36ec 48 \return Control Register value
emilmont 60:3d0ef94e36ec 49 */
emilmont 60:3d0ef94e36ec 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 60:3d0ef94e36ec 51 {
emilmont 60:3d0ef94e36ec 52 register uint32_t __regControl __ASM("control");
emilmont 60:3d0ef94e36ec 53 return(__regControl);
emilmont 60:3d0ef94e36ec 54 }
emilmont 60:3d0ef94e36ec 55
emilmont 60:3d0ef94e36ec 56
emilmont 60:3d0ef94e36ec 57 /** \brief Set Control Register
emilmont 60:3d0ef94e36ec 58
emilmont 60:3d0ef94e36ec 59 This function writes the given value to the Control Register.
emilmont 60:3d0ef94e36ec 60
emilmont 60:3d0ef94e36ec 61 \param [in] control Control Register value to set
emilmont 60:3d0ef94e36ec 62 */
emilmont 60:3d0ef94e36ec 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 60:3d0ef94e36ec 64 {
emilmont 60:3d0ef94e36ec 65 register uint32_t __regControl __ASM("control");
emilmont 60:3d0ef94e36ec 66 __regControl = control;
emilmont 60:3d0ef94e36ec 67 }
emilmont 60:3d0ef94e36ec 68
emilmont 60:3d0ef94e36ec 69
emilmont 60:3d0ef94e36ec 70 /** \brief Get IPSR Register
emilmont 60:3d0ef94e36ec 71
emilmont 60:3d0ef94e36ec 72 This function returns the content of the IPSR Register.
emilmont 60:3d0ef94e36ec 73
emilmont 60:3d0ef94e36ec 74 \return IPSR Register value
emilmont 60:3d0ef94e36ec 75 */
emilmont 60:3d0ef94e36ec 76 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 60:3d0ef94e36ec 77 {
emilmont 60:3d0ef94e36ec 78 register uint32_t __regIPSR __ASM("ipsr");
emilmont 60:3d0ef94e36ec 79 return(__regIPSR);
emilmont 60:3d0ef94e36ec 80 }
emilmont 60:3d0ef94e36ec 81
emilmont 60:3d0ef94e36ec 82
emilmont 60:3d0ef94e36ec 83 /** \brief Get APSR Register
emilmont 60:3d0ef94e36ec 84
emilmont 60:3d0ef94e36ec 85 This function returns the content of the APSR Register.
emilmont 60:3d0ef94e36ec 86
emilmont 60:3d0ef94e36ec 87 \return APSR Register value
emilmont 60:3d0ef94e36ec 88 */
emilmont 60:3d0ef94e36ec 89 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 60:3d0ef94e36ec 90 {
emilmont 60:3d0ef94e36ec 91 register uint32_t __regAPSR __ASM("apsr");
emilmont 60:3d0ef94e36ec 92 return(__regAPSR);
emilmont 60:3d0ef94e36ec 93 }
emilmont 60:3d0ef94e36ec 94
emilmont 60:3d0ef94e36ec 95
emilmont 60:3d0ef94e36ec 96 /** \brief Get xPSR Register
emilmont 60:3d0ef94e36ec 97
emilmont 60:3d0ef94e36ec 98 This function returns the content of the xPSR Register.
emilmont 60:3d0ef94e36ec 99
emilmont 60:3d0ef94e36ec 100 \return xPSR Register value
emilmont 60:3d0ef94e36ec 101 */
emilmont 60:3d0ef94e36ec 102 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 60:3d0ef94e36ec 103 {
emilmont 60:3d0ef94e36ec 104 register uint32_t __regXPSR __ASM("xpsr");
emilmont 60:3d0ef94e36ec 105 return(__regXPSR);
emilmont 60:3d0ef94e36ec 106 }
emilmont 60:3d0ef94e36ec 107
emilmont 60:3d0ef94e36ec 108
emilmont 60:3d0ef94e36ec 109 /** \brief Get Process Stack Pointer
emilmont 60:3d0ef94e36ec 110
emilmont 60:3d0ef94e36ec 111 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 60:3d0ef94e36ec 112
emilmont 60:3d0ef94e36ec 113 \return PSP Register value
emilmont 60:3d0ef94e36ec 114 */
emilmont 60:3d0ef94e36ec 115 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 60:3d0ef94e36ec 116 {
emilmont 60:3d0ef94e36ec 117 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 60:3d0ef94e36ec 118 return(__regProcessStackPointer);
emilmont 60:3d0ef94e36ec 119 }
emilmont 60:3d0ef94e36ec 120
emilmont 60:3d0ef94e36ec 121
emilmont 60:3d0ef94e36ec 122 /** \brief Set Process Stack Pointer
emilmont 60:3d0ef94e36ec 123
emilmont 60:3d0ef94e36ec 124 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 60:3d0ef94e36ec 125
emilmont 60:3d0ef94e36ec 126 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 60:3d0ef94e36ec 127 */
emilmont 60:3d0ef94e36ec 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 60:3d0ef94e36ec 129 {
emilmont 60:3d0ef94e36ec 130 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 60:3d0ef94e36ec 131 __regProcessStackPointer = topOfProcStack;
emilmont 60:3d0ef94e36ec 132 }
emilmont 60:3d0ef94e36ec 133
emilmont 60:3d0ef94e36ec 134
emilmont 60:3d0ef94e36ec 135 /** \brief Get Main Stack Pointer
emilmont 60:3d0ef94e36ec 136
emilmont 60:3d0ef94e36ec 137 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 60:3d0ef94e36ec 138
emilmont 60:3d0ef94e36ec 139 \return MSP Register value
emilmont 60:3d0ef94e36ec 140 */
emilmont 60:3d0ef94e36ec 141 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 60:3d0ef94e36ec 142 {
emilmont 60:3d0ef94e36ec 143 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 60:3d0ef94e36ec 144 return(__regMainStackPointer);
emilmont 60:3d0ef94e36ec 145 }
emilmont 60:3d0ef94e36ec 146
emilmont 60:3d0ef94e36ec 147
emilmont 60:3d0ef94e36ec 148 /** \brief Set Main Stack Pointer
emilmont 60:3d0ef94e36ec 149
emilmont 60:3d0ef94e36ec 150 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 60:3d0ef94e36ec 151
emilmont 60:3d0ef94e36ec 152 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 60:3d0ef94e36ec 153 */
emilmont 60:3d0ef94e36ec 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 60:3d0ef94e36ec 155 {
emilmont 60:3d0ef94e36ec 156 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 60:3d0ef94e36ec 157 __regMainStackPointer = topOfMainStack;
emilmont 60:3d0ef94e36ec 158 }
emilmont 60:3d0ef94e36ec 159
emilmont 60:3d0ef94e36ec 160
emilmont 60:3d0ef94e36ec 161 /** \brief Get Priority Mask
emilmont 60:3d0ef94e36ec 162
emilmont 60:3d0ef94e36ec 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 60:3d0ef94e36ec 164
emilmont 60:3d0ef94e36ec 165 \return Priority Mask value
emilmont 60:3d0ef94e36ec 166 */
emilmont 60:3d0ef94e36ec 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 60:3d0ef94e36ec 168 {
emilmont 60:3d0ef94e36ec 169 register uint32_t __regPriMask __ASM("primask");
emilmont 60:3d0ef94e36ec 170 return(__regPriMask);
emilmont 60:3d0ef94e36ec 171 }
emilmont 60:3d0ef94e36ec 172
emilmont 60:3d0ef94e36ec 173
emilmont 60:3d0ef94e36ec 174 /** \brief Set Priority Mask
emilmont 60:3d0ef94e36ec 175
emilmont 60:3d0ef94e36ec 176 This function assigns the given value to the Priority Mask Register.
emilmont 60:3d0ef94e36ec 177
emilmont 60:3d0ef94e36ec 178 \param [in] priMask Priority Mask
emilmont 60:3d0ef94e36ec 179 */
emilmont 60:3d0ef94e36ec 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 60:3d0ef94e36ec 181 {
emilmont 60:3d0ef94e36ec 182 register uint32_t __regPriMask __ASM("primask");
emilmont 60:3d0ef94e36ec 183 __regPriMask = (priMask);
emilmont 60:3d0ef94e36ec 184 }
emilmont 60:3d0ef94e36ec 185
emilmont 60:3d0ef94e36ec 186
emilmont 60:3d0ef94e36ec 187 #if (__CORTEX_M >= 0x03)
emilmont 60:3d0ef94e36ec 188
emilmont 60:3d0ef94e36ec 189 /** \brief Enable FIQ
emilmont 60:3d0ef94e36ec 190
emilmont 60:3d0ef94e36ec 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 60:3d0ef94e36ec 192 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 193 */
emilmont 60:3d0ef94e36ec 194 #define __enable_fault_irq __enable_fiq
emilmont 60:3d0ef94e36ec 195
emilmont 60:3d0ef94e36ec 196
emilmont 60:3d0ef94e36ec 197 /** \brief Disable FIQ
emilmont 60:3d0ef94e36ec 198
emilmont 60:3d0ef94e36ec 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 60:3d0ef94e36ec 200 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 201 */
emilmont 60:3d0ef94e36ec 202 #define __disable_fault_irq __disable_fiq
emilmont 60:3d0ef94e36ec 203
emilmont 60:3d0ef94e36ec 204
emilmont 60:3d0ef94e36ec 205 /** \brief Get Base Priority
emilmont 60:3d0ef94e36ec 206
emilmont 60:3d0ef94e36ec 207 This function returns the current value of the Base Priority register.
emilmont 60:3d0ef94e36ec 208
emilmont 60:3d0ef94e36ec 209 \return Base Priority register value
emilmont 60:3d0ef94e36ec 210 */
emilmont 60:3d0ef94e36ec 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 60:3d0ef94e36ec 212 {
emilmont 60:3d0ef94e36ec 213 register uint32_t __regBasePri __ASM("basepri");
emilmont 60:3d0ef94e36ec 214 return(__regBasePri);
emilmont 60:3d0ef94e36ec 215 }
emilmont 60:3d0ef94e36ec 216
emilmont 60:3d0ef94e36ec 217
emilmont 60:3d0ef94e36ec 218 /** \brief Set Base Priority
emilmont 60:3d0ef94e36ec 219
emilmont 60:3d0ef94e36ec 220 This function assigns the given value to the Base Priority register.
emilmont 60:3d0ef94e36ec 221
emilmont 60:3d0ef94e36ec 222 \param [in] basePri Base Priority value to set
emilmont 60:3d0ef94e36ec 223 */
emilmont 60:3d0ef94e36ec 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 60:3d0ef94e36ec 225 {
emilmont 60:3d0ef94e36ec 226 register uint32_t __regBasePri __ASM("basepri");
emilmont 60:3d0ef94e36ec 227 __regBasePri = (basePri & 0xff);
emilmont 60:3d0ef94e36ec 228 }
emilmont 60:3d0ef94e36ec 229
emilmont 60:3d0ef94e36ec 230
emilmont 60:3d0ef94e36ec 231 /** \brief Get Fault Mask
emilmont 60:3d0ef94e36ec 232
emilmont 60:3d0ef94e36ec 233 This function returns the current value of the Fault Mask register.
emilmont 60:3d0ef94e36ec 234
emilmont 60:3d0ef94e36ec 235 \return Fault Mask register value
emilmont 60:3d0ef94e36ec 236 */
emilmont 60:3d0ef94e36ec 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 60:3d0ef94e36ec 238 {
emilmont 60:3d0ef94e36ec 239 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 60:3d0ef94e36ec 240 return(__regFaultMask);
emilmont 60:3d0ef94e36ec 241 }
emilmont 60:3d0ef94e36ec 242
emilmont 60:3d0ef94e36ec 243
emilmont 60:3d0ef94e36ec 244 /** \brief Set Fault Mask
emilmont 60:3d0ef94e36ec 245
emilmont 60:3d0ef94e36ec 246 This function assigns the given value to the Fault Mask register.
emilmont 60:3d0ef94e36ec 247
emilmont 60:3d0ef94e36ec 248 \param [in] faultMask Fault Mask value to set
emilmont 60:3d0ef94e36ec 249 */
emilmont 60:3d0ef94e36ec 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 60:3d0ef94e36ec 251 {
emilmont 60:3d0ef94e36ec 252 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 60:3d0ef94e36ec 253 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 60:3d0ef94e36ec 254 }
emilmont 60:3d0ef94e36ec 255
emilmont 60:3d0ef94e36ec 256 #endif /* (__CORTEX_M >= 0x03) */
emilmont 60:3d0ef94e36ec 257
emilmont 60:3d0ef94e36ec 258
emilmont 60:3d0ef94e36ec 259 #if (__CORTEX_M == 0x04)
emilmont 60:3d0ef94e36ec 260
emilmont 60:3d0ef94e36ec 261 /** \brief Get FPSCR
emilmont 60:3d0ef94e36ec 262
emilmont 60:3d0ef94e36ec 263 This function returns the current value of the Floating Point Status/Control register.
emilmont 60:3d0ef94e36ec 264
emilmont 60:3d0ef94e36ec 265 \return Floating Point Status/Control register value
emilmont 60:3d0ef94e36ec 266 */
emilmont 60:3d0ef94e36ec 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 60:3d0ef94e36ec 268 {
emilmont 60:3d0ef94e36ec 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 60:3d0ef94e36ec 270 register uint32_t __regfpscr __ASM("fpscr");
emilmont 60:3d0ef94e36ec 271 return(__regfpscr);
emilmont 60:3d0ef94e36ec 272 #else
emilmont 60:3d0ef94e36ec 273 return(0);
emilmont 60:3d0ef94e36ec 274 #endif
emilmont 60:3d0ef94e36ec 275 }
emilmont 60:3d0ef94e36ec 276
emilmont 60:3d0ef94e36ec 277
emilmont 60:3d0ef94e36ec 278 /** \brief Set FPSCR
emilmont 60:3d0ef94e36ec 279
emilmont 60:3d0ef94e36ec 280 This function assigns the given value to the Floating Point Status/Control register.
emilmont 60:3d0ef94e36ec 281
emilmont 60:3d0ef94e36ec 282 \param [in] fpscr Floating Point Status/Control value to set
emilmont 60:3d0ef94e36ec 283 */
emilmont 60:3d0ef94e36ec 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 60:3d0ef94e36ec 285 {
emilmont 60:3d0ef94e36ec 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 60:3d0ef94e36ec 287 register uint32_t __regfpscr __ASM("fpscr");
emilmont 60:3d0ef94e36ec 288 __regfpscr = (fpscr);
emilmont 60:3d0ef94e36ec 289 #endif
emilmont 60:3d0ef94e36ec 290 }
emilmont 60:3d0ef94e36ec 291
emilmont 60:3d0ef94e36ec 292 #endif /* (__CORTEX_M == 0x04) */
emilmont 60:3d0ef94e36ec 293
emilmont 60:3d0ef94e36ec 294
emilmont 60:3d0ef94e36ec 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 60:3d0ef94e36ec 296 /* IAR iccarm specific functions */
emilmont 60:3d0ef94e36ec 297
emilmont 60:3d0ef94e36ec 298 #include <cmsis_iar.h>
emilmont 60:3d0ef94e36ec 299
emilmont 60:3d0ef94e36ec 300
emilmont 60:3d0ef94e36ec 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 60:3d0ef94e36ec 302 /* TI CCS specific functions */
emilmont 60:3d0ef94e36ec 303
emilmont 60:3d0ef94e36ec 304 #include <cmsis_ccs.h>
emilmont 60:3d0ef94e36ec 305
emilmont 60:3d0ef94e36ec 306
emilmont 60:3d0ef94e36ec 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 60:3d0ef94e36ec 308 /* GNU gcc specific functions */
emilmont 60:3d0ef94e36ec 309
emilmont 60:3d0ef94e36ec 310 /** \brief Enable IRQ Interrupts
emilmont 60:3d0ef94e36ec 311
emilmont 60:3d0ef94e36ec 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 60:3d0ef94e36ec 313 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 314 */
emilmont 60:3d0ef94e36ec 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 60:3d0ef94e36ec 316 {
emilmont 60:3d0ef94e36ec 317 __ASM volatile ("cpsie i" : : : "memory");
emilmont 60:3d0ef94e36ec 318 }
emilmont 60:3d0ef94e36ec 319
emilmont 60:3d0ef94e36ec 320
emilmont 60:3d0ef94e36ec 321 /** \brief Disable IRQ Interrupts
emilmont 60:3d0ef94e36ec 322
emilmont 60:3d0ef94e36ec 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 60:3d0ef94e36ec 324 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 325 */
emilmont 60:3d0ef94e36ec 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 60:3d0ef94e36ec 327 {
emilmont 60:3d0ef94e36ec 328 __ASM volatile ("cpsid i" : : : "memory");
emilmont 60:3d0ef94e36ec 329 }
emilmont 60:3d0ef94e36ec 330
emilmont 60:3d0ef94e36ec 331
emilmont 60:3d0ef94e36ec 332 /** \brief Get Control Register
emilmont 60:3d0ef94e36ec 333
emilmont 60:3d0ef94e36ec 334 This function returns the content of the Control Register.
emilmont 60:3d0ef94e36ec 335
emilmont 60:3d0ef94e36ec 336 \return Control Register value
emilmont 60:3d0ef94e36ec 337 */
emilmont 60:3d0ef94e36ec 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 60:3d0ef94e36ec 339 {
emilmont 60:3d0ef94e36ec 340 uint32_t result;
emilmont 60:3d0ef94e36ec 341
emilmont 60:3d0ef94e36ec 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 60:3d0ef94e36ec 343 return(result);
emilmont 60:3d0ef94e36ec 344 }
emilmont 60:3d0ef94e36ec 345
emilmont 60:3d0ef94e36ec 346
emilmont 60:3d0ef94e36ec 347 /** \brief Set Control Register
emilmont 60:3d0ef94e36ec 348
emilmont 60:3d0ef94e36ec 349 This function writes the given value to the Control Register.
emilmont 60:3d0ef94e36ec 350
emilmont 60:3d0ef94e36ec 351 \param [in] control Control Register value to set
emilmont 60:3d0ef94e36ec 352 */
emilmont 60:3d0ef94e36ec 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 60:3d0ef94e36ec 354 {
emilmont 60:3d0ef94e36ec 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 60:3d0ef94e36ec 356 }
emilmont 60:3d0ef94e36ec 357
emilmont 60:3d0ef94e36ec 358
emilmont 60:3d0ef94e36ec 359 /** \brief Get IPSR Register
emilmont 60:3d0ef94e36ec 360
emilmont 60:3d0ef94e36ec 361 This function returns the content of the IPSR Register.
emilmont 60:3d0ef94e36ec 362
emilmont 60:3d0ef94e36ec 363 \return IPSR Register value
emilmont 60:3d0ef94e36ec 364 */
emilmont 60:3d0ef94e36ec 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 60:3d0ef94e36ec 366 {
emilmont 60:3d0ef94e36ec 367 uint32_t result;
emilmont 60:3d0ef94e36ec 368
emilmont 60:3d0ef94e36ec 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 60:3d0ef94e36ec 370 return(result);
emilmont 60:3d0ef94e36ec 371 }
emilmont 60:3d0ef94e36ec 372
emilmont 60:3d0ef94e36ec 373
emilmont 60:3d0ef94e36ec 374 /** \brief Get APSR Register
emilmont 60:3d0ef94e36ec 375
emilmont 60:3d0ef94e36ec 376 This function returns the content of the APSR Register.
emilmont 60:3d0ef94e36ec 377
emilmont 60:3d0ef94e36ec 378 \return APSR Register value
emilmont 60:3d0ef94e36ec 379 */
emilmont 60:3d0ef94e36ec 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 60:3d0ef94e36ec 381 {
emilmont 60:3d0ef94e36ec 382 uint32_t result;
emilmont 60:3d0ef94e36ec 383
emilmont 60:3d0ef94e36ec 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 60:3d0ef94e36ec 385 return(result);
emilmont 60:3d0ef94e36ec 386 }
emilmont 60:3d0ef94e36ec 387
emilmont 60:3d0ef94e36ec 388
emilmont 60:3d0ef94e36ec 389 /** \brief Get xPSR Register
emilmont 60:3d0ef94e36ec 390
emilmont 60:3d0ef94e36ec 391 This function returns the content of the xPSR Register.
emilmont 60:3d0ef94e36ec 392
emilmont 60:3d0ef94e36ec 393 \return xPSR Register value
emilmont 60:3d0ef94e36ec 394 */
emilmont 60:3d0ef94e36ec 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 60:3d0ef94e36ec 396 {
emilmont 60:3d0ef94e36ec 397 uint32_t result;
emilmont 60:3d0ef94e36ec 398
emilmont 60:3d0ef94e36ec 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 60:3d0ef94e36ec 400 return(result);
emilmont 60:3d0ef94e36ec 401 }
emilmont 60:3d0ef94e36ec 402
emilmont 60:3d0ef94e36ec 403
emilmont 60:3d0ef94e36ec 404 /** \brief Get Process Stack Pointer
emilmont 60:3d0ef94e36ec 405
emilmont 60:3d0ef94e36ec 406 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 60:3d0ef94e36ec 407
emilmont 60:3d0ef94e36ec 408 \return PSP Register value
emilmont 60:3d0ef94e36ec 409 */
emilmont 60:3d0ef94e36ec 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 60:3d0ef94e36ec 411 {
emilmont 60:3d0ef94e36ec 412 register uint32_t result;
emilmont 60:3d0ef94e36ec 413
emilmont 60:3d0ef94e36ec 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 60:3d0ef94e36ec 415 return(result);
emilmont 60:3d0ef94e36ec 416 }
emilmont 60:3d0ef94e36ec 417
emilmont 60:3d0ef94e36ec 418
emilmont 60:3d0ef94e36ec 419 /** \brief Set Process Stack Pointer
emilmont 60:3d0ef94e36ec 420
emilmont 60:3d0ef94e36ec 421 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 60:3d0ef94e36ec 422
emilmont 60:3d0ef94e36ec 423 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 60:3d0ef94e36ec 424 */
emilmont 60:3d0ef94e36ec 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 60:3d0ef94e36ec 426 {
emilmont 60:3d0ef94e36ec 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 60:3d0ef94e36ec 428 }
emilmont 60:3d0ef94e36ec 429
emilmont 60:3d0ef94e36ec 430
emilmont 60:3d0ef94e36ec 431 /** \brief Get Main Stack Pointer
emilmont 60:3d0ef94e36ec 432
emilmont 60:3d0ef94e36ec 433 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 60:3d0ef94e36ec 434
emilmont 60:3d0ef94e36ec 435 \return MSP Register value
emilmont 60:3d0ef94e36ec 436 */
emilmont 60:3d0ef94e36ec 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 60:3d0ef94e36ec 438 {
emilmont 60:3d0ef94e36ec 439 register uint32_t result;
emilmont 60:3d0ef94e36ec 440
emilmont 60:3d0ef94e36ec 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 60:3d0ef94e36ec 442 return(result);
emilmont 60:3d0ef94e36ec 443 }
emilmont 60:3d0ef94e36ec 444
emilmont 60:3d0ef94e36ec 445
emilmont 60:3d0ef94e36ec 446 /** \brief Set Main Stack Pointer
emilmont 60:3d0ef94e36ec 447
emilmont 60:3d0ef94e36ec 448 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 60:3d0ef94e36ec 449
emilmont 60:3d0ef94e36ec 450 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 60:3d0ef94e36ec 451 */
emilmont 60:3d0ef94e36ec 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 60:3d0ef94e36ec 453 {
emilmont 60:3d0ef94e36ec 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 60:3d0ef94e36ec 455 }
emilmont 60:3d0ef94e36ec 456
emilmont 60:3d0ef94e36ec 457
emilmont 60:3d0ef94e36ec 458 /** \brief Get Priority Mask
emilmont 60:3d0ef94e36ec 459
emilmont 60:3d0ef94e36ec 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 60:3d0ef94e36ec 461
emilmont 60:3d0ef94e36ec 462 \return Priority Mask value
emilmont 60:3d0ef94e36ec 463 */
emilmont 60:3d0ef94e36ec 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 60:3d0ef94e36ec 465 {
emilmont 60:3d0ef94e36ec 466 uint32_t result;
emilmont 60:3d0ef94e36ec 467
emilmont 60:3d0ef94e36ec 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 60:3d0ef94e36ec 469 return(result);
emilmont 60:3d0ef94e36ec 470 }
emilmont 60:3d0ef94e36ec 471
emilmont 60:3d0ef94e36ec 472
emilmont 60:3d0ef94e36ec 473 /** \brief Set Priority Mask
emilmont 60:3d0ef94e36ec 474
emilmont 60:3d0ef94e36ec 475 This function assigns the given value to the Priority Mask Register.
emilmont 60:3d0ef94e36ec 476
emilmont 60:3d0ef94e36ec 477 \param [in] priMask Priority Mask
emilmont 60:3d0ef94e36ec 478 */
emilmont 60:3d0ef94e36ec 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 60:3d0ef94e36ec 480 {
emilmont 60:3d0ef94e36ec 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 60:3d0ef94e36ec 482 }
emilmont 60:3d0ef94e36ec 483
emilmont 60:3d0ef94e36ec 484
emilmont 60:3d0ef94e36ec 485 #if (__CORTEX_M >= 0x03)
emilmont 60:3d0ef94e36ec 486
emilmont 60:3d0ef94e36ec 487 /** \brief Enable FIQ
emilmont 60:3d0ef94e36ec 488
emilmont 60:3d0ef94e36ec 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 60:3d0ef94e36ec 490 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 491 */
emilmont 60:3d0ef94e36ec 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 60:3d0ef94e36ec 493 {
emilmont 60:3d0ef94e36ec 494 __ASM volatile ("cpsie f" : : : "memory");
emilmont 60:3d0ef94e36ec 495 }
emilmont 60:3d0ef94e36ec 496
emilmont 60:3d0ef94e36ec 497
emilmont 60:3d0ef94e36ec 498 /** \brief Disable FIQ
emilmont 60:3d0ef94e36ec 499
emilmont 60:3d0ef94e36ec 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 60:3d0ef94e36ec 501 Can only be executed in Privileged modes.
emilmont 60:3d0ef94e36ec 502 */
emilmont 60:3d0ef94e36ec 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 60:3d0ef94e36ec 504 {
emilmont 60:3d0ef94e36ec 505 __ASM volatile ("cpsid f" : : : "memory");
emilmont 60:3d0ef94e36ec 506 }
emilmont 60:3d0ef94e36ec 507
emilmont 60:3d0ef94e36ec 508
emilmont 60:3d0ef94e36ec 509 /** \brief Get Base Priority
emilmont 60:3d0ef94e36ec 510
emilmont 60:3d0ef94e36ec 511 This function returns the current value of the Base Priority register.
emilmont 60:3d0ef94e36ec 512
emilmont 60:3d0ef94e36ec 513 \return Base Priority register value
emilmont 60:3d0ef94e36ec 514 */
emilmont 60:3d0ef94e36ec 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 60:3d0ef94e36ec 516 {
emilmont 60:3d0ef94e36ec 517 uint32_t result;
emilmont 60:3d0ef94e36ec 518
emilmont 60:3d0ef94e36ec 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 60:3d0ef94e36ec 520 return(result);
emilmont 60:3d0ef94e36ec 521 }
emilmont 60:3d0ef94e36ec 522
emilmont 60:3d0ef94e36ec 523
emilmont 60:3d0ef94e36ec 524 /** \brief Set Base Priority
emilmont 60:3d0ef94e36ec 525
emilmont 60:3d0ef94e36ec 526 This function assigns the given value to the Base Priority register.
emilmont 60:3d0ef94e36ec 527
emilmont 60:3d0ef94e36ec 528 \param [in] basePri Base Priority value to set
emilmont 60:3d0ef94e36ec 529 */
emilmont 60:3d0ef94e36ec 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 60:3d0ef94e36ec 531 {
emilmont 60:3d0ef94e36ec 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 60:3d0ef94e36ec 533 }
emilmont 60:3d0ef94e36ec 534
emilmont 60:3d0ef94e36ec 535
emilmont 60:3d0ef94e36ec 536 /** \brief Get Fault Mask
emilmont 60:3d0ef94e36ec 537
emilmont 60:3d0ef94e36ec 538 This function returns the current value of the Fault Mask register.
emilmont 60:3d0ef94e36ec 539
emilmont 60:3d0ef94e36ec 540 \return Fault Mask register value
emilmont 60:3d0ef94e36ec 541 */
emilmont 60:3d0ef94e36ec 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 60:3d0ef94e36ec 543 {
emilmont 60:3d0ef94e36ec 544 uint32_t result;
emilmont 60:3d0ef94e36ec 545
emilmont 60:3d0ef94e36ec 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 60:3d0ef94e36ec 547 return(result);
emilmont 60:3d0ef94e36ec 548 }
emilmont 60:3d0ef94e36ec 549
emilmont 60:3d0ef94e36ec 550
emilmont 60:3d0ef94e36ec 551 /** \brief Set Fault Mask
emilmont 60:3d0ef94e36ec 552
emilmont 60:3d0ef94e36ec 553 This function assigns the given value to the Fault Mask register.
emilmont 60:3d0ef94e36ec 554
emilmont 60:3d0ef94e36ec 555 \param [in] faultMask Fault Mask value to set
emilmont 60:3d0ef94e36ec 556 */
emilmont 60:3d0ef94e36ec 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 60:3d0ef94e36ec 558 {
emilmont 60:3d0ef94e36ec 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 60:3d0ef94e36ec 560 }
emilmont 60:3d0ef94e36ec 561
emilmont 60:3d0ef94e36ec 562 #endif /* (__CORTEX_M >= 0x03) */
emilmont 60:3d0ef94e36ec 563
emilmont 60:3d0ef94e36ec 564
emilmont 60:3d0ef94e36ec 565 #if (__CORTEX_M == 0x04)
emilmont 60:3d0ef94e36ec 566
emilmont 60:3d0ef94e36ec 567 /** \brief Get FPSCR
emilmont 60:3d0ef94e36ec 568
emilmont 60:3d0ef94e36ec 569 This function returns the current value of the Floating Point Status/Control register.
emilmont 60:3d0ef94e36ec 570
emilmont 60:3d0ef94e36ec 571 \return Floating Point Status/Control register value
emilmont 60:3d0ef94e36ec 572 */
emilmont 60:3d0ef94e36ec 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 60:3d0ef94e36ec 574 {
emilmont 60:3d0ef94e36ec 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 60:3d0ef94e36ec 576 uint32_t result;
emilmont 60:3d0ef94e36ec 577
emilmont 60:3d0ef94e36ec 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 60:3d0ef94e36ec 579 return(result);
emilmont 60:3d0ef94e36ec 580 #else
emilmont 60:3d0ef94e36ec 581 return(0);
emilmont 60:3d0ef94e36ec 582 #endif
emilmont 60:3d0ef94e36ec 583 }
emilmont 60:3d0ef94e36ec 584
emilmont 60:3d0ef94e36ec 585
emilmont 60:3d0ef94e36ec 586 /** \brief Set FPSCR
emilmont 60:3d0ef94e36ec 587
emilmont 60:3d0ef94e36ec 588 This function assigns the given value to the Floating Point Status/Control register.
emilmont 60:3d0ef94e36ec 589
emilmont 60:3d0ef94e36ec 590 \param [in] fpscr Floating Point Status/Control value to set
emilmont 60:3d0ef94e36ec 591 */
emilmont 60:3d0ef94e36ec 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 60:3d0ef94e36ec 593 {
emilmont 60:3d0ef94e36ec 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 60:3d0ef94e36ec 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
emilmont 60:3d0ef94e36ec 596 #endif
emilmont 60:3d0ef94e36ec 597 }
emilmont 60:3d0ef94e36ec 598
emilmont 60:3d0ef94e36ec 599 #endif /* (__CORTEX_M == 0x04) */
emilmont 60:3d0ef94e36ec 600
emilmont 60:3d0ef94e36ec 601
emilmont 60:3d0ef94e36ec 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 60:3d0ef94e36ec 603 /* TASKING carm specific functions */
emilmont 60:3d0ef94e36ec 604
emilmont 60:3d0ef94e36ec 605 /*
emilmont 60:3d0ef94e36ec 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 60:3d0ef94e36ec 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 60:3d0ef94e36ec 608 * Including the CMSIS ones.
emilmont 60:3d0ef94e36ec 609 */
emilmont 60:3d0ef94e36ec 610
emilmont 60:3d0ef94e36ec 611 #endif
emilmont 60:3d0ef94e36ec 612
emilmont 60:3d0ef94e36ec 613 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 60:3d0ef94e36ec 614
emilmont 60:3d0ef94e36ec 615
emilmont 60:3d0ef94e36ec 616 #endif /* __CORE_CMFUNC_H */