Andrea Corrado
/
RFID-RC522
Added extra RFID readers
Fork of RFID-RC522 by
MFRC522.cpp@3:654723104cc9, 2018-06-22 (annotated)
- Committer:
- andcor02
- Date:
- Fri Jun 22 09:41:42 2018 +0000
- Revision:
- 3:654723104cc9
- Parent:
- 1:63d729186747
- Child:
- 4:320ce84c8f43
Added extra RFID readers
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AtomX | 0:efd786b99a72 | 1 | /* |
AtomX | 0:efd786b99a72 | 2 | * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT. |
AtomX | 0:efd786b99a72 | 3 | * _Please_ see the comments in MFRC522.h - they give useful hints and background. |
AtomX | 0:efd786b99a72 | 4 | * Released into the public domain. |
AtomX | 0:efd786b99a72 | 5 | */ |
AtomX | 0:efd786b99a72 | 6 | |
AtomX | 0:efd786b99a72 | 7 | #include "MFRC522.h" |
AtomX | 0:efd786b99a72 | 8 | |
AtomX | 0:efd786b99a72 | 9 | static const char* const _TypeNamePICC[] = |
AtomX | 0:efd786b99a72 | 10 | { |
AtomX | 0:efd786b99a72 | 11 | "Unknown type", |
AtomX | 0:efd786b99a72 | 12 | "PICC compliant with ISO/IEC 14443-4", |
AtomX | 0:efd786b99a72 | 13 | "PICC compliant with ISO/IEC 18092 (NFC)", |
AtomX | 0:efd786b99a72 | 14 | "MIFARE Mini, 320 bytes", |
AtomX | 0:efd786b99a72 | 15 | "MIFARE 1KB", |
AtomX | 0:efd786b99a72 | 16 | "MIFARE 4KB", |
AtomX | 0:efd786b99a72 | 17 | "MIFARE Ultralight or Ultralight C", |
AtomX | 0:efd786b99a72 | 18 | "MIFARE Plus", |
AtomX | 0:efd786b99a72 | 19 | "MIFARE TNP3XXX", |
AtomX | 0:efd786b99a72 | 20 | |
AtomX | 0:efd786b99a72 | 21 | /* not complete UID */ |
AtomX | 0:efd786b99a72 | 22 | "SAK indicates UID is not complete" |
AtomX | 0:efd786b99a72 | 23 | }; |
AtomX | 0:efd786b99a72 | 24 | |
AtomX | 0:efd786b99a72 | 25 | static const char* const _ErrorMessage[] = |
AtomX | 0:efd786b99a72 | 26 | { |
AtomX | 0:efd786b99a72 | 27 | "Unknown error", |
AtomX | 0:efd786b99a72 | 28 | "Success", |
AtomX | 0:efd786b99a72 | 29 | "Error in communication", |
AtomX | 0:efd786b99a72 | 30 | "Collision detected", |
AtomX | 0:efd786b99a72 | 31 | "Timeout in communication", |
AtomX | 0:efd786b99a72 | 32 | "A buffer is not big enough", |
AtomX | 0:efd786b99a72 | 33 | "Internal error in the code, should not happen", |
AtomX | 0:efd786b99a72 | 34 | "Invalid argument", |
AtomX | 0:efd786b99a72 | 35 | "The CRC_A does not match", |
AtomX | 0:efd786b99a72 | 36 | "A MIFARE PICC responded with NAK" |
AtomX | 0:efd786b99a72 | 37 | }; |
AtomX | 0:efd786b99a72 | 38 | |
AtomX | 0:efd786b99a72 | 39 | #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0])) |
AtomX | 0:efd786b99a72 | 40 | #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0])) |
AtomX | 0:efd786b99a72 | 41 | |
AtomX | 0:efd786b99a72 | 42 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 43 | // Functions for setting up the driver |
AtomX | 0:efd786b99a72 | 44 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 45 | |
AtomX | 0:efd786b99a72 | 46 | /** |
AtomX | 0:efd786b99a72 | 47 | * Constructor. |
AtomX | 0:efd786b99a72 | 48 | * Prepares the output pins. |
AtomX | 0:efd786b99a72 | 49 | */ |
AtomX | 0:efd786b99a72 | 50 | MFRC522::MFRC522(PinName mosi, |
AtomX | 0:efd786b99a72 | 51 | PinName miso, |
AtomX | 0:efd786b99a72 | 52 | PinName sclk, |
AtomX | 0:efd786b99a72 | 53 | PinName cs, |
AtomX | 0:efd786b99a72 | 54 | PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset) |
AtomX | 0:efd786b99a72 | 55 | { |
AtomX | 0:efd786b99a72 | 56 | /* Configure SPI bus */ |
AtomX | 0:efd786b99a72 | 57 | m_SPI.format(8, 0); |
andcor02 | 3:654723104cc9 | 58 | // m_SPI.frequency(8000000); |
andcor02 | 3:654723104cc9 | 59 | m_SPI.frequency(1000000); |
AtomX | 0:efd786b99a72 | 60 | |
AtomX | 0:efd786b99a72 | 61 | /* Release SPI-CS pin */ |
AtomX | 0:efd786b99a72 | 62 | m_CS = 1; |
AtomX | 0:efd786b99a72 | 63 | |
AtomX | 0:efd786b99a72 | 64 | /* Release RESET pin */ |
AtomX | 0:efd786b99a72 | 65 | m_RESET = 1; |
AtomX | 0:efd786b99a72 | 66 | } // End constructor |
AtomX | 0:efd786b99a72 | 67 | |
AtomX | 0:efd786b99a72 | 68 | |
AtomX | 0:efd786b99a72 | 69 | /** |
AtomX | 0:efd786b99a72 | 70 | * Destructor. |
AtomX | 0:efd786b99a72 | 71 | */ |
AtomX | 0:efd786b99a72 | 72 | MFRC522::~MFRC522() |
AtomX | 0:efd786b99a72 | 73 | { |
AtomX | 0:efd786b99a72 | 74 | |
AtomX | 0:efd786b99a72 | 75 | } |
AtomX | 0:efd786b99a72 | 76 | |
AtomX | 0:efd786b99a72 | 77 | |
AtomX | 0:efd786b99a72 | 78 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 79 | // Basic interface functions for communicating with the MFRC522 |
AtomX | 0:efd786b99a72 | 80 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 81 | |
AtomX | 0:efd786b99a72 | 82 | /** |
AtomX | 0:efd786b99a72 | 83 | * Writes a byte to the specified register in the MFRC522 chip. |
AtomX | 0:efd786b99a72 | 84 | * The interface is described in the datasheet section 8.1.2. |
AtomX | 0:efd786b99a72 | 85 | */ |
AtomX | 0:efd786b99a72 | 86 | void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value) |
AtomX | 0:efd786b99a72 | 87 | { |
AtomX | 0:efd786b99a72 | 88 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 89 | |
AtomX | 0:efd786b99a72 | 90 | // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. |
AtomX | 0:efd786b99a72 | 91 | (void) m_SPI.write(reg & 0x7E); |
AtomX | 0:efd786b99a72 | 92 | (void) m_SPI.write(value); |
AtomX | 0:efd786b99a72 | 93 | |
AtomX | 0:efd786b99a72 | 94 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 95 | } // End PCD_WriteRegister() |
AtomX | 0:efd786b99a72 | 96 | |
AtomX | 0:efd786b99a72 | 97 | /** |
AtomX | 0:efd786b99a72 | 98 | * Writes a number of bytes to the specified register in the MFRC522 chip. |
AtomX | 0:efd786b99a72 | 99 | * The interface is described in the datasheet section 8.1.2. |
AtomX | 0:efd786b99a72 | 100 | */ |
AtomX | 0:efd786b99a72 | 101 | void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values) |
AtomX | 0:efd786b99a72 | 102 | { |
AtomX | 0:efd786b99a72 | 103 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 104 | |
AtomX | 0:efd786b99a72 | 105 | // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. |
AtomX | 0:efd786b99a72 | 106 | (void) m_SPI.write(reg & 0x7E); |
AtomX | 0:efd786b99a72 | 107 | for (uint8_t index = 0; index < count; index++) |
AtomX | 0:efd786b99a72 | 108 | { |
AtomX | 0:efd786b99a72 | 109 | (void) m_SPI.write(values[index]); |
AtomX | 0:efd786b99a72 | 110 | } |
AtomX | 0:efd786b99a72 | 111 | |
AtomX | 0:efd786b99a72 | 112 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 113 | } // End PCD_WriteRegister() |
AtomX | 0:efd786b99a72 | 114 | |
AtomX | 0:efd786b99a72 | 115 | /** |
AtomX | 0:efd786b99a72 | 116 | * Reads a byte from the specified register in the MFRC522 chip. |
AtomX | 0:efd786b99a72 | 117 | * The interface is described in the datasheet section 8.1.2. |
AtomX | 0:efd786b99a72 | 118 | */ |
AtomX | 0:efd786b99a72 | 119 | uint8_t MFRC522::PCD_ReadRegister(uint8_t reg) |
AtomX | 0:efd786b99a72 | 120 | { |
AtomX | 0:efd786b99a72 | 121 | uint8_t value; |
AtomX | 0:efd786b99a72 | 122 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 123 | |
AtomX | 0:efd786b99a72 | 124 | // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3. |
AtomX | 0:efd786b99a72 | 125 | (void) m_SPI.write(0x80 | reg); |
AtomX | 0:efd786b99a72 | 126 | |
AtomX | 0:efd786b99a72 | 127 | // Read the value back. Send 0 to stop reading. |
AtomX | 0:efd786b99a72 | 128 | value = m_SPI.write(0); |
AtomX | 0:efd786b99a72 | 129 | |
AtomX | 0:efd786b99a72 | 130 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 131 | |
AtomX | 0:efd786b99a72 | 132 | return value; |
AtomX | 0:efd786b99a72 | 133 | } // End PCD_ReadRegister() |
AtomX | 0:efd786b99a72 | 134 | |
AtomX | 0:efd786b99a72 | 135 | /** |
AtomX | 0:efd786b99a72 | 136 | * Reads a number of bytes from the specified register in the MFRC522 chip. |
AtomX | 0:efd786b99a72 | 137 | * The interface is described in the datasheet section 8.1.2. |
AtomX | 0:efd786b99a72 | 138 | */ |
AtomX | 0:efd786b99a72 | 139 | void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign) |
AtomX | 0:efd786b99a72 | 140 | { |
AtomX | 0:efd786b99a72 | 141 | if (count == 0) { return; } |
AtomX | 0:efd786b99a72 | 142 | |
AtomX | 0:efd786b99a72 | 143 | uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3. |
AtomX | 0:efd786b99a72 | 144 | uint8_t index = 0; // Index in values array. |
AtomX | 0:efd786b99a72 | 145 | |
AtomX | 0:efd786b99a72 | 146 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 147 | count--; // One read is performed outside of the loop |
AtomX | 0:efd786b99a72 | 148 | (void) m_SPI.write(address); // Tell MFRC522 which address we want to read |
AtomX | 0:efd786b99a72 | 149 | |
AtomX | 0:efd786b99a72 | 150 | while (index < count) |
AtomX | 0:efd786b99a72 | 151 | { |
AtomX | 0:efd786b99a72 | 152 | if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0] |
AtomX | 0:efd786b99a72 | 153 | { |
AtomX | 0:efd786b99a72 | 154 | // Create bit mask for bit positions rxAlign..7 |
AtomX | 0:efd786b99a72 | 155 | uint8_t mask = 0; |
AtomX | 0:efd786b99a72 | 156 | for (uint8_t i = rxAlign; i <= 7; i++) |
AtomX | 0:efd786b99a72 | 157 | { |
AtomX | 0:efd786b99a72 | 158 | mask |= (1 << i); |
AtomX | 0:efd786b99a72 | 159 | } |
AtomX | 0:efd786b99a72 | 160 | |
AtomX | 0:efd786b99a72 | 161 | // Read value and tell that we want to read the same address again. |
AtomX | 0:efd786b99a72 | 162 | uint8_t value = m_SPI.write(address); |
AtomX | 0:efd786b99a72 | 163 | |
AtomX | 0:efd786b99a72 | 164 | // Apply mask to both current value of values[0] and the new data in value. |
AtomX | 0:efd786b99a72 | 165 | values[0] = (values[index] & ~mask) | (value & mask); |
AtomX | 0:efd786b99a72 | 166 | } |
AtomX | 0:efd786b99a72 | 167 | else |
AtomX | 0:efd786b99a72 | 168 | { |
AtomX | 0:efd786b99a72 | 169 | // Read value and tell that we want to read the same address again. |
AtomX | 0:efd786b99a72 | 170 | values[index] = m_SPI.write(address); |
AtomX | 0:efd786b99a72 | 171 | } |
AtomX | 0:efd786b99a72 | 172 | |
AtomX | 0:efd786b99a72 | 173 | index++; |
AtomX | 0:efd786b99a72 | 174 | } |
AtomX | 0:efd786b99a72 | 175 | |
AtomX | 0:efd786b99a72 | 176 | values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading. |
AtomX | 0:efd786b99a72 | 177 | |
AtomX | 0:efd786b99a72 | 178 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
AtomX | 0:efd786b99a72 | 179 | } // End PCD_ReadRegister() |
AtomX | 0:efd786b99a72 | 180 | |
AtomX | 0:efd786b99a72 | 181 | /** |
AtomX | 0:efd786b99a72 | 182 | * Sets the bits given in mask in register reg. |
AtomX | 0:efd786b99a72 | 183 | */ |
AtomX | 0:efd786b99a72 | 184 | void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask) |
AtomX | 0:efd786b99a72 | 185 | { |
AtomX | 0:efd786b99a72 | 186 | uint8_t tmp = PCD_ReadRegister(reg); |
AtomX | 0:efd786b99a72 | 187 | PCD_WriteRegister(reg, tmp | mask); // set bit mask |
AtomX | 0:efd786b99a72 | 188 | } // End PCD_SetRegisterBitMask() |
AtomX | 0:efd786b99a72 | 189 | |
AtomX | 0:efd786b99a72 | 190 | /** |
AtomX | 0:efd786b99a72 | 191 | * Clears the bits given in mask from register reg. |
AtomX | 0:efd786b99a72 | 192 | */ |
AtomX | 0:efd786b99a72 | 193 | void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask) |
AtomX | 0:efd786b99a72 | 194 | { |
AtomX | 0:efd786b99a72 | 195 | uint8_t tmp = PCD_ReadRegister(reg); |
AtomX | 0:efd786b99a72 | 196 | PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask |
AtomX | 0:efd786b99a72 | 197 | } // End PCD_ClearRegisterBitMask() |
AtomX | 0:efd786b99a72 | 198 | |
AtomX | 0:efd786b99a72 | 199 | |
AtomX | 0:efd786b99a72 | 200 | /** |
AtomX | 0:efd786b99a72 | 201 | * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A. |
AtomX | 0:efd786b99a72 | 202 | */ |
AtomX | 0:efd786b99a72 | 203 | uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result) |
AtomX | 0:efd786b99a72 | 204 | { |
AtomX | 0:efd786b99a72 | 205 | PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command. |
AtomX | 1:63d729186747 | 206 | PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit |
AtomX | 1:63d729186747 | 207 | PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization |
AtomX | 1:63d729186747 | 208 | PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO |
AtomX | 0:efd786b99a72 | 209 | PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation |
AtomX | 0:efd786b99a72 | 210 | |
AtomX | 1:63d729186747 | 211 | // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us. |
AtomX | 0:efd786b99a72 | 212 | uint16_t i = 5000; |
AtomX | 0:efd786b99a72 | 213 | uint8_t n; |
AtomX | 0:efd786b99a72 | 214 | while (1) |
AtomX | 0:efd786b99a72 | 215 | { |
AtomX | 0:efd786b99a72 | 216 | n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved |
AtomX | 0:efd786b99a72 | 217 | if (n & 0x04) |
AtomX | 0:efd786b99a72 | 218 | { |
AtomX | 0:efd786b99a72 | 219 | // CRCIRq bit set - calculation done |
AtomX | 0:efd786b99a72 | 220 | break; |
AtomX | 0:efd786b99a72 | 221 | } |
AtomX | 1:63d729186747 | 222 | |
AtomX | 0:efd786b99a72 | 223 | if (--i == 0) |
AtomX | 0:efd786b99a72 | 224 | { |
AtomX | 0:efd786b99a72 | 225 | // The emergency break. We will eventually terminate on this one after 89ms. |
AtomX | 0:efd786b99a72 | 226 | // Communication with the MFRC522 might be down. |
AtomX | 0:efd786b99a72 | 227 | return STATUS_TIMEOUT; |
AtomX | 0:efd786b99a72 | 228 | } |
AtomX | 0:efd786b99a72 | 229 | } |
AtomX | 0:efd786b99a72 | 230 | |
AtomX | 0:efd786b99a72 | 231 | // Stop calculating CRC for new content in the FIFO. |
AtomX | 0:efd786b99a72 | 232 | PCD_WriteRegister(CommandReg, PCD_Idle); |
AtomX | 0:efd786b99a72 | 233 | |
AtomX | 0:efd786b99a72 | 234 | // Transfer the result from the registers to the result buffer |
AtomX | 0:efd786b99a72 | 235 | result[0] = PCD_ReadRegister(CRCResultRegL); |
AtomX | 0:efd786b99a72 | 236 | result[1] = PCD_ReadRegister(CRCResultRegH); |
AtomX | 0:efd786b99a72 | 237 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 238 | } // End PCD_CalculateCRC() |
AtomX | 0:efd786b99a72 | 239 | |
AtomX | 0:efd786b99a72 | 240 | |
AtomX | 0:efd786b99a72 | 241 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 242 | // Functions for manipulating the MFRC522 |
AtomX | 0:efd786b99a72 | 243 | ///////////////////////////////////////////////////////////////////////////////////// |
andcor02 | 3:654723104cc9 | 244 | void MFRC522::PCD_Reset_On() |
andcor02 | 3:654723104cc9 | 245 | { |
andcor02 | 3:654723104cc9 | 246 | m_RESET = 0; |
andcor02 | 3:654723104cc9 | 247 | } |
andcor02 | 3:654723104cc9 | 248 | |
andcor02 | 3:654723104cc9 | 249 | void MFRC522::PCD_Reset_Off() |
andcor02 | 3:654723104cc9 | 250 | { |
andcor02 | 3:654723104cc9 | 251 | m_RESET = 1; |
andcor02 | 3:654723104cc9 | 252 | } |
andcor02 | 3:654723104cc9 | 253 | |
AtomX | 0:efd786b99a72 | 254 | |
AtomX | 0:efd786b99a72 | 255 | /** |
AtomX | 0:efd786b99a72 | 256 | * Initializes the MFRC522 chip. |
AtomX | 0:efd786b99a72 | 257 | */ |
AtomX | 0:efd786b99a72 | 258 | void MFRC522::PCD_Init() |
AtomX | 0:efd786b99a72 | 259 | { |
AtomX | 0:efd786b99a72 | 260 | /* Reset MFRC522 */ |
AtomX | 0:efd786b99a72 | 261 | m_RESET = 0; |
AtomX | 0:efd786b99a72 | 262 | wait_ms(10); |
AtomX | 0:efd786b99a72 | 263 | m_RESET = 1; |
AtomX | 1:63d729186747 | 264 | |
AtomX | 1:63d729186747 | 265 | // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms. |
AtomX | 0:efd786b99a72 | 266 | wait_ms(50); |
AtomX | 0:efd786b99a72 | 267 | |
AtomX | 0:efd786b99a72 | 268 | // When communicating with a PICC we need a timeout if something goes wrong. |
AtomX | 0:efd786b99a72 | 269 | // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]. |
AtomX | 0:efd786b99a72 | 270 | // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg. |
AtomX | 0:efd786b99a72 | 271 | PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds |
AtomX | 1:63d729186747 | 272 | PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us. |
AtomX | 0:efd786b99a72 | 273 | PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout. |
AtomX | 0:efd786b99a72 | 274 | PCD_WriteRegister(TReloadRegL, 0xE8); |
AtomX | 0:efd786b99a72 | 275 | |
AtomX | 0:efd786b99a72 | 276 | PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting |
AtomX | 0:efd786b99a72 | 277 | PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4) |
AtomX | 0:efd786b99a72 | 278 | |
AtomX | 0:efd786b99a72 | 279 | PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max |
AtomX | 0:efd786b99a72 | 280 | |
AtomX | 0:efd786b99a72 | 281 | PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset) |
AtomX | 0:efd786b99a72 | 282 | } // End PCD_Init() |
AtomX | 0:efd786b99a72 | 283 | |
AtomX | 0:efd786b99a72 | 284 | /** |
AtomX | 0:efd786b99a72 | 285 | * Performs a soft reset on the MFRC522 chip and waits for it to be ready again. |
AtomX | 0:efd786b99a72 | 286 | */ |
AtomX | 0:efd786b99a72 | 287 | void MFRC522::PCD_Reset() |
AtomX | 0:efd786b99a72 | 288 | { |
AtomX | 0:efd786b99a72 | 289 | PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command. |
AtomX | 0:efd786b99a72 | 290 | // The datasheet does not mention how long the SoftRest command takes to complete. |
AtomX | 0:efd786b99a72 | 291 | // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg) |
AtomX | 1:63d729186747 | 292 | // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms. |
AtomX | 0:efd786b99a72 | 293 | wait_ms(50); |
AtomX | 0:efd786b99a72 | 294 | |
AtomX | 0:efd786b99a72 | 295 | // Wait for the PowerDown bit in CommandReg to be cleared |
AtomX | 0:efd786b99a72 | 296 | while (PCD_ReadRegister(CommandReg) & (1<<4)) |
AtomX | 0:efd786b99a72 | 297 | { |
AtomX | 0:efd786b99a72 | 298 | // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry. |
AtomX | 0:efd786b99a72 | 299 | } |
AtomX | 0:efd786b99a72 | 300 | } // End PCD_Reset() |
AtomX | 0:efd786b99a72 | 301 | |
AtomX | 0:efd786b99a72 | 302 | /** |
AtomX | 0:efd786b99a72 | 303 | * Turns the antenna on by enabling pins TX1 and TX2. |
AtomX | 0:efd786b99a72 | 304 | * After a reset these pins disabled. |
AtomX | 0:efd786b99a72 | 305 | */ |
AtomX | 0:efd786b99a72 | 306 | void MFRC522::PCD_AntennaOn() |
AtomX | 0:efd786b99a72 | 307 | { |
AtomX | 0:efd786b99a72 | 308 | uint8_t value = PCD_ReadRegister(TxControlReg); |
AtomX | 0:efd786b99a72 | 309 | if ((value & 0x03) != 0x03) |
AtomX | 0:efd786b99a72 | 310 | { |
AtomX | 0:efd786b99a72 | 311 | PCD_WriteRegister(TxControlReg, value | 0x03); |
AtomX | 0:efd786b99a72 | 312 | } |
AtomX | 0:efd786b99a72 | 313 | } // End PCD_AntennaOn() |
AtomX | 0:efd786b99a72 | 314 | |
AtomX | 0:efd786b99a72 | 315 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 316 | // Functions for communicating with PICCs |
AtomX | 0:efd786b99a72 | 317 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 318 | |
AtomX | 0:efd786b99a72 | 319 | /** |
AtomX | 0:efd786b99a72 | 320 | * Executes the Transceive command. |
AtomX | 0:efd786b99a72 | 321 | * CRC validation can only be done if backData and backLen are specified. |
AtomX | 0:efd786b99a72 | 322 | */ |
AtomX | 1:63d729186747 | 323 | uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData, |
AtomX | 1:63d729186747 | 324 | uint8_t sendLen, |
AtomX | 1:63d729186747 | 325 | uint8_t *backData, |
AtomX | 1:63d729186747 | 326 | uint8_t *backLen, |
AtomX | 1:63d729186747 | 327 | uint8_t *validBits, |
AtomX | 1:63d729186747 | 328 | uint8_t rxAlign, |
AtomX | 1:63d729186747 | 329 | bool checkCRC) |
AtomX | 0:efd786b99a72 | 330 | { |
AtomX | 0:efd786b99a72 | 331 | uint8_t waitIRq = 0x30; // RxIRq and IdleIRq |
AtomX | 0:efd786b99a72 | 332 | return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC); |
AtomX | 0:efd786b99a72 | 333 | } // End PCD_TransceiveData() |
AtomX | 0:efd786b99a72 | 334 | |
AtomX | 0:efd786b99a72 | 335 | /** |
AtomX | 0:efd786b99a72 | 336 | * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO. |
AtomX | 0:efd786b99a72 | 337 | * CRC validation can only be done if backData and backLen are specified. |
AtomX | 0:efd786b99a72 | 338 | */ |
AtomX | 1:63d729186747 | 339 | uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command, |
AtomX | 1:63d729186747 | 340 | uint8_t waitIRq, |
AtomX | 1:63d729186747 | 341 | uint8_t *sendData, |
AtomX | 1:63d729186747 | 342 | uint8_t sendLen, |
AtomX | 1:63d729186747 | 343 | uint8_t *backData, |
AtomX | 1:63d729186747 | 344 | uint8_t *backLen, |
AtomX | 1:63d729186747 | 345 | uint8_t *validBits, |
AtomX | 1:63d729186747 | 346 | uint8_t rxAlign, |
AtomX | 1:63d729186747 | 347 | bool checkCRC) |
AtomX | 0:efd786b99a72 | 348 | { |
AtomX | 0:efd786b99a72 | 349 | uint8_t n, _validBits = 0; |
AtomX | 0:efd786b99a72 | 350 | uint32_t i; |
AtomX | 0:efd786b99a72 | 351 | |
AtomX | 0:efd786b99a72 | 352 | // Prepare values for BitFramingReg |
AtomX | 0:efd786b99a72 | 353 | uint8_t txLastBits = validBits ? *validBits : 0; |
AtomX | 0:efd786b99a72 | 354 | uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0] |
AtomX | 0:efd786b99a72 | 355 | |
AtomX | 0:efd786b99a72 | 356 | PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command. |
AtomX | 0:efd786b99a72 | 357 | PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits |
AtomX | 0:efd786b99a72 | 358 | PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization |
AtomX | 0:efd786b99a72 | 359 | PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO |
AtomX | 0:efd786b99a72 | 360 | PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments |
AtomX | 0:efd786b99a72 | 361 | PCD_WriteRegister(CommandReg, command); // Execute the command |
AtomX | 0:efd786b99a72 | 362 | if (command == PCD_Transceive) |
AtomX | 0:efd786b99a72 | 363 | { |
AtomX | 0:efd786b99a72 | 364 | PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts |
AtomX | 0:efd786b99a72 | 365 | } |
AtomX | 0:efd786b99a72 | 366 | |
AtomX | 0:efd786b99a72 | 367 | // Wait for the command to complete. |
AtomX | 0:efd786b99a72 | 368 | // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting. |
AtomX | 1:63d729186747 | 369 | // Each iteration of the do-while-loop takes 17.86us. |
AtomX | 0:efd786b99a72 | 370 | i = 2000; |
AtomX | 0:efd786b99a72 | 371 | while (1) |
AtomX | 0:efd786b99a72 | 372 | { |
AtomX | 0:efd786b99a72 | 373 | n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq |
AtomX | 0:efd786b99a72 | 374 | if (n & waitIRq) |
AtomX | 0:efd786b99a72 | 375 | { // One of the interrupts that signal success has been set. |
AtomX | 0:efd786b99a72 | 376 | break; |
AtomX | 0:efd786b99a72 | 377 | } |
AtomX | 0:efd786b99a72 | 378 | |
AtomX | 0:efd786b99a72 | 379 | if (n & 0x01) |
AtomX | 0:efd786b99a72 | 380 | { // Timer interrupt - nothing received in 25ms |
AtomX | 0:efd786b99a72 | 381 | return STATUS_TIMEOUT; |
AtomX | 0:efd786b99a72 | 382 | } |
AtomX | 0:efd786b99a72 | 383 | |
AtomX | 0:efd786b99a72 | 384 | if (--i == 0) |
AtomX | 0:efd786b99a72 | 385 | { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down. |
AtomX | 0:efd786b99a72 | 386 | return STATUS_TIMEOUT; |
AtomX | 0:efd786b99a72 | 387 | } |
AtomX | 0:efd786b99a72 | 388 | } |
AtomX | 0:efd786b99a72 | 389 | |
AtomX | 0:efd786b99a72 | 390 | // Stop now if any errors except collisions were detected. |
AtomX | 0:efd786b99a72 | 391 | uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr |
AtomX | 0:efd786b99a72 | 392 | if (errorRegValue & 0x13) |
AtomX | 0:efd786b99a72 | 393 | { // BufferOvfl ParityErr ProtocolErr |
AtomX | 0:efd786b99a72 | 394 | return STATUS_ERROR; |
AtomX | 0:efd786b99a72 | 395 | } |
AtomX | 0:efd786b99a72 | 396 | |
AtomX | 0:efd786b99a72 | 397 | // If the caller wants data back, get it from the MFRC522. |
AtomX | 0:efd786b99a72 | 398 | if (backData && backLen) |
AtomX | 0:efd786b99a72 | 399 | { |
AtomX | 0:efd786b99a72 | 400 | n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO |
AtomX | 0:efd786b99a72 | 401 | if (n > *backLen) |
AtomX | 0:efd786b99a72 | 402 | { |
AtomX | 0:efd786b99a72 | 403 | return STATUS_NO_ROOM; |
AtomX | 0:efd786b99a72 | 404 | } |
AtomX | 0:efd786b99a72 | 405 | |
AtomX | 0:efd786b99a72 | 406 | *backLen = n; // Number of bytes returned |
AtomX | 0:efd786b99a72 | 407 | PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO |
AtomX | 0:efd786b99a72 | 408 | _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid. |
AtomX | 0:efd786b99a72 | 409 | if (validBits) |
AtomX | 0:efd786b99a72 | 410 | { |
AtomX | 0:efd786b99a72 | 411 | *validBits = _validBits; |
AtomX | 0:efd786b99a72 | 412 | } |
AtomX | 0:efd786b99a72 | 413 | } |
AtomX | 0:efd786b99a72 | 414 | |
AtomX | 0:efd786b99a72 | 415 | // Tell about collisions |
AtomX | 0:efd786b99a72 | 416 | if (errorRegValue & 0x08) |
AtomX | 0:efd786b99a72 | 417 | { // CollErr |
AtomX | 0:efd786b99a72 | 418 | return STATUS_COLLISION; |
AtomX | 0:efd786b99a72 | 419 | } |
AtomX | 0:efd786b99a72 | 420 | |
AtomX | 0:efd786b99a72 | 421 | // Perform CRC_A validation if requested. |
AtomX | 0:efd786b99a72 | 422 | if (backData && backLen && checkCRC) |
AtomX | 0:efd786b99a72 | 423 | { |
AtomX | 0:efd786b99a72 | 424 | // In this case a MIFARE Classic NAK is not OK. |
AtomX | 0:efd786b99a72 | 425 | if ((*backLen == 1) && (_validBits == 4)) |
AtomX | 0:efd786b99a72 | 426 | { |
AtomX | 0:efd786b99a72 | 427 | return STATUS_MIFARE_NACK; |
AtomX | 0:efd786b99a72 | 428 | } |
AtomX | 0:efd786b99a72 | 429 | |
AtomX | 0:efd786b99a72 | 430 | // We need at least the CRC_A value and all 8 bits of the last byte must be received. |
AtomX | 0:efd786b99a72 | 431 | if ((*backLen < 2) || (_validBits != 0)) |
AtomX | 0:efd786b99a72 | 432 | { |
AtomX | 0:efd786b99a72 | 433 | return STATUS_CRC_WRONG; |
AtomX | 0:efd786b99a72 | 434 | } |
AtomX | 0:efd786b99a72 | 435 | |
AtomX | 0:efd786b99a72 | 436 | // Verify CRC_A - do our own calculation and store the control in controlBuffer. |
AtomX | 0:efd786b99a72 | 437 | uint8_t controlBuffer[2]; |
AtomX | 0:efd786b99a72 | 438 | n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]); |
AtomX | 0:efd786b99a72 | 439 | if (n != STATUS_OK) |
AtomX | 0:efd786b99a72 | 440 | { |
AtomX | 0:efd786b99a72 | 441 | return n; |
AtomX | 0:efd786b99a72 | 442 | } |
AtomX | 0:efd786b99a72 | 443 | |
AtomX | 0:efd786b99a72 | 444 | if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1])) |
AtomX | 0:efd786b99a72 | 445 | { |
AtomX | 0:efd786b99a72 | 446 | return STATUS_CRC_WRONG; |
AtomX | 0:efd786b99a72 | 447 | } |
AtomX | 0:efd786b99a72 | 448 | } |
AtomX | 0:efd786b99a72 | 449 | |
AtomX | 0:efd786b99a72 | 450 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 451 | } // End PCD_CommunicateWithPICC() |
AtomX | 0:efd786b99a72 | 452 | |
AtomX | 1:63d729186747 | 453 | /* |
AtomX | 0:efd786b99a72 | 454 | * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame. |
AtomX | 0:efd786b99a72 | 455 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
AtomX | 0:efd786b99a72 | 456 | */ |
AtomX | 0:efd786b99a72 | 457 | uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize) |
AtomX | 0:efd786b99a72 | 458 | { |
AtomX | 0:efd786b99a72 | 459 | return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize); |
AtomX | 0:efd786b99a72 | 460 | } // End PICC_RequestA() |
AtomX | 0:efd786b99a72 | 461 | |
AtomX | 0:efd786b99a72 | 462 | /** |
AtomX | 0:efd786b99a72 | 463 | * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame. |
AtomX | 0:efd786b99a72 | 464 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
AtomX | 0:efd786b99a72 | 465 | */ |
AtomX | 0:efd786b99a72 | 466 | uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize) |
AtomX | 0:efd786b99a72 | 467 | { |
AtomX | 0:efd786b99a72 | 468 | return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize); |
AtomX | 0:efd786b99a72 | 469 | } // End PICC_WakeupA() |
AtomX | 0:efd786b99a72 | 470 | |
AtomX | 1:63d729186747 | 471 | /* |
AtomX | 0:efd786b99a72 | 472 | * Transmits REQA or WUPA commands. |
AtomX | 0:efd786b99a72 | 473 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
AtomX | 0:efd786b99a72 | 474 | */ |
AtomX | 0:efd786b99a72 | 475 | uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize) |
AtomX | 0:efd786b99a72 | 476 | { |
AtomX | 0:efd786b99a72 | 477 | uint8_t validBits; |
AtomX | 0:efd786b99a72 | 478 | uint8_t status; |
AtomX | 0:efd786b99a72 | 479 | |
AtomX | 0:efd786b99a72 | 480 | if (bufferATQA == NULL || *bufferSize < 2) |
AtomX | 0:efd786b99a72 | 481 | { // The ATQA response is 2 bytes long. |
AtomX | 0:efd786b99a72 | 482 | return STATUS_NO_ROOM; |
AtomX | 0:efd786b99a72 | 483 | } |
AtomX | 0:efd786b99a72 | 484 | |
AtomX | 0:efd786b99a72 | 485 | // ValuesAfterColl=1 => Bits received after collision are cleared. |
AtomX | 0:efd786b99a72 | 486 | PCD_ClrRegisterBits(CollReg, 0x80); |
AtomX | 0:efd786b99a72 | 487 | |
AtomX | 0:efd786b99a72 | 488 | // For REQA and WUPA we need the short frame format |
AtomX | 0:efd786b99a72 | 489 | // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0] |
AtomX | 0:efd786b99a72 | 490 | validBits = 7; |
AtomX | 0:efd786b99a72 | 491 | |
AtomX | 0:efd786b99a72 | 492 | status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits); |
AtomX | 0:efd786b99a72 | 493 | if (status != STATUS_OK) |
AtomX | 0:efd786b99a72 | 494 | { |
AtomX | 0:efd786b99a72 | 495 | return status; |
AtomX | 0:efd786b99a72 | 496 | } |
AtomX | 0:efd786b99a72 | 497 | |
AtomX | 0:efd786b99a72 | 498 | if ((*bufferSize != 2) || (validBits != 0)) |
AtomX | 0:efd786b99a72 | 499 | { // ATQA must be exactly 16 bits. |
AtomX | 0:efd786b99a72 | 500 | return STATUS_ERROR; |
AtomX | 0:efd786b99a72 | 501 | } |
AtomX | 0:efd786b99a72 | 502 | |
AtomX | 0:efd786b99a72 | 503 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 504 | } // End PICC_REQA_or_WUPA() |
AtomX | 0:efd786b99a72 | 505 | |
AtomX | 1:63d729186747 | 506 | /* |
AtomX | 0:efd786b99a72 | 507 | * Transmits SELECT/ANTICOLLISION commands to select a single PICC. |
AtomX | 0:efd786b99a72 | 508 | */ |
AtomX | 0:efd786b99a72 | 509 | uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits) |
AtomX | 0:efd786b99a72 | 510 | { |
AtomX | 0:efd786b99a72 | 511 | bool uidComplete; |
AtomX | 0:efd786b99a72 | 512 | bool selectDone; |
AtomX | 0:efd786b99a72 | 513 | bool useCascadeTag; |
AtomX | 0:efd786b99a72 | 514 | uint8_t cascadeLevel = 1; |
AtomX | 0:efd786b99a72 | 515 | uint8_t result; |
AtomX | 0:efd786b99a72 | 516 | uint8_t count; |
AtomX | 0:efd786b99a72 | 517 | uint8_t index; |
AtomX | 0:efd786b99a72 | 518 | uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level. |
AtomX | 0:efd786b99a72 | 519 | uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level. |
AtomX | 0:efd786b99a72 | 520 | uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A |
AtomX | 0:efd786b99a72 | 521 | uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO. |
AtomX | 0:efd786b99a72 | 522 | uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received. |
AtomX | 0:efd786b99a72 | 523 | uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte. |
AtomX | 0:efd786b99a72 | 524 | uint8_t *responseBuffer; |
AtomX | 0:efd786b99a72 | 525 | uint8_t responseLength; |
AtomX | 0:efd786b99a72 | 526 | |
AtomX | 0:efd786b99a72 | 527 | // Description of buffer structure: |
AtomX | 0:efd786b99a72 | 528 | // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3 |
AtomX | 0:efd786b99a72 | 529 | // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits. |
AtomX | 0:efd786b99a72 | 530 | // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag. |
AtomX | 0:efd786b99a72 | 531 | // Byte 3: UID-data |
AtomX | 0:efd786b99a72 | 532 | // Byte 4: UID-data |
AtomX | 0:efd786b99a72 | 533 | // Byte 5: UID-data |
AtomX | 0:efd786b99a72 | 534 | // Byte 6: BCC Block Check Character - XOR of bytes 2-5 |
AtomX | 0:efd786b99a72 | 535 | // Byte 7: CRC_A |
AtomX | 0:efd786b99a72 | 536 | // Byte 8: CRC_A |
AtomX | 0:efd786b99a72 | 537 | // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level. |
AtomX | 0:efd786b99a72 | 538 | // |
AtomX | 0:efd786b99a72 | 539 | // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels) |
AtomX | 0:efd786b99a72 | 540 | // UID size Cascade level Byte2 Byte3 Byte4 Byte5 |
AtomX | 0:efd786b99a72 | 541 | // ======== ============= ===== ===== ===== ===== |
AtomX | 0:efd786b99a72 | 542 | // 4 bytes 1 uid0 uid1 uid2 uid3 |
AtomX | 0:efd786b99a72 | 543 | // 7 bytes 1 CT uid0 uid1 uid2 |
AtomX | 0:efd786b99a72 | 544 | // 2 uid3 uid4 uid5 uid6 |
AtomX | 0:efd786b99a72 | 545 | // 10 bytes 1 CT uid0 uid1 uid2 |
AtomX | 0:efd786b99a72 | 546 | // 2 CT uid3 uid4 uid5 |
AtomX | 0:efd786b99a72 | 547 | // 3 uid6 uid7 uid8 uid9 |
AtomX | 0:efd786b99a72 | 548 | |
AtomX | 0:efd786b99a72 | 549 | // Sanity checks |
AtomX | 0:efd786b99a72 | 550 | if (validBits > 80) |
AtomX | 0:efd786b99a72 | 551 | { |
AtomX | 0:efd786b99a72 | 552 | return STATUS_INVALID; |
AtomX | 0:efd786b99a72 | 553 | } |
AtomX | 0:efd786b99a72 | 554 | |
AtomX | 0:efd786b99a72 | 555 | // Prepare MFRC522 |
AtomX | 0:efd786b99a72 | 556 | // ValuesAfterColl=1 => Bits received after collision are cleared. |
AtomX | 0:efd786b99a72 | 557 | PCD_ClrRegisterBits(CollReg, 0x80); |
AtomX | 0:efd786b99a72 | 558 | |
AtomX | 0:efd786b99a72 | 559 | // Repeat Cascade Level loop until we have a complete UID. |
AtomX | 0:efd786b99a72 | 560 | uidComplete = false; |
AtomX | 0:efd786b99a72 | 561 | while ( ! uidComplete) |
AtomX | 0:efd786b99a72 | 562 | { |
AtomX | 0:efd786b99a72 | 563 | // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2. |
AtomX | 0:efd786b99a72 | 564 | switch (cascadeLevel) |
AtomX | 0:efd786b99a72 | 565 | { |
AtomX | 0:efd786b99a72 | 566 | case 1: |
AtomX | 0:efd786b99a72 | 567 | buffer[0] = PICC_CMD_SEL_CL1; |
AtomX | 0:efd786b99a72 | 568 | uidIndex = 0; |
AtomX | 0:efd786b99a72 | 569 | useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes |
AtomX | 0:efd786b99a72 | 570 | break; |
AtomX | 0:efd786b99a72 | 571 | |
AtomX | 0:efd786b99a72 | 572 | case 2: |
AtomX | 0:efd786b99a72 | 573 | buffer[0] = PICC_CMD_SEL_CL2; |
AtomX | 0:efd786b99a72 | 574 | uidIndex = 3; |
AtomX | 0:efd786b99a72 | 575 | useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes |
AtomX | 0:efd786b99a72 | 576 | break; |
AtomX | 0:efd786b99a72 | 577 | |
AtomX | 0:efd786b99a72 | 578 | case 3: |
AtomX | 0:efd786b99a72 | 579 | buffer[0] = PICC_CMD_SEL_CL3; |
AtomX | 0:efd786b99a72 | 580 | uidIndex = 6; |
AtomX | 0:efd786b99a72 | 581 | useCascadeTag = false; // Never used in CL3. |
AtomX | 0:efd786b99a72 | 582 | break; |
AtomX | 0:efd786b99a72 | 583 | |
AtomX | 0:efd786b99a72 | 584 | default: |
AtomX | 0:efd786b99a72 | 585 | return STATUS_INTERNAL_ERROR; |
AtomX | 0:efd786b99a72 | 586 | //break; |
AtomX | 0:efd786b99a72 | 587 | } |
AtomX | 0:efd786b99a72 | 588 | |
AtomX | 0:efd786b99a72 | 589 | // How many UID bits are known in this Cascade Level? |
AtomX | 0:efd786b99a72 | 590 | if(validBits > (8 * uidIndex)) |
AtomX | 0:efd786b99a72 | 591 | { |
AtomX | 0:efd786b99a72 | 592 | currentLevelKnownBits = validBits - (8 * uidIndex); |
AtomX | 0:efd786b99a72 | 593 | } |
AtomX | 0:efd786b99a72 | 594 | else |
AtomX | 0:efd786b99a72 | 595 | { |
AtomX | 0:efd786b99a72 | 596 | currentLevelKnownBits = 0; |
AtomX | 0:efd786b99a72 | 597 | } |
AtomX | 0:efd786b99a72 | 598 | |
AtomX | 0:efd786b99a72 | 599 | // Copy the known bits from uid->uidByte[] to buffer[] |
AtomX | 0:efd786b99a72 | 600 | index = 2; // destination index in buffer[] |
AtomX | 0:efd786b99a72 | 601 | if (useCascadeTag) |
AtomX | 0:efd786b99a72 | 602 | { |
AtomX | 0:efd786b99a72 | 603 | buffer[index++] = PICC_CMD_CT; |
AtomX | 0:efd786b99a72 | 604 | } |
AtomX | 0:efd786b99a72 | 605 | |
AtomX | 0:efd786b99a72 | 606 | uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level. |
AtomX | 0:efd786b99a72 | 607 | if (bytesToCopy) |
AtomX | 0:efd786b99a72 | 608 | { |
AtomX | 0:efd786b99a72 | 609 | // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag |
AtomX | 0:efd786b99a72 | 610 | uint8_t maxBytes = useCascadeTag ? 3 : 4; |
AtomX | 0:efd786b99a72 | 611 | if (bytesToCopy > maxBytes) |
AtomX | 0:efd786b99a72 | 612 | { |
AtomX | 0:efd786b99a72 | 613 | bytesToCopy = maxBytes; |
AtomX | 0:efd786b99a72 | 614 | } |
AtomX | 0:efd786b99a72 | 615 | |
AtomX | 0:efd786b99a72 | 616 | for (count = 0; count < bytesToCopy; count++) |
AtomX | 0:efd786b99a72 | 617 | { |
AtomX | 0:efd786b99a72 | 618 | buffer[index++] = uid->uidByte[uidIndex + count]; |
AtomX | 0:efd786b99a72 | 619 | } |
AtomX | 0:efd786b99a72 | 620 | } |
AtomX | 0:efd786b99a72 | 621 | |
AtomX | 0:efd786b99a72 | 622 | // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits |
AtomX | 0:efd786b99a72 | 623 | if (useCascadeTag) |
AtomX | 0:efd786b99a72 | 624 | { |
AtomX | 0:efd786b99a72 | 625 | currentLevelKnownBits += 8; |
AtomX | 0:efd786b99a72 | 626 | } |
AtomX | 0:efd786b99a72 | 627 | |
AtomX | 0:efd786b99a72 | 628 | // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations. |
AtomX | 0:efd786b99a72 | 629 | selectDone = false; |
AtomX | 0:efd786b99a72 | 630 | while ( ! selectDone) |
AtomX | 0:efd786b99a72 | 631 | { |
AtomX | 0:efd786b99a72 | 632 | // Find out how many bits and bytes to send and receive. |
AtomX | 0:efd786b99a72 | 633 | if (currentLevelKnownBits >= 32) |
AtomX | 0:efd786b99a72 | 634 | { // All UID bits in this Cascade Level are known. This is a SELECT. |
AtomX | 0:efd786b99a72 | 635 | //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC); |
AtomX | 0:efd786b99a72 | 636 | buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes |
AtomX | 0:efd786b99a72 | 637 | |
AtomX | 0:efd786b99a72 | 638 | // Calulate BCC - Block Check Character |
AtomX | 0:efd786b99a72 | 639 | buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5]; |
AtomX | 0:efd786b99a72 | 640 | |
AtomX | 0:efd786b99a72 | 641 | // Calculate CRC_A |
AtomX | 0:efd786b99a72 | 642 | result = PCD_CalculateCRC(buffer, 7, &buffer[7]); |
AtomX | 0:efd786b99a72 | 643 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 644 | { |
AtomX | 0:efd786b99a72 | 645 | return result; |
AtomX | 0:efd786b99a72 | 646 | } |
AtomX | 0:efd786b99a72 | 647 | |
AtomX | 0:efd786b99a72 | 648 | txLastBits = 0; // 0 => All 8 bits are valid. |
AtomX | 0:efd786b99a72 | 649 | bufferUsed = 9; |
AtomX | 0:efd786b99a72 | 650 | |
AtomX | 0:efd786b99a72 | 651 | // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx) |
AtomX | 0:efd786b99a72 | 652 | responseBuffer = &buffer[6]; |
AtomX | 0:efd786b99a72 | 653 | responseLength = 3; |
AtomX | 0:efd786b99a72 | 654 | } |
AtomX | 0:efd786b99a72 | 655 | else |
AtomX | 0:efd786b99a72 | 656 | { // This is an ANTICOLLISION. |
AtomX | 0:efd786b99a72 | 657 | //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC); |
AtomX | 0:efd786b99a72 | 658 | txLastBits = currentLevelKnownBits % 8; |
AtomX | 0:efd786b99a72 | 659 | count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part. |
AtomX | 0:efd786b99a72 | 660 | index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs |
AtomX | 0:efd786b99a72 | 661 | buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits |
AtomX | 0:efd786b99a72 | 662 | bufferUsed = index + (txLastBits ? 1 : 0); |
AtomX | 0:efd786b99a72 | 663 | |
AtomX | 0:efd786b99a72 | 664 | // Store response in the unused part of buffer |
AtomX | 0:efd786b99a72 | 665 | responseBuffer = &buffer[index]; |
AtomX | 0:efd786b99a72 | 666 | responseLength = sizeof(buffer) - index; |
AtomX | 0:efd786b99a72 | 667 | } |
AtomX | 0:efd786b99a72 | 668 | |
AtomX | 0:efd786b99a72 | 669 | // Set bit adjustments |
AtomX | 0:efd786b99a72 | 670 | rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read. |
AtomX | 0:efd786b99a72 | 671 | PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0] |
AtomX | 0:efd786b99a72 | 672 | |
AtomX | 0:efd786b99a72 | 673 | // Transmit the buffer and receive the response. |
AtomX | 0:efd786b99a72 | 674 | result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign); |
AtomX | 0:efd786b99a72 | 675 | if (result == STATUS_COLLISION) |
AtomX | 0:efd786b99a72 | 676 | { // More than one PICC in the field => collision. |
AtomX | 0:efd786b99a72 | 677 | result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0] |
AtomX | 0:efd786b99a72 | 678 | if (result & 0x20) |
AtomX | 0:efd786b99a72 | 679 | { // CollPosNotValid |
AtomX | 0:efd786b99a72 | 680 | return STATUS_COLLISION; // Without a valid collision position we cannot continue |
AtomX | 0:efd786b99a72 | 681 | } |
AtomX | 0:efd786b99a72 | 682 | |
AtomX | 0:efd786b99a72 | 683 | uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32. |
AtomX | 0:efd786b99a72 | 684 | if (collisionPos == 0) |
AtomX | 0:efd786b99a72 | 685 | { |
AtomX | 0:efd786b99a72 | 686 | collisionPos = 32; |
AtomX | 0:efd786b99a72 | 687 | } |
AtomX | 0:efd786b99a72 | 688 | |
AtomX | 0:efd786b99a72 | 689 | if (collisionPos <= currentLevelKnownBits) |
AtomX | 0:efd786b99a72 | 690 | { // No progress - should not happen |
AtomX | 0:efd786b99a72 | 691 | return STATUS_INTERNAL_ERROR; |
AtomX | 0:efd786b99a72 | 692 | } |
AtomX | 0:efd786b99a72 | 693 | |
AtomX | 0:efd786b99a72 | 694 | // Choose the PICC with the bit set. |
AtomX | 0:efd786b99a72 | 695 | currentLevelKnownBits = collisionPos; |
AtomX | 0:efd786b99a72 | 696 | count = (currentLevelKnownBits - 1) % 8; // The bit to modify |
AtomX | 0:efd786b99a72 | 697 | index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0. |
AtomX | 0:efd786b99a72 | 698 | buffer[index] |= (1 << count); |
AtomX | 0:efd786b99a72 | 699 | } |
AtomX | 0:efd786b99a72 | 700 | else if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 701 | { |
AtomX | 0:efd786b99a72 | 702 | return result; |
AtomX | 0:efd786b99a72 | 703 | } |
AtomX | 0:efd786b99a72 | 704 | else |
AtomX | 0:efd786b99a72 | 705 | { // STATUS_OK |
AtomX | 0:efd786b99a72 | 706 | if (currentLevelKnownBits >= 32) |
AtomX | 0:efd786b99a72 | 707 | { // This was a SELECT. |
AtomX | 0:efd786b99a72 | 708 | selectDone = true; // No more anticollision |
AtomX | 0:efd786b99a72 | 709 | // We continue below outside the while. |
AtomX | 0:efd786b99a72 | 710 | } |
AtomX | 0:efd786b99a72 | 711 | else |
AtomX | 0:efd786b99a72 | 712 | { // This was an ANTICOLLISION. |
AtomX | 0:efd786b99a72 | 713 | // We now have all 32 bits of the UID in this Cascade Level |
AtomX | 0:efd786b99a72 | 714 | currentLevelKnownBits = 32; |
AtomX | 0:efd786b99a72 | 715 | // Run loop again to do the SELECT. |
AtomX | 0:efd786b99a72 | 716 | } |
AtomX | 0:efd786b99a72 | 717 | } |
AtomX | 0:efd786b99a72 | 718 | } // End of while ( ! selectDone) |
AtomX | 0:efd786b99a72 | 719 | |
AtomX | 0:efd786b99a72 | 720 | // We do not check the CBB - it was constructed by us above. |
AtomX | 0:efd786b99a72 | 721 | |
AtomX | 0:efd786b99a72 | 722 | // Copy the found UID bytes from buffer[] to uid->uidByte[] |
AtomX | 0:efd786b99a72 | 723 | index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[] |
AtomX | 0:efd786b99a72 | 724 | bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4; |
AtomX | 0:efd786b99a72 | 725 | for (count = 0; count < bytesToCopy; count++) |
AtomX | 0:efd786b99a72 | 726 | { |
AtomX | 0:efd786b99a72 | 727 | uid->uidByte[uidIndex + count] = buffer[index++]; |
AtomX | 0:efd786b99a72 | 728 | } |
AtomX | 0:efd786b99a72 | 729 | |
AtomX | 0:efd786b99a72 | 730 | // Check response SAK (Select Acknowledge) |
AtomX | 0:efd786b99a72 | 731 | if (responseLength != 3 || txLastBits != 0) |
AtomX | 0:efd786b99a72 | 732 | { // SAK must be exactly 24 bits (1 byte + CRC_A). |
AtomX | 0:efd786b99a72 | 733 | return STATUS_ERROR; |
AtomX | 0:efd786b99a72 | 734 | } |
AtomX | 0:efd786b99a72 | 735 | |
AtomX | 0:efd786b99a72 | 736 | // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore. |
AtomX | 0:efd786b99a72 | 737 | result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]); |
AtomX | 0:efd786b99a72 | 738 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 739 | { |
AtomX | 0:efd786b99a72 | 740 | return result; |
AtomX | 0:efd786b99a72 | 741 | } |
AtomX | 0:efd786b99a72 | 742 | |
AtomX | 0:efd786b99a72 | 743 | if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2])) |
AtomX | 0:efd786b99a72 | 744 | { |
AtomX | 0:efd786b99a72 | 745 | return STATUS_CRC_WRONG; |
AtomX | 0:efd786b99a72 | 746 | } |
AtomX | 0:efd786b99a72 | 747 | |
AtomX | 0:efd786b99a72 | 748 | if (responseBuffer[0] & 0x04) |
AtomX | 0:efd786b99a72 | 749 | { // Cascade bit set - UID not complete yes |
AtomX | 0:efd786b99a72 | 750 | cascadeLevel++; |
AtomX | 0:efd786b99a72 | 751 | } |
AtomX | 0:efd786b99a72 | 752 | else |
AtomX | 0:efd786b99a72 | 753 | { |
AtomX | 0:efd786b99a72 | 754 | uidComplete = true; |
AtomX | 0:efd786b99a72 | 755 | uid->sak = responseBuffer[0]; |
AtomX | 0:efd786b99a72 | 756 | } |
AtomX | 0:efd786b99a72 | 757 | } // End of while ( ! uidComplete) |
AtomX | 0:efd786b99a72 | 758 | |
AtomX | 0:efd786b99a72 | 759 | // Set correct uid->size |
AtomX | 0:efd786b99a72 | 760 | uid->size = 3 * cascadeLevel + 1; |
AtomX | 0:efd786b99a72 | 761 | |
AtomX | 0:efd786b99a72 | 762 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 763 | } // End PICC_Select() |
AtomX | 0:efd786b99a72 | 764 | |
AtomX | 1:63d729186747 | 765 | /* |
AtomX | 0:efd786b99a72 | 766 | * Instructs a PICC in state ACTIVE(*) to go to state HALT. |
AtomX | 0:efd786b99a72 | 767 | */ |
AtomX | 0:efd786b99a72 | 768 | uint8_t MFRC522::PICC_HaltA() |
AtomX | 0:efd786b99a72 | 769 | { |
AtomX | 0:efd786b99a72 | 770 | uint8_t result; |
AtomX | 0:efd786b99a72 | 771 | uint8_t buffer[4]; |
AtomX | 0:efd786b99a72 | 772 | |
AtomX | 0:efd786b99a72 | 773 | // Build command buffer |
AtomX | 0:efd786b99a72 | 774 | buffer[0] = PICC_CMD_HLTA; |
AtomX | 0:efd786b99a72 | 775 | buffer[1] = 0; |
AtomX | 0:efd786b99a72 | 776 | |
AtomX | 0:efd786b99a72 | 777 | // Calculate CRC_A |
AtomX | 0:efd786b99a72 | 778 | result = PCD_CalculateCRC(buffer, 2, &buffer[2]); |
AtomX | 0:efd786b99a72 | 779 | if (result == STATUS_OK) |
AtomX | 0:efd786b99a72 | 780 | { |
AtomX | 0:efd786b99a72 | 781 | // Send the command. |
AtomX | 0:efd786b99a72 | 782 | // The standard says: |
AtomX | 0:efd786b99a72 | 783 | // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the |
AtomX | 0:efd786b99a72 | 784 | // HLTA command, this response shall be interpreted as 'not acknowledge'. |
AtomX | 0:efd786b99a72 | 785 | // We interpret that this way: Only STATUS_TIMEOUT is an success. |
AtomX | 0:efd786b99a72 | 786 | result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0); |
AtomX | 0:efd786b99a72 | 787 | if (result == STATUS_TIMEOUT) |
AtomX | 0:efd786b99a72 | 788 | { |
AtomX | 0:efd786b99a72 | 789 | result = STATUS_OK; |
AtomX | 0:efd786b99a72 | 790 | } |
AtomX | 0:efd786b99a72 | 791 | else if (result == STATUS_OK) |
AtomX | 0:efd786b99a72 | 792 | { // That is ironically NOT ok in this case ;-) |
AtomX | 0:efd786b99a72 | 793 | result = STATUS_ERROR; |
AtomX | 0:efd786b99a72 | 794 | } |
AtomX | 0:efd786b99a72 | 795 | } |
AtomX | 0:efd786b99a72 | 796 | |
AtomX | 0:efd786b99a72 | 797 | return result; |
AtomX | 0:efd786b99a72 | 798 | } // End PICC_HaltA() |
AtomX | 0:efd786b99a72 | 799 | |
AtomX | 0:efd786b99a72 | 800 | |
AtomX | 0:efd786b99a72 | 801 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 802 | // Functions for communicating with MIFARE PICCs |
AtomX | 0:efd786b99a72 | 803 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 804 | |
AtomX | 1:63d729186747 | 805 | /* |
AtomX | 0:efd786b99a72 | 806 | * Executes the MFRC522 MFAuthent command. |
AtomX | 0:efd786b99a72 | 807 | */ |
AtomX | 0:efd786b99a72 | 808 | uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid) |
AtomX | 0:efd786b99a72 | 809 | { |
AtomX | 0:efd786b99a72 | 810 | uint8_t i, waitIRq = 0x10; // IdleIRq |
AtomX | 0:efd786b99a72 | 811 | |
AtomX | 0:efd786b99a72 | 812 | // Build command buffer |
AtomX | 0:efd786b99a72 | 813 | uint8_t sendData[12]; |
AtomX | 0:efd786b99a72 | 814 | sendData[0] = command; |
AtomX | 0:efd786b99a72 | 815 | sendData[1] = blockAddr; |
AtomX | 0:efd786b99a72 | 816 | |
AtomX | 0:efd786b99a72 | 817 | for (i = 0; i < MF_KEY_SIZE; i++) |
AtomX | 0:efd786b99a72 | 818 | { // 6 key bytes |
AtomX | 0:efd786b99a72 | 819 | sendData[2+i] = key->keyByte[i]; |
AtomX | 0:efd786b99a72 | 820 | } |
AtomX | 0:efd786b99a72 | 821 | |
AtomX | 0:efd786b99a72 | 822 | for (i = 0; i < 4; i++) |
AtomX | 0:efd786b99a72 | 823 | { // The first 4 bytes of the UID |
AtomX | 0:efd786b99a72 | 824 | sendData[8+i] = uid->uidByte[i]; |
AtomX | 0:efd786b99a72 | 825 | } |
AtomX | 0:efd786b99a72 | 826 | |
AtomX | 0:efd786b99a72 | 827 | // Start the authentication. |
AtomX | 0:efd786b99a72 | 828 | return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData)); |
AtomX | 0:efd786b99a72 | 829 | } // End PCD_Authenticate() |
AtomX | 0:efd786b99a72 | 830 | |
AtomX | 1:63d729186747 | 831 | /* |
AtomX | 0:efd786b99a72 | 832 | * Used to exit the PCD from its authenticated state. |
AtomX | 0:efd786b99a72 | 833 | * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start. |
AtomX | 0:efd786b99a72 | 834 | */ |
AtomX | 0:efd786b99a72 | 835 | void MFRC522::PCD_StopCrypto1() |
AtomX | 0:efd786b99a72 | 836 | { |
AtomX | 0:efd786b99a72 | 837 | // Clear MFCrypto1On bit |
AtomX | 0:efd786b99a72 | 838 | PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0] |
AtomX | 0:efd786b99a72 | 839 | } // End PCD_StopCrypto1() |
AtomX | 0:efd786b99a72 | 840 | |
AtomX | 1:63d729186747 | 841 | /* |
AtomX | 0:efd786b99a72 | 842 | * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC. |
AtomX | 0:efd786b99a72 | 843 | */ |
AtomX | 0:efd786b99a72 | 844 | uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize) |
AtomX | 0:efd786b99a72 | 845 | { |
AtomX | 0:efd786b99a72 | 846 | uint8_t result = STATUS_NO_ROOM; |
AtomX | 0:efd786b99a72 | 847 | |
AtomX | 0:efd786b99a72 | 848 | // Sanity check |
AtomX | 0:efd786b99a72 | 849 | if ((buffer == NULL) || (*bufferSize < 18)) |
AtomX | 0:efd786b99a72 | 850 | { |
AtomX | 0:efd786b99a72 | 851 | return result; |
AtomX | 0:efd786b99a72 | 852 | } |
AtomX | 0:efd786b99a72 | 853 | |
AtomX | 0:efd786b99a72 | 854 | // Build command buffer |
AtomX | 0:efd786b99a72 | 855 | buffer[0] = PICC_CMD_MF_READ; |
AtomX | 0:efd786b99a72 | 856 | buffer[1] = blockAddr; |
AtomX | 0:efd786b99a72 | 857 | |
AtomX | 0:efd786b99a72 | 858 | // Calculate CRC_A |
AtomX | 0:efd786b99a72 | 859 | result = PCD_CalculateCRC(buffer, 2, &buffer[2]); |
AtomX | 0:efd786b99a72 | 860 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 861 | { |
AtomX | 0:efd786b99a72 | 862 | return result; |
AtomX | 0:efd786b99a72 | 863 | } |
AtomX | 0:efd786b99a72 | 864 | |
AtomX | 0:efd786b99a72 | 865 | // Transmit the buffer and receive the response, validate CRC_A. |
AtomX | 0:efd786b99a72 | 866 | return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true); |
AtomX | 0:efd786b99a72 | 867 | } // End MIFARE_Read() |
AtomX | 0:efd786b99a72 | 868 | |
AtomX | 1:63d729186747 | 869 | /* |
AtomX | 0:efd786b99a72 | 870 | * Writes 16 bytes to the active PICC. |
AtomX | 0:efd786b99a72 | 871 | */ |
AtomX | 0:efd786b99a72 | 872 | uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize) |
AtomX | 0:efd786b99a72 | 873 | { |
AtomX | 0:efd786b99a72 | 874 | uint8_t result; |
AtomX | 0:efd786b99a72 | 875 | |
AtomX | 0:efd786b99a72 | 876 | // Sanity check |
AtomX | 0:efd786b99a72 | 877 | if (buffer == NULL || bufferSize < 16) |
AtomX | 0:efd786b99a72 | 878 | { |
AtomX | 0:efd786b99a72 | 879 | return STATUS_INVALID; |
AtomX | 0:efd786b99a72 | 880 | } |
AtomX | 0:efd786b99a72 | 881 | |
AtomX | 0:efd786b99a72 | 882 | // Mifare Classic protocol requires two communications to perform a write. |
AtomX | 0:efd786b99a72 | 883 | // Step 1: Tell the PICC we want to write to block blockAddr. |
AtomX | 0:efd786b99a72 | 884 | uint8_t cmdBuffer[2]; |
AtomX | 0:efd786b99a72 | 885 | cmdBuffer[0] = PICC_CMD_MF_WRITE; |
AtomX | 0:efd786b99a72 | 886 | cmdBuffer[1] = blockAddr; |
AtomX | 0:efd786b99a72 | 887 | // Adds CRC_A and checks that the response is MF_ACK. |
AtomX | 0:efd786b99a72 | 888 | result = PCD_MIFARE_Transceive(cmdBuffer, 2); |
AtomX | 0:efd786b99a72 | 889 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 890 | { |
AtomX | 0:efd786b99a72 | 891 | return result; |
AtomX | 0:efd786b99a72 | 892 | } |
AtomX | 0:efd786b99a72 | 893 | |
AtomX | 0:efd786b99a72 | 894 | // Step 2: Transfer the data |
AtomX | 0:efd786b99a72 | 895 | // Adds CRC_A and checks that the response is MF_ACK. |
AtomX | 0:efd786b99a72 | 896 | result = PCD_MIFARE_Transceive(buffer, bufferSize); |
AtomX | 0:efd786b99a72 | 897 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 898 | { |
AtomX | 0:efd786b99a72 | 899 | return result; |
AtomX | 0:efd786b99a72 | 900 | } |
AtomX | 0:efd786b99a72 | 901 | |
AtomX | 0:efd786b99a72 | 902 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 903 | } // End MIFARE_Write() |
AtomX | 0:efd786b99a72 | 904 | |
AtomX | 1:63d729186747 | 905 | /* |
AtomX | 0:efd786b99a72 | 906 | * Writes a 4 byte page to the active MIFARE Ultralight PICC. |
AtomX | 0:efd786b99a72 | 907 | */ |
AtomX | 0:efd786b99a72 | 908 | uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize) |
AtomX | 0:efd786b99a72 | 909 | { |
AtomX | 0:efd786b99a72 | 910 | uint8_t result; |
AtomX | 0:efd786b99a72 | 911 | |
AtomX | 0:efd786b99a72 | 912 | // Sanity check |
AtomX | 0:efd786b99a72 | 913 | if (buffer == NULL || bufferSize < 4) |
AtomX | 0:efd786b99a72 | 914 | { |
AtomX | 0:efd786b99a72 | 915 | return STATUS_INVALID; |
AtomX | 0:efd786b99a72 | 916 | } |
AtomX | 0:efd786b99a72 | 917 | |
AtomX | 0:efd786b99a72 | 918 | // Build commmand buffer |
AtomX | 0:efd786b99a72 | 919 | uint8_t cmdBuffer[6]; |
AtomX | 0:efd786b99a72 | 920 | cmdBuffer[0] = PICC_CMD_UL_WRITE; |
AtomX | 0:efd786b99a72 | 921 | cmdBuffer[1] = page; |
AtomX | 0:efd786b99a72 | 922 | memcpy(&cmdBuffer[2], buffer, 4); |
AtomX | 0:efd786b99a72 | 923 | |
AtomX | 0:efd786b99a72 | 924 | // Perform the write |
AtomX | 0:efd786b99a72 | 925 | result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK. |
AtomX | 0:efd786b99a72 | 926 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 927 | { |
AtomX | 0:efd786b99a72 | 928 | return result; |
AtomX | 0:efd786b99a72 | 929 | } |
AtomX | 0:efd786b99a72 | 930 | |
AtomX | 0:efd786b99a72 | 931 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 932 | } // End MIFARE_Ultralight_Write() |
AtomX | 0:efd786b99a72 | 933 | |
AtomX | 1:63d729186747 | 934 | /* |
AtomX | 0:efd786b99a72 | 935 | * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory. |
AtomX | 0:efd786b99a72 | 936 | */ |
AtomX | 0:efd786b99a72 | 937 | uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta) |
AtomX | 0:efd786b99a72 | 938 | { |
AtomX | 0:efd786b99a72 | 939 | return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta); |
AtomX | 0:efd786b99a72 | 940 | } // End MIFARE_Decrement() |
AtomX | 0:efd786b99a72 | 941 | |
AtomX | 1:63d729186747 | 942 | /* |
AtomX | 0:efd786b99a72 | 943 | * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory. |
AtomX | 0:efd786b99a72 | 944 | */ |
AtomX | 0:efd786b99a72 | 945 | uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta) |
AtomX | 0:efd786b99a72 | 946 | { |
AtomX | 0:efd786b99a72 | 947 | return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta); |
AtomX | 0:efd786b99a72 | 948 | } // End MIFARE_Increment() |
AtomX | 0:efd786b99a72 | 949 | |
AtomX | 0:efd786b99a72 | 950 | /** |
AtomX | 0:efd786b99a72 | 951 | * MIFARE Restore copies the value of the addressed block into a volatile memory. |
AtomX | 0:efd786b99a72 | 952 | */ |
AtomX | 0:efd786b99a72 | 953 | uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr) |
AtomX | 0:efd786b99a72 | 954 | { |
AtomX | 0:efd786b99a72 | 955 | // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2. |
AtomX | 0:efd786b99a72 | 956 | // Doing only a single step does not work, so I chose to transfer 0L in step two. |
AtomX | 0:efd786b99a72 | 957 | return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L); |
AtomX | 0:efd786b99a72 | 958 | } // End MIFARE_Restore() |
AtomX | 0:efd786b99a72 | 959 | |
AtomX | 1:63d729186747 | 960 | /* |
AtomX | 0:efd786b99a72 | 961 | * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore. |
AtomX | 0:efd786b99a72 | 962 | */ |
AtomX | 0:efd786b99a72 | 963 | uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data) |
AtomX | 0:efd786b99a72 | 964 | { |
AtomX | 0:efd786b99a72 | 965 | uint8_t result; |
AtomX | 0:efd786b99a72 | 966 | uint8_t cmdBuffer[2]; // We only need room for 2 bytes. |
AtomX | 0:efd786b99a72 | 967 | |
AtomX | 0:efd786b99a72 | 968 | // Step 1: Tell the PICC the command and block address |
AtomX | 0:efd786b99a72 | 969 | cmdBuffer[0] = command; |
AtomX | 0:efd786b99a72 | 970 | cmdBuffer[1] = blockAddr; |
AtomX | 0:efd786b99a72 | 971 | |
AtomX | 0:efd786b99a72 | 972 | // Adds CRC_A and checks that the response is MF_ACK. |
AtomX | 0:efd786b99a72 | 973 | result = PCD_MIFARE_Transceive(cmdBuffer, 2); |
AtomX | 0:efd786b99a72 | 974 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 975 | { |
AtomX | 0:efd786b99a72 | 976 | return result; |
AtomX | 0:efd786b99a72 | 977 | } |
AtomX | 0:efd786b99a72 | 978 | |
AtomX | 0:efd786b99a72 | 979 | // Step 2: Transfer the data |
AtomX | 0:efd786b99a72 | 980 | // Adds CRC_A and accept timeout as success. |
AtomX | 0:efd786b99a72 | 981 | result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true); |
AtomX | 0:efd786b99a72 | 982 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 983 | { |
AtomX | 0:efd786b99a72 | 984 | return result; |
AtomX | 0:efd786b99a72 | 985 | } |
AtomX | 0:efd786b99a72 | 986 | |
AtomX | 0:efd786b99a72 | 987 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 988 | } // End MIFARE_TwoStepHelper() |
AtomX | 0:efd786b99a72 | 989 | |
AtomX | 1:63d729186747 | 990 | /* |
AtomX | 0:efd786b99a72 | 991 | * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block. |
AtomX | 0:efd786b99a72 | 992 | */ |
AtomX | 0:efd786b99a72 | 993 | uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr) |
AtomX | 0:efd786b99a72 | 994 | { |
AtomX | 0:efd786b99a72 | 995 | uint8_t cmdBuffer[2]; // We only need room for 2 bytes. |
AtomX | 0:efd786b99a72 | 996 | |
AtomX | 0:efd786b99a72 | 997 | // Tell the PICC we want to transfer the result into block blockAddr. |
AtomX | 0:efd786b99a72 | 998 | cmdBuffer[0] = PICC_CMD_MF_TRANSFER; |
AtomX | 0:efd786b99a72 | 999 | cmdBuffer[1] = blockAddr; |
AtomX | 0:efd786b99a72 | 1000 | |
AtomX | 0:efd786b99a72 | 1001 | // Adds CRC_A and checks that the response is MF_ACK. |
AtomX | 0:efd786b99a72 | 1002 | return PCD_MIFARE_Transceive(cmdBuffer, 2); |
AtomX | 0:efd786b99a72 | 1003 | } // End MIFARE_Transfer() |
AtomX | 0:efd786b99a72 | 1004 | |
AtomX | 0:efd786b99a72 | 1005 | |
AtomX | 0:efd786b99a72 | 1006 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 1007 | // Support functions |
AtomX | 0:efd786b99a72 | 1008 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 1009 | |
AtomX | 1:63d729186747 | 1010 | /* |
AtomX | 0:efd786b99a72 | 1011 | * Wrapper for MIFARE protocol communication. |
AtomX | 0:efd786b99a72 | 1012 | * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout. |
AtomX | 0:efd786b99a72 | 1013 | */ |
AtomX | 0:efd786b99a72 | 1014 | uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout) |
AtomX | 0:efd786b99a72 | 1015 | { |
AtomX | 0:efd786b99a72 | 1016 | uint8_t result; |
AtomX | 0:efd786b99a72 | 1017 | uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A. |
AtomX | 0:efd786b99a72 | 1018 | |
AtomX | 0:efd786b99a72 | 1019 | // Sanity check |
AtomX | 0:efd786b99a72 | 1020 | if (sendData == NULL || sendLen > 16) |
AtomX | 0:efd786b99a72 | 1021 | { |
AtomX | 0:efd786b99a72 | 1022 | return STATUS_INVALID; |
AtomX | 0:efd786b99a72 | 1023 | } |
AtomX | 0:efd786b99a72 | 1024 | |
AtomX | 0:efd786b99a72 | 1025 | // Copy sendData[] to cmdBuffer[] and add CRC_A |
AtomX | 0:efd786b99a72 | 1026 | memcpy(cmdBuffer, sendData, sendLen); |
AtomX | 0:efd786b99a72 | 1027 | result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]); |
AtomX | 0:efd786b99a72 | 1028 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 1029 | { |
AtomX | 0:efd786b99a72 | 1030 | return result; |
AtomX | 0:efd786b99a72 | 1031 | } |
AtomX | 0:efd786b99a72 | 1032 | |
AtomX | 0:efd786b99a72 | 1033 | sendLen += 2; |
AtomX | 0:efd786b99a72 | 1034 | |
AtomX | 0:efd786b99a72 | 1035 | // Transceive the data, store the reply in cmdBuffer[] |
AtomX | 0:efd786b99a72 | 1036 | uint8_t waitIRq = 0x30; // RxIRq and IdleIRq |
AtomX | 0:efd786b99a72 | 1037 | uint8_t cmdBufferSize = sizeof(cmdBuffer); |
AtomX | 0:efd786b99a72 | 1038 | uint8_t validBits = 0; |
AtomX | 0:efd786b99a72 | 1039 | result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits); |
AtomX | 0:efd786b99a72 | 1040 | if (acceptTimeout && result == STATUS_TIMEOUT) |
AtomX | 0:efd786b99a72 | 1041 | { |
AtomX | 0:efd786b99a72 | 1042 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 1043 | } |
AtomX | 0:efd786b99a72 | 1044 | |
AtomX | 0:efd786b99a72 | 1045 | if (result != STATUS_OK) |
AtomX | 0:efd786b99a72 | 1046 | { |
AtomX | 0:efd786b99a72 | 1047 | return result; |
AtomX | 0:efd786b99a72 | 1048 | } |
AtomX | 0:efd786b99a72 | 1049 | |
AtomX | 0:efd786b99a72 | 1050 | // The PICC must reply with a 4 bit ACK |
AtomX | 0:efd786b99a72 | 1051 | if (cmdBufferSize != 1 || validBits != 4) |
AtomX | 0:efd786b99a72 | 1052 | { |
AtomX | 0:efd786b99a72 | 1053 | return STATUS_ERROR; |
AtomX | 0:efd786b99a72 | 1054 | } |
AtomX | 0:efd786b99a72 | 1055 | |
AtomX | 0:efd786b99a72 | 1056 | if (cmdBuffer[0] != MF_ACK) |
AtomX | 0:efd786b99a72 | 1057 | { |
AtomX | 0:efd786b99a72 | 1058 | return STATUS_MIFARE_NACK; |
AtomX | 0:efd786b99a72 | 1059 | } |
AtomX | 0:efd786b99a72 | 1060 | |
AtomX | 0:efd786b99a72 | 1061 | return STATUS_OK; |
AtomX | 0:efd786b99a72 | 1062 | } // End PCD_MIFARE_Transceive() |
AtomX | 0:efd786b99a72 | 1063 | |
AtomX | 0:efd786b99a72 | 1064 | |
AtomX | 1:63d729186747 | 1065 | /* |
AtomX | 0:efd786b99a72 | 1066 | * Translates the SAK (Select Acknowledge) to a PICC type. |
AtomX | 0:efd786b99a72 | 1067 | */ |
AtomX | 0:efd786b99a72 | 1068 | uint8_t MFRC522::PICC_GetType(uint8_t sak) |
AtomX | 0:efd786b99a72 | 1069 | { |
AtomX | 0:efd786b99a72 | 1070 | uint8_t retType = PICC_TYPE_UNKNOWN; |
AtomX | 0:efd786b99a72 | 1071 | |
AtomX | 0:efd786b99a72 | 1072 | if (sak & 0x04) |
AtomX | 0:efd786b99a72 | 1073 | { // UID not complete |
AtomX | 0:efd786b99a72 | 1074 | retType = PICC_TYPE_NOT_COMPLETE; |
AtomX | 0:efd786b99a72 | 1075 | } |
AtomX | 0:efd786b99a72 | 1076 | else |
AtomX | 0:efd786b99a72 | 1077 | { |
AtomX | 0:efd786b99a72 | 1078 | switch (sak) |
AtomX | 0:efd786b99a72 | 1079 | { |
AtomX | 0:efd786b99a72 | 1080 | case 0x09: retType = PICC_TYPE_MIFARE_MINI; break; |
AtomX | 0:efd786b99a72 | 1081 | case 0x08: retType = PICC_TYPE_MIFARE_1K; break; |
AtomX | 0:efd786b99a72 | 1082 | case 0x18: retType = PICC_TYPE_MIFARE_4K; break; |
AtomX | 0:efd786b99a72 | 1083 | case 0x00: retType = PICC_TYPE_MIFARE_UL; break; |
AtomX | 0:efd786b99a72 | 1084 | case 0x10: |
AtomX | 0:efd786b99a72 | 1085 | case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break; |
AtomX | 0:efd786b99a72 | 1086 | case 0x01: retType = PICC_TYPE_TNP3XXX; break; |
AtomX | 0:efd786b99a72 | 1087 | default: |
AtomX | 0:efd786b99a72 | 1088 | if (sak & 0x20) |
AtomX | 0:efd786b99a72 | 1089 | { |
AtomX | 0:efd786b99a72 | 1090 | retType = PICC_TYPE_ISO_14443_4; |
AtomX | 0:efd786b99a72 | 1091 | } |
AtomX | 0:efd786b99a72 | 1092 | else if (sak & 0x40) |
AtomX | 0:efd786b99a72 | 1093 | { |
AtomX | 0:efd786b99a72 | 1094 | retType = PICC_TYPE_ISO_18092; |
AtomX | 0:efd786b99a72 | 1095 | } |
AtomX | 0:efd786b99a72 | 1096 | break; |
AtomX | 0:efd786b99a72 | 1097 | } |
AtomX | 0:efd786b99a72 | 1098 | } |
AtomX | 0:efd786b99a72 | 1099 | |
AtomX | 0:efd786b99a72 | 1100 | return (retType); |
AtomX | 0:efd786b99a72 | 1101 | } // End PICC_GetType() |
AtomX | 0:efd786b99a72 | 1102 | |
AtomX | 1:63d729186747 | 1103 | /* |
AtomX | 0:efd786b99a72 | 1104 | * Returns a string pointer to the PICC type name. |
AtomX | 0:efd786b99a72 | 1105 | */ |
AtomX | 0:efd786b99a72 | 1106 | char* MFRC522::PICC_GetTypeName(uint8_t piccType) |
AtomX | 0:efd786b99a72 | 1107 | { |
AtomX | 0:efd786b99a72 | 1108 | if(piccType == PICC_TYPE_NOT_COMPLETE) |
AtomX | 0:efd786b99a72 | 1109 | { |
AtomX | 0:efd786b99a72 | 1110 | piccType = MFRC522_MaxPICCs - 1; |
AtomX | 0:efd786b99a72 | 1111 | } |
AtomX | 0:efd786b99a72 | 1112 | |
AtomX | 0:efd786b99a72 | 1113 | return((char *) _TypeNamePICC[piccType]); |
AtomX | 0:efd786b99a72 | 1114 | } // End PICC_GetTypeName() |
AtomX | 0:efd786b99a72 | 1115 | |
AtomX | 1:63d729186747 | 1116 | /* |
AtomX | 0:efd786b99a72 | 1117 | * Returns a string pointer to a status code name. |
AtomX | 0:efd786b99a72 | 1118 | */ |
AtomX | 0:efd786b99a72 | 1119 | char* MFRC522::GetStatusCodeName(uint8_t code) |
AtomX | 0:efd786b99a72 | 1120 | { |
AtomX | 0:efd786b99a72 | 1121 | return((char *) _ErrorMessage[code]); |
AtomX | 0:efd786b99a72 | 1122 | } // End GetStatusCodeName() |
AtomX | 0:efd786b99a72 | 1123 | |
AtomX | 1:63d729186747 | 1124 | /* |
AtomX | 0:efd786b99a72 | 1125 | * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1). |
AtomX | 0:efd786b99a72 | 1126 | */ |
AtomX | 1:63d729186747 | 1127 | void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer, |
AtomX | 1:63d729186747 | 1128 | uint8_t g0, |
AtomX | 1:63d729186747 | 1129 | uint8_t g1, |
AtomX | 1:63d729186747 | 1130 | uint8_t g2, |
AtomX | 1:63d729186747 | 1131 | uint8_t g3) |
AtomX | 0:efd786b99a72 | 1132 | { |
AtomX | 0:efd786b99a72 | 1133 | uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2); |
AtomX | 0:efd786b99a72 | 1134 | uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1); |
AtomX | 0:efd786b99a72 | 1135 | uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0); |
AtomX | 0:efd786b99a72 | 1136 | |
AtomX | 0:efd786b99a72 | 1137 | accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF); |
AtomX | 0:efd786b99a72 | 1138 | accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF); |
AtomX | 0:efd786b99a72 | 1139 | accessBitBuffer[2] = c3 << 4 | c2; |
AtomX | 0:efd786b99a72 | 1140 | } // End MIFARE_SetAccessBits() |
AtomX | 0:efd786b99a72 | 1141 | |
AtomX | 0:efd786b99a72 | 1142 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 1143 | // Convenience functions - does not add extra functionality |
AtomX | 0:efd786b99a72 | 1144 | ///////////////////////////////////////////////////////////////////////////////////// |
AtomX | 0:efd786b99a72 | 1145 | |
AtomX | 1:63d729186747 | 1146 | /* |
AtomX | 0:efd786b99a72 | 1147 | * Returns true if a PICC responds to PICC_CMD_REQA. |
AtomX | 0:efd786b99a72 | 1148 | * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored. |
AtomX | 0:efd786b99a72 | 1149 | */ |
AtomX | 0:efd786b99a72 | 1150 | bool MFRC522::PICC_IsNewCardPresent(void) |
AtomX | 0:efd786b99a72 | 1151 | { |
AtomX | 0:efd786b99a72 | 1152 | uint8_t bufferATQA[2]; |
AtomX | 0:efd786b99a72 | 1153 | uint8_t bufferSize = sizeof(bufferATQA); |
AtomX | 0:efd786b99a72 | 1154 | uint8_t result = PICC_RequestA(bufferATQA, &bufferSize); |
AtomX | 0:efd786b99a72 | 1155 | return ((result == STATUS_OK) || (result == STATUS_COLLISION)); |
AtomX | 0:efd786b99a72 | 1156 | } // End PICC_IsNewCardPresent() |
AtomX | 0:efd786b99a72 | 1157 | |
AtomX | 1:63d729186747 | 1158 | /* |
AtomX | 0:efd786b99a72 | 1159 | * Simple wrapper around PICC_Select. |
AtomX | 0:efd786b99a72 | 1160 | */ |
AtomX | 0:efd786b99a72 | 1161 | bool MFRC522::PICC_ReadCardSerial(void) |
AtomX | 0:efd786b99a72 | 1162 | { |
AtomX | 0:efd786b99a72 | 1163 | uint8_t result = PICC_Select(&uid); |
AtomX | 0:efd786b99a72 | 1164 | return (result == STATUS_OK); |
AtomX | 0:efd786b99a72 | 1165 | } // End PICC_ReadCardSerial() |