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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:: mbed_official
Date:: Wed Feb 26 09:45:12 2014 +0000
Revision:: 106:ced8cbb51063
Parent:: 87:085cde657901

Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_spi.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	106:ced8cbb51063	5	* @version V1.0.0
mbed_official	106:ced8cbb51063	6	* @date 18-February-2014
mbed_official	87:085cde657901	7	* @brief SPI HAL module driver.
mbed_official	87:085cde657901	8	*
mbed_official	87:085cde657901	9	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	87:085cde657901	11	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	12	* + IO operation functions
mbed_official	87:085cde657901	13	* + Peripheral Control functions
mbed_official	87:085cde657901	14	* + Peripheral State functions
mbed_official	87:085cde657901	15	@verbatim
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	##### How to use this driver #####
mbed_official	87:085cde657901	18	==============================================================================
mbed_official	87:085cde657901	19	[..]
mbed_official	87:085cde657901	20	The SPI HAL driver can be used as follows:
mbed_official	87:085cde657901	21
mbed_official	87:085cde657901	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	87:085cde657901	23	SPI_HandleTypeDef hspi;
mbed_official	87:085cde657901	24
mbed_official	87:085cde657901	25	(#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official	87:085cde657901	26	(##) Enable the SPIx interface clock
mbed_official	87:085cde657901	27	(##) SPI pins configuration
mbed_official	87:085cde657901	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	87:085cde657901	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	87:085cde657901	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	87:085cde657901	31	(+++) Configure the SPIx interrupt priority
mbed_official	87:085cde657901	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	87:085cde657901	33	(##) DMA Configuration if you need to use DMA process
mbed_official	87:085cde657901	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official	87:085cde657901	35	(+++) Enable the DMAx interface clock using
mbed_official	87:085cde657901	36	(+++) Configure the DMA handle parameters
mbed_official	87:085cde657901	37	(+++) Configure the DMA Tx or Rx Stream
mbed_official	87:085cde657901	38	(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	87:085cde657901	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official	87:085cde657901	40
mbed_official	87:085cde657901	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	87:085cde657901	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	87:085cde657901	43
mbed_official	87:085cde657901	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	87:085cde657901	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	87:085cde657901	46	by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	@endverbatim
mbed_official	87:085cde657901	49	******************************************************************************
mbed_official	87:085cde657901	50	* @attention
mbed_official	87:085cde657901	51	*
mbed_official	87:085cde657901	52	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	53	*
mbed_official	87:085cde657901	54	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	55	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	56	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	57	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	58	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	59	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	60	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	61	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	62	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	63	* without specific prior written permission.
mbed_official	87:085cde657901	64	*
mbed_official	87:085cde657901	65	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	66	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	67	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	68	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	69	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	70	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	71	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	72	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	73	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	74	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	75	*
mbed_official	87:085cde657901	76	******************************************************************************
mbed_official	87:085cde657901	77	*/
mbed_official	87:085cde657901	78
mbed_official	87:085cde657901	79	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	80	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	81
mbed_official	87:085cde657901	82	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	83	* @{
mbed_official	87:085cde657901	84	*/
mbed_official	87:085cde657901	85
mbed_official	87:085cde657901	86	/** @defgroup SPI
mbed_official	87:085cde657901	87	* @brief SPI HAL module driver
mbed_official	87:085cde657901	88	* @{
mbed_official	87:085cde657901	89	*/
mbed_official	87:085cde657901	90
mbed_official	87:085cde657901	91	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	94	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	95	#define SPI_TIMEOUT_VALUE 10
mbed_official	87:085cde657901	96	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	97	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	98	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	99	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	100	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	106:ced8cbb51063	101	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	102	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	103	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	104	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	105	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	106	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	107	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	108	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	111
mbed_official	87:085cde657901	112	/** @defgroup SPI_Private_Functions
mbed_official	87:085cde657901	113	* @{
mbed_official	87:085cde657901	114	*/
mbed_official	87:085cde657901	115
mbed_official	87:085cde657901	116	/** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	117	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	118	*
mbed_official	87:085cde657901	119	@verbatim
mbed_official	87:085cde657901	120	===============================================================================
mbed_official	87:085cde657901	121	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	122	===============================================================================
mbed_official	87:085cde657901	123	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	87:085cde657901	124	de-initialiaze the SPIx peripheral:
mbed_official	87:085cde657901	125
mbed_official	87:085cde657901	126	(+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official	87:085cde657901	127	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	87:085cde657901	128
mbed_official	87:085cde657901	129	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	87:085cde657901	130	the selected configuration:
mbed_official	87:085cde657901	131	(++) Mode
mbed_official	87:085cde657901	132	(++) Direction
mbed_official	87:085cde657901	133	(++) Data Size
mbed_official	87:085cde657901	134	(++) Clock Polarity and Phase
mbed_official	87:085cde657901	135	(++) NSS Management
mbed_official	87:085cde657901	136	(++) BaudRate Prescaler
mbed_official	87:085cde657901	137	(++) FirstBit
mbed_official	87:085cde657901	138	(++) TIMode
mbed_official	87:085cde657901	139	(++) CRC Calculation
mbed_official	87:085cde657901	140	(++) CRC Polynomial if CRC enabled
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	87:085cde657901	143	of the selected SPIx periperal.
mbed_official	87:085cde657901	144
mbed_official	87:085cde657901	145	@endverbatim
mbed_official	87:085cde657901	146	* @{
mbed_official	87:085cde657901	147	*/
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	/**
mbed_official	87:085cde657901	150	* @brief Initializes the SPI according to the specified parameters
mbed_official	87:085cde657901	151	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	87:085cde657901	152	* @param hspi: SPI handle
mbed_official	87:085cde657901	153	* @retval HAL status
mbed_official	87:085cde657901	154	*/
mbed_official	87:085cde657901	155	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	156	{
mbed_official	87:085cde657901	157	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	158	if(hspi == NULL)
mbed_official	87:085cde657901	159	{
mbed_official	87:085cde657901	160	return HAL_ERROR;
mbed_official	87:085cde657901	161	}
mbed_official	87:085cde657901	162
mbed_official	87:085cde657901	163	/* Check the parameters */
mbed_official	87:085cde657901	164	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	87:085cde657901	165	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	87:085cde657901	166	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	87:085cde657901	167	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	87:085cde657901	168	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	87:085cde657901	169	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	87:085cde657901	170	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	87:085cde657901	171	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	87:085cde657901	172	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	87:085cde657901	173	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	87:085cde657901	174	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	87:085cde657901	175
mbed_official	87:085cde657901	176	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	87:085cde657901	177	{
mbed_official	87:085cde657901	178	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	179	HAL_SPI_MspInit(hspi);
mbed_official	87:085cde657901	180	}
mbed_official	87:085cde657901	181
mbed_official	87:085cde657901	182	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	87:085cde657901	183
mbed_official	87:085cde657901	184	/* Disble the selected SPI peripheral */
mbed_official	87:085cde657901	185	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	186
mbed_official	87:085cde657901	187	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	87:085cde657901	188	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	87:085cde657901	189	Communication speed, First bit and CRC calculation state */
mbed_official	87:085cde657901	190	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	87:085cde657901	191	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	87:085cde657901	192	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	/* Configure : NSS management */
mbed_official	87:085cde657901	195	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
mbed_official	87:085cde657901	196
mbed_official	87:085cde657901	197	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	87:085cde657901	198	/* Configure : CRC Polynomial */
mbed_official	87:085cde657901	199	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	87:085cde657901	200
mbed_official	87:085cde657901	201	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	87:085cde657901	202	hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official	87:085cde657901	203
mbed_official	87:085cde657901	204	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	205	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	206
mbed_official	87:085cde657901	207	return HAL_OK;
mbed_official	87:085cde657901	208	}
mbed_official	87:085cde657901	209
mbed_official	87:085cde657901	210	/**
mbed_official	87:085cde657901	211	* @brief DeInitializes the SPI peripheral
mbed_official	87:085cde657901	212	* @param hspi: SPI handle
mbed_official	87:085cde657901	213	* @retval HAL status
mbed_official	87:085cde657901	214	*/
mbed_official	87:085cde657901	215	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	216	{
mbed_official	87:085cde657901	217	/* Check the SPI handle allocation */
mbed_official	87:085cde657901	218	if(hspi == NULL)
mbed_official	87:085cde657901	219	{
mbed_official	87:085cde657901	220	return HAL_ERROR;
mbed_official	87:085cde657901	221	}
mbed_official	87:085cde657901	222
mbed_official	87:085cde657901	223	/* Disable the SPI Peripheral Clock */
mbed_official	87:085cde657901	224	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	225
mbed_official	87:085cde657901	226	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	227	HAL_SPI_MspDeInit(hspi);
mbed_official	87:085cde657901	228
mbed_official	87:085cde657901	229	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	230	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	87:085cde657901	231
mbed_official	106:ced8cbb51063	232	/* Release Lock */
mbed_official	106:ced8cbb51063	233	__HAL_UNLOCK(hspi);
mbed_official	106:ced8cbb51063	234
mbed_official	87:085cde657901	235	return HAL_OK;
mbed_official	87:085cde657901	236	}
mbed_official	87:085cde657901	237
mbed_official	87:085cde657901	238	/**
mbed_official	87:085cde657901	239	* @brief SPI MSP Init
mbed_official	87:085cde657901	240	* @param hspi: SPI handle
mbed_official	87:085cde657901	241	* @retval None
mbed_official	87:085cde657901	242	*/
mbed_official	87:085cde657901	243	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	244	{
mbed_official	87:085cde657901	245	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	246	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	87:085cde657901	247	*/
mbed_official	87:085cde657901	248	}
mbed_official	87:085cde657901	249
mbed_official	87:085cde657901	250	/**
mbed_official	87:085cde657901	251	* @brief SPI MSP DeInit
mbed_official	87:085cde657901	252	* @param hspi: SPI handle
mbed_official	87:085cde657901	253	* @retval None
mbed_official	87:085cde657901	254	*/
mbed_official	87:085cde657901	255	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	256	{
mbed_official	87:085cde657901	257	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	258	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	87:085cde657901	259	*/
mbed_official	87:085cde657901	260	}
mbed_official	87:085cde657901	261
mbed_official	87:085cde657901	262	/**
mbed_official	87:085cde657901	263	* @}
mbed_official	87:085cde657901	264	*/
mbed_official	87:085cde657901	265
mbed_official	87:085cde657901	266	/** @defgroup SPI_Group2 IO operation functions
mbed_official	87:085cde657901	267	* @brief Data transfers functions
mbed_official	87:085cde657901	268	*
mbed_official	87:085cde657901	269	@verbatim
mbed_official	87:085cde657901	270	==============================================================================
mbed_official	87:085cde657901	271	##### IO operation functions #####
mbed_official	87:085cde657901	272	===============================================================================
mbed_official	87:085cde657901	273	This subsection provides a set of functions allowing to manage the SPI
mbed_official	87:085cde657901	274	data transfers.
mbed_official	87:085cde657901	275
mbed_official	87:085cde657901	276	[..] The SPI supports master and slave mode :
mbed_official	87:085cde657901	277
mbed_official	87:085cde657901	278	(#) There are two mode of transfer:
mbed_official	87:085cde657901	279	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	87:085cde657901	280	The HAL status of all data processing is returned by the same function
mbed_official	87:085cde657901	281	after finishing transfer.
mbed_official	87:085cde657901	282	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	87:085cde657901	283	or DMA, These API's return the HAL status.
mbed_official	87:085cde657901	284	The end of the data processing will be indicated through the
mbed_official	87:085cde657901	285	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	87:085cde657901	286	using DMA mode.
mbed_official	87:085cde657901	287	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	87:085cde657901	288	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	87:085cde657901	289	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	87:085cde657901	290
mbed_official	87:085cde657901	291	(#) Blocking mode API's are :
mbed_official	87:085cde657901	292	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	293	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	294	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	87:085cde657901	295
mbed_official	87:085cde657901	296	(#) Non-Blocking mode API's with Interrupt are :
mbed_official	87:085cde657901	297	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	298	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	299	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	87:085cde657901	300	(++) HAL_SPI_IRQHandler()
mbed_official	87:085cde657901	301
mbed_official	87:085cde657901	302	(#) No-Blocking mode functions with DMA are :
mbed_official	87:085cde657901	303	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	304	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	305	(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	87:085cde657901	306
mbed_official	87:085cde657901	307	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official	87:085cde657901	308	(++) HAL_SPI_TxCpltCallback()
mbed_official	87:085cde657901	309	(++) HAL_SPI_RxCpltCallback()
mbed_official	87:085cde657901	310	(++) HAL_SPI_ErrorCallback()
mbed_official	87:085cde657901	311	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	87:085cde657901	312
mbed_official	87:085cde657901	313	@endverbatim
mbed_official	87:085cde657901	314	* @{
mbed_official	87:085cde657901	315	*/
mbed_official	87:085cde657901	316
mbed_official	87:085cde657901	317	/**
mbed_official	87:085cde657901	318	* @brief Transmit an amount of data in blocking mode
mbed_official	87:085cde657901	319	* @param hspi: SPI handle
mbed_official	87:085cde657901	320	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	321	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	322	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	323	* @retval HAL status
mbed_official	87:085cde657901	324	*/
mbed_official	87:085cde657901	325	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	326	{
mbed_official	87:085cde657901	327
mbed_official	87:085cde657901	328	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	329	{
mbed_official	87:085cde657901	330	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	331	{
mbed_official	87:085cde657901	332	return HAL_ERROR;
mbed_official	87:085cde657901	333	}
mbed_official	87:085cde657901	334
mbed_official	87:085cde657901	335	/* Check the parameters */
mbed_official	87:085cde657901	336	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	337
mbed_official	87:085cde657901	338	/* Process Locked */
mbed_official	87:085cde657901	339	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	340
mbed_official	87:085cde657901	341	/* Configure communication */
mbed_official	87:085cde657901	342	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	343	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	344
mbed_official	87:085cde657901	345	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	346	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	347	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	348
mbed_official	87:085cde657901	349	/Init field not used in handle to zero /
mbed_official	87:085cde657901	350	hspi->TxISR = 0;
mbed_official	87:085cde657901	351	hspi->RxISR = 0;
mbed_official	87:085cde657901	352	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	353	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	354
mbed_official	87:085cde657901	355	/* Reset CRC Calculation */
mbed_official	87:085cde657901	356	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	357	{
mbed_official	87:085cde657901	358	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	359	}
mbed_official	87:085cde657901	360
mbed_official	87:085cde657901	361	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	362	{
mbed_official	87:085cde657901	363	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	364	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	365	}
mbed_official	87:085cde657901	366
mbed_official	87:085cde657901	367	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	368	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	369	{
mbed_official	87:085cde657901	370	/* Enable SPI peripheral */
mbed_official	87:085cde657901	371	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	372	}
mbed_official	87:085cde657901	373
mbed_official	87:085cde657901	374	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	375	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	376	{
mbed_official	87:085cde657901	377
mbed_official	87:085cde657901	378	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	379	hspi->TxXferCount--;
mbed_official	87:085cde657901	380
mbed_official	87:085cde657901	381	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	382	{
mbed_official	87:085cde657901	383	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	384	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	385	{
mbed_official	87:085cde657901	386	return HAL_TIMEOUT;
mbed_official	87:085cde657901	387	}
mbed_official	87:085cde657901	388	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	389	hspi->TxXferCount--;
mbed_official	87:085cde657901	390	}
mbed_official	87:085cde657901	391	/* Enable CRC Transmission */
mbed_official	87:085cde657901	392	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	393	{
mbed_official	87:085cde657901	394	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	395	}
mbed_official	87:085cde657901	396	}
mbed_official	87:085cde657901	397	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	398	else
mbed_official	87:085cde657901	399	{
mbed_official	87:085cde657901	400	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	401	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	402	hspi->TxXferCount--;
mbed_official	87:085cde657901	403
mbed_official	87:085cde657901	404	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	405	{
mbed_official	87:085cde657901	406	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	407	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	408	{
mbed_official	87:085cde657901	409	return HAL_TIMEOUT;
mbed_official	87:085cde657901	410	}
mbed_official	87:085cde657901	411	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	412	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	413	hspi->TxXferCount--;
mbed_official	87:085cde657901	414	}
mbed_official	87:085cde657901	415	/* Enable CRC Transmission */
mbed_official	87:085cde657901	416	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	417	{
mbed_official	87:085cde657901	418	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	419	}
mbed_official	87:085cde657901	420	}
mbed_official	87:085cde657901	421
mbed_official	87:085cde657901	422	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	423	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	424	{
mbed_official	87:085cde657901	425	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	426	return HAL_TIMEOUT;
mbed_official	87:085cde657901	427	}
mbed_official	87:085cde657901	428
mbed_official	87:085cde657901	429	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	430	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	431	{
mbed_official	87:085cde657901	432	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	433	return HAL_TIMEOUT;
mbed_official	87:085cde657901	434	}
mbed_official	87:085cde657901	435
mbed_official	87:085cde657901	436	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	437	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	438	{
mbed_official	87:085cde657901	439	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	440	}
mbed_official	87:085cde657901	441
mbed_official	87:085cde657901	442	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	443
mbed_official	87:085cde657901	444	/* Process Unlocked */
mbed_official	87:085cde657901	445	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	446
mbed_official	87:085cde657901	447	return HAL_OK;
mbed_official	87:085cde657901	448	}
mbed_official	87:085cde657901	449	else
mbed_official	87:085cde657901	450	{
mbed_official	87:085cde657901	451	return HAL_BUSY;
mbed_official	87:085cde657901	452	}
mbed_official	87:085cde657901	453	}
mbed_official	87:085cde657901	454
mbed_official	87:085cde657901	455	/**
mbed_official	87:085cde657901	456	* @brief Receive an amount of data in blocking mode
mbed_official	87:085cde657901	457	* @param hspi: SPI handle
mbed_official	87:085cde657901	458	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	459	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	460	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	461	* @retval HAL status
mbed_official	87:085cde657901	462	*/
mbed_official	87:085cde657901	463	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	464	{
mbed_official	87:085cde657901	465	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	466	uint32_t tmp = 0;
mbed_official	87:085cde657901	467
mbed_official	87:085cde657901	468	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	469	{
mbed_official	87:085cde657901	470	if((pData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	471	{
mbed_official	87:085cde657901	472	return HAL_ERROR;
mbed_official	87:085cde657901	473	}
mbed_official	87:085cde657901	474
mbed_official	87:085cde657901	475	/* Process Locked */
mbed_official	87:085cde657901	476	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	477
mbed_official	87:085cde657901	478	/* Configure communication */
mbed_official	87:085cde657901	479	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	480	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	481
mbed_official	87:085cde657901	482	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	483	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	484	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	485
mbed_official	87:085cde657901	486	/Init field not used in handle to zero /
mbed_official	87:085cde657901	487	hspi->RxISR = 0;
mbed_official	87:085cde657901	488	hspi->TxISR = 0;
mbed_official	87:085cde657901	489	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	490	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	491
mbed_official	87:085cde657901	492	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	493	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	494	{
mbed_official	87:085cde657901	495	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	496	}
mbed_official	87:085cde657901	497
mbed_official	87:085cde657901	498	/* Reset CRC Calculation */
mbed_official	87:085cde657901	499	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	500	{
mbed_official	87:085cde657901	501	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	502	}
mbed_official	87:085cde657901	503
mbed_official	87:085cde657901	504	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	87:085cde657901	505	{
mbed_official	87:085cde657901	506	/* Process Unlocked */
mbed_official	87:085cde657901	507	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	508
mbed_official	87:085cde657901	509	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	510	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	87:085cde657901	511	}
mbed_official	87:085cde657901	512
mbed_official	87:085cde657901	513	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	514	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	515	{
mbed_official	87:085cde657901	516	/* Enable SPI peripheral */
mbed_official	87:085cde657901	517	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	518	}
mbed_official	87:085cde657901	519
mbed_official	87:085cde657901	520	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	521	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	522	{
mbed_official	87:085cde657901	523	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	524	{
mbed_official	87:085cde657901	525	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	526	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	527	{
mbed_official	87:085cde657901	528	return HAL_TIMEOUT;
mbed_official	87:085cde657901	529	}
mbed_official	87:085cde657901	530
mbed_official	87:085cde657901	531	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	532	hspi->RxXferCount--;
mbed_official	87:085cde657901	533	}
mbed_official	87:085cde657901	534	/* Enable CRC Transmission */
mbed_official	87:085cde657901	535	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	536	{
mbed_official	87:085cde657901	537	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	538	}
mbed_official	87:085cde657901	539	}
mbed_official	87:085cde657901	540	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	541	else
mbed_official	87:085cde657901	542	{
mbed_official	87:085cde657901	543	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	544	{
mbed_official	87:085cde657901	545	/* Wait until RXNE flag is set to read data */
mbed_official	87:085cde657901	546	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	547	{
mbed_official	87:085cde657901	548	return HAL_TIMEOUT;
mbed_official	87:085cde657901	549	}
mbed_official	87:085cde657901	550
mbed_official	87:085cde657901	551	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	552	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	553	hspi->RxXferCount--;
mbed_official	87:085cde657901	554	}
mbed_official	87:085cde657901	555	/* Enable CRC Transmission */
mbed_official	87:085cde657901	556	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	557	{
mbed_official	87:085cde657901	558	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	559	}
mbed_official	87:085cde657901	560	}
mbed_official	87:085cde657901	561
mbed_official	87:085cde657901	562	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	563	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	564	{
mbed_official	87:085cde657901	565	return HAL_TIMEOUT;
mbed_official	87:085cde657901	566	}
mbed_official	87:085cde657901	567
mbed_official	87:085cde657901	568	/* Receive last data in 8 Bit mode */
mbed_official	87:085cde657901	569	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	570	{
mbed_official	87:085cde657901	571	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	572	}
mbed_official	87:085cde657901	573	/* Receive last data in 16 Bit mode */
mbed_official	87:085cde657901	574	else
mbed_official	87:085cde657901	575	{
mbed_official	87:085cde657901	576	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	577	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	578	}
mbed_official	87:085cde657901	579	hspi->RxXferCount--;
mbed_official	87:085cde657901	580
mbed_official	87:085cde657901	581	/* Wait until RXNE flag is set: CRC Received */
mbed_official	87:085cde657901	582	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	583	{
mbed_official	87:085cde657901	584	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	585	{
mbed_official	87:085cde657901	586	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	587	return HAL_TIMEOUT;
mbed_official	87:085cde657901	588	}
mbed_official	87:085cde657901	589
mbed_official	87:085cde657901	590	/* Read CRC to Flush RXNE flag */
mbed_official	87:085cde657901	591	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	592	}
mbed_official	87:085cde657901	593
mbed_official	87:085cde657901	594	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	595	{
mbed_official	87:085cde657901	596	/* Disable SPI peripheral */
mbed_official	87:085cde657901	597	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	598	}
mbed_official	87:085cde657901	599
mbed_official	87:085cde657901	600	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	601
mbed_official	87:085cde657901	602	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	603	/* Check if CRC error occurred */
mbed_official	87:085cde657901	604	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	605	{
mbed_official	87:085cde657901	606	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	607
mbed_official	87:085cde657901	608	/* Reset CRC Calculation */
mbed_official	87:085cde657901	609	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	610
mbed_official	87:085cde657901	611	/* Process Unlocked */
mbed_official	87:085cde657901	612	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	613
mbed_official	87:085cde657901	614	return HAL_ERROR;
mbed_official	87:085cde657901	615	}
mbed_official	87:085cde657901	616
mbed_official	87:085cde657901	617	/* Process Unlocked */
mbed_official	87:085cde657901	618	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	619
mbed_official	87:085cde657901	620	return HAL_OK;
mbed_official	87:085cde657901	621	}
mbed_official	87:085cde657901	622	else
mbed_official	87:085cde657901	623	{
mbed_official	87:085cde657901	624	return HAL_BUSY;
mbed_official	87:085cde657901	625	}
mbed_official	87:085cde657901	626	}
mbed_official	87:085cde657901	627
mbed_official	87:085cde657901	628	/**
mbed_official	87:085cde657901	629	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	87:085cde657901	630	* @param hspi: SPI handle
mbed_official	87:085cde657901	631	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	632	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	633	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	634	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	635	* @retval HAL status
mbed_official	87:085cde657901	636	*/
mbed_official	87:085cde657901	637	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	638	{
mbed_official	87:085cde657901	639	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	640	uint32_t tmp = 0;
mbed_official	87:085cde657901	641
mbed_official	87:085cde657901	642	tmp = hspi->State;
mbed_official	87:085cde657901	643	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	644	{
mbed_official	87:085cde657901	645	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	646	{
mbed_official	87:085cde657901	647	return HAL_ERROR;
mbed_official	87:085cde657901	648	}
mbed_official	87:085cde657901	649
mbed_official	87:085cde657901	650	/* Check the parameters */
mbed_official	87:085cde657901	651	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	652
mbed_official	87:085cde657901	653	/* Process Locked */
mbed_official	87:085cde657901	654	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	655
mbed_official	87:085cde657901	656	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	657	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	658	{
mbed_official	106:ced8cbb51063	659	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	660	}
mbed_official	87:085cde657901	661
mbed_official	87:085cde657901	662	/* Configure communication */
mbed_official	87:085cde657901	663	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	664
mbed_official	87:085cde657901	665	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	666	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	667	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	668
mbed_official	87:085cde657901	669	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	670	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	671	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	672
mbed_official	87:085cde657901	673	/Init field not used in handle to zero /
mbed_official	87:085cde657901	674	hspi->RxISR = 0;
mbed_official	87:085cde657901	675	hspi->TxISR = 0;
mbed_official	87:085cde657901	676
mbed_official	87:085cde657901	677	/* Reset CRC Calculation */
mbed_official	87:085cde657901	678	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	679	{
mbed_official	87:085cde657901	680	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	681	}
mbed_official	87:085cde657901	682
mbed_official	87:085cde657901	683	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	684	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	685	{
mbed_official	87:085cde657901	686	/* Enable SPI peripheral */
mbed_official	87:085cde657901	687	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	688	}
mbed_official	87:085cde657901	689
mbed_official	87:085cde657901	690	/* Transmit and Receive data in 16 Bit mode */
mbed_official	87:085cde657901	691	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	87:085cde657901	692	{
mbed_official	87:085cde657901	693	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	694	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	695	hspi->TxXferCount--;
mbed_official	87:085cde657901	696
mbed_official	87:085cde657901	697	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	698	{
mbed_official	87:085cde657901	699	/* Enable CRC Transmission */
mbed_official	87:085cde657901	700	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	701	{
mbed_official	87:085cde657901	702	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	703	}
mbed_official	87:085cde657901	704
mbed_official	87:085cde657901	705	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	706	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	707	{
mbed_official	87:085cde657901	708	return HAL_TIMEOUT;
mbed_official	87:085cde657901	709	}
mbed_official	87:085cde657901	710
mbed_official	87:085cde657901	711	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	712	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	713	hspi->RxXferCount--;
mbed_official	87:085cde657901	714	}
mbed_official	87:085cde657901	715	else
mbed_official	87:085cde657901	716	{
mbed_official	87:085cde657901	717	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	718	{
mbed_official	87:085cde657901	719	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	720	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	721	{
mbed_official	87:085cde657901	722	return HAL_TIMEOUT;
mbed_official	87:085cde657901	723	}
mbed_official	87:085cde657901	724
mbed_official	87:085cde657901	725	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	726	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	727	hspi->TxXferCount--;
mbed_official	87:085cde657901	728
mbed_official	87:085cde657901	729	/* Enable CRC Transmission */
mbed_official	87:085cde657901	730	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	731	{
mbed_official	87:085cde657901	732	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	733	}
mbed_official	87:085cde657901	734
mbed_official	87:085cde657901	735	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	736	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	737	{
mbed_official	87:085cde657901	738	return HAL_TIMEOUT;
mbed_official	87:085cde657901	739	}
mbed_official	87:085cde657901	740
mbed_official	87:085cde657901	741	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	742	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	743	hspi->RxXferCount--;
mbed_official	87:085cde657901	744	}
mbed_official	87:085cde657901	745
mbed_official	87:085cde657901	746	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	747	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	748	{
mbed_official	87:085cde657901	749	return HAL_TIMEOUT;
mbed_official	87:085cde657901	750	}
mbed_official	87:085cde657901	751
mbed_official	87:085cde657901	752	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	753	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	754	hspi->RxXferCount--;
mbed_official	87:085cde657901	755	}
mbed_official	87:085cde657901	756	}
mbed_official	87:085cde657901	757	/* Transmit and Receive data in 8 Bit mode */
mbed_official	87:085cde657901	758	else
mbed_official	87:085cde657901	759	{
mbed_official	87:085cde657901	760
mbed_official	87:085cde657901	761	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	762	hspi->TxXferCount--;
mbed_official	87:085cde657901	763
mbed_official	87:085cde657901	764	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	765	{
mbed_official	87:085cde657901	766	/* Enable CRC Transmission */
mbed_official	87:085cde657901	767	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	768	{
mbed_official	87:085cde657901	769	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	770	}
mbed_official	87:085cde657901	771
mbed_official	87:085cde657901	772	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	773	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	774	{
mbed_official	87:085cde657901	775	return HAL_TIMEOUT;
mbed_official	87:085cde657901	776	}
mbed_official	87:085cde657901	777
mbed_official	87:085cde657901	778	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	779	hspi->RxXferCount--;
mbed_official	87:085cde657901	780	}
mbed_official	87:085cde657901	781	else
mbed_official	87:085cde657901	782	{
mbed_official	87:085cde657901	783	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	784	{
mbed_official	87:085cde657901	785	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	786	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	787	{
mbed_official	87:085cde657901	788	return HAL_TIMEOUT;
mbed_official	87:085cde657901	789	}
mbed_official	87:085cde657901	790
mbed_official	87:085cde657901	791	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	792	hspi->TxXferCount--;
mbed_official	87:085cde657901	793
mbed_official	87:085cde657901	794	/* Enable CRC Transmission */
mbed_official	87:085cde657901	795	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	796	{
mbed_official	87:085cde657901	797	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	798	}
mbed_official	87:085cde657901	799
mbed_official	87:085cde657901	800	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	801	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	802	{
mbed_official	87:085cde657901	803	return HAL_TIMEOUT;
mbed_official	87:085cde657901	804	}
mbed_official	87:085cde657901	805
mbed_official	87:085cde657901	806	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	807	hspi->RxXferCount--;
mbed_official	87:085cde657901	808	}
mbed_official	87:085cde657901	809
mbed_official	87:085cde657901	810	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	811	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	812	{
mbed_official	87:085cde657901	813	return HAL_TIMEOUT;
mbed_official	87:085cde657901	814	}
mbed_official	87:085cde657901	815
mbed_official	87:085cde657901	816	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	817	hspi->RxXferCount--;
mbed_official	87:085cde657901	818	}
mbed_official	87:085cde657901	819	}
mbed_official	87:085cde657901	820
mbed_official	87:085cde657901	821	/* Read CRC from DR to close CRC calculation process */
mbed_official	87:085cde657901	822	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	823	{
mbed_official	87:085cde657901	824	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	825	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	826	{
mbed_official	87:085cde657901	827	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	828	return HAL_TIMEOUT;
mbed_official	87:085cde657901	829	}
mbed_official	87:085cde657901	830	/* Read CRC */
mbed_official	87:085cde657901	831	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	832	}
mbed_official	87:085cde657901	833
mbed_official	87:085cde657901	834	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	835	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	836	{
mbed_official	87:085cde657901	837	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	838	return HAL_TIMEOUT;
mbed_official	87:085cde657901	839	}
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	842
mbed_official	87:085cde657901	843	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	844	/* Check if CRC error occurred */
mbed_official	87:085cde657901	845	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	846	{
mbed_official	87:085cde657901	847	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	848
mbed_official	87:085cde657901	849	/* Reset CRC Calculation */
mbed_official	87:085cde657901	850	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	851	{
mbed_official	87:085cde657901	852	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	853	}
mbed_official	87:085cde657901	854
mbed_official	87:085cde657901	855	/* Process Unlocked */
mbed_official	87:085cde657901	856	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	857
mbed_official	87:085cde657901	858	return HAL_ERROR;
mbed_official	87:085cde657901	859	}
mbed_official	87:085cde657901	860
mbed_official	87:085cde657901	861	/* Process Unlocked */
mbed_official	87:085cde657901	862	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	863
mbed_official	87:085cde657901	864	return HAL_OK;
mbed_official	87:085cde657901	865	}
mbed_official	87:085cde657901	866	else
mbed_official	87:085cde657901	867	{
mbed_official	87:085cde657901	868	return HAL_BUSY;
mbed_official	87:085cde657901	869	}
mbed_official	87:085cde657901	870	}
mbed_official	87:085cde657901	871
mbed_official	87:085cde657901	872	/**
mbed_official	87:085cde657901	873	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	874	* @param hspi: SPI handle
mbed_official	87:085cde657901	875	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	876	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	877	* @retval HAL status
mbed_official	87:085cde657901	878	*/
mbed_official	87:085cde657901	879	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	880	{
mbed_official	87:085cde657901	881	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	882	{
mbed_official	87:085cde657901	883	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	884	{
mbed_official	87:085cde657901	885	return HAL_ERROR;
mbed_official	87:085cde657901	886	}
mbed_official	87:085cde657901	887
mbed_official	87:085cde657901	888	/* Check the parameters */
mbed_official	87:085cde657901	889	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	890
mbed_official	87:085cde657901	891	/* Process Locked */
mbed_official	87:085cde657901	892	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	893
mbed_official	87:085cde657901	894	/* Configure communication */
mbed_official	87:085cde657901	895	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	896	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	897
mbed_official	87:085cde657901	898	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	899	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	900	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	901	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	902
mbed_official	87:085cde657901	903	/Init field not used in handle to zero /
mbed_official	87:085cde657901	904	hspi->RxISR = 0;
mbed_official	87:085cde657901	905	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	906	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	907
mbed_official	87:085cde657901	908	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	909	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	910	{
mbed_official	87:085cde657901	911	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	912	}
mbed_official	87:085cde657901	913
mbed_official	87:085cde657901	914	/* Reset CRC Calculation */
mbed_official	87:085cde657901	915	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	916	{
mbed_official	87:085cde657901	917	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	918	}
mbed_official	87:085cde657901	919
mbed_official	87:085cde657901	920	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	921	{
mbed_official	87:085cde657901	922	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	87:085cde657901	923	}else
mbed_official	87:085cde657901	924	{
mbed_official	87:085cde657901	925	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	926	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	87:085cde657901	927	}
mbed_official	87:085cde657901	928	/* Process Unlocked */
mbed_official	87:085cde657901	929	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	930
mbed_official	87:085cde657901	931	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	932	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	933	{
mbed_official	87:085cde657901	934	/* Enable SPI peripheral */
mbed_official	87:085cde657901	935	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	936	}
mbed_official	87:085cde657901	937
mbed_official	87:085cde657901	938	return HAL_OK;
mbed_official	87:085cde657901	939	}
mbed_official	87:085cde657901	940	else
mbed_official	87:085cde657901	941	{
mbed_official	87:085cde657901	942	return HAL_BUSY;
mbed_official	87:085cde657901	943	}
mbed_official	87:085cde657901	944	}
mbed_official	87:085cde657901	945
mbed_official	87:085cde657901	946	/**
mbed_official	87:085cde657901	947	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	948	* @param hspi: SPI handle
mbed_official	87:085cde657901	949	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	950	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	951	* @retval HAL status
mbed_official	87:085cde657901	952	*/
mbed_official	87:085cde657901	953	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	954	{
mbed_official	87:085cde657901	955	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	956	{
mbed_official	87:085cde657901	957	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	958	{
mbed_official	87:085cde657901	959	return HAL_ERROR;
mbed_official	87:085cde657901	960	}
mbed_official	87:085cde657901	961
mbed_official	87:085cde657901	962	/* Process Locked */
mbed_official	87:085cde657901	963	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	964
mbed_official	87:085cde657901	965	/* Configure communication */
mbed_official	87:085cde657901	966	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	967	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	968
mbed_official	87:085cde657901	969	hspi->RxISR = &SPI_RxISR;
mbed_official	87:085cde657901	970	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	971	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	972	hspi->RxXferCount = Size ;
mbed_official	87:085cde657901	973
mbed_official	87:085cde657901	974	/Init field not used in handle to zero /
mbed_official	87:085cde657901	975	hspi->TxISR = 0;
mbed_official	87:085cde657901	976	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	977	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	978
mbed_official	87:085cde657901	979	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	980	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	981	{
mbed_official	87:085cde657901	982	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	983	}
mbed_official	87:085cde657901	984	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	985	{
mbed_official	87:085cde657901	986	/* Process Unlocked */
mbed_official	87:085cde657901	987	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	988
mbed_official	87:085cde657901	989	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	990	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	87:085cde657901	991	}
mbed_official	87:085cde657901	992
mbed_official	87:085cde657901	993	/* Reset CRC Calculation */
mbed_official	87:085cde657901	994	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	995	{
mbed_official	87:085cde657901	996	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	997	}
mbed_official	87:085cde657901	998
mbed_official	87:085cde657901	999	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	1000	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1001
mbed_official	87:085cde657901	1002	/* Process Unlocked */
mbed_official	87:085cde657901	1003	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1004
mbed_official	87:085cde657901	1005	/* Note : The SPI must be enabled after unlocking current process
mbed_official	87:085cde657901	1006	to avoid the risk of SPI interrupt handle execution before current
mbed_official	87:085cde657901	1007	process unlock */
mbed_official	87:085cde657901	1008
mbed_official	87:085cde657901	1009	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1010	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1011	{
mbed_official	87:085cde657901	1012	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1013	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1014	}
mbed_official	87:085cde657901	1015
mbed_official	87:085cde657901	1016	return HAL_OK;
mbed_official	87:085cde657901	1017	}
mbed_official	87:085cde657901	1018	else
mbed_official	87:085cde657901	1019	{
mbed_official	87:085cde657901	1020	return HAL_BUSY;
mbed_official	87:085cde657901	1021	}
mbed_official	87:085cde657901	1022	}
mbed_official	87:085cde657901	1023
mbed_official	87:085cde657901	1024	/**
mbed_official	87:085cde657901	1025	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	87:085cde657901	1026	* @param hspi: SPI handle
mbed_official	87:085cde657901	1027	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1028	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	1029	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1030	* @retval HAL status
mbed_official	87:085cde657901	1031	*/
mbed_official	87:085cde657901	1032	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1033	{
mbed_official	87:085cde657901	1034	uint32_t tmp = 0;
mbed_official	87:085cde657901	1035
mbed_official	87:085cde657901	1036	tmp = hspi->State;
mbed_official	87:085cde657901	1037	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1038	{
mbed_official	87:085cde657901	1039	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1040	{
mbed_official	87:085cde657901	1041	return HAL_ERROR;
mbed_official	87:085cde657901	1042	}
mbed_official	87:085cde657901	1043
mbed_official	87:085cde657901	1044	/* Check the parameters */
mbed_official	87:085cde657901	1045	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1046
mbed_official	87:085cde657901	1047	/* Process locked */
mbed_official	87:085cde657901	1048	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1049
mbed_official	87:085cde657901	1050	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1051	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1052	{
mbed_official	106:ced8cbb51063	1053	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1054	}
mbed_official	87:085cde657901	1055
mbed_official	87:085cde657901	1056	/* Configure communication */
mbed_official	87:085cde657901	1057	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1058
mbed_official	87:085cde657901	1059	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	1060	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	1061	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1062	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1063
mbed_official	87:085cde657901	1064	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	87:085cde657901	1065	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	1066	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1067	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1068
mbed_official	87:085cde657901	1069	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1070	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1071	{
mbed_official	87:085cde657901	1072	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1073	}
mbed_official	87:085cde657901	1074
mbed_official	87:085cde657901	1075	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	87:085cde657901	1076	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1077
mbed_official	87:085cde657901	1078	/* Process Unlocked */
mbed_official	87:085cde657901	1079	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1080
mbed_official	87:085cde657901	1081	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1082	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1083	{
mbed_official	87:085cde657901	1084	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1085	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1086	}
mbed_official	87:085cde657901	1087
mbed_official	87:085cde657901	1088	return HAL_OK;
mbed_official	87:085cde657901	1089	}
mbed_official	87:085cde657901	1090	else
mbed_official	87:085cde657901	1091	{
mbed_official	87:085cde657901	1092	return HAL_BUSY;
mbed_official	87:085cde657901	1093	}
mbed_official	87:085cde657901	1094	}
mbed_official	87:085cde657901	1095
mbed_official	87:085cde657901	1096	/**
mbed_official	87:085cde657901	1097	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1098	* @param hspi: SPI handle
mbed_official	87:085cde657901	1099	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1100	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1101	* @retval HAL status
mbed_official	87:085cde657901	1102	*/
mbed_official	87:085cde657901	1103	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1104	{
mbed_official	87:085cde657901	1105	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1106	{
mbed_official	87:085cde657901	1107	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1108	{
mbed_official	87:085cde657901	1109	return HAL_ERROR;
mbed_official	87:085cde657901	1110	}
mbed_official	87:085cde657901	1111
mbed_official	87:085cde657901	1112	/* Check the parameters */
mbed_official	87:085cde657901	1113	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	1114
mbed_official	87:085cde657901	1115	/* Process Locked */
mbed_official	87:085cde657901	1116	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1117
mbed_official	87:085cde657901	1118	/* Configure communication */
mbed_official	87:085cde657901	1119	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	1120	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1121
mbed_official	87:085cde657901	1122	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	1123	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1124	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1125
mbed_official	87:085cde657901	1126	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1127	hspi->TxISR = 0;
mbed_official	87:085cde657901	1128	hspi->RxISR = 0;
mbed_official	87:085cde657901	1129	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	1130	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1131
mbed_official	87:085cde657901	1132	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1133	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1134	{
mbed_official	87:085cde657901	1135	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	1136	}
mbed_official	87:085cde657901	1137
mbed_official	87:085cde657901	1138	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1139	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1140	{
mbed_official	87:085cde657901	1141	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1142	}
mbed_official	87:085cde657901	1143
mbed_official	87:085cde657901	1144	/* Set the SPI TxDMA transfer complete callback */
mbed_official	87:085cde657901	1145	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	87:085cde657901	1146
mbed_official	87:085cde657901	1147	/* Set the DMA error callback */
mbed_official	87:085cde657901	1148	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1149
mbed_official	87:085cde657901	1150	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1151	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1152
mbed_official	87:085cde657901	1153	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1154	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1155
mbed_official	87:085cde657901	1156	/* Process Unlocked */
mbed_official	87:085cde657901	1157	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1158
mbed_official	87:085cde657901	1159	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1160	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1161	{
mbed_official	87:085cde657901	1162	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1163	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1164	}
mbed_official	87:085cde657901	1165
mbed_official	87:085cde657901	1166	return HAL_OK;
mbed_official	87:085cde657901	1167	}
mbed_official	87:085cde657901	1168	else
mbed_official	87:085cde657901	1169	{
mbed_official	87:085cde657901	1170	return HAL_BUSY;
mbed_official	87:085cde657901	1171	}
mbed_official	87:085cde657901	1172	}
mbed_official	87:085cde657901	1173
mbed_official	87:085cde657901	1174	/**
mbed_official	87:085cde657901	1175	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1176	* @param hspi: SPI handle
mbed_official	87:085cde657901	1177	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1178	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	87:085cde657901	1179	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1180	* @retval HAL status
mbed_official	87:085cde657901	1181	*/
mbed_official	87:085cde657901	1182	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1183	{
mbed_official	87:085cde657901	1184	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1185	{
mbed_official	87:085cde657901	1186	if((pData == NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1187	{
mbed_official	87:085cde657901	1188	return HAL_ERROR;
mbed_official	87:085cde657901	1189	}
mbed_official	87:085cde657901	1190
mbed_official	87:085cde657901	1191	/* Process Locked */
mbed_official	87:085cde657901	1192	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1193
mbed_official	87:085cde657901	1194	/* Configure communication */
mbed_official	87:085cde657901	1195	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	1196	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1197
mbed_official	87:085cde657901	1198	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	1199	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1200	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1201
mbed_official	87:085cde657901	1202	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1203	hspi->RxISR = 0;
mbed_official	87:085cde657901	1204	hspi->TxISR = 0;
mbed_official	87:085cde657901	1205	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	1206	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1207
mbed_official	87:085cde657901	1208	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1209	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1210	{
mbed_official	87:085cde657901	1211	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	1212	}
mbed_official	87:085cde657901	1213	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	1214	{
mbed_official	87:085cde657901	1215	/* Process Unlocked */
mbed_official	87:085cde657901	1216	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1217
mbed_official	87:085cde657901	1218	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	1219	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1220	}
mbed_official	87:085cde657901	1221
mbed_official	87:085cde657901	1222	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1223	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1224	{
mbed_official	87:085cde657901	1225	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1226	}
mbed_official	87:085cde657901	1227
mbed_official	87:085cde657901	1228	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	87:085cde657901	1229	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	/* Set the DMA error callback */
mbed_official	87:085cde657901	1232	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1233
mbed_official	87:085cde657901	1234	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1235	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1236
mbed_official	87:085cde657901	1237	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1238	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1239
mbed_official	87:085cde657901	1240	/* Process Unlocked */
mbed_official	87:085cde657901	1241	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1242
mbed_official	87:085cde657901	1243	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1244	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1245	{
mbed_official	87:085cde657901	1246	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1247	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1248	}
mbed_official	87:085cde657901	1249
mbed_official	87:085cde657901	1250	return HAL_OK;
mbed_official	87:085cde657901	1251	}
mbed_official	87:085cde657901	1252	else
mbed_official	87:085cde657901	1253	{
mbed_official	87:085cde657901	1254	return HAL_BUSY;
mbed_official	87:085cde657901	1255	}
mbed_official	87:085cde657901	1256	}
mbed_official	87:085cde657901	1257
mbed_official	87:085cde657901	1258	/**
mbed_official	87:085cde657901	1259	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	87:085cde657901	1260	* @param hspi: SPI handle
mbed_official	87:085cde657901	1261	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1262	* @param pRxData: pointer to reception data buffer
mbed_official	87:085cde657901	1263	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	87:085cde657901	1264	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1265	* @retval HAL status
mbed_official	87:085cde657901	1266	*/
mbed_official	87:085cde657901	1267	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1268	{
mbed_official	87:085cde657901	1269	uint32_t tmpstate = 0;
mbed_official	87:085cde657901	1270	tmpstate = hspi->State;
mbed_official	87:085cde657901	1271	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	1272	{
mbed_official	87:085cde657901	1273	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1274	{
mbed_official	87:085cde657901	1275	return HAL_ERROR;
mbed_official	87:085cde657901	1276	}
mbed_official	87:085cde657901	1277
mbed_official	87:085cde657901	1278	/* Check the parameters */
mbed_official	87:085cde657901	1279	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1280
mbed_official	87:085cde657901	1281	/* Process locked */
mbed_official	87:085cde657901	1282	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1283
mbed_official	87:085cde657901	1284	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	1285	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1286	{
mbed_official	106:ced8cbb51063	1287	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1288	}
mbed_official	87:085cde657901	1289
mbed_official	87:085cde657901	1290	/* Configure communication */
mbed_official	87:085cde657901	1291	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1292
mbed_official	87:085cde657901	1293	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	87:085cde657901	1294	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1295	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1296
mbed_official	87:085cde657901	1297	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	87:085cde657901	1298	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1299	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1300
mbed_official	87:085cde657901	1301	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1302	hspi->RxISR = 0;
mbed_official	87:085cde657901	1303	hspi->TxISR = 0;
mbed_official	87:085cde657901	1304
mbed_official	87:085cde657901	1305	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1306	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1307	{
mbed_official	87:085cde657901	1308	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1309	}
mbed_official	87:085cde657901	1310
mbed_official	106:ced8cbb51063	1311	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	106:ced8cbb51063	1312	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	106:ced8cbb51063	1313	{
mbed_official	106:ced8cbb51063	1314	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	106:ced8cbb51063	1315	}
mbed_official	106:ced8cbb51063	1316	else
mbed_official	106:ced8cbb51063	1317	{
mbed_official	106:ced8cbb51063	1318	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	106:ced8cbb51063	1319	}
mbed_official	87:085cde657901	1320
mbed_official	87:085cde657901	1321	/* Set the DMA error callback */
mbed_official	87:085cde657901	1322	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1323
mbed_official	87:085cde657901	1324	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1325	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1326
mbed_official	87:085cde657901	1327	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1328	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1329
mbed_official	87:085cde657901	1330	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	87:085cde657901	1331	is performed in DMA reception complete callback */
mbed_official	87:085cde657901	1332	hspi->hdmatx->XferCpltCallback = NULL;
mbed_official	87:085cde657901	1333
mbed_official	87:085cde657901	1334	/* Set the DMA error callback */
mbed_official	87:085cde657901	1335	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1336
mbed_official	87:085cde657901	1337	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1338	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1339
mbed_official	87:085cde657901	1340	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1341	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1342
mbed_official	87:085cde657901	1343	/* Process Unlocked */
mbed_official	87:085cde657901	1344	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1345
mbed_official	87:085cde657901	1346	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1347	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1348	{
mbed_official	87:085cde657901	1349	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1350	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1351	}
mbed_official	87:085cde657901	1352
mbed_official	87:085cde657901	1353	return HAL_OK;
mbed_official	87:085cde657901	1354	}
mbed_official	87:085cde657901	1355	else
mbed_official	87:085cde657901	1356	{
mbed_official	87:085cde657901	1357	return HAL_BUSY;
mbed_official	87:085cde657901	1358	}
mbed_official	87:085cde657901	1359	}
mbed_official	87:085cde657901	1360
mbed_official	87:085cde657901	1361	/**
mbed_official	87:085cde657901	1362	* @brief This function handles SPI interrupt request.
mbed_official	87:085cde657901	1363	* @param hspi: SPI handle
mbed_official	87:085cde657901	1364	* @retval HAL status
mbed_official	87:085cde657901	1365	*/
mbed_official	87:085cde657901	1366	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1367	{
mbed_official	87:085cde657901	1368	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official	87:085cde657901	1369
mbed_official	87:085cde657901	1370	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official	87:085cde657901	1371	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official	87:085cde657901	1372	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official	87:085cde657901	1373	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	87:085cde657901	1374	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official	87:085cde657901	1375	{
mbed_official	87:085cde657901	1376	hspi->RxISR(hspi);
mbed_official	87:085cde657901	1377	return;
mbed_official	87:085cde657901	1378	}
mbed_official	87:085cde657901	1379
mbed_official	87:085cde657901	1380	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official	87:085cde657901	1381	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official	87:085cde657901	1382	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	87:085cde657901	1383	if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official	87:085cde657901	1384	{
mbed_official	87:085cde657901	1385	hspi->TxISR(hspi);
mbed_official	87:085cde657901	1386	return;
mbed_official	87:085cde657901	1387	}
mbed_official	87:085cde657901	1388
mbed_official	87:085cde657901	1389	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	87:085cde657901	1390	{
mbed_official	87:085cde657901	1391	/* SPI CRC error interrupt occured ---------------------------------------*/
mbed_official	87:085cde657901	1392	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1393	{
mbed_official	87:085cde657901	1394	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1395	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1396	}
mbed_official	87:085cde657901	1397	/* SPI Mode Fault error interrupt occured --------------------------------*/
mbed_official	87:085cde657901	1398	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	87:085cde657901	1399	{
mbed_official	87:085cde657901	1400	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	87:085cde657901	1401	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	87:085cde657901	1402	}
mbed_official	87:085cde657901	1403
mbed_official	87:085cde657901	1404	/* SPI Overrun error interrupt occured -----------------------------------*/
mbed_official	87:085cde657901	1405	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	87:085cde657901	1406	{
mbed_official	87:085cde657901	1407	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	87:085cde657901	1408	{
mbed_official	87:085cde657901	1409	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	87:085cde657901	1410	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1411	}
mbed_official	87:085cde657901	1412	}
mbed_official	87:085cde657901	1413
mbed_official	87:085cde657901	1414	/* SPI Frame error interrupt occured -------------------------------------*/
mbed_official	87:085cde657901	1415	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	87:085cde657901	1416	{
mbed_official	87:085cde657901	1417	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	87:085cde657901	1418	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	87:085cde657901	1419	}
mbed_official	87:085cde657901	1420
mbed_official	87:085cde657901	1421	/* Call the Error call Back in case of Errors */
mbed_official	87:085cde657901	1422	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1423	{
mbed_official	87:085cde657901	1424	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1425	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1426	}
mbed_official	87:085cde657901	1427	}
mbed_official	87:085cde657901	1428	}
mbed_official	87:085cde657901	1429
mbed_official	87:085cde657901	1430	/**
mbed_official	87:085cde657901	1431	* @brief Tx Transfer completed callbacks
mbed_official	87:085cde657901	1432	* @param hspi: SPI handle
mbed_official	87:085cde657901	1433	* @retval None
mbed_official	87:085cde657901	1434	*/
mbed_official	87:085cde657901	1435	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1436	{
mbed_official	87:085cde657901	1437	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1438	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	87:085cde657901	1439	*/
mbed_official	87:085cde657901	1440	}
mbed_official	87:085cde657901	1441
mbed_official	87:085cde657901	1442	/**
mbed_official	87:085cde657901	1443	* @brief Rx Transfer completed callbacks
mbed_official	87:085cde657901	1444	* @param hspi: SPI handle
mbed_official	87:085cde657901	1445	* @retval None
mbed_official	87:085cde657901	1446	*/
mbed_official	87:085cde657901	1447	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1448	{
mbed_official	87:085cde657901	1449	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1450	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1451	*/
mbed_official	87:085cde657901	1452	}
mbed_official	87:085cde657901	1453
mbed_official	87:085cde657901	1454	/**
mbed_official	87:085cde657901	1455	* @brief Tx and Rx Transfer completed callbacks
mbed_official	87:085cde657901	1456	* @param hspi: SPI handle
mbed_official	87:085cde657901	1457	* @retval None
mbed_official	87:085cde657901	1458	*/
mbed_official	87:085cde657901	1459	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1460	{
mbed_official	87:085cde657901	1461	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1462	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1463	*/
mbed_official	87:085cde657901	1464	}
mbed_official	87:085cde657901	1465
mbed_official	87:085cde657901	1466	/**
mbed_official	87:085cde657901	1467	* @brief SPI error callbacks
mbed_official	87:085cde657901	1468	* @param hspi: SPI handle
mbed_official	87:085cde657901	1469	* @retval None
mbed_official	87:085cde657901	1470	*/
mbed_official	87:085cde657901	1471	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1472	{
mbed_official	87:085cde657901	1473	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1474	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	87:085cde657901	1475	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	87:085cde657901	1476	and user can use HAL_SPI_GetError() API to check the latest error occured.
mbed_official	87:085cde657901	1477	*/
mbed_official	87:085cde657901	1478	}
mbed_official	87:085cde657901	1479
mbed_official	87:085cde657901	1480	/**
mbed_official	87:085cde657901	1481	* @}
mbed_official	87:085cde657901	1482	*/
mbed_official	87:085cde657901	1483
mbed_official	87:085cde657901	1484	/** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official	87:085cde657901	1485	* @brief SPI control functions
mbed_official	87:085cde657901	1486	*
mbed_official	87:085cde657901	1487	@verbatim
mbed_official	87:085cde657901	1488	===============================================================================
mbed_official	87:085cde657901	1489	##### Peripheral State and Errors functions #####
mbed_official	87:085cde657901	1490	===============================================================================
mbed_official	87:085cde657901	1491	[..]
mbed_official	87:085cde657901	1492	This subsection provides a set of functions allowing to control the SPI.
mbed_official	87:085cde657901	1493	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	87:085cde657901	1494	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	87:085cde657901	1495	@endverbatim
mbed_official	87:085cde657901	1496	* @{
mbed_official	87:085cde657901	1497	*/
mbed_official	87:085cde657901	1498
mbed_official	87:085cde657901	1499	/**
mbed_official	87:085cde657901	1500	* @brief Return the SPI state
mbed_official	87:085cde657901	1501	* @param hspi : SPI handle
mbed_official	87:085cde657901	1502	* @retval SPI state
mbed_official	87:085cde657901	1503	*/
mbed_official	87:085cde657901	1504	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1505	{
mbed_official	87:085cde657901	1506	return hspi->State;
mbed_official	87:085cde657901	1507	}
mbed_official	87:085cde657901	1508
mbed_official	87:085cde657901	1509	/**
mbed_official	87:085cde657901	1510	* @brief Return the SPI error code
mbed_official	87:085cde657901	1511	* @param hspi : SPI handle
mbed_official	87:085cde657901	1512	* @retval SPI Error Code
mbed_official	87:085cde657901	1513	*/
mbed_official	87:085cde657901	1514	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1515	{
mbed_official	87:085cde657901	1516	return hspi->ErrorCode;
mbed_official	87:085cde657901	1517	}
mbed_official	87:085cde657901	1518
mbed_official	87:085cde657901	1519	/**
mbed_official	87:085cde657901	1520	* @}
mbed_official	87:085cde657901	1521	*/
mbed_official	87:085cde657901	1522
mbed_official	87:085cde657901	1523	/**
mbed_official	87:085cde657901	1524	* @brief Interrupt Handler to close Tx transfer
mbed_official	87:085cde657901	1525	* @param hspi: SPI handle
mbed_official	87:085cde657901	1526	* @retval void
mbed_official	87:085cde657901	1527	*/
mbed_official	87:085cde657901	1528	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1529	{
mbed_official	106:ced8cbb51063	1530	/* Wait until TXE flag is set to send data */
mbed_official	106:ced8cbb51063	1531	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1532	{
mbed_official	106:ced8cbb51063	1533	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1534	}
mbed_official	87:085cde657901	1535
mbed_official	87:085cde657901	1536	/* Disable TXE interrupt */
mbed_official	87:085cde657901	1537	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official	87:085cde657901	1538
mbed_official	87:085cde657901	1539	/* Disable ERR interrupt if Receive process is finished */
mbed_official	87:085cde657901	1540	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	87:085cde657901	1541	{
mbed_official	87:085cde657901	1542	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1543
mbed_official	87:085cde657901	1544	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1545	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1546	{
mbed_official	87:085cde657901	1547	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1548	}
mbed_official	87:085cde657901	1549
mbed_official	87:085cde657901	1550	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1551	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1552	{
mbed_official	87:085cde657901	1553	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1554	}
mbed_official	87:085cde657901	1555
mbed_official	87:085cde657901	1556	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1557	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1558	{
mbed_official	87:085cde657901	1559	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1560	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1561	{
mbed_official	106:ced8cbb51063	1562	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1563	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1564	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1565	}
mbed_official	87:085cde657901	1566	else
mbed_official	87:085cde657901	1567	{
mbed_official	106:ced8cbb51063	1568	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1569	hspi->State = HAL_SPI_STATE_READY;
mbed_official	106:ced8cbb51063	1570	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1571	}
mbed_official	87:085cde657901	1572	}
mbed_official	87:085cde657901	1573	else
mbed_official	87:085cde657901	1574	{
mbed_official	106:ced8cbb51063	1575	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1576	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1577	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1578	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1579	}
mbed_official	87:085cde657901	1580	}
mbed_official	87:085cde657901	1581	}
mbed_official	87:085cde657901	1582
mbed_official	87:085cde657901	1583	/**
mbed_official	87:085cde657901	1584	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	87:085cde657901	1585	* @param hspi: SPI handle
mbed_official	87:085cde657901	1586	* @retval void
mbed_official	87:085cde657901	1587	*/
mbed_official	87:085cde657901	1588	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1589	{
mbed_official	87:085cde657901	1590	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	1591	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1592	{
mbed_official	87:085cde657901	1593	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	1594	}
mbed_official	87:085cde657901	1595	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	1596	else
mbed_official	87:085cde657901	1597	{
mbed_official	87:085cde657901	1598	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	1599	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	1600	}
mbed_official	87:085cde657901	1601	hspi->TxXferCount--;
mbed_official	87:085cde657901	1602
mbed_official	87:085cde657901	1603	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	1604	{
mbed_official	87:085cde657901	1605	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1606	{
mbed_official	87:085cde657901	1607	/* calculate and transfer CRC on Tx line */
mbed_official	87:085cde657901	1608	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1609	}
mbed_official	87:085cde657901	1610	SPI_TxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1611	}
mbed_official	87:085cde657901	1612	}
mbed_official	87:085cde657901	1613
mbed_official	87:085cde657901	1614	/**
mbed_official	87:085cde657901	1615	* @brief Interrupt Handler to close Rx transfer
mbed_official	87:085cde657901	1616	* @param hspi: SPI handle
mbed_official	87:085cde657901	1617	* @retval void
mbed_official	87:085cde657901	1618	*/
mbed_official	106:ced8cbb51063	1619	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1620	{
mbed_official	87:085cde657901	1621	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1622
mbed_official	87:085cde657901	1623	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1624	{
mbed_official	87:085cde657901	1625	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1626	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1627	{
mbed_official	87:085cde657901	1628	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1629	}
mbed_official	87:085cde657901	1630
mbed_official	87:085cde657901	1631	/* Read CRC to reset RXNE flag */
mbed_official	87:085cde657901	1632	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1633
mbed_official	87:085cde657901	1634	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1635	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1636	{
mbed_official	87:085cde657901	1637	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1638	}
mbed_official	87:085cde657901	1639
mbed_official	87:085cde657901	1640	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1641	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1642	{
mbed_official	87:085cde657901	1643	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1644
mbed_official	87:085cde657901	1645	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1646	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1647	}
mbed_official	87:085cde657901	1648	}
mbed_official	87:085cde657901	1649
mbed_official	87:085cde657901	1650	/* Disable RXNE and ERR interrupt */
mbed_official	87:085cde657901	1651	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	87:085cde657901	1652
mbed_official	87:085cde657901	1653	/* if Transmit process is finished */
mbed_official	87:085cde657901	1654	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	87:085cde657901	1655	{
mbed_official	87:085cde657901	1656	/* Disable ERR interrupt */
mbed_official	87:085cde657901	1657	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1658
mbed_official	87:085cde657901	1659	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1660	{
mbed_official	87:085cde657901	1661	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1662	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1663	}
mbed_official	87:085cde657901	1664
mbed_official	87:085cde657901	1665	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1666	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1667	{
mbed_official	87:085cde657901	1668	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1669	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1670	{
mbed_official	106:ced8cbb51063	1671	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1672	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1673	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1674	}else
mbed_official	87:085cde657901	1675	{
mbed_official	106:ced8cbb51063	1676	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1677	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1678	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1679	}
mbed_official	87:085cde657901	1680	}
mbed_official	87:085cde657901	1681	else
mbed_official	87:085cde657901	1682	{
mbed_official	106:ced8cbb51063	1683	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1684	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1685	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1686	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1687	}
mbed_official	87:085cde657901	1688	}
mbed_official	87:085cde657901	1689	}
mbed_official	87:085cde657901	1690
mbed_official	87:085cde657901	1691	/**
mbed_official	87:085cde657901	1692	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	87:085cde657901	1693	* @param hspi: SPI handle
mbed_official	87:085cde657901	1694	* @retval void
mbed_official	87:085cde657901	1695	*/
mbed_official	87:085cde657901	1696	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1697	{
mbed_official	87:085cde657901	1698	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1699	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1700	{
mbed_official	87:085cde657901	1701	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1702	}
mbed_official	87:085cde657901	1703	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1704	else
mbed_official	87:085cde657901	1705	{
mbed_official	87:085cde657901	1706	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1707	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1708	}
mbed_official	87:085cde657901	1709	hspi->RxXferCount--;
mbed_official	87:085cde657901	1710
mbed_official	87:085cde657901	1711	if(hspi->RxXferCount==0)
mbed_official	87:085cde657901	1712	{
mbed_official	106:ced8cbb51063	1713	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1714	}
mbed_official	87:085cde657901	1715	}
mbed_official	87:085cde657901	1716
mbed_official	87:085cde657901	1717	/**
mbed_official	87:085cde657901	1718	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	87:085cde657901	1719	* @param hspi: SPI handle
mbed_official	87:085cde657901	1720	* @retval void
mbed_official	87:085cde657901	1721	*/
mbed_official	87:085cde657901	1722	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1723	{
mbed_official	87:085cde657901	1724	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1725	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1726	{
mbed_official	87:085cde657901	1727	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1728	}
mbed_official	87:085cde657901	1729	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1730	else
mbed_official	87:085cde657901	1731	{
mbed_official	87:085cde657901	1732	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1733	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1734	}
mbed_official	87:085cde657901	1735	hspi->RxXferCount--;
mbed_official	87:085cde657901	1736
mbed_official	87:085cde657901	1737	/* Enable CRC Transmission */
mbed_official	87:085cde657901	1738	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	1739	{
mbed_official	87:085cde657901	1740	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	87:085cde657901	1741	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1742	}
mbed_official	87:085cde657901	1743
mbed_official	87:085cde657901	1744	if(hspi->RxXferCount == 0)
mbed_official	87:085cde657901	1745	{
mbed_official	106:ced8cbb51063	1746	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1747	}
mbed_official	87:085cde657901	1748	}
mbed_official	87:085cde657901	1749
mbed_official	87:085cde657901	1750	/**
mbed_official	87:085cde657901	1751	* @brief DMA SPI transmit process complete callback
mbed_official	87:085cde657901	1752	* @param hdma : DMA handle
mbed_official	87:085cde657901	1753	* @retval None
mbed_official	87:085cde657901	1754	*/
mbed_official	87:085cde657901	1755	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1756	{
mbed_official	87:085cde657901	1757	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1758
mbed_official	87:085cde657901	1759	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1760	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1761	{
mbed_official	87:085cde657901	1762	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1763	}
mbed_official	87:085cde657901	1764
mbed_official	87:085cde657901	1765	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1766	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1767
mbed_official	87:085cde657901	1768	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1769	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1770	{
mbed_official	87:085cde657901	1771	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1772	}
mbed_official	87:085cde657901	1773
mbed_official	87:085cde657901	1774	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1775
mbed_official	87:085cde657901	1776	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1777
mbed_official	87:085cde657901	1778	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1779	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1780	{
mbed_official	87:085cde657901	1781	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1782	}
mbed_official	87:085cde657901	1783
mbed_official	87:085cde657901	1784	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1785	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1786	{
mbed_official	87:085cde657901	1787	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1788	}
mbed_official	87:085cde657901	1789	else
mbed_official	87:085cde657901	1790	{
mbed_official	87:085cde657901	1791	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1792	}
mbed_official	87:085cde657901	1793	}
mbed_official	87:085cde657901	1794
mbed_official	87:085cde657901	1795	/**
mbed_official	87:085cde657901	1796	* @brief DMA SPI receive process complete callback
mbed_official	87:085cde657901	1797	* @param hdma : DMA handle
mbed_official	87:085cde657901	1798	* @retval None
mbed_official	87:085cde657901	1799	*/
mbed_official	87:085cde657901	1800	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1801	{
mbed_official	87:085cde657901	1802	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1803
mbed_official	87:085cde657901	1804	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1805
mbed_official	87:085cde657901	1806	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1807	{
mbed_official	87:085cde657901	1808	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1809	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1810	}
mbed_official	87:085cde657901	1811
mbed_official	87:085cde657901	1812	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1813	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1814
mbed_official	87:085cde657901	1815	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1816	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1817	{
mbed_official	87:085cde657901	1818	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1819	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1820	{
mbed_official	87:085cde657901	1821	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1822	}
mbed_official	87:085cde657901	1823
mbed_official	87:085cde657901	1824	/* Read CRC */
mbed_official	87:085cde657901	1825	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1826
mbed_official	87:085cde657901	1827	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1828	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1829	{
mbed_official	87:085cde657901	1830	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1831	}
mbed_official	87:085cde657901	1832	}
mbed_official	87:085cde657901	1833
mbed_official	87:085cde657901	1834	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1835	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1836
mbed_official	87:085cde657901	1837	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1838	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1839	{
mbed_official	87:085cde657901	1840	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1841	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1842	}
mbed_official	87:085cde657901	1843
mbed_official	87:085cde657901	1844	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1845	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1846	{
mbed_official	87:085cde657901	1847	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1848	}
mbed_official	87:085cde657901	1849	else
mbed_official	87:085cde657901	1850	{
mbed_official	87:085cde657901	1851	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1852	}
mbed_official	87:085cde657901	1853	}
mbed_official	87:085cde657901	1854
mbed_official	87:085cde657901	1855	/**
mbed_official	87:085cde657901	1856	* @brief DMA SPI transmit receive process complete callback
mbed_official	87:085cde657901	1857	* @param hdma : DMA handle
mbed_official	87:085cde657901	1858	* @retval None
mbed_official	87:085cde657901	1859	*/
mbed_official	87:085cde657901	1860	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1861	{
mbed_official	87:085cde657901	1862	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1863
mbed_official	87:085cde657901	1864	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1865
mbed_official	87:085cde657901	1866	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1867	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1868	{
mbed_official	87:085cde657901	1869	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	87:085cde657901	1870	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	87:085cde657901	1871	{
mbed_official	87:085cde657901	1872	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1873	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1874	{
mbed_official	87:085cde657901	1875	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1876	}
mbed_official	87:085cde657901	1877	}
mbed_official	87:085cde657901	1878	/* Read CRC */
mbed_official	87:085cde657901	1879	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1880	}
mbed_official	87:085cde657901	1881
mbed_official	87:085cde657901	1882	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	1883	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1884	{
mbed_official	87:085cde657901	1885	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1886	}
mbed_official	87:085cde657901	1887	/* Disable Tx DMA Request */
mbed_official	87:085cde657901	1888	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1889
mbed_official	87:085cde657901	1890	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1891	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1892	{
mbed_official	87:085cde657901	1893	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1894	}
mbed_official	87:085cde657901	1895
mbed_official	87:085cde657901	1896	/* Disable Rx DMA Request */
mbed_official	87:085cde657901	1897	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	87:085cde657901	1898
mbed_official	87:085cde657901	1899	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1900	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1901
mbed_official	87:085cde657901	1902	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1903
mbed_official	87:085cde657901	1904	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1905	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1906	{
mbed_official	87:085cde657901	1907	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1908	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1909	}
mbed_official	87:085cde657901	1910
mbed_official	87:085cde657901	1911	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1912	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1913	{
mbed_official	87:085cde657901	1914	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1915	}
mbed_official	87:085cde657901	1916	else
mbed_official	87:085cde657901	1917	{
mbed_official	87:085cde657901	1918	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1919	}
mbed_official	87:085cde657901	1920	}
mbed_official	87:085cde657901	1921
mbed_official	87:085cde657901	1922	/**
mbed_official	87:085cde657901	1923	* @brief DMA SPI communication error callback
mbed_official	87:085cde657901	1924	* @param hdma : DMA handle
mbed_official	87:085cde657901	1925	* @retval None
mbed_official	87:085cde657901	1926	*/
mbed_official	87:085cde657901	1927	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1928	{
mbed_official	87:085cde657901	1929	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1930	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1931	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1932	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1933	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
mbed_official	87:085cde657901	1934	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1935	}
mbed_official	87:085cde657901	1936
mbed_official	87:085cde657901	1937	/**
mbed_official	87:085cde657901	1938	* @brief This function handles SPI Communication Timeout.
mbed_official	87:085cde657901	1939	* @param hspi: SPI handle
mbed_official	87:085cde657901	1940	* @retval HAL status
mbed_official	87:085cde657901	1941	*/
mbed_official	87:085cde657901	1942	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	87:085cde657901	1943	{
mbed_official	87:085cde657901	1944	uint32_t timeout = 0;
mbed_official	87:085cde657901	1945
mbed_official	87:085cde657901	1946	timeout = HAL_GetTick() + Timeout;
mbed_official	87:085cde657901	1947
mbed_official	87:085cde657901	1948	/* Wait until flag is set */
mbed_official	87:085cde657901	1949	if(Status == RESET)
mbed_official	87:085cde657901	1950	{
mbed_official	87:085cde657901	1951	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	87:085cde657901	1952	{
mbed_official	87:085cde657901	1953	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	1954	{
mbed_official	87:085cde657901	1955	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	1956	{
mbed_official	87:085cde657901	1957	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	1958	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	1959	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	1960
mbed_official	87:085cde657901	1961	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	1962	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1963
mbed_official	87:085cde657901	1964	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1965	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1966
mbed_official	87:085cde657901	1967	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1968	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1969	{
mbed_official	87:085cde657901	1970	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1971	}
mbed_official	87:085cde657901	1972
mbed_official	87:085cde657901	1973	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1974
mbed_official	87:085cde657901	1975	/* Process Unlocked */
mbed_official	87:085cde657901	1976	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1977
mbed_official	87:085cde657901	1978	return HAL_TIMEOUT;
mbed_official	87:085cde657901	1979	}
mbed_official	87:085cde657901	1980	}
mbed_official	87:085cde657901	1981	}
mbed_official	87:085cde657901	1982	}
mbed_official	87:085cde657901	1983	else
mbed_official	87:085cde657901	1984	{
mbed_official	87:085cde657901	1985	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	87:085cde657901	1986	{
mbed_official	87:085cde657901	1987	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	1988	{
mbed_official	87:085cde657901	1989	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	1990	{
mbed_official	87:085cde657901	1991	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	1992	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	1993	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	1994
mbed_official	87:085cde657901	1995	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	1996	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1997
mbed_official	87:085cde657901	1998	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1999	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	2000
mbed_official	87:085cde657901	2001	/* Reset CRC Calculation */
mbed_official	87:085cde657901	2002	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2003	{
mbed_official	87:085cde657901	2004	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	2005	}
mbed_official	87:085cde657901	2006
mbed_official	87:085cde657901	2007	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2008
mbed_official	87:085cde657901	2009	/* Process Unlocked */
mbed_official	87:085cde657901	2010	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	2011
mbed_official	87:085cde657901	2012	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2013	}
mbed_official	87:085cde657901	2014	}
mbed_official	87:085cde657901	2015	}
mbed_official	87:085cde657901	2016	}
mbed_official	87:085cde657901	2017	return HAL_OK;
mbed_official	87:085cde657901	2018	}
mbed_official	87:085cde657901	2019
mbed_official	87:085cde657901	2020
mbed_official	87:085cde657901	2021	/**
mbed_official	87:085cde657901	2022	* @}
mbed_official	87:085cde657901	2023	*/
mbed_official	87:085cde657901	2024
mbed_official	87:085cde657901	2025	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	87:085cde657901	2026	/**
mbed_official	87:085cde657901	2027	* @}
mbed_official	87:085cde657901	2028	*/
mbed_official	87:085cde657901	2029
mbed_official	87:085cde657901	2030	/**
mbed_official	87:085cde657901	2031	* @}
mbed_official	87:085cde657901	2032	*/
mbed_official	87:085cde657901	2033
mbed_official	87:085cde657901	2034	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	19 Apr 2014
Imports:	9
Forks:	0
Commits:	164
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@106:ced8cbb51063, 2014-02-26 (annotated)

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