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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.c@106:ced8cbb51063, 2014-02-26 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Feb 26 09:45:12 2014 +0000
- Revision:
- 106:ced8cbb51063
- Parent:
- 87:085cde657901
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd
Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/
[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 87:085cde657901 | 1 | /** |
mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_i2s.c |
mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
mbed_official | 106:ced8cbb51063 | 5 | * @version V1.0.0 |
mbed_official | 106:ced8cbb51063 | 6 | * @date 18-February-2014 |
mbed_official | 87:085cde657901 | 7 | * @brief I2S HAL module driver. |
mbed_official | 87:085cde657901 | 8 | * This file provides firmware functions to manage the following |
mbed_official | 87:085cde657901 | 9 | * functionalities of the Integrated Interchip Sound (I2S) peripheral: |
mbed_official | 87:085cde657901 | 10 | * + Initialization and de-initialization functions |
mbed_official | 87:085cde657901 | 11 | * + IO operation functions |
mbed_official | 87:085cde657901 | 12 | * + Peripheral State and Errors functions |
mbed_official | 87:085cde657901 | 13 | @verbatim |
mbed_official | 87:085cde657901 | 14 | =============================================================================== |
mbed_official | 87:085cde657901 | 15 | ##### How to use this driver ##### |
mbed_official | 87:085cde657901 | 16 | =============================================================================== |
mbed_official | 87:085cde657901 | 17 | [..] |
mbed_official | 87:085cde657901 | 18 | The I2S HAL driver can be used as follow: |
mbed_official | 87:085cde657901 | 19 | |
mbed_official | 87:085cde657901 | 20 | (#) Declare a I2S_HandleTypeDef handle structure. |
mbed_official | 87:085cde657901 | 21 | (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: |
mbed_official | 87:085cde657901 | 22 | (##) Enable the SPIx interface clock. |
mbed_official | 87:085cde657901 | 23 | (##) I2S pins configuration: |
mbed_official | 87:085cde657901 | 24 | (+++) Enable the clock for the I2S GPIOs. |
mbed_official | 87:085cde657901 | 25 | (+++) Configure these I2S pins as alternate function pull-up. |
mbed_official | 87:085cde657901 | 26 | (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() |
mbed_official | 87:085cde657901 | 27 | and HAL_I2S_Receive_IT() APIs). |
mbed_official | 87:085cde657901 | 28 | (+++) Configure the I2Sx interrupt priority. |
mbed_official | 87:085cde657901 | 29 | (+++) Enable the NVIC I2S IRQ handle. |
mbed_official | 87:085cde657901 | 30 | (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() |
mbed_official | 87:085cde657901 | 31 | and HAL_I2S_Receive_DMA() APIs: |
mbed_official | 87:085cde657901 | 32 | (+++) Declare a DMA handle structure for the Tx/Rx stream. |
mbed_official | 87:085cde657901 | 33 | (+++) Enable the DMAx interface clock. |
mbed_official | 87:085cde657901 | 34 | (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. |
mbed_official | 87:085cde657901 | 35 | (+++) Configure the DMA Tx/Rx Stream. |
mbed_official | 87:085cde657901 | 36 | (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. |
mbed_official | 87:085cde657901 | 37 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the |
mbed_official | 87:085cde657901 | 38 | DMA Tx/Rx Stream. |
mbed_official | 87:085cde657901 | 39 | |
mbed_official | 87:085cde657901 | 40 | (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity |
mbed_official | 87:085cde657901 | 41 | using HAL_I2S_Init() function. |
mbed_official | 87:085cde657901 | 42 | |
mbed_official | 87:085cde657901 | 43 | -@- The specific I2S interrupts (Transmission complete interrupt, |
mbed_official | 87:085cde657901 | 44 | RXNE interrupt and Error Interrupts) will be managed using the macros |
mbed_official | 87:085cde657901 | 45 | __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process. |
mbed_official | 87:085cde657901 | 46 | -@- Make sure that either: |
mbed_official | 87:085cde657901 | 47 | (+@) I2S PLL is configured or |
mbed_official | 87:085cde657901 | 48 | (+@) External clock source is configured after setting correctly |
mbed_official | 87:085cde657901 | 49 | the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. |
mbed_official | 87:085cde657901 | 50 | |
mbed_official | 87:085cde657901 | 51 | (#) Three mode of operations are available within this driver : |
mbed_official | 87:085cde657901 | 52 | |
mbed_official | 87:085cde657901 | 53 | *** Polling mode IO operation *** |
mbed_official | 87:085cde657901 | 54 | ================================= |
mbed_official | 87:085cde657901 | 55 | [..] |
mbed_official | 87:085cde657901 | 56 | (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() |
mbed_official | 87:085cde657901 | 57 | (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() |
mbed_official | 87:085cde657901 | 58 | |
mbed_official | 87:085cde657901 | 59 | *** Interrupt mode IO operation *** |
mbed_official | 87:085cde657901 | 60 | =================================== |
mbed_official | 87:085cde657901 | 61 | [..] |
mbed_official | 87:085cde657901 | 62 | (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() |
mbed_official | 87:085cde657901 | 63 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 64 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
mbed_official | 87:085cde657901 | 65 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 66 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
mbed_official | 87:085cde657901 | 67 | (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() |
mbed_official | 87:085cde657901 | 68 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 69 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
mbed_official | 87:085cde657901 | 70 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 71 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
mbed_official | 87:085cde657901 | 72 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
mbed_official | 87:085cde657901 | 73 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
mbed_official | 87:085cde657901 | 74 | |
mbed_official | 87:085cde657901 | 75 | *** DMA mode IO operation *** |
mbed_official | 87:085cde657901 | 76 | ============================== |
mbed_official | 87:085cde657901 | 77 | [..] |
mbed_official | 87:085cde657901 | 78 | (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() |
mbed_official | 87:085cde657901 | 79 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 80 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
mbed_official | 87:085cde657901 | 81 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 82 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
mbed_official | 87:085cde657901 | 83 | (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() |
mbed_official | 87:085cde657901 | 84 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 85 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
mbed_official | 87:085cde657901 | 86 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
mbed_official | 87:085cde657901 | 87 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
mbed_official | 87:085cde657901 | 88 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
mbed_official | 87:085cde657901 | 89 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
mbed_official | 87:085cde657901 | 90 | (+) Pause the DMA Transfer using HAL_I2S_DMAPause() |
mbed_official | 87:085cde657901 | 91 | (+) Resume the DMA Transfer using HAL_I2S_DMAResume() |
mbed_official | 87:085cde657901 | 92 | (+) Stop the DMA Transfer using HAL_I2S_DMAStop() |
mbed_official | 87:085cde657901 | 93 | |
mbed_official | 87:085cde657901 | 94 | *** I2S HAL driver macros list *** |
mbed_official | 87:085cde657901 | 95 | ============================================= |
mbed_official | 87:085cde657901 | 96 | [..] |
mbed_official | 87:085cde657901 | 97 | Below the list of most used macros in USART HAL driver. |
mbed_official | 87:085cde657901 | 98 | |
mbed_official | 87:085cde657901 | 99 | (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) |
mbed_official | 87:085cde657901 | 100 | (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) |
mbed_official | 87:085cde657901 | 101 | (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts |
mbed_official | 87:085cde657901 | 102 | (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts |
mbed_official | 87:085cde657901 | 103 | (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not |
mbed_official | 87:085cde657901 | 104 | |
mbed_official | 87:085cde657901 | 105 | [..] |
mbed_official | 87:085cde657901 | 106 | (@) You can refer to the I2S HAL driver header file for more useful macros |
mbed_official | 87:085cde657901 | 107 | |
mbed_official | 87:085cde657901 | 108 | @endverbatim |
mbed_official | 87:085cde657901 | 109 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 110 | * @attention |
mbed_official | 87:085cde657901 | 111 | * |
mbed_official | 87:085cde657901 | 112 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 87:085cde657901 | 113 | * |
mbed_official | 87:085cde657901 | 114 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 87:085cde657901 | 115 | * are permitted provided that the following conditions are met: |
mbed_official | 87:085cde657901 | 116 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 87:085cde657901 | 117 | * this list of conditions and the following disclaimer. |
mbed_official | 87:085cde657901 | 118 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 87:085cde657901 | 119 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 87:085cde657901 | 120 | * and/or other materials provided with the distribution. |
mbed_official | 87:085cde657901 | 121 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 87:085cde657901 | 122 | * may be used to endorse or promote products derived from this software |
mbed_official | 87:085cde657901 | 123 | * without specific prior written permission. |
mbed_official | 87:085cde657901 | 124 | * |
mbed_official | 87:085cde657901 | 125 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 87:085cde657901 | 126 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 87:085cde657901 | 127 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 87:085cde657901 | 128 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 87:085cde657901 | 129 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 87:085cde657901 | 130 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 87:085cde657901 | 131 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 87:085cde657901 | 132 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 87:085cde657901 | 133 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 87:085cde657901 | 134 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 87:085cde657901 | 135 | * |
mbed_official | 87:085cde657901 | 136 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 137 | */ |
mbed_official | 87:085cde657901 | 138 | |
mbed_official | 87:085cde657901 | 139 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 140 | #include "stm32f4xx_hal.h" |
mbed_official | 87:085cde657901 | 141 | |
mbed_official | 87:085cde657901 | 142 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 87:085cde657901 | 143 | * @{ |
mbed_official | 87:085cde657901 | 144 | */ |
mbed_official | 87:085cde657901 | 145 | |
mbed_official | 87:085cde657901 | 146 | /** @defgroup I2S |
mbed_official | 87:085cde657901 | 147 | * @brief I2S HAL module driver |
mbed_official | 87:085cde657901 | 148 | * @{ |
mbed_official | 87:085cde657901 | 149 | */ |
mbed_official | 87:085cde657901 | 150 | |
mbed_official | 87:085cde657901 | 151 | #ifdef HAL_I2S_MODULE_ENABLED |
mbed_official | 87:085cde657901 | 152 | |
mbed_official | 87:085cde657901 | 153 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 154 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 155 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 156 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 157 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 158 | static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); |
mbed_official | 87:085cde657901 | 159 | static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s); |
mbed_official | 87:085cde657901 | 160 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 161 | |
mbed_official | 87:085cde657901 | 162 | /** @defgroup I2S_Private_Functions |
mbed_official | 87:085cde657901 | 163 | * @{ |
mbed_official | 87:085cde657901 | 164 | */ |
mbed_official | 87:085cde657901 | 165 | |
mbed_official | 87:085cde657901 | 166 | /** @defgroup I2S_Group1 Initialization and de-initialization functions |
mbed_official | 87:085cde657901 | 167 | * @brief Initialization and Configuration functions |
mbed_official | 87:085cde657901 | 168 | * |
mbed_official | 87:085cde657901 | 169 | @verbatim |
mbed_official | 87:085cde657901 | 170 | =============================================================================== |
mbed_official | 87:085cde657901 | 171 | ##### Initialization and de-initialization functions ##### |
mbed_official | 87:085cde657901 | 172 | =============================================================================== |
mbed_official | 87:085cde657901 | 173 | [..] This subsection provides a set of functions allowing to initialize and |
mbed_official | 87:085cde657901 | 174 | de-initialiaze the I2Sx peripheral in simplex mode: |
mbed_official | 87:085cde657901 | 175 | |
mbed_official | 87:085cde657901 | 176 | (+) User must Implement HAL_I2S_MspInit() function in which he configures |
mbed_official | 87:085cde657901 | 177 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
mbed_official | 87:085cde657901 | 178 | |
mbed_official | 87:085cde657901 | 179 | (+) Call the function HAL_I2S_Init() to configure the selected device with |
mbed_official | 87:085cde657901 | 180 | the selected configuration: |
mbed_official | 87:085cde657901 | 181 | (++) Mode |
mbed_official | 87:085cde657901 | 182 | (++) Standard |
mbed_official | 87:085cde657901 | 183 | (++) Data Format |
mbed_official | 87:085cde657901 | 184 | (++) MCLK Output |
mbed_official | 87:085cde657901 | 185 | (++) Audio frequency |
mbed_official | 87:085cde657901 | 186 | (++) Polarity |
mbed_official | 87:085cde657901 | 187 | (++) Full duplex mode |
mbed_official | 87:085cde657901 | 188 | |
mbed_official | 87:085cde657901 | 189 | (+) Call the function HAL_I2S_DeInit() to restore the default configuration |
mbed_official | 87:085cde657901 | 190 | of the selected I2Sx periperal. |
mbed_official | 87:085cde657901 | 191 | @endverbatim |
mbed_official | 87:085cde657901 | 192 | * @{ |
mbed_official | 87:085cde657901 | 193 | */ |
mbed_official | 87:085cde657901 | 194 | |
mbed_official | 87:085cde657901 | 195 | /** |
mbed_official | 87:085cde657901 | 196 | * @brief Initializes the I2S according to the specified parameters |
mbed_official | 87:085cde657901 | 197 | * in the I2S_InitTypeDef and create the associated handle. |
mbed_official | 87:085cde657901 | 198 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 199 | * @retval HAL status |
mbed_official | 87:085cde657901 | 200 | */ |
mbed_official | 87:085cde657901 | 201 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 202 | { |
mbed_official | 87:085cde657901 | 203 | uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; |
mbed_official | 87:085cde657901 | 204 | uint32_t tmp = 0, i2sclk = 0; |
mbed_official | 87:085cde657901 | 205 | |
mbed_official | 87:085cde657901 | 206 | /* Check the I2S handle allocation */ |
mbed_official | 87:085cde657901 | 207 | if(hi2s == NULL) |
mbed_official | 87:085cde657901 | 208 | { |
mbed_official | 87:085cde657901 | 209 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 210 | } |
mbed_official | 87:085cde657901 | 211 | |
mbed_official | 87:085cde657901 | 212 | /* Check the I2S parameters */ |
mbed_official | 87:085cde657901 | 213 | assert_param(IS_I2S_MODE(hi2s->Init.Mode)); |
mbed_official | 87:085cde657901 | 214 | assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); |
mbed_official | 87:085cde657901 | 215 | assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); |
mbed_official | 87:085cde657901 | 216 | assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); |
mbed_official | 87:085cde657901 | 217 | assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); |
mbed_official | 87:085cde657901 | 218 | assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); |
mbed_official | 87:085cde657901 | 219 | assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); |
mbed_official | 87:085cde657901 | 220 | assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode)); |
mbed_official | 87:085cde657901 | 221 | |
mbed_official | 87:085cde657901 | 222 | if(hi2s->State == HAL_I2S_STATE_RESET) |
mbed_official | 87:085cde657901 | 223 | { |
mbed_official | 87:085cde657901 | 224 | /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ |
mbed_official | 87:085cde657901 | 225 | HAL_I2S_MspInit(hi2s); |
mbed_official | 87:085cde657901 | 226 | } |
mbed_official | 87:085cde657901 | 227 | |
mbed_official | 87:085cde657901 | 228 | hi2s->State = HAL_I2S_STATE_BUSY; |
mbed_official | 87:085cde657901 | 229 | |
mbed_official | 87:085cde657901 | 230 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ |
mbed_official | 87:085cde657901 | 231 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
mbed_official | 87:085cde657901 | 232 | hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
mbed_official | 87:085cde657901 | 233 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
mbed_official | 87:085cde657901 | 234 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); |
mbed_official | 87:085cde657901 | 235 | hi2s->Instance->I2SPR = 0x0002; |
mbed_official | 87:085cde657901 | 236 | |
mbed_official | 87:085cde657901 | 237 | /* Get the I2SCFGR register value */ |
mbed_official | 87:085cde657901 | 238 | tmpreg = hi2s->Instance->I2SCFGR; |
mbed_official | 87:085cde657901 | 239 | |
mbed_official | 87:085cde657901 | 240 | /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */ |
mbed_official | 87:085cde657901 | 241 | /* If the requested audio frequency is not the default, compute the prescaler */ |
mbed_official | 87:085cde657901 | 242 | if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) |
mbed_official | 87:085cde657901 | 243 | { |
mbed_official | 87:085cde657901 | 244 | /* Check the frame length (For the Prescaler computing) *******************/ |
mbed_official | 87:085cde657901 | 245 | if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) |
mbed_official | 87:085cde657901 | 246 | { |
mbed_official | 87:085cde657901 | 247 | /* Packet length is 32 bits */ |
mbed_official | 87:085cde657901 | 248 | packetlength = 2; |
mbed_official | 87:085cde657901 | 249 | } |
mbed_official | 87:085cde657901 | 250 | |
mbed_official | 87:085cde657901 | 251 | /* Get I2S source Clock frequency ****************************************/ |
mbed_official | 87:085cde657901 | 252 | /* If an external I2S clock has to be used, the specific define should be set |
mbed_official | 87:085cde657901 | 253 | in the project configuration or in the stm32f4xx_conf.h file */ |
mbed_official | 87:085cde657901 | 254 | if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) |
mbed_official | 87:085cde657901 | 255 | { |
mbed_official | 87:085cde657901 | 256 | /* Set external clock as I2S clock source */ |
mbed_official | 87:085cde657901 | 257 | if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) |
mbed_official | 87:085cde657901 | 258 | { |
mbed_official | 87:085cde657901 | 259 | RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; |
mbed_official | 87:085cde657901 | 260 | } |
mbed_official | 87:085cde657901 | 261 | |
mbed_official | 87:085cde657901 | 262 | /* Set the I2S clock to the external clock value */ |
mbed_official | 87:085cde657901 | 263 | i2sclk = EXTERNAL_CLOCK_VALUE; |
mbed_official | 87:085cde657901 | 264 | } |
mbed_official | 87:085cde657901 | 265 | else |
mbed_official | 87:085cde657901 | 266 | { |
mbed_official | 87:085cde657901 | 267 | /* Check if PLLI2S is enabled or Not */ |
mbed_official | 87:085cde657901 | 268 | if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON) |
mbed_official | 87:085cde657901 | 269 | { |
mbed_official | 87:085cde657901 | 270 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 271 | |
mbed_official | 87:085cde657901 | 272 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 273 | } |
mbed_official | 87:085cde657901 | 274 | |
mbed_official | 87:085cde657901 | 275 | /* Set PLLI2S as I2S clock source */ |
mbed_official | 87:085cde657901 | 276 | if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) |
mbed_official | 87:085cde657901 | 277 | { |
mbed_official | 87:085cde657901 | 278 | RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; |
mbed_official | 87:085cde657901 | 279 | } |
mbed_official | 87:085cde657901 | 280 | |
mbed_official | 87:085cde657901 | 281 | /* Get the PLLM value */ |
mbed_official | 87:085cde657901 | 282 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
mbed_official | 87:085cde657901 | 283 | { |
mbed_official | 87:085cde657901 | 284 | /* Get the I2S source clock value */ |
mbed_official | 87:085cde657901 | 285 | i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
mbed_official | 87:085cde657901 | 286 | } |
mbed_official | 87:085cde657901 | 287 | else |
mbed_official | 87:085cde657901 | 288 | { |
mbed_official | 87:085cde657901 | 289 | /* Get the I2S source clock value */ |
mbed_official | 87:085cde657901 | 290 | i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
mbed_official | 87:085cde657901 | 291 | } |
mbed_official | 87:085cde657901 | 292 | i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)); |
mbed_official | 87:085cde657901 | 293 | i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)); |
mbed_official | 87:085cde657901 | 294 | } |
mbed_official | 87:085cde657901 | 295 | |
mbed_official | 87:085cde657901 | 296 | /* Compute the Real divider depending on the MCLK output state, with a floating point */ |
mbed_official | 87:085cde657901 | 297 | if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) |
mbed_official | 87:085cde657901 | 298 | { |
mbed_official | 87:085cde657901 | 299 | /* MCLK output is enabled */ |
mbed_official | 87:085cde657901 | 300 | tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); |
mbed_official | 87:085cde657901 | 301 | } |
mbed_official | 87:085cde657901 | 302 | else |
mbed_official | 87:085cde657901 | 303 | { |
mbed_official | 87:085cde657901 | 304 | /* MCLK output is disabled */ |
mbed_official | 87:085cde657901 | 305 | tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); |
mbed_official | 87:085cde657901 | 306 | } |
mbed_official | 87:085cde657901 | 307 | |
mbed_official | 87:085cde657901 | 308 | /* Remove the flatting point */ |
mbed_official | 87:085cde657901 | 309 | tmp = tmp / 10; |
mbed_official | 87:085cde657901 | 310 | |
mbed_official | 87:085cde657901 | 311 | /* Check the parity of the divider */ |
mbed_official | 87:085cde657901 | 312 | i2sodd = (uint32_t)(tmp & (uint32_t)1); |
mbed_official | 87:085cde657901 | 313 | |
mbed_official | 87:085cde657901 | 314 | /* Compute the i2sdiv prescaler */ |
mbed_official | 87:085cde657901 | 315 | i2sdiv = (uint32_t)((tmp - i2sodd) / 2); |
mbed_official | 87:085cde657901 | 316 | |
mbed_official | 87:085cde657901 | 317 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
mbed_official | 87:085cde657901 | 318 | i2sodd = (uint32_t) (i2sodd << 8); |
mbed_official | 87:085cde657901 | 319 | } |
mbed_official | 87:085cde657901 | 320 | |
mbed_official | 87:085cde657901 | 321 | /* Test if the divider is 1 or 0 or greater than 0xFF */ |
mbed_official | 87:085cde657901 | 322 | if((i2sdiv < 2) || (i2sdiv > 0xFF)) |
mbed_official | 87:085cde657901 | 323 | { |
mbed_official | 87:085cde657901 | 324 | /* Set the default values */ |
mbed_official | 87:085cde657901 | 325 | i2sdiv = 2; |
mbed_official | 87:085cde657901 | 326 | i2sodd = 0; |
mbed_official | 87:085cde657901 | 327 | } |
mbed_official | 87:085cde657901 | 328 | |
mbed_official | 87:085cde657901 | 329 | /* Write to SPIx I2SPR register the computed value */ |
mbed_official | 87:085cde657901 | 330 | hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); |
mbed_official | 87:085cde657901 | 331 | |
mbed_official | 87:085cde657901 | 332 | /* Configure the I2S with the I2S_InitStruct values */ |
mbed_official | 87:085cde657901 | 333 | tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); |
mbed_official | 87:085cde657901 | 334 | |
mbed_official | 87:085cde657901 | 335 | /* Write to SPIx I2SCFGR */ |
mbed_official | 87:085cde657901 | 336 | hi2s->Instance->I2SCFGR = tmpreg; |
mbed_official | 87:085cde657901 | 337 | |
mbed_official | 87:085cde657901 | 338 | /* Configure the I2S extended if the full duplex mode is enabled */ |
mbed_official | 87:085cde657901 | 339 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 340 | { |
mbed_official | 87:085cde657901 | 341 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
mbed_official | 87:085cde657901 | 342 | I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
mbed_official | 87:085cde657901 | 343 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
mbed_official | 87:085cde657901 | 344 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); |
mbed_official | 87:085cde657901 | 345 | I2SxEXT(hi2s->Instance)->I2SPR = 2; |
mbed_official | 87:085cde657901 | 346 | |
mbed_official | 87:085cde657901 | 347 | /* Get the I2SCFGR register value */ |
mbed_official | 87:085cde657901 | 348 | tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; |
mbed_official | 87:085cde657901 | 349 | |
mbed_official | 87:085cde657901 | 350 | /* Get the mode to be configured for the extended I2S */ |
mbed_official | 87:085cde657901 | 351 | if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) |
mbed_official | 87:085cde657901 | 352 | { |
mbed_official | 87:085cde657901 | 353 | tmp = I2S_MODE_SLAVE_RX; |
mbed_official | 87:085cde657901 | 354 | } |
mbed_official | 87:085cde657901 | 355 | else |
mbed_official | 87:085cde657901 | 356 | { |
mbed_official | 87:085cde657901 | 357 | if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) |
mbed_official | 87:085cde657901 | 358 | { |
mbed_official | 87:085cde657901 | 359 | tmp = I2S_MODE_SLAVE_TX; |
mbed_official | 87:085cde657901 | 360 | } |
mbed_official | 87:085cde657901 | 361 | } |
mbed_official | 87:085cde657901 | 362 | |
mbed_official | 87:085cde657901 | 363 | /* Configure the I2S Slave with the I2S Master parameter values */ |
mbed_official | 87:085cde657901 | 364 | tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); |
mbed_official | 87:085cde657901 | 365 | |
mbed_official | 87:085cde657901 | 366 | /* Write to SPIx I2SCFGR */ |
mbed_official | 87:085cde657901 | 367 | I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg; |
mbed_official | 87:085cde657901 | 368 | } |
mbed_official | 87:085cde657901 | 369 | |
mbed_official | 87:085cde657901 | 370 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
mbed_official | 87:085cde657901 | 371 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 372 | |
mbed_official | 87:085cde657901 | 373 | return HAL_OK; |
mbed_official | 87:085cde657901 | 374 | } |
mbed_official | 87:085cde657901 | 375 | |
mbed_official | 87:085cde657901 | 376 | /** |
mbed_official | 87:085cde657901 | 377 | * @brief DeInitializes the I2S peripheral |
mbed_official | 87:085cde657901 | 378 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 379 | * @retval HAL status |
mbed_official | 87:085cde657901 | 380 | */ |
mbed_official | 87:085cde657901 | 381 | HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 382 | { |
mbed_official | 87:085cde657901 | 383 | /* Check the I2S handle allocation */ |
mbed_official | 87:085cde657901 | 384 | if(hi2s == NULL) |
mbed_official | 87:085cde657901 | 385 | { |
mbed_official | 87:085cde657901 | 386 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 387 | } |
mbed_official | 87:085cde657901 | 388 | |
mbed_official | 87:085cde657901 | 389 | hi2s->State = HAL_I2S_STATE_BUSY; |
mbed_official | 87:085cde657901 | 390 | |
mbed_official | 87:085cde657901 | 391 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
mbed_official | 87:085cde657901 | 392 | HAL_I2S_MspDeInit(hi2s); |
mbed_official | 87:085cde657901 | 393 | |
mbed_official | 87:085cde657901 | 394 | hi2s->State = HAL_I2S_STATE_RESET; |
mbed_official | 106:ced8cbb51063 | 395 | |
mbed_official | 106:ced8cbb51063 | 396 | /* Release Lock */ |
mbed_official | 106:ced8cbb51063 | 397 | __HAL_UNLOCK(hi2s); |
mbed_official | 106:ced8cbb51063 | 398 | |
mbed_official | 87:085cde657901 | 399 | return HAL_OK; |
mbed_official | 87:085cde657901 | 400 | } |
mbed_official | 87:085cde657901 | 401 | |
mbed_official | 87:085cde657901 | 402 | /** |
mbed_official | 87:085cde657901 | 403 | * @brief I2S MSP Init |
mbed_official | 87:085cde657901 | 404 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 405 | * @retval None |
mbed_official | 87:085cde657901 | 406 | */ |
mbed_official | 87:085cde657901 | 407 | __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 408 | { |
mbed_official | 87:085cde657901 | 409 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 410 | the HAL_I2S_MspInit could be implenetd in the user file |
mbed_official | 87:085cde657901 | 411 | */ |
mbed_official | 87:085cde657901 | 412 | } |
mbed_official | 87:085cde657901 | 413 | |
mbed_official | 87:085cde657901 | 414 | /** |
mbed_official | 87:085cde657901 | 415 | * @brief I2S MSP DeInit |
mbed_official | 87:085cde657901 | 416 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 417 | * @retval None |
mbed_official | 87:085cde657901 | 418 | */ |
mbed_official | 87:085cde657901 | 419 | __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 420 | { |
mbed_official | 87:085cde657901 | 421 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 422 | the HAL_I2S_MspDeInit could be implenetd in the user file |
mbed_official | 87:085cde657901 | 423 | */ |
mbed_official | 87:085cde657901 | 424 | } |
mbed_official | 87:085cde657901 | 425 | |
mbed_official | 87:085cde657901 | 426 | /** |
mbed_official | 87:085cde657901 | 427 | * @} |
mbed_official | 87:085cde657901 | 428 | */ |
mbed_official | 87:085cde657901 | 429 | |
mbed_official | 87:085cde657901 | 430 | /** @defgroup I2S_Group2 IO operation functions |
mbed_official | 87:085cde657901 | 431 | * @brief Data transfers functions |
mbed_official | 87:085cde657901 | 432 | * |
mbed_official | 87:085cde657901 | 433 | @verbatim |
mbed_official | 87:085cde657901 | 434 | =============================================================================== |
mbed_official | 87:085cde657901 | 435 | ##### IO operation functions ##### |
mbed_official | 87:085cde657901 | 436 | =============================================================================== |
mbed_official | 87:085cde657901 | 437 | [..] |
mbed_official | 87:085cde657901 | 438 | This subsection provides a set of functions allowing to manage the I2S data |
mbed_official | 87:085cde657901 | 439 | transfers. |
mbed_official | 87:085cde657901 | 440 | |
mbed_official | 87:085cde657901 | 441 | (#) There is two mode of transfer: |
mbed_official | 87:085cde657901 | 442 | (++) Blocking mode : The communication is performed in the polling mode. |
mbed_official | 87:085cde657901 | 443 | The status of all data processing is returned by the same function |
mbed_official | 87:085cde657901 | 444 | after finishing transfer. |
mbed_official | 87:085cde657901 | 445 | (++) No-Blocking mode : The communication is performed using Interrupts |
mbed_official | 87:085cde657901 | 446 | or DMA. These functions return the status of the transfer startup. |
mbed_official | 87:085cde657901 | 447 | The end of the data processing will be indicated through the |
mbed_official | 87:085cde657901 | 448 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
mbed_official | 87:085cde657901 | 449 | using DMA mode. |
mbed_official | 87:085cde657901 | 450 | |
mbed_official | 87:085cde657901 | 451 | (#) Blocking mode functions are : |
mbed_official | 87:085cde657901 | 452 | (++) HAL_I2S_Transmit() |
mbed_official | 87:085cde657901 | 453 | (++) HAL_I2S_Receive() |
mbed_official | 87:085cde657901 | 454 | |
mbed_official | 87:085cde657901 | 455 | (#) No-Blocking mode functions with Interrupt are : |
mbed_official | 87:085cde657901 | 456 | (++) HAL_I2S_Transmit_IT() |
mbed_official | 87:085cde657901 | 457 | (++) HAL_I2S_Receive_IT() |
mbed_official | 87:085cde657901 | 458 | |
mbed_official | 87:085cde657901 | 459 | (#) No-Blocking mode functions with DMA are : |
mbed_official | 87:085cde657901 | 460 | (++) HAL_I2S_Transmit_DMA() |
mbed_official | 87:085cde657901 | 461 | (++) HAL_I2S_Receive_DMA() |
mbed_official | 87:085cde657901 | 462 | |
mbed_official | 87:085cde657901 | 463 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
mbed_official | 87:085cde657901 | 464 | (++) HAL_I2S_TxCpltCallback() |
mbed_official | 87:085cde657901 | 465 | (++) HAL_I2S_RxCpltCallback() |
mbed_official | 87:085cde657901 | 466 | (++) HAL_I2S_ErrorCallback() |
mbed_official | 87:085cde657901 | 467 | |
mbed_official | 87:085cde657901 | 468 | @endverbatim |
mbed_official | 87:085cde657901 | 469 | * @{ |
mbed_official | 87:085cde657901 | 470 | */ |
mbed_official | 87:085cde657901 | 471 | |
mbed_official | 87:085cde657901 | 472 | /** |
mbed_official | 87:085cde657901 | 473 | * @brief Transmit an amount of data in blocking mode |
mbed_official | 87:085cde657901 | 474 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 475 | * @param pData: a 16-bit pointer to data buffer. |
mbed_official | 87:085cde657901 | 476 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 477 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 478 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 479 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 480 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 481 | * @param Timeout: Timeout duration |
mbed_official | 87:085cde657901 | 482 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 483 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 484 | * @retval HAL status |
mbed_official | 87:085cde657901 | 485 | */ |
mbed_official | 87:085cde657901 | 486 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
mbed_official | 87:085cde657901 | 487 | { |
mbed_official | 87:085cde657901 | 488 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 489 | if((pData == NULL ) || (Size == 0)) |
mbed_official | 87:085cde657901 | 490 | { |
mbed_official | 87:085cde657901 | 491 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 492 | } |
mbed_official | 87:085cde657901 | 493 | |
mbed_official | 87:085cde657901 | 494 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 495 | { |
mbed_official | 87:085cde657901 | 496 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 497 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 498 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
mbed_official | 87:085cde657901 | 499 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 500 | { |
mbed_official | 87:085cde657901 | 501 | hi2s->TxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 502 | hi2s->TxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 503 | } |
mbed_official | 87:085cde657901 | 504 | else |
mbed_official | 87:085cde657901 | 505 | { |
mbed_official | 87:085cde657901 | 506 | hi2s->TxXferSize = Size; |
mbed_official | 87:085cde657901 | 507 | hi2s->TxXferCount = Size; |
mbed_official | 87:085cde657901 | 508 | } |
mbed_official | 87:085cde657901 | 509 | |
mbed_official | 87:085cde657901 | 510 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 511 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 512 | |
mbed_official | 87:085cde657901 | 513 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
mbed_official | 87:085cde657901 | 514 | |
mbed_official | 87:085cde657901 | 515 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 516 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 517 | { |
mbed_official | 87:085cde657901 | 518 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 519 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 520 | } |
mbed_official | 87:085cde657901 | 521 | |
mbed_official | 87:085cde657901 | 522 | while(hi2s->TxXferCount > 0) |
mbed_official | 87:085cde657901 | 523 | { |
mbed_official | 87:085cde657901 | 524 | hi2s->Instance->DR = (*pData++); |
mbed_official | 87:085cde657901 | 525 | hi2s->TxXferCount--; |
mbed_official | 87:085cde657901 | 526 | /* Wait until TXE flag is set */ |
mbed_official | 87:085cde657901 | 527 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) |
mbed_official | 87:085cde657901 | 528 | { |
mbed_official | 87:085cde657901 | 529 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 530 | } |
mbed_official | 87:085cde657901 | 531 | } |
mbed_official | 87:085cde657901 | 532 | /* Wait until Busy flag is reset */ |
mbed_official | 87:085cde657901 | 533 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) |
mbed_official | 87:085cde657901 | 534 | { |
mbed_official | 87:085cde657901 | 535 | return HAL_TIMEOUT; |
mbed_official | 106:ced8cbb51063 | 536 | } |
mbed_official | 87:085cde657901 | 537 | |
mbed_official | 87:085cde657901 | 538 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 539 | |
mbed_official | 87:085cde657901 | 540 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 541 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 542 | |
mbed_official | 87:085cde657901 | 543 | return HAL_OK; |
mbed_official | 87:085cde657901 | 544 | } |
mbed_official | 87:085cde657901 | 545 | else |
mbed_official | 87:085cde657901 | 546 | { |
mbed_official | 87:085cde657901 | 547 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 548 | } |
mbed_official | 87:085cde657901 | 549 | } |
mbed_official | 87:085cde657901 | 550 | |
mbed_official | 87:085cde657901 | 551 | /** |
mbed_official | 87:085cde657901 | 552 | * @brief Receive an amount of data in blocking mode |
mbed_official | 87:085cde657901 | 553 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 554 | * @param pData: a 16-bit pointer to data buffer. |
mbed_official | 87:085cde657901 | 555 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 556 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 557 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 558 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 559 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 560 | * @param Timeout: Timeout duration |
mbed_official | 87:085cde657901 | 561 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 562 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 563 | * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate |
mbed_official | 87:085cde657901 | 564 | * in continouse way and as the I2S is not disabled at the end of the I2S transaction. |
mbed_official | 87:085cde657901 | 565 | * @retval HAL status |
mbed_official | 87:085cde657901 | 566 | */ |
mbed_official | 87:085cde657901 | 567 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
mbed_official | 87:085cde657901 | 568 | { |
mbed_official | 87:085cde657901 | 569 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 570 | if((pData == NULL ) || (Size == 0)) |
mbed_official | 87:085cde657901 | 571 | { |
mbed_official | 87:085cde657901 | 572 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 573 | } |
mbed_official | 87:085cde657901 | 574 | |
mbed_official | 87:085cde657901 | 575 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 576 | { |
mbed_official | 87:085cde657901 | 577 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 578 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 579 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
mbed_official | 87:085cde657901 | 580 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 581 | { |
mbed_official | 87:085cde657901 | 582 | hi2s->RxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 583 | hi2s->RxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 584 | } |
mbed_official | 87:085cde657901 | 585 | else |
mbed_official | 87:085cde657901 | 586 | { |
mbed_official | 87:085cde657901 | 587 | hi2s->RxXferSize = Size; |
mbed_official | 87:085cde657901 | 588 | hi2s->RxXferCount = Size; |
mbed_official | 87:085cde657901 | 589 | } |
mbed_official | 87:085cde657901 | 590 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 591 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 592 | |
mbed_official | 87:085cde657901 | 593 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
mbed_official | 87:085cde657901 | 594 | |
mbed_official | 87:085cde657901 | 595 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 596 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 597 | { |
mbed_official | 87:085cde657901 | 598 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 599 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 600 | } |
mbed_official | 87:085cde657901 | 601 | |
mbed_official | 87:085cde657901 | 602 | /* Check if Master Receiver mode is selected */ |
mbed_official | 87:085cde657901 | 603 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
mbed_official | 87:085cde657901 | 604 | { |
mbed_official | 87:085cde657901 | 605 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
mbed_official | 87:085cde657901 | 606 | access to the SPI_SR register. */ |
mbed_official | 87:085cde657901 | 607 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 608 | } |
mbed_official | 87:085cde657901 | 609 | |
mbed_official | 87:085cde657901 | 610 | /* Receive data */ |
mbed_official | 87:085cde657901 | 611 | while(hi2s->RxXferCount > 0) |
mbed_official | 87:085cde657901 | 612 | { |
mbed_official | 87:085cde657901 | 613 | /* Wait until RXNE flag is set */ |
mbed_official | 87:085cde657901 | 614 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) |
mbed_official | 87:085cde657901 | 615 | { |
mbed_official | 87:085cde657901 | 616 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 617 | } |
mbed_official | 87:085cde657901 | 618 | |
mbed_official | 87:085cde657901 | 619 | (*pData++) = hi2s->Instance->DR; |
mbed_official | 87:085cde657901 | 620 | hi2s->RxXferCount--; |
mbed_official | 87:085cde657901 | 621 | } |
mbed_official | 87:085cde657901 | 622 | |
mbed_official | 87:085cde657901 | 623 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 624 | |
mbed_official | 87:085cde657901 | 625 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 626 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 627 | |
mbed_official | 87:085cde657901 | 628 | return HAL_OK; |
mbed_official | 87:085cde657901 | 629 | } |
mbed_official | 87:085cde657901 | 630 | else |
mbed_official | 87:085cde657901 | 631 | { |
mbed_official | 87:085cde657901 | 632 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 633 | } |
mbed_official | 87:085cde657901 | 634 | } |
mbed_official | 87:085cde657901 | 635 | |
mbed_official | 87:085cde657901 | 636 | /** |
mbed_official | 87:085cde657901 | 637 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
mbed_official | 87:085cde657901 | 638 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 639 | * @param pData: a 16-bit pointer to data buffer. |
mbed_official | 87:085cde657901 | 640 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 641 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 642 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 643 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 644 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 645 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 646 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 647 | * @retval HAL status |
mbed_official | 87:085cde657901 | 648 | */ |
mbed_official | 87:085cde657901 | 649 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
mbed_official | 87:085cde657901 | 650 | { |
mbed_official | 87:085cde657901 | 651 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 652 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 653 | { |
mbed_official | 87:085cde657901 | 654 | if((pData == NULL) || (Size == 0)) |
mbed_official | 87:085cde657901 | 655 | { |
mbed_official | 87:085cde657901 | 656 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 657 | } |
mbed_official | 87:085cde657901 | 658 | |
mbed_official | 87:085cde657901 | 659 | hi2s->pTxBuffPtr = pData; |
mbed_official | 87:085cde657901 | 660 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 661 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 662 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
mbed_official | 87:085cde657901 | 663 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 664 | { |
mbed_official | 87:085cde657901 | 665 | hi2s->TxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 666 | hi2s->TxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 667 | } |
mbed_official | 87:085cde657901 | 668 | else |
mbed_official | 87:085cde657901 | 669 | { |
mbed_official | 87:085cde657901 | 670 | hi2s->TxXferSize = Size; |
mbed_official | 87:085cde657901 | 671 | hi2s->TxXferCount = Size; |
mbed_official | 87:085cde657901 | 672 | } |
mbed_official | 87:085cde657901 | 673 | |
mbed_official | 87:085cde657901 | 674 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 675 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 676 | |
mbed_official | 87:085cde657901 | 677 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
mbed_official | 87:085cde657901 | 678 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
mbed_official | 87:085cde657901 | 679 | |
mbed_official | 87:085cde657901 | 680 | /* Enable TXE and ERR interrupt */ |
mbed_official | 87:085cde657901 | 681 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
mbed_official | 87:085cde657901 | 682 | |
mbed_official | 87:085cde657901 | 683 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 684 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 685 | { |
mbed_official | 87:085cde657901 | 686 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 687 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 688 | } |
mbed_official | 87:085cde657901 | 689 | |
mbed_official | 87:085cde657901 | 690 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 691 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 692 | |
mbed_official | 87:085cde657901 | 693 | return HAL_OK; |
mbed_official | 87:085cde657901 | 694 | } |
mbed_official | 87:085cde657901 | 695 | else |
mbed_official | 87:085cde657901 | 696 | { |
mbed_official | 87:085cde657901 | 697 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 698 | } |
mbed_official | 87:085cde657901 | 699 | } |
mbed_official | 87:085cde657901 | 700 | |
mbed_official | 87:085cde657901 | 701 | /** |
mbed_official | 87:085cde657901 | 702 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
mbed_official | 87:085cde657901 | 703 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 704 | * @param pData: a 16-bit pointer to the Receive data buffer. |
mbed_official | 87:085cde657901 | 705 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 706 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 707 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 708 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 709 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 710 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 711 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 712 | * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation |
mbed_official | 87:085cde657901 | 713 | * between Master and Slave otherwise the I2S interrupt should be optimized. |
mbed_official | 87:085cde657901 | 714 | * @retval HAL status |
mbed_official | 87:085cde657901 | 715 | */ |
mbed_official | 87:085cde657901 | 716 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
mbed_official | 87:085cde657901 | 717 | { |
mbed_official | 87:085cde657901 | 718 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 719 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 720 | { |
mbed_official | 87:085cde657901 | 721 | if((pData == NULL) || (Size == 0)) |
mbed_official | 87:085cde657901 | 722 | { |
mbed_official | 87:085cde657901 | 723 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 724 | } |
mbed_official | 87:085cde657901 | 725 | |
mbed_official | 87:085cde657901 | 726 | hi2s->pRxBuffPtr = pData; |
mbed_official | 87:085cde657901 | 727 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 728 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 729 | if((tmp1 == I2S_DATAFORMAT_24B)||\ |
mbed_official | 87:085cde657901 | 730 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 731 | { |
mbed_official | 87:085cde657901 | 732 | hi2s->RxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 733 | hi2s->RxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 734 | } |
mbed_official | 87:085cde657901 | 735 | else |
mbed_official | 87:085cde657901 | 736 | { |
mbed_official | 87:085cde657901 | 737 | hi2s->RxXferSize = Size; |
mbed_official | 87:085cde657901 | 738 | hi2s->RxXferCount = Size; |
mbed_official | 87:085cde657901 | 739 | } |
mbed_official | 87:085cde657901 | 740 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 741 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 742 | |
mbed_official | 87:085cde657901 | 743 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
mbed_official | 87:085cde657901 | 744 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
mbed_official | 87:085cde657901 | 745 | |
mbed_official | 87:085cde657901 | 746 | /* Enable TXE and ERR interrupt */ |
mbed_official | 87:085cde657901 | 747 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
mbed_official | 87:085cde657901 | 748 | |
mbed_official | 87:085cde657901 | 749 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 750 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 751 | { |
mbed_official | 87:085cde657901 | 752 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 753 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 754 | } |
mbed_official | 87:085cde657901 | 755 | |
mbed_official | 87:085cde657901 | 756 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 757 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 758 | |
mbed_official | 87:085cde657901 | 759 | return HAL_OK; |
mbed_official | 87:085cde657901 | 760 | } |
mbed_official | 87:085cde657901 | 761 | |
mbed_official | 87:085cde657901 | 762 | else |
mbed_official | 87:085cde657901 | 763 | { |
mbed_official | 87:085cde657901 | 764 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 765 | } |
mbed_official | 87:085cde657901 | 766 | } |
mbed_official | 87:085cde657901 | 767 | |
mbed_official | 87:085cde657901 | 768 | /** |
mbed_official | 87:085cde657901 | 769 | * @brief Transmit an amount of data in non-blocking mode with DMA |
mbed_official | 87:085cde657901 | 770 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 771 | * @param pData: a 16-bit pointer to the Transmit data buffer. |
mbed_official | 87:085cde657901 | 772 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 773 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 774 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 775 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 776 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 777 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 778 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 779 | * @retval HAL status |
mbed_official | 87:085cde657901 | 780 | */ |
mbed_official | 87:085cde657901 | 781 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
mbed_official | 87:085cde657901 | 782 | { |
mbed_official | 87:085cde657901 | 783 | uint32_t *tmp; |
mbed_official | 87:085cde657901 | 784 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 785 | |
mbed_official | 87:085cde657901 | 786 | if((pData == NULL) || (Size == 0)) |
mbed_official | 87:085cde657901 | 787 | { |
mbed_official | 87:085cde657901 | 788 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 789 | } |
mbed_official | 87:085cde657901 | 790 | |
mbed_official | 87:085cde657901 | 791 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 792 | { |
mbed_official | 87:085cde657901 | 793 | hi2s->pTxBuffPtr = pData; |
mbed_official | 87:085cde657901 | 794 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 795 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 796 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
mbed_official | 87:085cde657901 | 797 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 798 | { |
mbed_official | 87:085cde657901 | 799 | hi2s->TxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 800 | hi2s->TxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 801 | } |
mbed_official | 87:085cde657901 | 802 | else |
mbed_official | 87:085cde657901 | 803 | { |
mbed_official | 87:085cde657901 | 804 | hi2s->TxXferSize = Size; |
mbed_official | 87:085cde657901 | 805 | hi2s->TxXferCount = Size; |
mbed_official | 87:085cde657901 | 806 | } |
mbed_official | 87:085cde657901 | 807 | |
mbed_official | 87:085cde657901 | 808 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 809 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 810 | |
mbed_official | 87:085cde657901 | 811 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
mbed_official | 87:085cde657901 | 812 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
mbed_official | 87:085cde657901 | 813 | |
mbed_official | 87:085cde657901 | 814 | /* Set the I2S Tx DMA Half transfert complete callback */ |
mbed_official | 87:085cde657901 | 815 | hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; |
mbed_official | 87:085cde657901 | 816 | |
mbed_official | 87:085cde657901 | 817 | /* Set the I2S Tx DMA transfert complete callback */ |
mbed_official | 87:085cde657901 | 818 | hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; |
mbed_official | 87:085cde657901 | 819 | |
mbed_official | 87:085cde657901 | 820 | /* Set the DMA error callback */ |
mbed_official | 87:085cde657901 | 821 | hi2s->hdmatx->XferErrorCallback = I2S_DMAError; |
mbed_official | 87:085cde657901 | 822 | |
mbed_official | 87:085cde657901 | 823 | /* Enable the Tx DMA Stream */ |
mbed_official | 87:085cde657901 | 824 | tmp = (uint32_t*)&pData; |
mbed_official | 87:085cde657901 | 825 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); |
mbed_official | 87:085cde657901 | 826 | |
mbed_official | 87:085cde657901 | 827 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 828 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 829 | { |
mbed_official | 87:085cde657901 | 830 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 831 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 832 | } |
mbed_official | 87:085cde657901 | 833 | |
mbed_official | 87:085cde657901 | 834 | /* Check if the I2S Tx request is already enabled */ |
mbed_official | 87:085cde657901 | 835 | if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) |
mbed_official | 87:085cde657901 | 836 | { |
mbed_official | 87:085cde657901 | 837 | /* Enable Tx DMA Request */ |
mbed_official | 87:085cde657901 | 838 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
mbed_official | 87:085cde657901 | 839 | } |
mbed_official | 87:085cde657901 | 840 | |
mbed_official | 87:085cde657901 | 841 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 842 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 843 | |
mbed_official | 87:085cde657901 | 844 | return HAL_OK; |
mbed_official | 87:085cde657901 | 845 | } |
mbed_official | 87:085cde657901 | 846 | else |
mbed_official | 87:085cde657901 | 847 | { |
mbed_official | 87:085cde657901 | 848 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 849 | } |
mbed_official | 87:085cde657901 | 850 | } |
mbed_official | 87:085cde657901 | 851 | |
mbed_official | 87:085cde657901 | 852 | /** |
mbed_official | 87:085cde657901 | 853 | * @brief Receive an amount of data in non-blocking mode with DMA |
mbed_official | 87:085cde657901 | 854 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 855 | * @param pData: a 16-bit pointer to the Receive data buffer. |
mbed_official | 87:085cde657901 | 856 | * @param Size: number of data sample to be sent: |
mbed_official | 87:085cde657901 | 857 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
mbed_official | 87:085cde657901 | 858 | * configuration phase, the Size parameter means the number of 16-bit data length |
mbed_official | 87:085cde657901 | 859 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
mbed_official | 87:085cde657901 | 860 | * the Size parameter means the number of 16-bit data length. |
mbed_official | 87:085cde657901 | 861 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
mbed_official | 87:085cde657901 | 862 | * between Master and Slave(example: audio streaming). |
mbed_official | 87:085cde657901 | 863 | * @retval HAL status |
mbed_official | 87:085cde657901 | 864 | */ |
mbed_official | 87:085cde657901 | 865 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
mbed_official | 87:085cde657901 | 866 | { |
mbed_official | 87:085cde657901 | 867 | uint32_t *tmp; |
mbed_official | 87:085cde657901 | 868 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 869 | |
mbed_official | 87:085cde657901 | 870 | if((pData == NULL) || (Size == 0)) |
mbed_official | 87:085cde657901 | 871 | { |
mbed_official | 87:085cde657901 | 872 | return HAL_ERROR; |
mbed_official | 87:085cde657901 | 873 | } |
mbed_official | 87:085cde657901 | 874 | |
mbed_official | 87:085cde657901 | 875 | if(hi2s->State == HAL_I2S_STATE_READY) |
mbed_official | 87:085cde657901 | 876 | { |
mbed_official | 87:085cde657901 | 877 | hi2s->pRxBuffPtr = pData; |
mbed_official | 87:085cde657901 | 878 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 879 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
mbed_official | 87:085cde657901 | 880 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
mbed_official | 87:085cde657901 | 881 | (tmp2 == I2S_DATAFORMAT_32B)) |
mbed_official | 87:085cde657901 | 882 | { |
mbed_official | 87:085cde657901 | 883 | hi2s->RxXferSize = Size*2; |
mbed_official | 87:085cde657901 | 884 | hi2s->RxXferCount = Size*2; |
mbed_official | 87:085cde657901 | 885 | } |
mbed_official | 87:085cde657901 | 886 | else |
mbed_official | 87:085cde657901 | 887 | { |
mbed_official | 87:085cde657901 | 888 | hi2s->RxXferSize = Size; |
mbed_official | 87:085cde657901 | 889 | hi2s->RxXferCount = Size; |
mbed_official | 87:085cde657901 | 890 | } |
mbed_official | 87:085cde657901 | 891 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 892 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 893 | |
mbed_official | 87:085cde657901 | 894 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
mbed_official | 87:085cde657901 | 895 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
mbed_official | 87:085cde657901 | 896 | |
mbed_official | 87:085cde657901 | 897 | /* Set the I2S Rx DMA Half transfert complete callback */ |
mbed_official | 87:085cde657901 | 898 | hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; |
mbed_official | 87:085cde657901 | 899 | |
mbed_official | 87:085cde657901 | 900 | /* Set the I2S Rx DMA transfert complete callback */ |
mbed_official | 87:085cde657901 | 901 | hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; |
mbed_official | 87:085cde657901 | 902 | |
mbed_official | 87:085cde657901 | 903 | /* Set the DMA error callback */ |
mbed_official | 87:085cde657901 | 904 | hi2s->hdmarx->XferErrorCallback = I2S_DMAError; |
mbed_official | 87:085cde657901 | 905 | |
mbed_official | 87:085cde657901 | 906 | /* Check if Master Receiver mode is selected */ |
mbed_official | 87:085cde657901 | 907 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
mbed_official | 87:085cde657901 | 908 | { |
mbed_official | 87:085cde657901 | 909 | /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read |
mbed_official | 87:085cde657901 | 910 | access to the SPI_SR register. */ |
mbed_official | 87:085cde657901 | 911 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 912 | } |
mbed_official | 87:085cde657901 | 913 | |
mbed_official | 87:085cde657901 | 914 | /* Enable the Rx DMA Stream */ |
mbed_official | 87:085cde657901 | 915 | tmp = (uint32_t*)&pData; |
mbed_official | 87:085cde657901 | 916 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
mbed_official | 87:085cde657901 | 917 | |
mbed_official | 87:085cde657901 | 918 | /* Check if the I2S is already enabled */ |
mbed_official | 87:085cde657901 | 919 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
mbed_official | 87:085cde657901 | 920 | { |
mbed_official | 87:085cde657901 | 921 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 922 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 923 | } |
mbed_official | 87:085cde657901 | 924 | |
mbed_official | 87:085cde657901 | 925 | /* Check if the I2S Rx request is already enabled */ |
mbed_official | 87:085cde657901 | 926 | if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) |
mbed_official | 87:085cde657901 | 927 | { |
mbed_official | 87:085cde657901 | 928 | /* Enable Rx DMA Request */ |
mbed_official | 87:085cde657901 | 929 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
mbed_official | 87:085cde657901 | 930 | } |
mbed_official | 87:085cde657901 | 931 | |
mbed_official | 87:085cde657901 | 932 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 933 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 934 | |
mbed_official | 87:085cde657901 | 935 | return HAL_OK; |
mbed_official | 87:085cde657901 | 936 | } |
mbed_official | 87:085cde657901 | 937 | else |
mbed_official | 87:085cde657901 | 938 | { |
mbed_official | 87:085cde657901 | 939 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 940 | } |
mbed_official | 87:085cde657901 | 941 | } |
mbed_official | 87:085cde657901 | 942 | |
mbed_official | 87:085cde657901 | 943 | /** |
mbed_official | 87:085cde657901 | 944 | * @brief Pauses the audio stream playing from the Media. |
mbed_official | 87:085cde657901 | 945 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 946 | * @retval None |
mbed_official | 87:085cde657901 | 947 | */ |
mbed_official | 87:085cde657901 | 948 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 949 | { |
mbed_official | 87:085cde657901 | 950 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 951 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 952 | |
mbed_official | 87:085cde657901 | 953 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
mbed_official | 87:085cde657901 | 954 | { |
mbed_official | 87:085cde657901 | 955 | /* Disable the I2S DMA Tx request */ |
mbed_official | 87:085cde657901 | 956 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 957 | } |
mbed_official | 87:085cde657901 | 958 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
mbed_official | 87:085cde657901 | 959 | { |
mbed_official | 87:085cde657901 | 960 | /* Disable the I2S DMA Rx request */ |
mbed_official | 87:085cde657901 | 961 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 962 | } |
mbed_official | 87:085cde657901 | 963 | else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
mbed_official | 87:085cde657901 | 964 | { |
mbed_official | 87:085cde657901 | 965 | if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) |
mbed_official | 87:085cde657901 | 966 | { |
mbed_official | 87:085cde657901 | 967 | /* Disable the I2S DMA Tx request */ |
mbed_official | 87:085cde657901 | 968 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 969 | /* Disable the I2SEx Rx DMA Request */ |
mbed_official | 87:085cde657901 | 970 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 971 | } |
mbed_official | 87:085cde657901 | 972 | else |
mbed_official | 87:085cde657901 | 973 | { |
mbed_official | 87:085cde657901 | 974 | /* Disable the I2S DMA Rx request */ |
mbed_official | 87:085cde657901 | 975 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 976 | /* Disable the I2SEx Tx DMA Request */ |
mbed_official | 87:085cde657901 | 977 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 978 | } |
mbed_official | 87:085cde657901 | 979 | } |
mbed_official | 87:085cde657901 | 980 | |
mbed_official | 87:085cde657901 | 981 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 982 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 983 | |
mbed_official | 87:085cde657901 | 984 | return HAL_OK; |
mbed_official | 87:085cde657901 | 985 | } |
mbed_official | 87:085cde657901 | 986 | |
mbed_official | 87:085cde657901 | 987 | /** |
mbed_official | 87:085cde657901 | 988 | * @brief Resumes the audio stream playing from the Media. |
mbed_official | 87:085cde657901 | 989 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 990 | * @retval None |
mbed_official | 87:085cde657901 | 991 | */ |
mbed_official | 87:085cde657901 | 992 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 993 | { |
mbed_official | 87:085cde657901 | 994 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 995 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 996 | |
mbed_official | 87:085cde657901 | 997 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
mbed_official | 87:085cde657901 | 998 | { |
mbed_official | 87:085cde657901 | 999 | /* Enable the I2S DMA Tx request */ |
mbed_official | 87:085cde657901 | 1000 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
mbed_official | 87:085cde657901 | 1001 | } |
mbed_official | 87:085cde657901 | 1002 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
mbed_official | 87:085cde657901 | 1003 | { |
mbed_official | 87:085cde657901 | 1004 | /* Enable the I2S DMA Rx request */ |
mbed_official | 87:085cde657901 | 1005 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
mbed_official | 87:085cde657901 | 1006 | } |
mbed_official | 87:085cde657901 | 1007 | else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
mbed_official | 87:085cde657901 | 1008 | { |
mbed_official | 87:085cde657901 | 1009 | if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) |
mbed_official | 87:085cde657901 | 1010 | { |
mbed_official | 87:085cde657901 | 1011 | /* Enable the I2S DMA Tx request */ |
mbed_official | 87:085cde657901 | 1012 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
mbed_official | 87:085cde657901 | 1013 | /* Disable the I2SEx Rx DMA Request */ |
mbed_official | 87:085cde657901 | 1014 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN; |
mbed_official | 87:085cde657901 | 1015 | } |
mbed_official | 87:085cde657901 | 1016 | else |
mbed_official | 87:085cde657901 | 1017 | { |
mbed_official | 87:085cde657901 | 1018 | /* Enable the I2S DMA Rx request */ |
mbed_official | 87:085cde657901 | 1019 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
mbed_official | 87:085cde657901 | 1020 | /* Enable the I2SEx Tx DMA Request */ |
mbed_official | 87:085cde657901 | 1021 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN; |
mbed_official | 87:085cde657901 | 1022 | } |
mbed_official | 87:085cde657901 | 1023 | } |
mbed_official | 87:085cde657901 | 1024 | |
mbed_official | 87:085cde657901 | 1025 | /* If the I2S peripheral is still not enabled, enable it */ |
mbed_official | 87:085cde657901 | 1026 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) |
mbed_official | 87:085cde657901 | 1027 | { |
mbed_official | 87:085cde657901 | 1028 | /* Enable I2S peripheral */ |
mbed_official | 87:085cde657901 | 1029 | __HAL_I2S_ENABLE(hi2s); |
mbed_official | 87:085cde657901 | 1030 | } |
mbed_official | 87:085cde657901 | 1031 | |
mbed_official | 87:085cde657901 | 1032 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1033 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1034 | |
mbed_official | 87:085cde657901 | 1035 | return HAL_OK; |
mbed_official | 87:085cde657901 | 1036 | } |
mbed_official | 87:085cde657901 | 1037 | |
mbed_official | 87:085cde657901 | 1038 | /** |
mbed_official | 87:085cde657901 | 1039 | * @brief Resumes the audio stream playing from the Media. |
mbed_official | 87:085cde657901 | 1040 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1041 | * @retval None |
mbed_official | 87:085cde657901 | 1042 | */ |
mbed_official | 87:085cde657901 | 1043 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1044 | { |
mbed_official | 87:085cde657901 | 1045 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 1046 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 1047 | |
mbed_official | 87:085cde657901 | 1048 | /* Disable the I2S Tx/Rx DMA requests */ |
mbed_official | 87:085cde657901 | 1049 | hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN; |
mbed_official | 87:085cde657901 | 1050 | hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN; |
mbed_official | 87:085cde657901 | 1051 | |
mbed_official | 87:085cde657901 | 1052 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 1053 | { |
mbed_official | 87:085cde657901 | 1054 | /* Disable the I2S extended Tx/Rx DMA requests */ |
mbed_official | 87:085cde657901 | 1055 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 1056 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 1057 | } |
mbed_official | 87:085cde657901 | 1058 | |
mbed_official | 106:ced8cbb51063 | 1059 | /* Abort the I2S DMA Stream tx */ |
mbed_official | 106:ced8cbb51063 | 1060 | if(hi2s->hdmatx != NULL) |
mbed_official | 106:ced8cbb51063 | 1061 | { |
mbed_official | 106:ced8cbb51063 | 1062 | HAL_DMA_Abort(hi2s->hdmatx); |
mbed_official | 106:ced8cbb51063 | 1063 | } |
mbed_official | 106:ced8cbb51063 | 1064 | /* Abort the I2S DMA Stream rx */ |
mbed_official | 106:ced8cbb51063 | 1065 | if(hi2s->hdmarx != NULL) |
mbed_official | 106:ced8cbb51063 | 1066 | { |
mbed_official | 106:ced8cbb51063 | 1067 | HAL_DMA_Abort(hi2s->hdmarx); |
mbed_official | 106:ced8cbb51063 | 1068 | } |
mbed_official | 106:ced8cbb51063 | 1069 | |
mbed_official | 87:085cde657901 | 1070 | /* Disable I2S peripheral */ |
mbed_official | 87:085cde657901 | 1071 | __HAL_I2S_DISABLE(hi2s); |
mbed_official | 87:085cde657901 | 1072 | |
mbed_official | 87:085cde657901 | 1073 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 1074 | { |
mbed_official | 87:085cde657901 | 1075 | /* Disable the I2Sext peripheral */ |
mbed_official | 87:085cde657901 | 1076 | I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE; |
mbed_official | 87:085cde657901 | 1077 | } |
mbed_official | 87:085cde657901 | 1078 | |
mbed_official | 87:085cde657901 | 1079 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1080 | |
mbed_official | 87:085cde657901 | 1081 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1082 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1083 | |
mbed_official | 87:085cde657901 | 1084 | return HAL_OK; |
mbed_official | 87:085cde657901 | 1085 | } |
mbed_official | 87:085cde657901 | 1086 | |
mbed_official | 87:085cde657901 | 1087 | /** |
mbed_official | 87:085cde657901 | 1088 | * @brief This function handles I2S interrupt request. |
mbed_official | 87:085cde657901 | 1089 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1090 | * @retval HAL status |
mbed_official | 87:085cde657901 | 1091 | */ |
mbed_official | 87:085cde657901 | 1092 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1093 | { |
mbed_official | 87:085cde657901 | 1094 | uint32_t tmp1 = 0, tmp2 = 0; |
mbed_official | 87:085cde657901 | 1095 | if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 1096 | { |
mbed_official | 87:085cde657901 | 1097 | if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
mbed_official | 87:085cde657901 | 1098 | { |
mbed_official | 87:085cde657901 | 1099 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE); |
mbed_official | 87:085cde657901 | 1100 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE); |
mbed_official | 87:085cde657901 | 1101 | /* I2S in mode Receiver ------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1102 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1103 | { |
mbed_official | 87:085cde657901 | 1104 | I2S_Receive_IT(hi2s); |
mbed_official | 87:085cde657901 | 1105 | } |
mbed_official | 87:085cde657901 | 1106 | |
mbed_official | 87:085cde657901 | 1107 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); |
mbed_official | 87:085cde657901 | 1108 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
mbed_official | 87:085cde657901 | 1109 | /* I2S Overrun error interrupt occured ---------------------------------*/ |
mbed_official | 87:085cde657901 | 1110 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1111 | { |
mbed_official | 87:085cde657901 | 1112 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 1113 | hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; |
mbed_official | 87:085cde657901 | 1114 | } |
mbed_official | 87:085cde657901 | 1115 | } |
mbed_official | 87:085cde657901 | 1116 | |
mbed_official | 87:085cde657901 | 1117 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
mbed_official | 87:085cde657901 | 1118 | { |
mbed_official | 87:085cde657901 | 1119 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE); |
mbed_official | 87:085cde657901 | 1120 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE); |
mbed_official | 87:085cde657901 | 1121 | /* I2S in mode Tramitter -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1122 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1123 | { |
mbed_official | 87:085cde657901 | 1124 | I2S_Transmit_IT(hi2s); |
mbed_official | 87:085cde657901 | 1125 | } |
mbed_official | 87:085cde657901 | 1126 | |
mbed_official | 87:085cde657901 | 1127 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); |
mbed_official | 87:085cde657901 | 1128 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
mbed_official | 87:085cde657901 | 1129 | /* I2S Underrun error interrupt occured --------------------------------*/ |
mbed_official | 87:085cde657901 | 1130 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1131 | { |
mbed_official | 87:085cde657901 | 1132 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 1133 | hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; |
mbed_official | 87:085cde657901 | 1134 | } |
mbed_official | 87:085cde657901 | 1135 | } |
mbed_official | 87:085cde657901 | 1136 | } |
mbed_official | 87:085cde657901 | 1137 | else |
mbed_official | 87:085cde657901 | 1138 | { |
mbed_official | 87:085cde657901 | 1139 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1140 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1141 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
mbed_official | 87:085cde657901 | 1142 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
mbed_official | 87:085cde657901 | 1143 | { |
mbed_official | 87:085cde657901 | 1144 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE; |
mbed_official | 87:085cde657901 | 1145 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE; |
mbed_official | 87:085cde657901 | 1146 | /* I2Sext in mode Receiver ---------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1147 | if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE)) |
mbed_official | 87:085cde657901 | 1148 | { |
mbed_official | 87:085cde657901 | 1149 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1150 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1151 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
mbed_official | 87:085cde657901 | 1152 | the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
mbed_official | 87:085cde657901 | 1153 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
mbed_official | 87:085cde657901 | 1154 | { |
mbed_official | 87:085cde657901 | 1155 | I2SEx_TransmitReceive_IT(hi2s); |
mbed_official | 87:085cde657901 | 1156 | } |
mbed_official | 87:085cde657901 | 1157 | } |
mbed_official | 87:085cde657901 | 1158 | |
mbed_official | 87:085cde657901 | 1159 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR; |
mbed_official | 87:085cde657901 | 1160 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; |
mbed_official | 87:085cde657901 | 1161 | /* I2Sext Overrun error interrupt occured ------------------------------*/ |
mbed_official | 87:085cde657901 | 1162 | if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR)) |
mbed_official | 87:085cde657901 | 1163 | { |
mbed_official | 87:085cde657901 | 1164 | /* Clear I2Sext OVR Flag */ |
mbed_official | 87:085cde657901 | 1165 | I2SxEXT(hi2s->Instance)->DR; |
mbed_official | 87:085cde657901 | 1166 | I2SxEXT(hi2s->Instance)->SR; |
mbed_official | 87:085cde657901 | 1167 | hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR; |
mbed_official | 87:085cde657901 | 1168 | } |
mbed_official | 87:085cde657901 | 1169 | |
mbed_official | 87:085cde657901 | 1170 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE); |
mbed_official | 87:085cde657901 | 1171 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE); |
mbed_official | 87:085cde657901 | 1172 | /* I2S in mode Tramitter -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1173 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1174 | { |
mbed_official | 87:085cde657901 | 1175 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1176 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1177 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
mbed_official | 87:085cde657901 | 1178 | the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
mbed_official | 87:085cde657901 | 1179 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
mbed_official | 87:085cde657901 | 1180 | { |
mbed_official | 87:085cde657901 | 1181 | I2SEx_TransmitReceive_IT(hi2s); |
mbed_official | 87:085cde657901 | 1182 | } |
mbed_official | 87:085cde657901 | 1183 | } |
mbed_official | 87:085cde657901 | 1184 | |
mbed_official | 87:085cde657901 | 1185 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); |
mbed_official | 87:085cde657901 | 1186 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
mbed_official | 87:085cde657901 | 1187 | /* I2S Underrun error interrupt occured --------------------------------*/ |
mbed_official | 87:085cde657901 | 1188 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1189 | { |
mbed_official | 87:085cde657901 | 1190 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 1191 | hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; |
mbed_official | 87:085cde657901 | 1192 | } |
mbed_official | 87:085cde657901 | 1193 | } |
mbed_official | 87:085cde657901 | 1194 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
mbed_official | 87:085cde657901 | 1195 | else |
mbed_official | 87:085cde657901 | 1196 | { |
mbed_official | 87:085cde657901 | 1197 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE); |
mbed_official | 87:085cde657901 | 1198 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE); |
mbed_official | 87:085cde657901 | 1199 | /* I2S in mode Receiver ------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1200 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1201 | { |
mbed_official | 87:085cde657901 | 1202 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1203 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1204 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
mbed_official | 87:085cde657901 | 1205 | the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
mbed_official | 87:085cde657901 | 1206 | if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX)) |
mbed_official | 87:085cde657901 | 1207 | { |
mbed_official | 87:085cde657901 | 1208 | I2SEx_TransmitReceive_IT(hi2s); |
mbed_official | 87:085cde657901 | 1209 | } |
mbed_official | 87:085cde657901 | 1210 | } |
mbed_official | 87:085cde657901 | 1211 | |
mbed_official | 87:085cde657901 | 1212 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); |
mbed_official | 87:085cde657901 | 1213 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
mbed_official | 87:085cde657901 | 1214 | /* I2S Overrun error interrupt occured ---------------------------------*/ |
mbed_official | 87:085cde657901 | 1215 | if((tmp1 != RESET) && (tmp2 != RESET)) |
mbed_official | 87:085cde657901 | 1216 | { |
mbed_official | 87:085cde657901 | 1217 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 1218 | hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; |
mbed_official | 87:085cde657901 | 1219 | } |
mbed_official | 87:085cde657901 | 1220 | |
mbed_official | 87:085cde657901 | 1221 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE; |
mbed_official | 87:085cde657901 | 1222 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE; |
mbed_official | 87:085cde657901 | 1223 | /* I2Sext in mode Tramitter --------------------------------------------*/ |
mbed_official | 87:085cde657901 | 1224 | if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE)) |
mbed_official | 87:085cde657901 | 1225 | { |
mbed_official | 87:085cde657901 | 1226 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1227 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
mbed_official | 87:085cde657901 | 1228 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
mbed_official | 87:085cde657901 | 1229 | the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
mbed_official | 87:085cde657901 | 1230 | if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX)) |
mbed_official | 87:085cde657901 | 1231 | { |
mbed_official | 87:085cde657901 | 1232 | I2SEx_TransmitReceive_IT(hi2s); |
mbed_official | 87:085cde657901 | 1233 | } |
mbed_official | 87:085cde657901 | 1234 | } |
mbed_official | 87:085cde657901 | 1235 | |
mbed_official | 87:085cde657901 | 1236 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR; |
mbed_official | 87:085cde657901 | 1237 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; |
mbed_official | 87:085cde657901 | 1238 | /* I2Sext Underrun error interrupt occured -----------------------------*/ |
mbed_official | 87:085cde657901 | 1239 | if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR)) |
mbed_official | 87:085cde657901 | 1240 | { |
mbed_official | 87:085cde657901 | 1241 | /* Clear I2Sext UDR Flag */ |
mbed_official | 87:085cde657901 | 1242 | I2SxEXT(hi2s->Instance)->SR; |
mbed_official | 87:085cde657901 | 1243 | hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR; |
mbed_official | 87:085cde657901 | 1244 | } |
mbed_official | 87:085cde657901 | 1245 | } |
mbed_official | 87:085cde657901 | 1246 | } |
mbed_official | 87:085cde657901 | 1247 | |
mbed_official | 87:085cde657901 | 1248 | /* Call the Error call Back in case of Errors */ |
mbed_official | 87:085cde657901 | 1249 | if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE) |
mbed_official | 87:085cde657901 | 1250 | { |
mbed_official | 87:085cde657901 | 1251 | /* Set the I2S state ready to be able to start again the process */ |
mbed_official | 87:085cde657901 | 1252 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1253 | HAL_I2S_ErrorCallback(hi2s); |
mbed_official | 87:085cde657901 | 1254 | } |
mbed_official | 87:085cde657901 | 1255 | } |
mbed_official | 87:085cde657901 | 1256 | |
mbed_official | 87:085cde657901 | 1257 | /** |
mbed_official | 87:085cde657901 | 1258 | * @brief Tx Transfer Half completed callbacks |
mbed_official | 87:085cde657901 | 1259 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1260 | * @retval None |
mbed_official | 87:085cde657901 | 1261 | */ |
mbed_official | 87:085cde657901 | 1262 | __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1263 | { |
mbed_official | 87:085cde657901 | 1264 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 1265 | the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file |
mbed_official | 87:085cde657901 | 1266 | */ |
mbed_official | 87:085cde657901 | 1267 | } |
mbed_official | 87:085cde657901 | 1268 | |
mbed_official | 87:085cde657901 | 1269 | /** |
mbed_official | 87:085cde657901 | 1270 | * @brief Tx Transfer completed callbacks |
mbed_official | 87:085cde657901 | 1271 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1272 | * @retval None |
mbed_official | 87:085cde657901 | 1273 | */ |
mbed_official | 87:085cde657901 | 1274 | __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1275 | { |
mbed_official | 87:085cde657901 | 1276 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 1277 | the HAL_I2S_TxCpltCallback could be implenetd in the user file |
mbed_official | 87:085cde657901 | 1278 | */ |
mbed_official | 87:085cde657901 | 1279 | } |
mbed_official | 87:085cde657901 | 1280 | |
mbed_official | 87:085cde657901 | 1281 | /** |
mbed_official | 87:085cde657901 | 1282 | * @brief Rx Transfer half completed callbacks |
mbed_official | 87:085cde657901 | 1283 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1284 | * @retval None |
mbed_official | 87:085cde657901 | 1285 | */ |
mbed_official | 87:085cde657901 | 1286 | __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1287 | { |
mbed_official | 87:085cde657901 | 1288 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 1289 | the HAL_I2S_RxCpltCallback could be implenetd in the user file |
mbed_official | 87:085cde657901 | 1290 | */ |
mbed_official | 87:085cde657901 | 1291 | } |
mbed_official | 87:085cde657901 | 1292 | |
mbed_official | 87:085cde657901 | 1293 | /** |
mbed_official | 87:085cde657901 | 1294 | * @brief Rx Transfer completed callbacks |
mbed_official | 87:085cde657901 | 1295 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1296 | * @retval None |
mbed_official | 87:085cde657901 | 1297 | */ |
mbed_official | 87:085cde657901 | 1298 | __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1299 | { |
mbed_official | 87:085cde657901 | 1300 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 1301 | the HAL_I2S_RxCpltCallback could be implenetd in the user file |
mbed_official | 87:085cde657901 | 1302 | */ |
mbed_official | 87:085cde657901 | 1303 | } |
mbed_official | 87:085cde657901 | 1304 | |
mbed_official | 87:085cde657901 | 1305 | /** |
mbed_official | 87:085cde657901 | 1306 | * @brief I2S error callbacks |
mbed_official | 87:085cde657901 | 1307 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1308 | * @retval None |
mbed_official | 87:085cde657901 | 1309 | */ |
mbed_official | 87:085cde657901 | 1310 | __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1311 | { |
mbed_official | 87:085cde657901 | 1312 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 87:085cde657901 | 1313 | the HAL_I2S_ErrorCallback could be implenetd in the user file |
mbed_official | 87:085cde657901 | 1314 | */ |
mbed_official | 87:085cde657901 | 1315 | } |
mbed_official | 87:085cde657901 | 1316 | |
mbed_official | 87:085cde657901 | 1317 | /** |
mbed_official | 87:085cde657901 | 1318 | * @} |
mbed_official | 87:085cde657901 | 1319 | */ |
mbed_official | 87:085cde657901 | 1320 | |
mbed_official | 87:085cde657901 | 1321 | /** @defgroup I2S_Group3 Peripheral State and Errors functions |
mbed_official | 87:085cde657901 | 1322 | * @brief Peripheral State functions |
mbed_official | 87:085cde657901 | 1323 | * |
mbed_official | 87:085cde657901 | 1324 | @verbatim |
mbed_official | 87:085cde657901 | 1325 | =============================================================================== |
mbed_official | 87:085cde657901 | 1326 | ##### Peripheral State and Errors functions ##### |
mbed_official | 87:085cde657901 | 1327 | =============================================================================== |
mbed_official | 87:085cde657901 | 1328 | [..] |
mbed_official | 87:085cde657901 | 1329 | This subsection permit to get in run-time the status of the peripheral |
mbed_official | 87:085cde657901 | 1330 | and the data flow. |
mbed_official | 87:085cde657901 | 1331 | |
mbed_official | 87:085cde657901 | 1332 | @endverbatim |
mbed_official | 87:085cde657901 | 1333 | * @{ |
mbed_official | 87:085cde657901 | 1334 | */ |
mbed_official | 87:085cde657901 | 1335 | |
mbed_official | 87:085cde657901 | 1336 | /** |
mbed_official | 87:085cde657901 | 1337 | * @brief Return the I2S state |
mbed_official | 87:085cde657901 | 1338 | * @param hi2s : I2S handle |
mbed_official | 87:085cde657901 | 1339 | * @retval HAL state |
mbed_official | 87:085cde657901 | 1340 | */ |
mbed_official | 87:085cde657901 | 1341 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1342 | { |
mbed_official | 87:085cde657901 | 1343 | return hi2s->State; |
mbed_official | 87:085cde657901 | 1344 | } |
mbed_official | 87:085cde657901 | 1345 | |
mbed_official | 87:085cde657901 | 1346 | /** |
mbed_official | 87:085cde657901 | 1347 | * @brief Return the I2S error code |
mbed_official | 87:085cde657901 | 1348 | * @param hi2s : I2S handle |
mbed_official | 87:085cde657901 | 1349 | * @retval I2S Error Code |
mbed_official | 87:085cde657901 | 1350 | */ |
mbed_official | 87:085cde657901 | 1351 | HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1352 | { |
mbed_official | 87:085cde657901 | 1353 | return hi2s->ErrorCode; |
mbed_official | 87:085cde657901 | 1354 | } |
mbed_official | 87:085cde657901 | 1355 | |
mbed_official | 87:085cde657901 | 1356 | /** |
mbed_official | 87:085cde657901 | 1357 | * @} |
mbed_official | 87:085cde657901 | 1358 | */ |
mbed_official | 87:085cde657901 | 1359 | |
mbed_official | 87:085cde657901 | 1360 | /** |
mbed_official | 87:085cde657901 | 1361 | * @brief DMA I2S transmit process complete callback |
mbed_official | 87:085cde657901 | 1362 | * @param hdma : DMA handle |
mbed_official | 87:085cde657901 | 1363 | * @retval None |
mbed_official | 87:085cde657901 | 1364 | */ |
mbed_official | 87:085cde657901 | 1365 | void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 1366 | { |
mbed_official | 87:085cde657901 | 1367 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 87:085cde657901 | 1368 | |
mbed_official | 87:085cde657901 | 1369 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
mbed_official | 87:085cde657901 | 1370 | { |
mbed_official | 87:085cde657901 | 1371 | hi2s->TxXferCount = 0; |
mbed_official | 87:085cde657901 | 1372 | |
mbed_official | 87:085cde657901 | 1373 | /* Disable Tx DMA Request */ |
mbed_official | 87:085cde657901 | 1374 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 1375 | |
mbed_official | 87:085cde657901 | 1376 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 1377 | { |
mbed_official | 87:085cde657901 | 1378 | /* Disable Rx DMA Request for the slave*/ |
mbed_official | 87:085cde657901 | 1379 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 1380 | } |
mbed_official | 87:085cde657901 | 1381 | |
mbed_official | 87:085cde657901 | 1382 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
mbed_official | 87:085cde657901 | 1383 | { |
mbed_official | 87:085cde657901 | 1384 | if(hi2s->RxXferCount == 0) |
mbed_official | 87:085cde657901 | 1385 | { |
mbed_official | 87:085cde657901 | 1386 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1387 | } |
mbed_official | 87:085cde657901 | 1388 | } |
mbed_official | 87:085cde657901 | 1389 | else |
mbed_official | 87:085cde657901 | 1390 | { |
mbed_official | 87:085cde657901 | 1391 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1392 | } |
mbed_official | 87:085cde657901 | 1393 | } |
mbed_official | 87:085cde657901 | 1394 | HAL_I2S_TxCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1395 | } |
mbed_official | 87:085cde657901 | 1396 | |
mbed_official | 87:085cde657901 | 1397 | /** |
mbed_official | 87:085cde657901 | 1398 | * @brief DMA I2S transmit process half complete callback |
mbed_official | 87:085cde657901 | 1399 | * @param hdma : DMA handle |
mbed_official | 87:085cde657901 | 1400 | * @retval None |
mbed_official | 87:085cde657901 | 1401 | */ |
mbed_official | 87:085cde657901 | 1402 | void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 1403 | { |
mbed_official | 87:085cde657901 | 1404 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 87:085cde657901 | 1405 | |
mbed_official | 87:085cde657901 | 1406 | HAL_I2S_TxHalfCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1407 | } |
mbed_official | 87:085cde657901 | 1408 | |
mbed_official | 87:085cde657901 | 1409 | /** |
mbed_official | 87:085cde657901 | 1410 | * @brief DMA I2S receive process complete callback |
mbed_official | 87:085cde657901 | 1411 | * @param hdma : DMA handle |
mbed_official | 87:085cde657901 | 1412 | * @retval None |
mbed_official | 87:085cde657901 | 1413 | */ |
mbed_official | 87:085cde657901 | 1414 | void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 1415 | { |
mbed_official | 87:085cde657901 | 1416 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 87:085cde657901 | 1417 | |
mbed_official | 87:085cde657901 | 1418 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
mbed_official | 87:085cde657901 | 1419 | { |
mbed_official | 87:085cde657901 | 1420 | /* Disable Rx DMA Request */ |
mbed_official | 87:085cde657901 | 1421 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
mbed_official | 87:085cde657901 | 1422 | |
mbed_official | 87:085cde657901 | 1423 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
mbed_official | 87:085cde657901 | 1424 | { |
mbed_official | 87:085cde657901 | 1425 | /* Disable Tx DMA Request for the slave*/ |
mbed_official | 87:085cde657901 | 1426 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
mbed_official | 87:085cde657901 | 1427 | } |
mbed_official | 87:085cde657901 | 1428 | |
mbed_official | 87:085cde657901 | 1429 | hi2s->RxXferCount = 0; |
mbed_official | 87:085cde657901 | 1430 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
mbed_official | 87:085cde657901 | 1431 | { |
mbed_official | 87:085cde657901 | 1432 | if(hi2s->TxXferCount == 0) |
mbed_official | 87:085cde657901 | 1433 | { |
mbed_official | 87:085cde657901 | 1434 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1435 | } |
mbed_official | 87:085cde657901 | 1436 | } |
mbed_official | 87:085cde657901 | 1437 | else |
mbed_official | 87:085cde657901 | 1438 | { |
mbed_official | 87:085cde657901 | 1439 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1440 | } |
mbed_official | 87:085cde657901 | 1441 | } |
mbed_official | 87:085cde657901 | 1442 | HAL_I2S_RxCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1443 | } |
mbed_official | 87:085cde657901 | 1444 | |
mbed_official | 87:085cde657901 | 1445 | /** |
mbed_official | 87:085cde657901 | 1446 | * @brief DMA I2S receive process half complete callback |
mbed_official | 87:085cde657901 | 1447 | * @param hdma : DMA handle |
mbed_official | 87:085cde657901 | 1448 | * @retval None |
mbed_official | 87:085cde657901 | 1449 | */ |
mbed_official | 87:085cde657901 | 1450 | void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 1451 | { |
mbed_official | 87:085cde657901 | 1452 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 87:085cde657901 | 1453 | |
mbed_official | 87:085cde657901 | 1454 | HAL_I2S_RxHalfCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1455 | } |
mbed_official | 87:085cde657901 | 1456 | |
mbed_official | 87:085cde657901 | 1457 | /** |
mbed_official | 87:085cde657901 | 1458 | * @brief DMA I2S communication error callback |
mbed_official | 87:085cde657901 | 1459 | * @param hdma : DMA handle |
mbed_official | 87:085cde657901 | 1460 | * @retval None |
mbed_official | 87:085cde657901 | 1461 | */ |
mbed_official | 87:085cde657901 | 1462 | void I2S_DMAError(DMA_HandleTypeDef *hdma) |
mbed_official | 87:085cde657901 | 1463 | { |
mbed_official | 87:085cde657901 | 1464 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 87:085cde657901 | 1465 | |
mbed_official | 87:085cde657901 | 1466 | hi2s->TxXferCount = 0; |
mbed_official | 87:085cde657901 | 1467 | hi2s->RxXferCount = 0; |
mbed_official | 87:085cde657901 | 1468 | |
mbed_official | 87:085cde657901 | 1469 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1470 | |
mbed_official | 87:085cde657901 | 1471 | hi2s->ErrorCode |= HAL_I2S_ERROR_DMA; |
mbed_official | 87:085cde657901 | 1472 | HAL_I2S_ErrorCallback(hi2s); |
mbed_official | 87:085cde657901 | 1473 | } |
mbed_official | 87:085cde657901 | 1474 | |
mbed_official | 87:085cde657901 | 1475 | /** |
mbed_official | 87:085cde657901 | 1476 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
mbed_official | 87:085cde657901 | 1477 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1478 | * @retval HAL status |
mbed_official | 87:085cde657901 | 1479 | */ |
mbed_official | 87:085cde657901 | 1480 | static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1481 | { |
mbed_official | 87:085cde657901 | 1482 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
mbed_official | 87:085cde657901 | 1483 | { |
mbed_official | 87:085cde657901 | 1484 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 1485 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 1486 | |
mbed_official | 87:085cde657901 | 1487 | /* Transmit data */ |
mbed_official | 87:085cde657901 | 1488 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
mbed_official | 87:085cde657901 | 1489 | |
mbed_official | 87:085cde657901 | 1490 | hi2s->TxXferCount--; |
mbed_official | 87:085cde657901 | 1491 | |
mbed_official | 87:085cde657901 | 1492 | if(hi2s->TxXferCount == 0) |
mbed_official | 87:085cde657901 | 1493 | { |
mbed_official | 87:085cde657901 | 1494 | /* Disable TXE and ERR interrupt */ |
mbed_official | 87:085cde657901 | 1495 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
mbed_official | 87:085cde657901 | 1496 | |
mbed_official | 87:085cde657901 | 1497 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1498 | |
mbed_official | 87:085cde657901 | 1499 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1500 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1501 | HAL_I2S_TxCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1502 | } |
mbed_official | 87:085cde657901 | 1503 | else |
mbed_official | 87:085cde657901 | 1504 | { |
mbed_official | 87:085cde657901 | 1505 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1506 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1507 | } |
mbed_official | 87:085cde657901 | 1508 | |
mbed_official | 87:085cde657901 | 1509 | return HAL_OK; |
mbed_official | 87:085cde657901 | 1510 | } |
mbed_official | 87:085cde657901 | 1511 | |
mbed_official | 87:085cde657901 | 1512 | else |
mbed_official | 87:085cde657901 | 1513 | { |
mbed_official | 87:085cde657901 | 1514 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 1515 | } |
mbed_official | 87:085cde657901 | 1516 | } |
mbed_official | 87:085cde657901 | 1517 | |
mbed_official | 87:085cde657901 | 1518 | /** |
mbed_official | 87:085cde657901 | 1519 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
mbed_official | 87:085cde657901 | 1520 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1521 | * @retval HAL status |
mbed_official | 87:085cde657901 | 1522 | */ |
mbed_official | 87:085cde657901 | 1523 | static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s) |
mbed_official | 87:085cde657901 | 1524 | { |
mbed_official | 87:085cde657901 | 1525 | if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
mbed_official | 87:085cde657901 | 1526 | { |
mbed_official | 87:085cde657901 | 1527 | /* Process Locked */ |
mbed_official | 87:085cde657901 | 1528 | __HAL_LOCK(hi2s); |
mbed_official | 87:085cde657901 | 1529 | |
mbed_official | 87:085cde657901 | 1530 | /* Receive data */ |
mbed_official | 87:085cde657901 | 1531 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
mbed_official | 87:085cde657901 | 1532 | |
mbed_official | 87:085cde657901 | 1533 | hi2s->RxXferCount--; |
mbed_official | 87:085cde657901 | 1534 | |
mbed_official | 87:085cde657901 | 1535 | /* Check if Master Receiver mode is selected */ |
mbed_official | 87:085cde657901 | 1536 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
mbed_official | 87:085cde657901 | 1537 | { |
mbed_official | 87:085cde657901 | 1538 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
mbed_official | 87:085cde657901 | 1539 | access to the SPI_SR register. */ |
mbed_official | 87:085cde657901 | 1540 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
mbed_official | 87:085cde657901 | 1541 | } |
mbed_official | 87:085cde657901 | 1542 | |
mbed_official | 87:085cde657901 | 1543 | if(hi2s->RxXferCount == 0) |
mbed_official | 87:085cde657901 | 1544 | { |
mbed_official | 87:085cde657901 | 1545 | /* Disable RXNE and ERR interrupt */ |
mbed_official | 87:085cde657901 | 1546 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR); |
mbed_official | 87:085cde657901 | 1547 | |
mbed_official | 87:085cde657901 | 1548 | hi2s->State = HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1549 | |
mbed_official | 87:085cde657901 | 1550 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1551 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1552 | |
mbed_official | 87:085cde657901 | 1553 | HAL_I2S_RxCpltCallback(hi2s); |
mbed_official | 87:085cde657901 | 1554 | } |
mbed_official | 87:085cde657901 | 1555 | else |
mbed_official | 87:085cde657901 | 1556 | { |
mbed_official | 87:085cde657901 | 1557 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1558 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1559 | } |
mbed_official | 87:085cde657901 | 1560 | |
mbed_official | 87:085cde657901 | 1561 | return HAL_OK; |
mbed_official | 87:085cde657901 | 1562 | } |
mbed_official | 87:085cde657901 | 1563 | else |
mbed_official | 87:085cde657901 | 1564 | { |
mbed_official | 87:085cde657901 | 1565 | return HAL_BUSY; |
mbed_official | 87:085cde657901 | 1566 | } |
mbed_official | 87:085cde657901 | 1567 | } |
mbed_official | 87:085cde657901 | 1568 | |
mbed_official | 87:085cde657901 | 1569 | /** |
mbed_official | 87:085cde657901 | 1570 | * @brief This function handles I2S Communication Timeout. |
mbed_official | 87:085cde657901 | 1571 | * @param hi2s: I2S handle |
mbed_official | 87:085cde657901 | 1572 | * @param Flag: Flag checked |
mbed_official | 87:085cde657901 | 1573 | * @param State: Value of the flag expected |
mbed_official | 87:085cde657901 | 1574 | * @param Timeout: Duration of the timeout |
mbed_official | 87:085cde657901 | 1575 | * @retval HAL status |
mbed_official | 87:085cde657901 | 1576 | */ |
mbed_official | 87:085cde657901 | 1577 | HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) |
mbed_official | 87:085cde657901 | 1578 | { |
mbed_official | 87:085cde657901 | 1579 | uint32_t timeout = 0; |
mbed_official | 87:085cde657901 | 1580 | |
mbed_official | 87:085cde657901 | 1581 | timeout = HAL_GetTick() + Timeout; |
mbed_official | 87:085cde657901 | 1582 | |
mbed_official | 87:085cde657901 | 1583 | /* Wait until flag is set */ |
mbed_official | 87:085cde657901 | 1584 | if(Status == RESET) |
mbed_official | 87:085cde657901 | 1585 | { |
mbed_official | 87:085cde657901 | 1586 | while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) |
mbed_official | 87:085cde657901 | 1587 | { |
mbed_official | 87:085cde657901 | 1588 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 87:085cde657901 | 1589 | { |
mbed_official | 87:085cde657901 | 1590 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 1591 | { |
mbed_official | 87:085cde657901 | 1592 | /* Set the I2S State ready */ |
mbed_official | 87:085cde657901 | 1593 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1594 | |
mbed_official | 87:085cde657901 | 1595 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1596 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1597 | |
mbed_official | 87:085cde657901 | 1598 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 1599 | } |
mbed_official | 87:085cde657901 | 1600 | } |
mbed_official | 87:085cde657901 | 1601 | } |
mbed_official | 87:085cde657901 | 1602 | } |
mbed_official | 87:085cde657901 | 1603 | else |
mbed_official | 87:085cde657901 | 1604 | { |
mbed_official | 87:085cde657901 | 1605 | while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) |
mbed_official | 87:085cde657901 | 1606 | { |
mbed_official | 87:085cde657901 | 1607 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 87:085cde657901 | 1608 | { |
mbed_official | 87:085cde657901 | 1609 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 1610 | { |
mbed_official | 87:085cde657901 | 1611 | /* Set the I2S State ready */ |
mbed_official | 87:085cde657901 | 1612 | hi2s->State= HAL_I2S_STATE_READY; |
mbed_official | 87:085cde657901 | 1613 | |
mbed_official | 87:085cde657901 | 1614 | /* Process Unlocked */ |
mbed_official | 87:085cde657901 | 1615 | __HAL_UNLOCK(hi2s); |
mbed_official | 87:085cde657901 | 1616 | |
mbed_official | 87:085cde657901 | 1617 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 1618 | } |
mbed_official | 87:085cde657901 | 1619 | } |
mbed_official | 87:085cde657901 | 1620 | } |
mbed_official | 87:085cde657901 | 1621 | } |
mbed_official | 87:085cde657901 | 1622 | return HAL_OK; |
mbed_official | 87:085cde657901 | 1623 | } |
mbed_official | 87:085cde657901 | 1624 | |
mbed_official | 87:085cde657901 | 1625 | /** |
mbed_official | 87:085cde657901 | 1626 | * @} |
mbed_official | 87:085cde657901 | 1627 | */ |
mbed_official | 87:085cde657901 | 1628 | |
mbed_official | 87:085cde657901 | 1629 | #endif /* HAL_I2S_MODULE_ENABLED */ |
mbed_official | 87:085cde657901 | 1630 | /** |
mbed_official | 87:085cde657901 | 1631 | * @} |
mbed_official | 87:085cde657901 | 1632 | */ |
mbed_official | 87:085cde657901 | 1633 | |
mbed_official | 87:085cde657901 | 1634 | /** |
mbed_official | 87:085cde657901 | 1635 | * @} |
mbed_official | 87:085cde657901 | 1636 | */ |
mbed_official | 87:085cde657901 | 1637 | |
mbed_official | 87:085cde657901 | 1638 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |