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targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_wwdg.c@130:1dec54e4aec3, 2014-03-21 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Mar 21 11:45:09 2014 +0000
- Revision:
- 130:1dec54e4aec3
Synchronized with git revision e5c9ff6781a4e277a5a454e5a0b037f76e31739d
Full URL: https://github.com/mbedmicro/mbed/commit/e5c9ff6781a4e277a5a454e5a0b037f76e31739d/
STM32F0-Discovery (STM32F051R8) initial port
Who changed what in which revision?
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mbed_official | 130:1dec54e4aec3 | 1 | /** |
mbed_official | 130:1dec54e4aec3 | 2 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 3 | * @file stm32f0xx_wwdg.c |
mbed_official | 130:1dec54e4aec3 | 4 | * @author MCD Application Team |
mbed_official | 130:1dec54e4aec3 | 5 | * @version V1.3.0 |
mbed_official | 130:1dec54e4aec3 | 6 | * @date 16-January-2014 |
mbed_official | 130:1dec54e4aec3 | 7 | * @brief This file provides firmware functions to manage the following |
mbed_official | 130:1dec54e4aec3 | 8 | * functionalities of the Window watchdog (WWDG) peripheral: |
mbed_official | 130:1dec54e4aec3 | 9 | * + Prescaler, Refresh window and Counter configuration |
mbed_official | 130:1dec54e4aec3 | 10 | * + WWDG activation |
mbed_official | 130:1dec54e4aec3 | 11 | * + Interrupts and flags management |
mbed_official | 130:1dec54e4aec3 | 12 | * |
mbed_official | 130:1dec54e4aec3 | 13 | * @verbatim |
mbed_official | 130:1dec54e4aec3 | 14 | * |
mbed_official | 130:1dec54e4aec3 | 15 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 16 | ##### WWDG features ##### |
mbed_official | 130:1dec54e4aec3 | 17 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 18 | [..] Once enabled the WWDG generates a system reset on expiry of a programmed |
mbed_official | 130:1dec54e4aec3 | 19 | time period, unless the program refreshes the counter (downcounter) |
mbed_official | 130:1dec54e4aec3 | 20 | before to reach 0x3F value (i.e. a reset is generated when the counter |
mbed_official | 130:1dec54e4aec3 | 21 | value rolls over from 0x40 to 0x3F). |
mbed_official | 130:1dec54e4aec3 | 22 | [..] An MCU reset is also generated if the counter value is refreshed |
mbed_official | 130:1dec54e4aec3 | 23 | before the counter has reached the refresh window value. This |
mbed_official | 130:1dec54e4aec3 | 24 | implies that the counter must be refreshed in a limited window. |
mbed_official | 130:1dec54e4aec3 | 25 | |
mbed_official | 130:1dec54e4aec3 | 26 | [..] Once enabled the WWDG cannot be disabled except by a system reset. |
mbed_official | 130:1dec54e4aec3 | 27 | |
mbed_official | 130:1dec54e4aec3 | 28 | [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG |
mbed_official | 130:1dec54e4aec3 | 29 | reset occurs. |
mbed_official | 130:1dec54e4aec3 | 30 | |
mbed_official | 130:1dec54e4aec3 | 31 | [..] The WWDG counter input clock is derived from the APB clock divided |
mbed_official | 130:1dec54e4aec3 | 32 | by a programmable prescaler. |
mbed_official | 130:1dec54e4aec3 | 33 | |
mbed_official | 130:1dec54e4aec3 | 34 | [..] WWDG counter clock = PCLK1 / Prescaler. |
mbed_official | 130:1dec54e4aec3 | 35 | [..] WWDG timeout = (WWDG counter clock) * (counter value). |
mbed_official | 130:1dec54e4aec3 | 36 | |
mbed_official | 130:1dec54e4aec3 | 37 | [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. |
mbed_official | 130:1dec54e4aec3 | 38 | |
mbed_official | 130:1dec54e4aec3 | 39 | ##### How to use this driver ##### |
mbed_official | 130:1dec54e4aec3 | 40 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 41 | [..] |
mbed_official | 130:1dec54e4aec3 | 42 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) |
mbed_official | 130:1dec54e4aec3 | 43 | function. |
mbed_official | 130:1dec54e4aec3 | 44 | |
mbed_official | 130:1dec54e4aec3 | 45 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. |
mbed_official | 130:1dec54e4aec3 | 46 | |
mbed_official | 130:1dec54e4aec3 | 47 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. |
mbed_official | 130:1dec54e4aec3 | 48 | |
mbed_official | 130:1dec54e4aec3 | 49 | (#) Set the WWDG counter value and start it using WWDG_Enable() function. |
mbed_official | 130:1dec54e4aec3 | 50 | When the WWDG is enabled the counter value should be configured to |
mbed_official | 130:1dec54e4aec3 | 51 | a value greater than 0x40 to prevent generating an immediate reset. |
mbed_official | 130:1dec54e4aec3 | 52 | |
mbed_official | 130:1dec54e4aec3 | 53 | (#) Optionally you can enable the Early wakeup interrupt which is |
mbed_official | 130:1dec54e4aec3 | 54 | generated when the counter reach 0x40. |
mbed_official | 130:1dec54e4aec3 | 55 | Once enabled this interrupt cannot be disabled except by a system reset. |
mbed_official | 130:1dec54e4aec3 | 56 | |
mbed_official | 130:1dec54e4aec3 | 57 | (#) Then the application program must refresh the WWDG counter at regular |
mbed_official | 130:1dec54e4aec3 | 58 | intervals during normal operation to prevent an MCU reset, using |
mbed_official | 130:1dec54e4aec3 | 59 | WWDG_SetCounter() function. This operation must occur only when |
mbed_official | 130:1dec54e4aec3 | 60 | the counter value is lower than the refresh window value, |
mbed_official | 130:1dec54e4aec3 | 61 | programmed using WWDG_SetWindowValue(). |
mbed_official | 130:1dec54e4aec3 | 62 | |
mbed_official | 130:1dec54e4aec3 | 63 | * @endverbatim |
mbed_official | 130:1dec54e4aec3 | 64 | * |
mbed_official | 130:1dec54e4aec3 | 65 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 66 | * @attention |
mbed_official | 130:1dec54e4aec3 | 67 | * |
mbed_official | 130:1dec54e4aec3 | 68 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 130:1dec54e4aec3 | 69 | * |
mbed_official | 130:1dec54e4aec3 | 70 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 130:1dec54e4aec3 | 71 | * are permitted provided that the following conditions are met: |
mbed_official | 130:1dec54e4aec3 | 72 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 73 | * this list of conditions and the following disclaimer. |
mbed_official | 130:1dec54e4aec3 | 74 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 75 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 130:1dec54e4aec3 | 76 | * and/or other materials provided with the distribution. |
mbed_official | 130:1dec54e4aec3 | 77 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 130:1dec54e4aec3 | 78 | * may be used to endorse or promote products derived from this software |
mbed_official | 130:1dec54e4aec3 | 79 | * without specific prior written permission. |
mbed_official | 130:1dec54e4aec3 | 80 | * |
mbed_official | 130:1dec54e4aec3 | 81 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 130:1dec54e4aec3 | 82 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 130:1dec54e4aec3 | 83 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 130:1dec54e4aec3 | 84 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 130:1dec54e4aec3 | 85 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 130:1dec54e4aec3 | 86 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 130:1dec54e4aec3 | 87 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 130:1dec54e4aec3 | 88 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 130:1dec54e4aec3 | 89 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 130:1dec54e4aec3 | 90 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 130:1dec54e4aec3 | 91 | * |
mbed_official | 130:1dec54e4aec3 | 92 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 93 | */ |
mbed_official | 130:1dec54e4aec3 | 94 | |
mbed_official | 130:1dec54e4aec3 | 95 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 96 | #include "stm32f0xx_wwdg.h" |
mbed_official | 130:1dec54e4aec3 | 97 | #include "stm32f0xx_rcc.h" |
mbed_official | 130:1dec54e4aec3 | 98 | |
mbed_official | 130:1dec54e4aec3 | 99 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
mbed_official | 130:1dec54e4aec3 | 100 | * @{ |
mbed_official | 130:1dec54e4aec3 | 101 | */ |
mbed_official | 130:1dec54e4aec3 | 102 | |
mbed_official | 130:1dec54e4aec3 | 103 | /** @defgroup WWDG |
mbed_official | 130:1dec54e4aec3 | 104 | * @brief WWDG driver modules |
mbed_official | 130:1dec54e4aec3 | 105 | * @{ |
mbed_official | 130:1dec54e4aec3 | 106 | */ |
mbed_official | 130:1dec54e4aec3 | 107 | |
mbed_official | 130:1dec54e4aec3 | 108 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 109 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 110 | /* --------------------- WWDG registers bit mask ---------------------------- */ |
mbed_official | 130:1dec54e4aec3 | 111 | /* CFR register bit mask */ |
mbed_official | 130:1dec54e4aec3 | 112 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) |
mbed_official | 130:1dec54e4aec3 | 113 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80) |
mbed_official | 130:1dec54e4aec3 | 114 | #define BIT_MASK ((uint8_t)0x7F) |
mbed_official | 130:1dec54e4aec3 | 115 | |
mbed_official | 130:1dec54e4aec3 | 116 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 117 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 118 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 119 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 120 | |
mbed_official | 130:1dec54e4aec3 | 121 | /** @defgroup WWDG_Private_Functions |
mbed_official | 130:1dec54e4aec3 | 122 | * @{ |
mbed_official | 130:1dec54e4aec3 | 123 | */ |
mbed_official | 130:1dec54e4aec3 | 124 | |
mbed_official | 130:1dec54e4aec3 | 125 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions |
mbed_official | 130:1dec54e4aec3 | 126 | * @brief Prescaler, Refresh window and Counter configuration functions |
mbed_official | 130:1dec54e4aec3 | 127 | * |
mbed_official | 130:1dec54e4aec3 | 128 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 129 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 130 | ##### Prescaler, Refresh window and Counter configuration functions ##### |
mbed_official | 130:1dec54e4aec3 | 131 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 132 | |
mbed_official | 130:1dec54e4aec3 | 133 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 134 | * @{ |
mbed_official | 130:1dec54e4aec3 | 135 | */ |
mbed_official | 130:1dec54e4aec3 | 136 | |
mbed_official | 130:1dec54e4aec3 | 137 | /** |
mbed_official | 130:1dec54e4aec3 | 138 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. |
mbed_official | 130:1dec54e4aec3 | 139 | * @param None |
mbed_official | 130:1dec54e4aec3 | 140 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 141 | */ |
mbed_official | 130:1dec54e4aec3 | 142 | void WWDG_DeInit(void) |
mbed_official | 130:1dec54e4aec3 | 143 | { |
mbed_official | 130:1dec54e4aec3 | 144 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 145 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 146 | } |
mbed_official | 130:1dec54e4aec3 | 147 | |
mbed_official | 130:1dec54e4aec3 | 148 | /** |
mbed_official | 130:1dec54e4aec3 | 149 | * @brief Sets the WWDG Prescaler. |
mbed_official | 130:1dec54e4aec3 | 150 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. |
mbed_official | 130:1dec54e4aec3 | 151 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 152 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 |
mbed_official | 130:1dec54e4aec3 | 153 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 |
mbed_official | 130:1dec54e4aec3 | 154 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 |
mbed_official | 130:1dec54e4aec3 | 155 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 |
mbed_official | 130:1dec54e4aec3 | 156 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 157 | */ |
mbed_official | 130:1dec54e4aec3 | 158 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) |
mbed_official | 130:1dec54e4aec3 | 159 | { |
mbed_official | 130:1dec54e4aec3 | 160 | uint32_t tmpreg = 0; |
mbed_official | 130:1dec54e4aec3 | 161 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 162 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); |
mbed_official | 130:1dec54e4aec3 | 163 | /* Clear WDGTB[1:0] bits */ |
mbed_official | 130:1dec54e4aec3 | 164 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK; |
mbed_official | 130:1dec54e4aec3 | 165 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 166 | tmpreg |= WWDG_Prescaler; |
mbed_official | 130:1dec54e4aec3 | 167 | /* Store the new value */ |
mbed_official | 130:1dec54e4aec3 | 168 | WWDG->CFR = tmpreg; |
mbed_official | 130:1dec54e4aec3 | 169 | } |
mbed_official | 130:1dec54e4aec3 | 170 | |
mbed_official | 130:1dec54e4aec3 | 171 | /** |
mbed_official | 130:1dec54e4aec3 | 172 | * @brief Sets the WWDG window value. |
mbed_official | 130:1dec54e4aec3 | 173 | * @param WindowValue: specifies the window value to be compared to the downcounter. |
mbed_official | 130:1dec54e4aec3 | 174 | * This parameter value must be lower than 0x80. |
mbed_official | 130:1dec54e4aec3 | 175 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 176 | */ |
mbed_official | 130:1dec54e4aec3 | 177 | void WWDG_SetWindowValue(uint8_t WindowValue) |
mbed_official | 130:1dec54e4aec3 | 178 | { |
mbed_official | 130:1dec54e4aec3 | 179 | __IO uint32_t tmpreg = 0; |
mbed_official | 130:1dec54e4aec3 | 180 | |
mbed_official | 130:1dec54e4aec3 | 181 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 182 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); |
mbed_official | 130:1dec54e4aec3 | 183 | /* Clear W[6:0] bits */ |
mbed_official | 130:1dec54e4aec3 | 184 | |
mbed_official | 130:1dec54e4aec3 | 185 | tmpreg = WWDG->CFR & CFR_W_MASK; |
mbed_official | 130:1dec54e4aec3 | 186 | |
mbed_official | 130:1dec54e4aec3 | 187 | /* Set W[6:0] bits according to WindowValue value */ |
mbed_official | 130:1dec54e4aec3 | 188 | tmpreg |= WindowValue & (uint32_t) BIT_MASK; |
mbed_official | 130:1dec54e4aec3 | 189 | |
mbed_official | 130:1dec54e4aec3 | 190 | /* Store the new value */ |
mbed_official | 130:1dec54e4aec3 | 191 | WWDG->CFR = tmpreg; |
mbed_official | 130:1dec54e4aec3 | 192 | } |
mbed_official | 130:1dec54e4aec3 | 193 | |
mbed_official | 130:1dec54e4aec3 | 194 | /** |
mbed_official | 130:1dec54e4aec3 | 195 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). |
mbed_official | 130:1dec54e4aec3 | 196 | * @note Once enabled this interrupt cannot be disabled except by a system reset. |
mbed_official | 130:1dec54e4aec3 | 197 | * @param None |
mbed_official | 130:1dec54e4aec3 | 198 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 199 | */ |
mbed_official | 130:1dec54e4aec3 | 200 | void WWDG_EnableIT(void) |
mbed_official | 130:1dec54e4aec3 | 201 | { |
mbed_official | 130:1dec54e4aec3 | 202 | WWDG->CFR |= WWDG_CFR_EWI; |
mbed_official | 130:1dec54e4aec3 | 203 | } |
mbed_official | 130:1dec54e4aec3 | 204 | |
mbed_official | 130:1dec54e4aec3 | 205 | /** |
mbed_official | 130:1dec54e4aec3 | 206 | * @brief Sets the WWDG counter value. |
mbed_official | 130:1dec54e4aec3 | 207 | * @param Counter: specifies the watchdog counter value. |
mbed_official | 130:1dec54e4aec3 | 208 | * This parameter must be a number between 0x40 and 0x7F (to prevent |
mbed_official | 130:1dec54e4aec3 | 209 | * generating an immediate reset). |
mbed_official | 130:1dec54e4aec3 | 210 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 211 | */ |
mbed_official | 130:1dec54e4aec3 | 212 | void WWDG_SetCounter(uint8_t Counter) |
mbed_official | 130:1dec54e4aec3 | 213 | { |
mbed_official | 130:1dec54e4aec3 | 214 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 215 | assert_param(IS_WWDG_COUNTER(Counter)); |
mbed_official | 130:1dec54e4aec3 | 216 | /* Write to T[6:0] bits to configure the counter value, no need to do |
mbed_official | 130:1dec54e4aec3 | 217 | a read-modify-write; writing a 0 to WDGA bit does nothing */ |
mbed_official | 130:1dec54e4aec3 | 218 | WWDG->CR = Counter & BIT_MASK; |
mbed_official | 130:1dec54e4aec3 | 219 | } |
mbed_official | 130:1dec54e4aec3 | 220 | |
mbed_official | 130:1dec54e4aec3 | 221 | /** |
mbed_official | 130:1dec54e4aec3 | 222 | * @} |
mbed_official | 130:1dec54e4aec3 | 223 | */ |
mbed_official | 130:1dec54e4aec3 | 224 | |
mbed_official | 130:1dec54e4aec3 | 225 | /** @defgroup WWDG_Group2 WWDG activation functions |
mbed_official | 130:1dec54e4aec3 | 226 | * @brief WWDG activation functions |
mbed_official | 130:1dec54e4aec3 | 227 | * |
mbed_official | 130:1dec54e4aec3 | 228 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 229 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 230 | ##### WWDG activation function ##### |
mbed_official | 130:1dec54e4aec3 | 231 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 232 | |
mbed_official | 130:1dec54e4aec3 | 233 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 234 | * @{ |
mbed_official | 130:1dec54e4aec3 | 235 | */ |
mbed_official | 130:1dec54e4aec3 | 236 | |
mbed_official | 130:1dec54e4aec3 | 237 | /** |
mbed_official | 130:1dec54e4aec3 | 238 | * @brief Enables WWDG and load the counter value. |
mbed_official | 130:1dec54e4aec3 | 239 | * @param Counter: specifies the watchdog counter value. |
mbed_official | 130:1dec54e4aec3 | 240 | * This parameter must be a number between 0x40 and 0x7F (to prevent |
mbed_official | 130:1dec54e4aec3 | 241 | * generating an immediate reset). |
mbed_official | 130:1dec54e4aec3 | 242 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 243 | */ |
mbed_official | 130:1dec54e4aec3 | 244 | void WWDG_Enable(uint8_t Counter) |
mbed_official | 130:1dec54e4aec3 | 245 | { |
mbed_official | 130:1dec54e4aec3 | 246 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 247 | assert_param(IS_WWDG_COUNTER(Counter)); |
mbed_official | 130:1dec54e4aec3 | 248 | WWDG->CR = WWDG_CR_WDGA | Counter; |
mbed_official | 130:1dec54e4aec3 | 249 | } |
mbed_official | 130:1dec54e4aec3 | 250 | |
mbed_official | 130:1dec54e4aec3 | 251 | /** |
mbed_official | 130:1dec54e4aec3 | 252 | * @} |
mbed_official | 130:1dec54e4aec3 | 253 | */ |
mbed_official | 130:1dec54e4aec3 | 254 | |
mbed_official | 130:1dec54e4aec3 | 255 | /** @defgroup WWDG_Group3 Interrupts and flags management functions |
mbed_official | 130:1dec54e4aec3 | 256 | * @brief Interrupts and flags management functions |
mbed_official | 130:1dec54e4aec3 | 257 | * |
mbed_official | 130:1dec54e4aec3 | 258 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 259 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 260 | ##### Interrupts and flags management functions ##### |
mbed_official | 130:1dec54e4aec3 | 261 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 262 | |
mbed_official | 130:1dec54e4aec3 | 263 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 264 | * @{ |
mbed_official | 130:1dec54e4aec3 | 265 | */ |
mbed_official | 130:1dec54e4aec3 | 266 | |
mbed_official | 130:1dec54e4aec3 | 267 | /** |
mbed_official | 130:1dec54e4aec3 | 268 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. |
mbed_official | 130:1dec54e4aec3 | 269 | * @param None |
mbed_official | 130:1dec54e4aec3 | 270 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). |
mbed_official | 130:1dec54e4aec3 | 271 | */ |
mbed_official | 130:1dec54e4aec3 | 272 | FlagStatus WWDG_GetFlagStatus(void) |
mbed_official | 130:1dec54e4aec3 | 273 | { |
mbed_official | 130:1dec54e4aec3 | 274 | FlagStatus bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 275 | |
mbed_official | 130:1dec54e4aec3 | 276 | if ((WWDG->SR) != (uint32_t)RESET) |
mbed_official | 130:1dec54e4aec3 | 277 | { |
mbed_official | 130:1dec54e4aec3 | 278 | bitstatus = SET; |
mbed_official | 130:1dec54e4aec3 | 279 | } |
mbed_official | 130:1dec54e4aec3 | 280 | else |
mbed_official | 130:1dec54e4aec3 | 281 | { |
mbed_official | 130:1dec54e4aec3 | 282 | bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 283 | } |
mbed_official | 130:1dec54e4aec3 | 284 | return bitstatus; |
mbed_official | 130:1dec54e4aec3 | 285 | } |
mbed_official | 130:1dec54e4aec3 | 286 | |
mbed_official | 130:1dec54e4aec3 | 287 | /** |
mbed_official | 130:1dec54e4aec3 | 288 | * @brief Clears Early Wakeup interrupt flag. |
mbed_official | 130:1dec54e4aec3 | 289 | * @param None |
mbed_official | 130:1dec54e4aec3 | 290 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 291 | */ |
mbed_official | 130:1dec54e4aec3 | 292 | void WWDG_ClearFlag(void) |
mbed_official | 130:1dec54e4aec3 | 293 | { |
mbed_official | 130:1dec54e4aec3 | 294 | WWDG->SR = (uint32_t)RESET; |
mbed_official | 130:1dec54e4aec3 | 295 | } |
mbed_official | 130:1dec54e4aec3 | 296 | |
mbed_official | 130:1dec54e4aec3 | 297 | /** |
mbed_official | 130:1dec54e4aec3 | 298 | * @} |
mbed_official | 130:1dec54e4aec3 | 299 | */ |
mbed_official | 130:1dec54e4aec3 | 300 | |
mbed_official | 130:1dec54e4aec3 | 301 | /** |
mbed_official | 130:1dec54e4aec3 | 302 | * @} |
mbed_official | 130:1dec54e4aec3 | 303 | */ |
mbed_official | 130:1dec54e4aec3 | 304 | |
mbed_official | 130:1dec54e4aec3 | 305 | /** |
mbed_official | 130:1dec54e4aec3 | 306 | * @} |
mbed_official | 130:1dec54e4aec3 | 307 | */ |
mbed_official | 130:1dec54e4aec3 | 308 | |
mbed_official | 130:1dec54e4aec3 | 309 | /** |
mbed_official | 130:1dec54e4aec3 | 310 | * @} |
mbed_official | 130:1dec54e4aec3 | 311 | */ |
mbed_official | 130:1dec54e4aec3 | 312 | |
mbed_official | 130:1dec54e4aec3 | 313 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |