Zachary Rubin / Mbed 2 deprecated PVA_logger

a program i made a while back to log gps/accelerometer data

Dependencies:   FatFileSystem mbed

ACCEL_ADXL345.cpp@0:82a02991476c, 2012-09-08 (annotated)

Committer:
Xach
Date:
Sat Sep 08 20:40:58 2012 +0000
Revision:
0:82a02991476c
a program i made a while back to log gps/accelerometer data

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Xach 0:82a02991476c 1 #include "ACCEL_ADXL345.h"
Xach 0:82a02991476c 2 #include "mbed.h"
Xach 0:82a02991476c 3
Xach 0:82a02991476c 4 void accel_ISR() {
Xach 0:82a02991476c 5 accelRdy = true;
Xach 0:82a02991476c 6 accelTime = timer.read_us();
Xach 0:82a02991476c 7 updateAccel();
Xach 0:82a02991476c 8 }
Xach 0:82a02991476c 9
Xach 0:82a02991476c 10 void updateAccel() {
Xach 0:82a02991476c 11
Xach 0:82a02991476c 12 __disable_irq();// if we are interrupted here i could mean we get accel data from 2 different samples
Xach 0:82a02991476c 13 _cs = 0;
Xach 0:82a02991476c 14 _spi.write(0xF2); // Read X out reg and have it continue for 6 bytes
Xach 0:82a02991476c 15 xraw0 = _spi.write(0x0);
Xach 0:82a02991476c 16 xraw1 = _spi.write(0x0);
Xach 0:82a02991476c 17 yraw0 = _spi.write(0x0);
Xach 0:82a02991476c 18 yraw1 = _spi.write(0x0);
Xach 0:82a02991476c 19 zraw0 = _spi.write(0x0);
Xach 0:82a02991476c 20 zraw1 = _spi.write(0x0);
Xach 0:82a02991476c 21 _cs = 1;
Xach 0:82a02991476c 22 __enable_irq();
Xach 0:82a02991476c 23
Xach 0:82a02991476c 24 //pc.printf(" X1=%i, X0=%i, Y1=%i, Y0=%i, Z1=%i, Z0=%i, \n",xraw1,xraw0,yraw1,yraw0,zraw1,zraw0);
Xach 0:82a02991476c 25
Xach 0:82a02991476c 26 // pc.printf("%d %d %d",xaxis,yaxis,zaxis);
Xach 0:82a02991476c 27 }
Xach 0:82a02991476c 28
Xach 0:82a02991476c 29 void convertAccel(){
Xach 0:82a02991476c 30 xaxis = (float)(xraw0 | (xraw1 << 8))/250.0;//(((xraw1 & 0x01) | ((xraw1&0x01)<<3) )<< 8));
Xach 0:82a02991476c 31 yaxis = (float)(yraw0 | (yraw1 << 8))/250.0;//(((yraw1 & 0x01) | ((yraw1&0x01)<<3) ) << 8));
Xach 0:82a02991476c 32 zaxis = (float)(zraw0 | (zraw1 << 8))/250.0;//(((zraw1 & 0x01) | ((zraw1&0x01)<<3) ) << 8));
Xach 0:82a02991476c 33
Xach 0:82a02991476c 34 }
Xach 0:82a02991476c 35
Xach 0:82a02991476c 36
Xach 0:82a02991476c 37 void initAccel() {
Xach 0:82a02991476c 38
Xach 0:82a02991476c 39 // Taken from datasheet
Xach 0:82a02991476c 40 // 8 bit data
Xach 0:82a02991476c 41 // High steady state clock
Xach 0:82a02991476c 42 // Second edge capture
Xach 0:82a02991476c 43 _spi.format(8,3);
Xach 0:82a02991476c 44
Xach 0:82a02991476c 45 // 5MHz clock rate
Xach 0:82a02991476c 46 _spi.frequency(1000000);
Xach 0:82a02991476c 47
Xach 0:82a02991476c 48 // Select the device, active low chip select
Xach 0:82a02991476c 49 _cs = 0;
Xach 0:82a02991476c 50
Xach 0:82a02991476c 51 _spi.write(0x31); // set data_format to 0b00000001 to turn on 4 wire mode with act high interrupts,10 bit mode and +- 4g operation
Xach 0:82a02991476c 52 _spi.write(0x0B);
Xach 0:82a02991476c 53 // end this transfer
Xach 0:82a02991476c 54 _cs = 1;
Xach 0:82a02991476c 55
Xach 0:82a02991476c 56
Xach 0:82a02991476c 57 wait (0.01); //this is stupid, get rid of it
Xach 0:82a02991476c 58
Xach 0:82a02991476c 59
Xach 0:82a02991476c 60 // new transfer
Xach 0:82a02991476c 61 _cs = 0;
Xach 0:82a02991476c 62
Xach 0:82a02991476c 63 _spi.write(0x5D); // start writing at 0x1D but turn on sequential writes so we can set everything in one fowl swoop
Xach 0:82a02991476c 64
Xach 0:82a02991476c 65 _spi.write(0xFF); // set THRESH_TAP - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 66 _spi.write(0x00); // set OFSX
Xach 0:82a02991476c 67 _spi.write(0x00); // set OFSY
Xach 0:82a02991476c 68 _spi.write(0x00); // set OFSZ
Xach 0:82a02991476c 69 _spi.write(0xFF); // set DUR (min duration to be considered a TAP event)
Xach 0:82a02991476c 70 _spi.write(0x00); // set Latent (max duration between TAP events)
Xach 0:82a02991476c 71 _spi.write(0x00); // set Window (max time after a Latency to be in the same TAP window)
Xach 0:82a02991476c 72 _spi.write(0x00); // set THRESH_ACT - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 73 _spi.write(0x00); // set THRESH_INACT - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 74 _spi.write(0xFF); // set TIME_INACT - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 75 _spi.write(0x00); // set ACT_INACT_CTL - AC/DC coupling for activity registers + enabling/disabling in x,y.z - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 76 _spi.write(0xFF); // set THRESH_FF (free fall) - only used when corresponding interrupt is enabled
Xach 0:82a02991476c 77 _spi.write(0xFF); // set TIME_FF (free fall)
Xach 0:82a02991476c 78 _spi.write(0x00); // set TAP_AXES (with 0x00 we are disabling all tap detection)
Xach 0:82a02991476c 79 // end this transfer
Xach 0:82a02991476c 80 _cs = 1;
Xach 0:82a02991476c 81
Xach 0:82a02991476c 82 // start another multiple byte transfer
Xach 0:82a02991476c 83 _cs = 0;
Xach 0:82a02991476c 84 _spi.write(0x6C); // another sequential write starting at 0x2C
Xach 0:82a02991476c 85 _spi.write(0x0E); // set BW_RATE to disable low power and turn on max bandwidth
Xach 0:82a02991476c 86 _spi.write(0x0B); // set // set PWR_CTRL to start measurments, and not be asleep , and to do 8hz measurements if asleep
Xach 0:82a02991476c 87 _spi.write(0x00); // set INT_ENABLE
Xach 0:82a02991476c 88 _spi.write(0x00); // set INT_MAP - send all interrupts to INT1 but doesnt really matter because we wont use this (yet)
Xach 0:82a02991476c 89 _cs = 1;
Xach 0:82a02991476c 90
Xach 0:82a02991476c 91 // start new transfer
Xach 0:82a02991476c 92 _cs = 0;
Xach 0:82a02991476c 93 _spi.write(0x38); // FIFO_CTL
Xach 0:82a02991476c 94 _spi.write(0x00); // disable the FIFO
Xach 0:82a02991476c 95 _cs = 1;
Xach 0:82a02991476c 96
Xach 0:82a02991476c 97 _cs = 0;
Xach 0:82a02991476c 98 _spi.write(0x80);
Xach 0:82a02991476c 99 wait(.1);
Xach 0:82a02991476c 100 devid = _spi.write(0x0);
Xach 0:82a02991476c 101 _cs = 1;
Xach 0:82a02991476c 102 accel.attach_us(&accel_ISR, 625);
Xach 0:82a02991476c 103 accelRdy = false;
Xach 0:82a02991476c 104 }