tetsuya noguchi / Mbed 2 deprecated ov7670_CQ

CQ出版 Interface記事用サンプル。 トラ技カメラ+FIFOからデータを得て、 エリア判定後、デバイスに保存

Dependencies:   SDFileSystem mbed

ov7670.h@4:ed062dc75c52, 2014-02-04 (annotated)

Committer:
TETSUYA
Date:
Tue Feb 04 05:42:17 2014 +0000
Revision:
4:ed062dc75c52
Parent:
0:1648bb4e70e5 
???????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
TETSUYA 0:1648bb4e70e5 1 #include "mbed.h"
TETSUYA 0:1648bb4e70e5 2 #include "ov7670reg.h"
TETSUYA 0:1648bb4e70e5 3
TETSUYA 0:1648bb4e70e5 4 #define OV7670_WRITE (0x42)
TETSUYA 0:1648bb4e70e5 5 #define OV7670_READ (0x43)
TETSUYA 0:1648bb4e70e5 6 #define OV7670_WRITEWAIT (20)
TETSUYA 0:1648bb4e70e5 7 #define OV7670_NOACK (0)
TETSUYA 0:1648bb4e70e5 8 #define OV7670_REGMAX (201)
TETSUYA 0:1648bb4e70e5 9 #define OV7670_I2CFREQ (50000)
TETSUYA 0:1648bb4e70e5 10
TETSUYA 0:1648bb4e70e5 11 //
TETSUYA 0:1648bb4e70e5 12 // OV7670 + FIFO AL422B camera board test
TETSUYA 0:1648bb4e70e5 13 //
TETSUYA 0:1648bb4e70e5 14 class OV7670
TETSUYA 0:1648bb4e70e5 15 {
TETSUYA 0:1648bb4e70e5 16 public:
TETSUYA 0:1648bb4e70e5 17 I2C camera;
TETSUYA 0:1648bb4e70e5 18 InterruptIn vsync,href;
TETSUYA 0:1648bb4e70e5 19 DigitalOut wen;
TETSUYA 0:1648bb4e70e5 20 BusIn data;
TETSUYA 0:1648bb4e70e5 21 DigitalOut rrst,oe,rclk;
TETSUYA 0:1648bb4e70e5 22 volatile int LineCounter;
TETSUYA 0:1648bb4e70e5 23 volatile int LastLines;
TETSUYA 0:1648bb4e70e5 24 volatile bool CaptureReq;
TETSUYA 0:1648bb4e70e5 25 volatile bool Busy;
TETSUYA 0:1648bb4e70e5 26 volatile bool Done;
TETSUYA 0:1648bb4e70e5 27
TETSUYA 0:1648bb4e70e5 28 OV7670(
TETSUYA 0:1648bb4e70e5 29 PinName sda,// Camera I2C port
TETSUYA 0:1648bb4e70e5 30 PinName scl,// Camera I2C port
TETSUYA 0:1648bb4e70e5 31 PinName vs, // VSYNC
TETSUYA 0:1648bb4e70e5 32 PinName hr, // HREF
TETSUYA 0:1648bb4e70e5 33 PinName we, // WEN
TETSUYA 0:1648bb4e70e5 34 PinName d7, // D7
TETSUYA 0:1648bb4e70e5 35 PinName d6, // D6
TETSUYA 0:1648bb4e70e5 36 PinName d5, // D5
TETSUYA 0:1648bb4e70e5 37 PinName d4, // D4
TETSUYA 0:1648bb4e70e5 38 PinName d3, // D3
TETSUYA 0:1648bb4e70e5 39 PinName d2, // D2
TETSUYA 0:1648bb4e70e5 40 PinName d1, // D1
TETSUYA 0:1648bb4e70e5 41 PinName d0, // D0
TETSUYA 0:1648bb4e70e5 42 PinName rt, // /RRST
TETSUYA 0:1648bb4e70e5 43 PinName o, // /OE
TETSUYA 0:1648bb4e70e5 44 PinName rc // RCLK
TETSUYA 0:1648bb4e70e5 45 ) : camera(sda,scl),vsync(vs),href(hr),wen(we),data(d0,d1,d2,d3,d4,d5,d6,d7),rrst(rt),oe(o),rclk(rc)
TETSUYA 0:1648bb4e70e5 46 {
TETSUYA 0:1648bb4e70e5 47 camera.stop();
TETSUYA 0:1648bb4e70e5 48 camera.frequency(OV7670_I2CFREQ);
TETSUYA 0:1648bb4e70e5 49 vsync.fall(this,&OV7670::VsyncHandler);
TETSUYA 0:1648bb4e70e5 50 href.rise(this,&OV7670::HrefHandler);
TETSUYA 0:1648bb4e70e5 51 CaptureReq = false;
TETSUYA 0:1648bb4e70e5 52 Busy = false;
TETSUYA 0:1648bb4e70e5 53 Done = false;
TETSUYA 0:1648bb4e70e5 54 LineCounter = 0;
TETSUYA 0:1648bb4e70e5 55 rrst = 1;
TETSUYA 0:1648bb4e70e5 56 oe = 1;
TETSUYA 0:1648bb4e70e5 57 rclk = 1;
TETSUYA 0:1648bb4e70e5 58 wen = 0;
TETSUYA 0:1648bb4e70e5 59 }
TETSUYA 0:1648bb4e70e5 60
TETSUYA 0:1648bb4e70e5 61 // capture request
TETSUYA 0:1648bb4e70e5 62 void CaptureNext(void)
TETSUYA 0:1648bb4e70e5 63 {
TETSUYA 0:1648bb4e70e5 64 CaptureReq = true;
TETSUYA 0:1648bb4e70e5 65 Busy = true;
TETSUYA 0:1648bb4e70e5 66 }
TETSUYA 0:1648bb4e70e5 67
TETSUYA 0:1648bb4e70e5 68 // capture done? (with clear)
TETSUYA 0:1648bb4e70e5 69 bool CaptureDone(void)
TETSUYA 0:1648bb4e70e5 70 {
TETSUYA 0:1648bb4e70e5 71 bool result;
TETSUYA 0:1648bb4e70e5 72 if (Busy) {
TETSUYA 0:1648bb4e70e5 73 result = false;
TETSUYA 0:1648bb4e70e5 74 } else {
TETSUYA 0:1648bb4e70e5 75 result = Done;
TETSUYA 0:1648bb4e70e5 76 Done = false;
TETSUYA 0:1648bb4e70e5 77 }
TETSUYA 0:1648bb4e70e5 78 return result;
TETSUYA 0:1648bb4e70e5 79 }
TETSUYA 0:1648bb4e70e5 80
TETSUYA 0:1648bb4e70e5 81 // write to camera
TETSUYA 0:1648bb4e70e5 82 void WriteReg(int addr,int data)
TETSUYA 0:1648bb4e70e5 83 {
TETSUYA 0:1648bb4e70e5 84 // WRITE 0x42,ADDR,DATA
TETSUYA 0:1648bb4e70e5 85 camera.start();
TETSUYA 0:1648bb4e70e5 86 camera.write(OV7670_WRITE);
TETSUYA 0:1648bb4e70e5 87 wait_us(OV7670_WRITEWAIT);
TETSUYA 0:1648bb4e70e5 88 camera.write(addr);
TETSUYA 0:1648bb4e70e5 89 wait_us(OV7670_WRITEWAIT);
TETSUYA 0:1648bb4e70e5 90 camera.write(data);
TETSUYA 0:1648bb4e70e5 91 camera.stop();
TETSUYA 0:1648bb4e70e5 92 }
TETSUYA 0:1648bb4e70e5 93
TETSUYA 0:1648bb4e70e5 94 // read from camera
TETSUYA 0:1648bb4e70e5 95 int ReadReg(int addr)
TETSUYA 0:1648bb4e70e5 96 {
TETSUYA 0:1648bb4e70e5 97 int data;
TETSUYA 0:1648bb4e70e5 98
TETSUYA 0:1648bb4e70e5 99 // WRITE 0x42,ADDR
TETSUYA 0:1648bb4e70e5 100 camera.start();
TETSUYA 0:1648bb4e70e5 101 camera.write(OV7670_WRITE);
TETSUYA 0:1648bb4e70e5 102 wait_us(OV7670_WRITEWAIT);
TETSUYA 0:1648bb4e70e5 103 camera.write(addr);
TETSUYA 0:1648bb4e70e5 104 camera.stop();
TETSUYA 0:1648bb4e70e5 105 wait_us(OV7670_WRITEWAIT);
TETSUYA 0:1648bb4e70e5 106
TETSUYA 0:1648bb4e70e5 107 // WRITE 0x43,READ
TETSUYA 0:1648bb4e70e5 108 camera.start();
TETSUYA 0:1648bb4e70e5 109 camera.write(OV7670_READ);
TETSUYA 0:1648bb4e70e5 110 wait_us(OV7670_WRITEWAIT);
TETSUYA 0:1648bb4e70e5 111 data = camera.read(OV7670_NOACK);
TETSUYA 0:1648bb4e70e5 112 camera.stop();
TETSUYA 0:1648bb4e70e5 113
TETSUYA 0:1648bb4e70e5 114 return data;
TETSUYA 0:1648bb4e70e5 115 }
TETSUYA 0:1648bb4e70e5 116
TETSUYA 0:1648bb4e70e5 117 // print register
TETSUYA 0:1648bb4e70e5 118 void PrintRegister(void) {
TETSUYA 0:1648bb4e70e5 119 printf("AD : +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F");
TETSUYA 0:1648bb4e70e5 120 for (int i=0;i<OV7670_REGMAX;i++) {
TETSUYA 0:1648bb4e70e5 121 int data;
TETSUYA 0:1648bb4e70e5 122 data = ReadReg(i); // READ REG
TETSUYA 0:1648bb4e70e5 123 if ((i & 0x0F) == 0) {
TETSUYA 0:1648bb4e70e5 124 printf("\r\n%02X : ",i);
TETSUYA 0:1648bb4e70e5 125 }
TETSUYA 0:1648bb4e70e5 126 printf("%02X ",data);
TETSUYA 0:1648bb4e70e5 127 }
TETSUYA 0:1648bb4e70e5 128 printf("\r\n");
TETSUYA 0:1648bb4e70e5 129 }
TETSUYA 0:1648bb4e70e5 130
TETSUYA 0:1648bb4e70e5 131 void Reset(void) {
TETSUYA 0:1648bb4e70e5 132 WriteReg(REG_COM7,COM7_RESET); // RESET CAMERA
TETSUYA 0:1648bb4e70e5 133 wait_ms(200);
TETSUYA 0:1648bb4e70e5 134 }
TETSUYA 0:1648bb4e70e5 135
TETSUYA 0:1648bb4e70e5 136 void InitForFIFOWriteReset(void) {
TETSUYA 0:1648bb4e70e5 137 WriteReg(REG_COM10, COM10_VS_NEG);
TETSUYA 0:1648bb4e70e5 138 }
TETSUYA 0:1648bb4e70e5 139
TETSUYA 0:1648bb4e70e5 140 void InitSetColorbar(void) {
TETSUYA 0:1648bb4e70e5 141 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 142 // color bar
TETSUYA 0:1648bb4e70e5 143 WriteReg(REG_COM17, reg_com7|COM17_CBAR);
TETSUYA 0:1648bb4e70e5 144 }
TETSUYA 0:1648bb4e70e5 145
TETSUYA 0:1648bb4e70e5 146 void InitDefaultReg(bool flipv,bool fliph) {
TETSUYA 0:1648bb4e70e5 147 // Gamma curve values
TETSUYA 0:1648bb4e70e5 148 WriteReg(0x7a, 0x20);
TETSUYA 0:1648bb4e70e5 149 WriteReg(0x7b, 0x10);
TETSUYA 0:1648bb4e70e5 150 WriteReg(0x7c, 0x1e);
TETSUYA 0:1648bb4e70e5 151 WriteReg(0x7d, 0x35);
TETSUYA 0:1648bb4e70e5 152 WriteReg(0x7e, 0x5a);
TETSUYA 0:1648bb4e70e5 153 WriteReg(0x7f, 0x69);
TETSUYA 0:1648bb4e70e5 154 WriteReg(0x80, 0x76);
TETSUYA 0:1648bb4e70e5 155 WriteReg(0x81, 0x80);
TETSUYA 0:1648bb4e70e5 156 WriteReg(0x82, 0x88);
TETSUYA 0:1648bb4e70e5 157 WriteReg(0x83, 0x8f);
TETSUYA 0:1648bb4e70e5 158 WriteReg(0x84, 0x96);
TETSUYA 0:1648bb4e70e5 159 WriteReg(0x85, 0xa3);
TETSUYA 0:1648bb4e70e5 160 WriteReg(0x86, 0xaf);
TETSUYA 0:1648bb4e70e5 161 WriteReg(0x87, 0xc4);
TETSUYA 0:1648bb4e70e5 162 WriteReg(0x88, 0xd7);
TETSUYA 0:1648bb4e70e5 163 WriteReg(0x89, 0xe8);
TETSUYA 0:1648bb4e70e5 164
TETSUYA 0:1648bb4e70e5 165 // AGC and AEC parameters. Note we start by disabling those features,
TETSUYA 0:1648bb4e70e5 166 //then turn them only after tweaking the values.
TETSUYA 0:1648bb4e70e5 167 //WriteReg(REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT);
TETSUYA 0:1648bb4e70e5 168 //WriteReg(REG_COM8, COM8_AECSTEP | COM8_BFILT | COM8_AWB | COM8_AEC );
TETSUYA 0:1648bb4e70e5 169 WriteReg(REG_COM8, COM8_AECSTEP | COM8_BFILT | COM8_AGC | COM8_AEC );
TETSUYA 0:1648bb4e70e5 170 //WriteReg(REG_COM8, COM8_AECSTEP | COM8_BFILT | COM8_AGC | COM8_AWB );
TETSUYA 0:1648bb4e70e5 171
TETSUYA 0:1648bb4e70e5 172 WriteReg(REG_GAIN, 0);
TETSUYA 0:1648bb4e70e5 173 WriteReg(REG_AECH, 0);
TETSUYA 0:1648bb4e70e5 174 WriteReg(REG_COM4, 0x40);
TETSUYA 0:1648bb4e70e5 175 // magic reserved bit
TETSUYA 0:1648bb4e70e5 176 WriteReg(REG_COM9, 0x18);
TETSUYA 0:1648bb4e70e5 177 // 4x gain + magic rsvd bit
TETSUYA 0:1648bb4e70e5 178 WriteReg(REG_BD50MAX, 0x05);
TETSUYA 0:1648bb4e70e5 179 WriteReg(REG_BD60MAX, 0x07);
TETSUYA 0:1648bb4e70e5 180 WriteReg(REG_AEW, 0x95);
TETSUYA 0:1648bb4e70e5 181 WriteReg(REG_AEB, 0x33);
TETSUYA 0:1648bb4e70e5 182 WriteReg(REG_VPT, 0xe3);
TETSUYA 0:1648bb4e70e5 183 WriteReg(REG_HAECC1, 0x78);
TETSUYA 0:1648bb4e70e5 184 WriteReg(REG_HAECC2, 0x68);
TETSUYA 0:1648bb4e70e5 185 WriteReg(0xa1, 0x03);
TETSUYA 0:1648bb4e70e5 186 // magic
TETSUYA 0:1648bb4e70e5 187 WriteReg(REG_HAECC3, 0xd8);
TETSUYA 0:1648bb4e70e5 188 WriteReg(REG_HAECC4, 0xd8);
TETSUYA 0:1648bb4e70e5 189 WriteReg(REG_HAECC5, 0xf0);
TETSUYA 0:1648bb4e70e5 190 WriteReg(REG_HAECC6, 0x90);
TETSUYA 0:1648bb4e70e5 191 WriteReg(REG_HAECC7, 0x94);
TETSUYA 0:1648bb4e70e5 192 WriteReg(REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC);
TETSUYA 0:1648bb4e70e5 193
TETSUYA 0:1648bb4e70e5 194 // Almost all of these are magic "reserved" values.
TETSUYA 0:1648bb4e70e5 195 WriteReg(REG_COM5, 0x61);
TETSUYA 0:1648bb4e70e5 196 WriteReg(REG_COM6, 0x4b);
TETSUYA 0:1648bb4e70e5 197 WriteReg(0x16, 0x02);
TETSUYA 0:1648bb4e70e5 198 WriteReg(REG_MVFP, 0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0));
TETSUYA 0:1648bb4e70e5 199 WriteReg(0x21, 0x02);
TETSUYA 0:1648bb4e70e5 200 WriteReg(0x22, 0x91);
TETSUYA 0:1648bb4e70e5 201 WriteReg(0x29, 0x07);
TETSUYA 0:1648bb4e70e5 202 WriteReg(0x33, 0x0b);
TETSUYA 0:1648bb4e70e5 203 WriteReg(0x35, 0x0b);
TETSUYA 0:1648bb4e70e5 204 WriteReg(0x37, 0x1d);
TETSUYA 0:1648bb4e70e5 205 WriteReg(0x38, 0x71);
TETSUYA 0:1648bb4e70e5 206 WriteReg(0x39, 0x2a);
TETSUYA 0:1648bb4e70e5 207 WriteReg(REG_COM12, 0x78);
TETSUYA 0:1648bb4e70e5 208 WriteReg(0x4d, 0x40);
TETSUYA 0:1648bb4e70e5 209 WriteReg(0x4e, 0x20);
TETSUYA 0:1648bb4e70e5 210 WriteReg(REG_GFIX, 0);
TETSUYA 0:1648bb4e70e5 211 WriteReg(0x6b, 0x0a);
TETSUYA 0:1648bb4e70e5 212 WriteReg(0x74, 0x10);
TETSUYA 0:1648bb4e70e5 213 WriteReg(0x8d, 0x4f);
TETSUYA 0:1648bb4e70e5 214 WriteReg(0x8e, 0);
TETSUYA 0:1648bb4e70e5 215 WriteReg(0x8f, 0);
TETSUYA 0:1648bb4e70e5 216 WriteReg(0x90, 0);
TETSUYA 0:1648bb4e70e5 217 WriteReg(0x91, 0);
TETSUYA 0:1648bb4e70e5 218 WriteReg(0x96, 0);
TETSUYA 0:1648bb4e70e5 219 WriteReg(0x9a, 0);
TETSUYA 0:1648bb4e70e5 220 WriteReg(0xb0, 0x84);
TETSUYA 0:1648bb4e70e5 221 WriteReg(0xb1, 0x0c);
TETSUYA 0:1648bb4e70e5 222 WriteReg(0xb2, 0x0e);
TETSUYA 0:1648bb4e70e5 223 WriteReg(0xb3, 0x82);
TETSUYA 0:1648bb4e70e5 224 WriteReg(0xb8, 0x0a);
TETSUYA 0:1648bb4e70e5 225
TETSUYA 0:1648bb4e70e5 226 // More reserved magic, some of which tweaks white balance
TETSUYA 0:1648bb4e70e5 227 WriteReg(0x43, 0x0a);
TETSUYA 0:1648bb4e70e5 228 WriteReg(0x44, 0xf0);
TETSUYA 0:1648bb4e70e5 229 WriteReg(0x45, 0x34);
TETSUYA 0:1648bb4e70e5 230 WriteReg(0x46, 0x58);
TETSUYA 0:1648bb4e70e5 231 WriteReg(0x47, 0x28);
TETSUYA 0:1648bb4e70e5 232 WriteReg(0x48, 0x3a);
TETSUYA 0:1648bb4e70e5 233 WriteReg(0x59, 0x88);
TETSUYA 0:1648bb4e70e5 234 WriteReg(0x5a, 0x88);
TETSUYA 0:1648bb4e70e5 235 WriteReg(0x5b, 0x44);
TETSUYA 0:1648bb4e70e5 236 WriteReg(0x5c, 0x67);
TETSUYA 0:1648bb4e70e5 237 WriteReg(0x5d, 0x49);
TETSUYA 0:1648bb4e70e5 238 WriteReg(0x5e, 0x0e);
TETSUYA 0:1648bb4e70e5 239 WriteReg(0x6c, 0x0a);
TETSUYA 0:1648bb4e70e5 240 WriteReg(0x6d, 0x55);
TETSUYA 0:1648bb4e70e5 241 WriteReg(0x6e, 0x11);
TETSUYA 0:1648bb4e70e5 242 WriteReg(0x6f, 0x9f);
TETSUYA 0:1648bb4e70e5 243 // "9e for advance AWB"
TETSUYA 0:1648bb4e70e5 244 WriteReg(0x6a, 0x40);
TETSUYA 0:1648bb4e70e5 245 WriteReg(REG_BLUE, 0x40);
TETSUYA 0:1648bb4e70e5 246 WriteReg(REG_RED, 0x60);
TETSUYA 0:1648bb4e70e5 247 WriteReg(REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB);
TETSUYA 0:1648bb4e70e5 248
TETSUYA 0:1648bb4e70e5 249 // Matrix coefficients
TETSUYA 0:1648bb4e70e5 250 WriteReg(0x4f, 0x80);
TETSUYA 0:1648bb4e70e5 251 WriteReg(0x50, 0x80);
TETSUYA 0:1648bb4e70e5 252 WriteReg(0x51, 0);
TETSUYA 0:1648bb4e70e5 253 WriteReg(0x52, 0x22);
TETSUYA 0:1648bb4e70e5 254 WriteReg(0x53, 0x5e);
TETSUYA 0:1648bb4e70e5 255 WriteReg(0x54, 0x80);
TETSUYA 0:1648bb4e70e5 256 WriteReg(0x58, 0x9e);
TETSUYA 0:1648bb4e70e5 257
TETSUYA 0:1648bb4e70e5 258 WriteReg(REG_COM16, COM16_AWBGAIN);
TETSUYA 0:1648bb4e70e5 259 WriteReg(REG_EDGE, 0);
TETSUYA 0:1648bb4e70e5 260 WriteReg(0x75, 0x05);
TETSUYA 0:1648bb4e70e5 261 WriteReg(0x76, 0xe1);
TETSUYA 0:1648bb4e70e5 262 WriteReg(0x4c, 0);
TETSUYA 0:1648bb4e70e5 263 WriteReg(0x77, 0x01);
TETSUYA 0:1648bb4e70e5 264 WriteReg(0x4b, 0x09);
TETSUYA 0:1648bb4e70e5 265 WriteReg(0xc9, 0x60);
TETSUYA 0:1648bb4e70e5 266 WriteReg(REG_COM16, 0x38);
TETSUYA 0:1648bb4e70e5 267 WriteReg(0x56, 0x40);
TETSUYA 0:1648bb4e70e5 268
TETSUYA 0:1648bb4e70e5 269 WriteReg(0x34, 0x11);
TETSUYA 0:1648bb4e70e5 270 WriteReg(REG_COM11, COM11_EXP|COM11_HZAUTO_ON);
TETSUYA 0:1648bb4e70e5 271 WriteReg(0xa4, 0x88);
TETSUYA 0:1648bb4e70e5 272 WriteReg(0x96, 0);
TETSUYA 0:1648bb4e70e5 273 WriteReg(0x97, 0x30);
TETSUYA 0:1648bb4e70e5 274 WriteReg(0x98, 0x20);
TETSUYA 0:1648bb4e70e5 275 WriteReg(0x99, 0x30);
TETSUYA 0:1648bb4e70e5 276 WriteReg(0x9a, 0x84);
TETSUYA 0:1648bb4e70e5 277 WriteReg(0x9b, 0x29);
TETSUYA 0:1648bb4e70e5 278 WriteReg(0x9c, 0x03);
TETSUYA 0:1648bb4e70e5 279 WriteReg(0x9d, 0x4c);
TETSUYA 0:1648bb4e70e5 280 WriteReg(0x9e, 0x3f);
TETSUYA 0:1648bb4e70e5 281 WriteReg(0x78, 0x04);
TETSUYA 0:1648bb4e70e5 282
TETSUYA 0:1648bb4e70e5 283 // Extra-weird stuff. Some sort of multiplexor register
TETSUYA 0:1648bb4e70e5 284 WriteReg(0x79, 0x01);
TETSUYA 0:1648bb4e70e5 285 WriteReg(0xc8, 0xf0);
TETSUYA 0:1648bb4e70e5 286 WriteReg(0x79, 0x0f);
TETSUYA 0:1648bb4e70e5 287 WriteReg(0xc8, 0x00);
TETSUYA 0:1648bb4e70e5 288 WriteReg(0x79, 0x10);
TETSUYA 0:1648bb4e70e5 289 WriteReg(0xc8, 0x7e);
TETSUYA 0:1648bb4e70e5 290 WriteReg(0x79, 0x0a);
TETSUYA 0:1648bb4e70e5 291 WriteReg(0xc8, 0x80);
TETSUYA 0:1648bb4e70e5 292 WriteReg(0x79, 0x0b);
TETSUYA 0:1648bb4e70e5 293 WriteReg(0xc8, 0x01);
TETSUYA 0:1648bb4e70e5 294 WriteReg(0x79, 0x0c);
TETSUYA 0:1648bb4e70e5 295 WriteReg(0xc8, 0x0f);
TETSUYA 0:1648bb4e70e5 296 WriteReg(0x79, 0x0d);
TETSUYA 0:1648bb4e70e5 297 WriteReg(0xc8, 0x20);
TETSUYA 0:1648bb4e70e5 298 WriteReg(0x79, 0x09);
TETSUYA 0:1648bb4e70e5 299 WriteReg(0xc8, 0x80);
TETSUYA 0:1648bb4e70e5 300 WriteReg(0x79, 0x02);
TETSUYA 0:1648bb4e70e5 301 WriteReg(0xc8, 0xc0);
TETSUYA 0:1648bb4e70e5 302 WriteReg(0x79, 0x03);
TETSUYA 0:1648bb4e70e5 303 WriteReg(0xc8, 0x40);
TETSUYA 0:1648bb4e70e5 304 WriteReg(0x79, 0x05);
TETSUYA 0:1648bb4e70e5 305 WriteReg(0xc8, 0x30);
TETSUYA 0:1648bb4e70e5 306 WriteReg(0x79, 0x26);
TETSUYA 0:1648bb4e70e5 307 }
TETSUYA 0:1648bb4e70e5 308
TETSUYA 0:1648bb4e70e5 309 void InitRGB444(void){
TETSUYA 0:1648bb4e70e5 310 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 311
TETSUYA 0:1648bb4e70e5 312 WriteReg(REG_COM7, reg_com7|COM7_RGB);
TETSUYA 0:1648bb4e70e5 313 WriteReg(REG_RGB444, RGB444_ENABLE|RGB444_XBGR);
TETSUYA 0:1648bb4e70e5 314 WriteReg(REG_COM15, COM15_R01FE|COM15_RGB444);
TETSUYA 0:1648bb4e70e5 315
TETSUYA 0:1648bb4e70e5 316 WriteReg(REG_COM1, 0x40); // Magic reserved bit
TETSUYA 0:1648bb4e70e5 317 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
TETSUYA 0:1648bb4e70e5 318 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
TETSUYA 0:1648bb4e70e5 319 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
TETSUYA 0:1648bb4e70e5 320 WriteReg(0x51, 0x00); // vb
TETSUYA 0:1648bb4e70e5 321 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
TETSUYA 0:1648bb4e70e5 322 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
TETSUYA 0:1648bb4e70e5 323 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
TETSUYA 0:1648bb4e70e5 324 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2); // Magic rsvd bit
TETSUYA 0:1648bb4e70e5 325
TETSUYA 0:1648bb4e70e5 326 WriteReg(REG_TSLB, 0x04);
TETSUYA 0:1648bb4e70e5 327 }
TETSUYA 0:1648bb4e70e5 328
TETSUYA 0:1648bb4e70e5 329 void InitRGB555(void){
TETSUYA 0:1648bb4e70e5 330 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 331
TETSUYA 0:1648bb4e70e5 332 WriteReg(REG_COM7, reg_com7|COM7_RGB);
TETSUYA 0:1648bb4e70e5 333 WriteReg(REG_RGB444, RGB444_DISABLE);
TETSUYA 0:1648bb4e70e5 334 WriteReg(REG_COM15, COM15_RGB555|COM15_R00FF);
TETSUYA 0:1648bb4e70e5 335
TETSUYA 0:1648bb4e70e5 336 WriteReg(REG_TSLB, 0x04);
TETSUYA 0:1648bb4e70e5 337
TETSUYA 0:1648bb4e70e5 338 WriteReg(REG_COM1, 0x00);
TETSUYA 0:1648bb4e70e5 339 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
TETSUYA 0:1648bb4e70e5 340 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
TETSUYA 0:1648bb4e70e5 341 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
TETSUYA 0:1648bb4e70e5 342 WriteReg(0x51, 0x00); // vb
TETSUYA 0:1648bb4e70e5 343 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
TETSUYA 0:1648bb4e70e5 344 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
TETSUYA 0:1648bb4e70e5 345 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
TETSUYA 0:1648bb4e70e5 346 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT);
TETSUYA 0:1648bb4e70e5 347 }
TETSUYA 0:1648bb4e70e5 348
TETSUYA 0:1648bb4e70e5 349 void InitRGB565(void){
TETSUYA 0:1648bb4e70e5 350 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 351
TETSUYA 0:1648bb4e70e5 352 WriteReg(REG_COM7, reg_com7|COM7_RGB);
TETSUYA 0:1648bb4e70e5 353 WriteReg(REG_RGB444, RGB444_DISABLE);
TETSUYA 0:1648bb4e70e5 354 WriteReg(REG_COM15, COM15_R00FF|COM15_RGB565);
TETSUYA 0:1648bb4e70e5 355
TETSUYA 0:1648bb4e70e5 356 WriteReg(REG_TSLB, 0x04);
TETSUYA 0:1648bb4e70e5 357
TETSUYA 0:1648bb4e70e5 358 WriteReg(REG_COM1, 0x00);
TETSUYA 0:1648bb4e70e5 359 WriteReg(REG_COM9, 0x38); // 16x gain ceiling; 0x8 is reserved bit
TETSUYA 0:1648bb4e70e5 360 WriteReg(0x4f, 0xb3); // "matrix coefficient 1"
TETSUYA 0:1648bb4e70e5 361 WriteReg(0x50, 0xb3); // "matrix coefficient 2"
TETSUYA 0:1648bb4e70e5 362 WriteReg(0x51, 0x00); // vb
TETSUYA 0:1648bb4e70e5 363 WriteReg(0x52, 0x3d); // "matrix coefficient 4"
TETSUYA 0:1648bb4e70e5 364 WriteReg(0x53, 0xa7); // "matrix coefficient 5"
TETSUYA 0:1648bb4e70e5 365 WriteReg(0x54, 0xe4); // "matrix coefficient 6"
TETSUYA 0:1648bb4e70e5 366 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT);
TETSUYA 0:1648bb4e70e5 367 }
TETSUYA 0:1648bb4e70e5 368
TETSUYA 0:1648bb4e70e5 369 void InitYUV(void){
TETSUYA 0:1648bb4e70e5 370 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 371
TETSUYA 0:1648bb4e70e5 372 WriteReg(REG_COM7, reg_com7|COM7_YUV);
TETSUYA 0:1648bb4e70e5 373 WriteReg(REG_RGB444, RGB444_DISABLE);
TETSUYA 0:1648bb4e70e5 374 WriteReg(REG_COM15, COM15_R00FF);
TETSUYA 0:1648bb4e70e5 375
TETSUYA 0:1648bb4e70e5 376 WriteReg(REG_TSLB, 0x04);
TETSUYA 0:1648bb4e70e5 377 // WriteReg(REG_TSLB, 0x14);
TETSUYA 0:1648bb4e70e5 378 // WriteReg(REG_MANU, 0x00);
TETSUYA 0:1648bb4e70e5 379 // WriteReg(REG_MANV, 0x00);
TETSUYA 0:1648bb4e70e5 380
TETSUYA 0:1648bb4e70e5 381 WriteReg(REG_COM1, 0x00);
TETSUYA 0:1648bb4e70e5 382 WriteReg(REG_COM9, 0x18); // 4x gain ceiling; 0x8 is reserved bit
TETSUYA 0:1648bb4e70e5 383 WriteReg(0x4f, 0x80); // "matrix coefficient 1"
TETSUYA 0:1648bb4e70e5 384 WriteReg(0x50, 0x80); // "matrix coefficient 2"
TETSUYA 0:1648bb4e70e5 385 WriteReg(0x51, 0x00); // vb
TETSUYA 0:1648bb4e70e5 386 WriteReg(0x52, 0x22); // "matrix coefficient 4"
TETSUYA 0:1648bb4e70e5 387 WriteReg(0x53, 0x5e); // "matrix coefficient 5"
TETSUYA 0:1648bb4e70e5 388 WriteReg(0x54, 0x80); // "matrix coefficient 6"
TETSUYA 0:1648bb4e70e5 389 WriteReg(REG_COM13, COM13_GAMMA|COM13_UVSAT|COM13_UVSWAP);
TETSUYA 0:1648bb4e70e5 390 }
TETSUYA 0:1648bb4e70e5 391
TETSUYA 0:1648bb4e70e5 392 void InitBayerRGB(void){
TETSUYA 0:1648bb4e70e5 393 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 394
TETSUYA 0:1648bb4e70e5 395 // odd line BGBG... even line GRGR...
TETSUYA 0:1648bb4e70e5 396 WriteReg(REG_COM7, reg_com7|COM7_BAYER);
TETSUYA 0:1648bb4e70e5 397 // odd line GBGB... even line RGRG...
TETSUYA 0:1648bb4e70e5 398 //WriteReg(REG_COM7, reg_com7|COM7_PBAYER);
TETSUYA 0:1648bb4e70e5 399
TETSUYA 0:1648bb4e70e5 400 WriteReg(REG_RGB444, RGB444_DISABLE);
TETSUYA 0:1648bb4e70e5 401 WriteReg(REG_COM15, COM15_R00FF);
TETSUYA 0:1648bb4e70e5 402
TETSUYA 0:1648bb4e70e5 403 WriteReg(REG_COM13, 0x08); /* No gamma, magic rsvd bit */
TETSUYA 0:1648bb4e70e5 404 WriteReg(REG_COM16, 0x3d); /* Edge enhancement, denoise */
TETSUYA 0:1648bb4e70e5 405 WriteReg(REG_REG76, 0xe1); /* Pix correction, magic rsvd */
TETSUYA 0:1648bb4e70e5 406
TETSUYA 0:1648bb4e70e5 407 WriteReg(REG_TSLB, 0x04);
TETSUYA 0:1648bb4e70e5 408 }
TETSUYA 0:1648bb4e70e5 409
TETSUYA 0:1648bb4e70e5 410 void InitVGA(void) {
TETSUYA 0:1648bb4e70e5 411 // VGA
TETSUYA 0:1648bb4e70e5 412 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 413
TETSUYA 0:1648bb4e70e5 414 WriteReg(REG_COM7,reg_com7|COM7_VGA);
TETSUYA 0:1648bb4e70e5 415
TETSUYA 0:1648bb4e70e5 416 WriteReg(REG_HSTART,HSTART_VGA);
TETSUYA 0:1648bb4e70e5 417 WriteReg(REG_HSTOP,HSTOP_VGA);
TETSUYA 0:1648bb4e70e5 418 WriteReg(REG_HREF,HREF_VGA);
TETSUYA 0:1648bb4e70e5 419 WriteReg(REG_VSTART,VSTART_VGA);
TETSUYA 0:1648bb4e70e5 420 WriteReg(REG_VSTOP,VSTOP_VGA);
TETSUYA 0:1648bb4e70e5 421 WriteReg(REG_VREF,VREF_VGA);
TETSUYA 0:1648bb4e70e5 422 WriteReg(REG_COM3, COM3_VGA);
TETSUYA 0:1648bb4e70e5 423 WriteReg(REG_COM14, COM14_VGA);
TETSUYA 0:1648bb4e70e5 424 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
TETSUYA 0:1648bb4e70e5 425 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
TETSUYA 0:1648bb4e70e5 426 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
TETSUYA 0:1648bb4e70e5 427 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
TETSUYA 0:1648bb4e70e5 428 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
TETSUYA 0:1648bb4e70e5 429 }
TETSUYA 0:1648bb4e70e5 430
TETSUYA 0:1648bb4e70e5 431 void InitFIFO_2bytes_color_nealy_limit_size(void) {
TETSUYA 0:1648bb4e70e5 432 // nealy FIFO limit 544x360
TETSUYA 0:1648bb4e70e5 433 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 434
TETSUYA 0:1648bb4e70e5 435 WriteReg(REG_COM7,reg_com7|COM7_VGA);
TETSUYA 0:1648bb4e70e5 436
TETSUYA 0:1648bb4e70e5 437 WriteReg(REG_HSTART,HSTART_VGA);
TETSUYA 0:1648bb4e70e5 438 WriteReg(REG_HSTOP,HSTOP_VGA);
TETSUYA 0:1648bb4e70e5 439 WriteReg(REG_HREF,HREF_VGA);
TETSUYA 0:1648bb4e70e5 440 WriteReg(REG_VSTART,VSTART_VGA);
TETSUYA 0:1648bb4e70e5 441 WriteReg(REG_VSTOP,VSTOP_VGA);
TETSUYA 0:1648bb4e70e5 442 WriteReg(REG_VREF,VREF_VGA);
TETSUYA 0:1648bb4e70e5 443 WriteReg(REG_COM3, COM3_VGA);
TETSUYA 0:1648bb4e70e5 444 WriteReg(REG_COM14, COM14_VGA);
TETSUYA 0:1648bb4e70e5 445 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
TETSUYA 0:1648bb4e70e5 446 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
TETSUYA 0:1648bb4e70e5 447 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
TETSUYA 0:1648bb4e70e5 448 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
TETSUYA 0:1648bb4e70e5 449 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
TETSUYA 0:1648bb4e70e5 450
TETSUYA 0:1648bb4e70e5 451 WriteReg(REG_HSTART, 0x17);
TETSUYA 0:1648bb4e70e5 452 WriteReg(REG_HSTOP, 0x5b);
TETSUYA 0:1648bb4e70e5 453 WriteReg(REG_VSTART, 0x12);
TETSUYA 0:1648bb4e70e5 454 WriteReg(REG_VSTOP, 0x6c);
TETSUYA 0:1648bb4e70e5 455 }
TETSUYA 0:1648bb4e70e5 456
TETSUYA 0:1648bb4e70e5 457 void InitVGA_3_4(void) {
TETSUYA 0:1648bb4e70e5 458 // VGA 3/4 -> 480x360
TETSUYA 0:1648bb4e70e5 459 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 460
TETSUYA 0:1648bb4e70e5 461 WriteReg(REG_COM7,reg_com7|COM7_VGA);
TETSUYA 0:1648bb4e70e5 462
TETSUYA 0:1648bb4e70e5 463 WriteReg(REG_HSTART,HSTART_VGA);
TETSUYA 0:1648bb4e70e5 464 WriteReg(REG_HSTOP,HSTOP_VGA);
TETSUYA 0:1648bb4e70e5 465 WriteReg(REG_HREF,HREF_VGA);
TETSUYA 0:1648bb4e70e5 466 WriteReg(REG_VSTART,VSTART_VGA);
TETSUYA 0:1648bb4e70e5 467 WriteReg(REG_VSTOP,VSTOP_VGA);
TETSUYA 0:1648bb4e70e5 468 WriteReg(REG_VREF,VREF_VGA);
TETSUYA 0:1648bb4e70e5 469 WriteReg(REG_COM3, COM3_VGA);
TETSUYA 0:1648bb4e70e5 470 WriteReg(REG_COM14, COM14_VGA);
TETSUYA 0:1648bb4e70e5 471 WriteReg(REG_SCALING_XSC, SCALING_XSC_VGA);
TETSUYA 0:1648bb4e70e5 472 WriteReg(REG_SCALING_YSC, SCALING_YSC_VGA);
TETSUYA 0:1648bb4e70e5 473 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_VGA);
TETSUYA 0:1648bb4e70e5 474 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_VGA);
TETSUYA 0:1648bb4e70e5 475 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_VGA);
TETSUYA 0:1648bb4e70e5 476
TETSUYA 0:1648bb4e70e5 477 WriteReg(REG_HSTART, 0x1b);
TETSUYA 0:1648bb4e70e5 478 WriteReg(REG_HSTOP, 0x57);
TETSUYA 0:1648bb4e70e5 479 WriteReg(REG_VSTART, 0x12);
TETSUYA 0:1648bb4e70e5 480 WriteReg(REG_VSTOP, 0x6c);
TETSUYA 0:1648bb4e70e5 481 }
TETSUYA 0:1648bb4e70e5 482
TETSUYA 0:1648bb4e70e5 483 void InitQVGA(void) {
TETSUYA 0:1648bb4e70e5 484 // QQVGA
TETSUYA 0:1648bb4e70e5 485 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 486
TETSUYA 0:1648bb4e70e5 487 WriteReg(REG_COM7,reg_com7|COM7_QVGA);
TETSUYA 0:1648bb4e70e5 488
TETSUYA 0:1648bb4e70e5 489 WriteReg(REG_HSTART,HSTART_QVGA);
TETSUYA 0:1648bb4e70e5 490 WriteReg(REG_HSTOP,HSTOP_QVGA);
TETSUYA 0:1648bb4e70e5 491 WriteReg(REG_HREF,HREF_QVGA);
TETSUYA 0:1648bb4e70e5 492 WriteReg(REG_VSTART,VSTART_QVGA);
TETSUYA 0:1648bb4e70e5 493 WriteReg(REG_VSTOP,VSTOP_QVGA);
TETSUYA 0:1648bb4e70e5 494 WriteReg(REG_VREF,VREF_QVGA);
TETSUYA 0:1648bb4e70e5 495 WriteReg(REG_COM3, COM3_QVGA);
TETSUYA 0:1648bb4e70e5 496 WriteReg(REG_COM14, COM14_QVGA);
TETSUYA 0:1648bb4e70e5 497 WriteReg(REG_SCALING_XSC, SCALING_XSC_QVGA);
TETSUYA 0:1648bb4e70e5 498 WriteReg(REG_SCALING_YSC, SCALING_YSC_QVGA);
TETSUYA 0:1648bb4e70e5 499 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_QVGA);
TETSUYA 0:1648bb4e70e5 500 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_QVGA);
TETSUYA 0:1648bb4e70e5 501 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_QVGA);
TETSUYA 0:1648bb4e70e5 502 }
TETSUYA 0:1648bb4e70e5 503
TETSUYA 0:1648bb4e70e5 504 void InitQQVGA(void) {
TETSUYA 0:1648bb4e70e5 505 // QQVGA
TETSUYA 0:1648bb4e70e5 506 int reg_com7 = ReadReg(REG_COM7);
TETSUYA 0:1648bb4e70e5 507
TETSUYA 0:1648bb4e70e5 508 WriteReg(REG_COM7,reg_com7|COM7_QQVGA);
TETSUYA 0:1648bb4e70e5 509
TETSUYA 0:1648bb4e70e5 510 WriteReg(REG_HSTART,HSTART_QQVGA);
TETSUYA 0:1648bb4e70e5 511 WriteReg(REG_HSTOP,HSTOP_QQVGA);
TETSUYA 0:1648bb4e70e5 512 WriteReg(REG_HREF,HREF_QQVGA);
TETSUYA 0:1648bb4e70e5 513 WriteReg(REG_VSTART,VSTART_QQVGA);
TETSUYA 0:1648bb4e70e5 514 WriteReg(REG_VSTOP,VSTOP_QQVGA);
TETSUYA 0:1648bb4e70e5 515 WriteReg(REG_VREF,VREF_QQVGA);
TETSUYA 0:1648bb4e70e5 516 WriteReg(REG_COM3, COM3_QQVGA);
TETSUYA 0:1648bb4e70e5 517 WriteReg(REG_COM14, COM14_QQVGA);
TETSUYA 0:1648bb4e70e5 518 WriteReg(REG_SCALING_XSC, SCALING_XSC_QQVGA);
TETSUYA 0:1648bb4e70e5 519 WriteReg(REG_SCALING_YSC, SCALING_YSC_QQVGA);
TETSUYA 0:1648bb4e70e5 520 WriteReg(REG_SCALING_DCWCTR, SCALING_DCWCTR_QQVGA);
TETSUYA 0:1648bb4e70e5 521 WriteReg(REG_SCALING_PCLK_DIV, SCALING_PCLK_DIV_QQVGA);
TETSUYA 0:1648bb4e70e5 522 WriteReg(REG_SCALING_PCLK_DELAY, SCALING_PCLK_DELAY_QQVGA);
TETSUYA 0:1648bb4e70e5 523 }
TETSUYA 0:1648bb4e70e5 524
TETSUYA 0:1648bb4e70e5 525 // vsync handler
TETSUYA 0:1648bb4e70e5 526 void VsyncHandler(void)
TETSUYA 0:1648bb4e70e5 527 {
TETSUYA 0:1648bb4e70e5 528 // Capture Enable
TETSUYA 0:1648bb4e70e5 529 if (CaptureReq) {
TETSUYA 0:1648bb4e70e5 530 wen = 1;
TETSUYA 0:1648bb4e70e5 531 Done = false;
TETSUYA 0:1648bb4e70e5 532 CaptureReq = false;
TETSUYA 0:1648bb4e70e5 533 } else {
TETSUYA 0:1648bb4e70e5 534 wen = 0;
TETSUYA 0:1648bb4e70e5 535 if (Busy) {
TETSUYA 0:1648bb4e70e5 536 Busy = false;
TETSUYA 0:1648bb4e70e5 537 Done = true;
TETSUYA 0:1648bb4e70e5 538 }
TETSUYA 0:1648bb4e70e5 539 }
TETSUYA 0:1648bb4e70e5 540
TETSUYA 0:1648bb4e70e5 541 // Hline Counter
TETSUYA 0:1648bb4e70e5 542 LastLines = LineCounter;
TETSUYA 0:1648bb4e70e5 543 LineCounter = 0;
TETSUYA 0:1648bb4e70e5 544 }
TETSUYA 0:1648bb4e70e5 545
TETSUYA 0:1648bb4e70e5 546 // href handler
TETSUYA 0:1648bb4e70e5 547 void HrefHandler(void)
TETSUYA 0:1648bb4e70e5 548 {
TETSUYA 0:1648bb4e70e5 549 LineCounter++;
TETSUYA 0:1648bb4e70e5 550 }
TETSUYA 0:1648bb4e70e5 551
TETSUYA 0:1648bb4e70e5 552 // Data Read
TETSUYA 0:1648bb4e70e5 553 int ReadOneByte(void)
TETSUYA 0:1648bb4e70e5 554 {
TETSUYA 0:1648bb4e70e5 555 int result;
TETSUYA 0:1648bb4e70e5 556 rclk = 1;
TETSUYA 0:1648bb4e70e5 557 // wait_us(1);
TETSUYA 0:1648bb4e70e5 558 result = data;
TETSUYA 0:1648bb4e70e5 559 rclk = 0;
TETSUYA 0:1648bb4e70e5 560 return result;
TETSUYA 0:1648bb4e70e5 561 }
TETSUYA 0:1648bb4e70e5 562
TETSUYA 0:1648bb4e70e5 563 // Data Start
TETSUYA 0:1648bb4e70e5 564 void ReadStart(void)
TETSUYA 0:1648bb4e70e5 565 {
TETSUYA 0:1648bb4e70e5 566 rrst = 0;
TETSUYA 0:1648bb4e70e5 567 oe = 0;
TETSUYA 0:1648bb4e70e5 568 wait_us(1);
TETSUYA 0:1648bb4e70e5 569 rclk = 0;
TETSUYA 0:1648bb4e70e5 570 wait_us(1);
TETSUYA 0:1648bb4e70e5 571 rclk = 1;
TETSUYA 0:1648bb4e70e5 572 wait_us(1);
TETSUYA 0:1648bb4e70e5 573 rrst = 1;
TETSUYA 0:1648bb4e70e5 574 }
TETSUYA 0:1648bb4e70e5 575
TETSUYA 0:1648bb4e70e5 576 // Data Stop
TETSUYA 0:1648bb4e70e5 577 void ReadStop(void)
TETSUYA 0:1648bb4e70e5 578 {
TETSUYA 0:1648bb4e70e5 579 oe = 1;
TETSUYA 0:1648bb4e70e5 580 ReadOneByte();
TETSUYA 0:1648bb4e70e5 581 rclk = 1;
TETSUYA 0:1648bb4e70e5 582 }
TETSUYA 0:1648bb4e70e5 583 };