Rod Coleman / NetServSB2

Netservices modded to read fragmented HTTP respsonse/payload from special purpose server - 180 bytes only

drv/usb/UsbInc.h@0:850eacf3e945, 2011-09-08 (annotated)

Committer:
RodColeman
Date:
Thu Sep 08 10:48:09 2011 +0000
Revision:
0:850eacf3e945
revised fixed length to 178 bytes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
RodColeman 0:850eacf3e945 1
RodColeman 0:850eacf3e945 2 /*
RodColeman 0:850eacf3e945 3 Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
RodColeman 0:850eacf3e945 4
RodColeman 0:850eacf3e945 5 Permission is hereby granted, free of charge, to any person obtaining a copy
RodColeman 0:850eacf3e945 6 of this software and associated documentation files (the "Software"), to deal
RodColeman 0:850eacf3e945 7 in the Software without restriction, including without limitation the rights
RodColeman 0:850eacf3e945 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
RodColeman 0:850eacf3e945 9 copies of the Software, and to permit persons to whom the Software is
RodColeman 0:850eacf3e945 10 furnished to do so, subject to the following conditions:
RodColeman 0:850eacf3e945 11
RodColeman 0:850eacf3e945 12 The above copyright notice and this permission notice shall be included in
RodColeman 0:850eacf3e945 13 all copies or substantial portions of the Software.
RodColeman 0:850eacf3e945 14
RodColeman 0:850eacf3e945 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
RodColeman 0:850eacf3e945 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
RodColeman 0:850eacf3e945 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
RodColeman 0:850eacf3e945 18 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
RodColeman 0:850eacf3e945 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
RodColeman 0:850eacf3e945 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
RodColeman 0:850eacf3e945 21 THE SOFTWARE.
RodColeman 0:850eacf3e945 22 */
RodColeman 0:850eacf3e945 23
RodColeman 0:850eacf3e945 24 #ifndef USB_INC_H
RodColeman 0:850eacf3e945 25 #define USB_INC_H
RodColeman 0:850eacf3e945 26
RodColeman 0:850eacf3e945 27 #include "mbed.h"
RodColeman 0:850eacf3e945 28
RodColeman 0:850eacf3e945 29 #define MIN(a,b) ((a)<(b)?(a):(b))
RodColeman 0:850eacf3e945 30 #define MAX(a,b) ((a)>(b)?(a):(b))
RodColeman 0:850eacf3e945 31
RodColeman 0:850eacf3e945 32 //typedef int32_t RC;
RodColeman 0:850eacf3e945 33
RodColeman 0:850eacf3e945 34 typedef uint8_t byte;
RodColeman 0:850eacf3e945 35 typedef uint16_t word;
RodColeman 0:850eacf3e945 36
RodColeman 0:850eacf3e945 37 enum UsbErr
RodColeman 0:850eacf3e945 38 {
RodColeman 0:850eacf3e945 39 __USBERR_MIN = -0xFFFF,
RodColeman 0:850eacf3e945 40 USBERR_DISCONNECTED,
RodColeman 0:850eacf3e945 41 USBERR_NOTFOUND,
RodColeman 0:850eacf3e945 42 USBERR_BADCONFIG,
RodColeman 0:850eacf3e945 43 USBERR_PROCESSING,
RodColeman 0:850eacf3e945 44 USBERR_HALTED, //Transfer on an ep is stalled
RodColeman 0:850eacf3e945 45 USBERR_BUSY,
RodColeman 0:850eacf3e945 46 USBERR_TDFAIL,
RodColeman 0:850eacf3e945 47 USBERR_ERROR,
RodColeman 0:850eacf3e945 48 USBERR_OK = 0
RodColeman 0:850eacf3e945 49 };
RodColeman 0:850eacf3e945 50
RodColeman 0:850eacf3e945 51
RodColeman 0:850eacf3e945 52 /* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
RodColeman 0:850eacf3e945 53 /* Only the types names have been changed to avoid unecessary typedefs */
RodColeman 0:850eacf3e945 54
RodColeman 0:850eacf3e945 55
RodColeman 0:850eacf3e945 56 /*
RodColeman 0:850eacf3e945 57 **************************************************************************************************************
RodColeman 0:850eacf3e945 58 * NXP USB Host Stack
RodColeman 0:850eacf3e945 59 *
RodColeman 0:850eacf3e945 60 * (c) Copyright 2008, NXP SemiConductors
RodColeman 0:850eacf3e945 61 * (c) Copyright 2008, OnChip Technologies LLC
RodColeman 0:850eacf3e945 62 * All Rights Reserved
RodColeman 0:850eacf3e945 63 *
RodColeman 0:850eacf3e945 64 * www.nxp.com
RodColeman 0:850eacf3e945 65 * www.onchiptech.com
RodColeman 0:850eacf3e945 66 *
RodColeman 0:850eacf3e945 67 * File : usbhost_lpc17xx.h
RodColeman 0:850eacf3e945 68 * Programmer(s) : Ravikanth.P
RodColeman 0:850eacf3e945 69 * Version :
RodColeman 0:850eacf3e945 70 *
RodColeman 0:850eacf3e945 71 **************************************************************************************************************
RodColeman 0:850eacf3e945 72 */
RodColeman 0:850eacf3e945 73
RodColeman 0:850eacf3e945 74
RodColeman 0:850eacf3e945 75
RodColeman 0:850eacf3e945 76 /*
RodColeman 0:850eacf3e945 77 **************************************************************************************************************
RodColeman 0:850eacf3e945 78 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
RodColeman 0:850eacf3e945 79 **************************************************************************************************************
RodColeman 0:850eacf3e945 80 */
RodColeman 0:850eacf3e945 81
RodColeman 0:850eacf3e945 82 /* ------------------ HcControl Register --------------------- */
RodColeman 0:850eacf3e945 83 #define OR_CONTROL_CLE 0x00000010
RodColeman 0:850eacf3e945 84 #define OR_CONTROL_BLE 0x00000020
RodColeman 0:850eacf3e945 85 #define OR_CONTROL_HCFS 0x000000C0
RodColeman 0:850eacf3e945 86 #define OR_CONTROL_HC_OPER 0x00000080
RodColeman 0:850eacf3e945 87 /* ----------------- HcCommandStatus Register ----------------- */
RodColeman 0:850eacf3e945 88 #define OR_CMD_STATUS_HCR 0x00000001
RodColeman 0:850eacf3e945 89 #define OR_CMD_STATUS_CLF 0x00000002
RodColeman 0:850eacf3e945 90 #define OR_CMD_STATUS_BLF 0x00000004
RodColeman 0:850eacf3e945 91 /* --------------- HcInterruptStatus Register ----------------- */
RodColeman 0:850eacf3e945 92 #define OR_INTR_STATUS_WDH 0x00000002
RodColeman 0:850eacf3e945 93 #define OR_INTR_STATUS_RHSC 0x00000040
RodColeman 0:850eacf3e945 94 #define OR_INTR_STATUS_UE 0x00000010
RodColeman 0:850eacf3e945 95 /* --------------- HcInterruptEnable Register ----------------- */
RodColeman 0:850eacf3e945 96 #define OR_INTR_ENABLE_WDH 0x00000002
RodColeman 0:850eacf3e945 97 #define OR_INTR_ENABLE_RHSC 0x00000040
RodColeman 0:850eacf3e945 98 #define OR_INTR_ENABLE_MIE 0x80000000
RodColeman 0:850eacf3e945 99 /* ---------------- HcRhDescriptorA Register ------------------ */
RodColeman 0:850eacf3e945 100 #define OR_RH_STATUS_LPSC 0x00010000
RodColeman 0:850eacf3e945 101 #define OR_RH_STATUS_DRWE 0x00008000
RodColeman 0:850eacf3e945 102 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
RodColeman 0:850eacf3e945 103 #define OR_RH_PORT_CCS 0x00000001
RodColeman 0:850eacf3e945 104 #define OR_RH_PORT_PRS 0x00000010
RodColeman 0:850eacf3e945 105 #define OR_RH_PORT_CSC 0x00010000
RodColeman 0:850eacf3e945 106 #define OR_RH_PORT_PRSC 0x00100000
RodColeman 0:850eacf3e945 107
RodColeman 0:850eacf3e945 108
RodColeman 0:850eacf3e945 109 /*
RodColeman 0:850eacf3e945 110 **************************************************************************************************************
RodColeman 0:850eacf3e945 111 * FRAME INTERVAL
RodColeman 0:850eacf3e945 112 **************************************************************************************************************
RodColeman 0:850eacf3e945 113 */
RodColeman 0:850eacf3e945 114
RodColeman 0:850eacf3e945 115 #define FI 0x2EDF /* 12000 bits per frame (-1) */
RodColeman 0:850eacf3e945 116 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
RodColeman 0:850eacf3e945 117
RodColeman 0:850eacf3e945 118 /*
RodColeman 0:850eacf3e945 119 **************************************************************************************************************
RodColeman 0:850eacf3e945 120 * ENDPOINT DESCRIPTOR CONTROL FIELDS
RodColeman 0:850eacf3e945 121 **************************************************************************************************************
RodColeman 0:850eacf3e945 122 */
RodColeman 0:850eacf3e945 123
RodColeman 0:850eacf3e945 124 #define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
RodColeman 0:850eacf3e945 125
RodColeman 0:850eacf3e945 126 /*
RodColeman 0:850eacf3e945 127 **************************************************************************************************************
RodColeman 0:850eacf3e945 128 * TRANSFER DESCRIPTOR CONTROL FIELDS
RodColeman 0:850eacf3e945 129 **************************************************************************************************************
RodColeman 0:850eacf3e945 130 */
RodColeman 0:850eacf3e945 131
RodColeman 0:850eacf3e945 132 #define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
RodColeman 0:850eacf3e945 133 #define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
RodColeman 0:850eacf3e945 134 #define TD_IN (uint32_t)(0x00100000) /* Direction In */
RodColeman 0:850eacf3e945 135 #define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
RodColeman 0:850eacf3e945 136 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
RodColeman 0:850eacf3e945 137 #define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
RodColeman 0:850eacf3e945 138 #define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
RodColeman 0:850eacf3e945 139 #define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
RodColeman 0:850eacf3e945 140
RodColeman 0:850eacf3e945 141 /*
RodColeman 0:850eacf3e945 142 **************************************************************************************************************
RodColeman 0:850eacf3e945 143 * USB STANDARD REQUEST DEFINITIONS
RodColeman 0:850eacf3e945 144 **************************************************************************************************************
RodColeman 0:850eacf3e945 145 */
RodColeman 0:850eacf3e945 146
RodColeman 0:850eacf3e945 147 #define USB_DESCRIPTOR_TYPE_DEVICE 1
RodColeman 0:850eacf3e945 148 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
RodColeman 0:850eacf3e945 149 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
RodColeman 0:850eacf3e945 150 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
RodColeman 0:850eacf3e945 151 /* ----------- Control RequestType Fields ----------- */
RodColeman 0:850eacf3e945 152 #define USB_DEVICE_TO_HOST 0x80
RodColeman 0:850eacf3e945 153 #define USB_HOST_TO_DEVICE 0x00
RodColeman 0:850eacf3e945 154 #define USB_REQUEST_TYPE_CLASS 0x20
RodColeman 0:850eacf3e945 155 #define USB_RECIPIENT_DEVICE 0x00
RodColeman 0:850eacf3e945 156 #define USB_RECIPIENT_INTERFACE 0x01
RodColeman 0:850eacf3e945 157 /* -------------- USB Standard Requests -------------- */
RodColeman 0:850eacf3e945 158 #define SET_ADDRESS 5
RodColeman 0:850eacf3e945 159 #define GET_DESCRIPTOR 6
RodColeman 0:850eacf3e945 160 #define SET_CONFIGURATION 9
RodColeman 0:850eacf3e945 161 #define SET_INTERFACE 11
RodColeman 0:850eacf3e945 162
RodColeman 0:850eacf3e945 163 /*
RodColeman 0:850eacf3e945 164 **************************************************************************************************************
RodColeman 0:850eacf3e945 165 * TYPE DEFINITIONS
RodColeman 0:850eacf3e945 166 **************************************************************************************************************
RodColeman 0:850eacf3e945 167 */
RodColeman 0:850eacf3e945 168
RodColeman 0:850eacf3e945 169 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
RodColeman 0:850eacf3e945 170 volatile uint32_t Control; /* Endpoint descriptor control */
RodColeman 0:850eacf3e945 171 volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
RodColeman 0:850eacf3e945 172 volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
RodColeman 0:850eacf3e945 173 volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
RodColeman 0:850eacf3e945 174 } HCED;
RodColeman 0:850eacf3e945 175
RodColeman 0:850eacf3e945 176 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
RodColeman 0:850eacf3e945 177 volatile uint32_t Control; /* Transfer descriptor control */
RodColeman 0:850eacf3e945 178 volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
RodColeman 0:850eacf3e945 179 volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
RodColeman 0:850eacf3e945 180 volatile uint32_t BufEnd; /* Physical address of end of buffer */
RodColeman 0:850eacf3e945 181 } HCTD;
RodColeman 0:850eacf3e945 182
RodColeman 0:850eacf3e945 183 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
RodColeman 0:850eacf3e945 184 volatile uint32_t IntTable[32]; /* Interrupt Table */
RodColeman 0:850eacf3e945 185 volatile uint32_t FrameNumber; /* Frame Number */
RodColeman 0:850eacf3e945 186 volatile uint32_t DoneHead; /* Done Head */
RodColeman 0:850eacf3e945 187 volatile uint8_t Reserved[116]; /* Reserved for future use */
RodColeman 0:850eacf3e945 188 volatile uint8_t Unknown[4]; /* Unused */
RodColeman 0:850eacf3e945 189 } HCCA;
RodColeman 0:850eacf3e945 190
RodColeman 0:850eacf3e945 191
RodColeman 0:850eacf3e945 192
RodColeman 0:850eacf3e945 193 #endif