Egor Rumjantsev
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TARGET_NUCLEO_F103RB/stm32f1xx_ll_fsmc.h@99:7f6c6de930c0, 2015-05-03 (annotated)
- Committer:
- Mikchel
- Date:
- Sun May 03 16:04:42 2015 +0000
- Revision:
- 99:7f6c6de930c0
- Parent:
- 96:487b796308b0
12
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 96:487b796308b0 | 1 | /** |
| Kojto | 96:487b796308b0 | 2 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 3 | * @file stm32f1xx_ll_fsmc.h |
| Kojto | 96:487b796308b0 | 4 | * @author MCD Application Team |
| Kojto | 96:487b796308b0 | 5 | * @version V1.0.0 |
| Kojto | 96:487b796308b0 | 6 | * @date 15-December-2014 |
| Kojto | 96:487b796308b0 | 7 | * @brief Header file of FSMC HAL module. |
| Kojto | 96:487b796308b0 | 8 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 9 | * @attention |
| Kojto | 96:487b796308b0 | 10 | * |
| Kojto | 96:487b796308b0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| Kojto | 96:487b796308b0 | 12 | * |
| Kojto | 96:487b796308b0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 96:487b796308b0 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 96:487b796308b0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 96:487b796308b0 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 96:487b796308b0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 96:487b796308b0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 96:487b796308b0 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 96:487b796308b0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 96:487b796308b0 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 96:487b796308b0 | 22 | * without specific prior written permission. |
| Kojto | 96:487b796308b0 | 23 | * |
| Kojto | 96:487b796308b0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 96:487b796308b0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 96:487b796308b0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 96:487b796308b0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 96:487b796308b0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 96:487b796308b0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 96:487b796308b0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 96:487b796308b0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 96:487b796308b0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 96:487b796308b0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 96:487b796308b0 | 34 | * |
| Kojto | 96:487b796308b0 | 35 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 36 | */ |
| Kojto | 96:487b796308b0 | 37 | |
| Kojto | 96:487b796308b0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 96:487b796308b0 | 39 | #ifndef __STM32F1xx_LL_FSMC_H |
| Kojto | 96:487b796308b0 | 40 | #define __STM32F1xx_LL_FSMC_H |
| Kojto | 96:487b796308b0 | 41 | |
| Kojto | 96:487b796308b0 | 42 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 43 | extern "C" { |
| Kojto | 96:487b796308b0 | 44 | #endif |
| Kojto | 96:487b796308b0 | 45 | |
| Kojto | 96:487b796308b0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 47 | #include "stm32f1xx_hal_def.h" |
| Kojto | 96:487b796308b0 | 48 | |
| Kojto | 96:487b796308b0 | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| Kojto | 96:487b796308b0 | 50 | * @{ |
| Kojto | 96:487b796308b0 | 51 | */ |
| Kojto | 96:487b796308b0 | 52 | |
| Kojto | 96:487b796308b0 | 53 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) |
| Kojto | 96:487b796308b0 | 54 | |
| Kojto | 96:487b796308b0 | 55 | /** @addtogroup FSMC_LL |
| Kojto | 96:487b796308b0 | 56 | * @{ |
| Kojto | 96:487b796308b0 | 57 | */ |
| Kojto | 96:487b796308b0 | 58 | |
| Kojto | 96:487b796308b0 | 59 | /** @addtogroup FSMC_LL_Private_Macros |
| Kojto | 96:487b796308b0 | 60 | * @{ |
| Kojto | 96:487b796308b0 | 61 | */ |
| Kojto | 96:487b796308b0 | 62 | |
| Kojto | 96:487b796308b0 | 63 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
| Kojto | 96:487b796308b0 | 64 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| Kojto | 96:487b796308b0 | 65 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| Kojto | 96:487b796308b0 | 66 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| Kojto | 96:487b796308b0 | 67 | |
| Kojto | 96:487b796308b0 | 68 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 69 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| Kojto | 96:487b796308b0 | 70 | |
| Kojto | 96:487b796308b0 | 71 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| Kojto | 96:487b796308b0 | 72 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| Kojto | 96:487b796308b0 | 73 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| Kojto | 96:487b796308b0 | 74 | |
| Kojto | 96:487b796308b0 | 75 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| Kojto | 96:487b796308b0 | 76 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| Kojto | 96:487b796308b0 | 77 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| Kojto | 96:487b796308b0 | 78 | |
| Kojto | 96:487b796308b0 | 79 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| Kojto | 96:487b796308b0 | 80 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| Kojto | 96:487b796308b0 | 81 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| Kojto | 96:487b796308b0 | 82 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| Kojto | 96:487b796308b0 | 83 | |
| Kojto | 96:487b796308b0 | 84 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
| Kojto | 96:487b796308b0 | 85 | ((BANK) == FSMC_NAND_BANK3)) |
| Kojto | 96:487b796308b0 | 86 | |
| Kojto | 96:487b796308b0 | 87 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 88 | ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| Kojto | 96:487b796308b0 | 89 | |
| Kojto | 96:487b796308b0 | 90 | #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| Kojto | 96:487b796308b0 | 91 | ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| Kojto | 96:487b796308b0 | 92 | |
| Kojto | 96:487b796308b0 | 93 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 94 | ((STATE) == FSMC_NAND_ECC_ENABLE)) |
| Kojto | 96:487b796308b0 | 95 | |
| Kojto | 96:487b796308b0 | 96 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| Kojto | 96:487b796308b0 | 97 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| Kojto | 96:487b796308b0 | 98 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| Kojto | 96:487b796308b0 | 99 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| Kojto | 96:487b796308b0 | 100 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| Kojto | 96:487b796308b0 | 101 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| Kojto | 96:487b796308b0 | 102 | /** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time |
| Kojto | 96:487b796308b0 | 103 | * @{ |
| Kojto | 96:487b796308b0 | 104 | */ |
| Kojto | 96:487b796308b0 | 105 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 106 | /** |
| Kojto | 96:487b796308b0 | 107 | * @} |
| Kojto | 96:487b796308b0 | 108 | */ |
| Kojto | 96:487b796308b0 | 109 | |
| Kojto | 96:487b796308b0 | 110 | /** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time |
| Kojto | 96:487b796308b0 | 111 | * @{ |
| Kojto | 96:487b796308b0 | 112 | */ |
| Kojto | 96:487b796308b0 | 113 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 114 | /** |
| Kojto | 96:487b796308b0 | 115 | * @} |
| Kojto | 96:487b796308b0 | 116 | */ |
| Kojto | 96:487b796308b0 | 117 | |
| Kojto | 96:487b796308b0 | 118 | /** @defgroup FSMC_Setup_Time FSMC_Setup_Time |
| Kojto | 96:487b796308b0 | 119 | * @{ |
| Kojto | 96:487b796308b0 | 120 | */ |
| Kojto | 96:487b796308b0 | 121 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 122 | /** |
| Kojto | 96:487b796308b0 | 123 | * @} |
| Kojto | 96:487b796308b0 | 124 | */ |
| Kojto | 96:487b796308b0 | 125 | |
| Kojto | 96:487b796308b0 | 126 | /** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time |
| Kojto | 96:487b796308b0 | 127 | * @{ |
| Kojto | 96:487b796308b0 | 128 | */ |
| Kojto | 96:487b796308b0 | 129 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 130 | /** |
| Kojto | 96:487b796308b0 | 131 | * @} |
| Kojto | 96:487b796308b0 | 132 | */ |
| Kojto | 96:487b796308b0 | 133 | |
| Kojto | 96:487b796308b0 | 134 | /** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time |
| Kojto | 96:487b796308b0 | 135 | * @{ |
| Kojto | 96:487b796308b0 | 136 | */ |
| Kojto | 96:487b796308b0 | 137 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 138 | /** |
| Kojto | 96:487b796308b0 | 139 | * @} |
| Kojto | 96:487b796308b0 | 140 | */ |
| Kojto | 96:487b796308b0 | 141 | |
| Kojto | 96:487b796308b0 | 142 | /** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time |
| Kojto | 96:487b796308b0 | 143 | * @{ |
| Kojto | 96:487b796308b0 | 144 | */ |
| Kojto | 96:487b796308b0 | 145 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255) |
| Kojto | 96:487b796308b0 | 146 | /** |
| Kojto | 96:487b796308b0 | 147 | * @} |
| Kojto | 96:487b796308b0 | 148 | */ |
| Kojto | 96:487b796308b0 | 149 | |
| Kojto | 96:487b796308b0 | 150 | /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance |
| Kojto | 96:487b796308b0 | 151 | * @{ |
| Kojto | 96:487b796308b0 | 152 | */ |
| Kojto | 96:487b796308b0 | 153 | |
| Kojto | 96:487b796308b0 | 154 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| Kojto | 96:487b796308b0 | 155 | |
| Kojto | 96:487b796308b0 | 156 | /** |
| Kojto | 96:487b796308b0 | 157 | * @} |
| Kojto | 96:487b796308b0 | 158 | */ |
| Kojto | 96:487b796308b0 | 159 | |
| Kojto | 96:487b796308b0 | 160 | /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance |
| Kojto | 96:487b796308b0 | 161 | * @{ |
| Kojto | 96:487b796308b0 | 162 | */ |
| Kojto | 96:487b796308b0 | 163 | |
| Kojto | 96:487b796308b0 | 164 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| Kojto | 96:487b796308b0 | 165 | |
| Kojto | 96:487b796308b0 | 166 | /** |
| Kojto | 96:487b796308b0 | 167 | * @} |
| Kojto | 96:487b796308b0 | 168 | */ |
| Kojto | 96:487b796308b0 | 169 | |
| Kojto | 96:487b796308b0 | 170 | /** @defgroup FSMC_NAND_Device_Instance FSMC_NAND_Device_Instance |
| Kojto | 96:487b796308b0 | 171 | * @{ |
| Kojto | 96:487b796308b0 | 172 | */ |
| Kojto | 96:487b796308b0 | 173 | #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
| Kojto | 96:487b796308b0 | 174 | /** |
| Kojto | 96:487b796308b0 | 175 | * @} |
| Kojto | 96:487b796308b0 | 176 | */ |
| Kojto | 96:487b796308b0 | 177 | |
| Kojto | 96:487b796308b0 | 178 | /** @defgroup FSMC_PCCARD_Device_Instance FSMC_PCCARD_Device_Instance |
| Kojto | 96:487b796308b0 | 179 | * @{ |
| Kojto | 96:487b796308b0 | 180 | */ |
| Kojto | 96:487b796308b0 | 181 | #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
| Kojto | 96:487b796308b0 | 182 | |
| Kojto | 96:487b796308b0 | 183 | /** |
| Kojto | 96:487b796308b0 | 184 | * @} |
| Kojto | 96:487b796308b0 | 185 | */ |
| Kojto | 96:487b796308b0 | 186 | |
| Kojto | 96:487b796308b0 | 187 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 188 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| Kojto | 96:487b796308b0 | 189 | |
| Kojto | 96:487b796308b0 | 190 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| Kojto | 96:487b796308b0 | 191 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| Kojto | 96:487b796308b0 | 192 | |
| Kojto | 96:487b796308b0 | 193 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 194 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| Kojto | 96:487b796308b0 | 195 | |
| Kojto | 96:487b796308b0 | 196 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| Kojto | 96:487b796308b0 | 197 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| Kojto | 96:487b796308b0 | 198 | |
| Kojto | 96:487b796308b0 | 199 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 200 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| Kojto | 96:487b796308b0 | 201 | |
| Kojto | 96:487b796308b0 | 202 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 203 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| Kojto | 96:487b796308b0 | 204 | |
| Kojto | 96:487b796308b0 | 205 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 206 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| Kojto | 96:487b796308b0 | 207 | |
| Kojto | 96:487b796308b0 | 208 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 209 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| Kojto | 96:487b796308b0 | 210 | |
| Kojto | 96:487b796308b0 | 211 | #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) |
| Kojto | 96:487b796308b0 | 212 | |
| Kojto | 96:487b796308b0 | 213 | /** @defgroup FSMC_Data_Latency FSMC Data Latency |
| Kojto | 96:487b796308b0 | 214 | * @{ |
| Kojto | 96:487b796308b0 | 215 | */ |
| Kojto | 96:487b796308b0 | 216 | |
| Kojto | 96:487b796308b0 | 217 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| Kojto | 96:487b796308b0 | 218 | /** |
| Kojto | 96:487b796308b0 | 219 | * @} |
| Kojto | 96:487b796308b0 | 220 | */ |
| Kojto | 96:487b796308b0 | 221 | |
| Kojto | 96:487b796308b0 | 222 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 223 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| Kojto | 96:487b796308b0 | 224 | /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time |
| Kojto | 96:487b796308b0 | 225 | * @{ |
| Kojto | 96:487b796308b0 | 226 | */ |
| Kojto | 96:487b796308b0 | 227 | |
| Kojto | 96:487b796308b0 | 228 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| Kojto | 96:487b796308b0 | 229 | /** |
| Kojto | 96:487b796308b0 | 230 | * @} |
| Kojto | 96:487b796308b0 | 231 | */ |
| Kojto | 96:487b796308b0 | 232 | |
| Kojto | 96:487b796308b0 | 233 | /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time |
| Kojto | 96:487b796308b0 | 234 | * @{ |
| Kojto | 96:487b796308b0 | 235 | */ |
| Kojto | 96:487b796308b0 | 236 | |
| Kojto | 96:487b796308b0 | 237 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| Kojto | 96:487b796308b0 | 238 | /** |
| Kojto | 96:487b796308b0 | 239 | * @} |
| Kojto | 96:487b796308b0 | 240 | */ |
| Kojto | 96:487b796308b0 | 241 | |
| Kojto | 96:487b796308b0 | 242 | /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time |
| Kojto | 96:487b796308b0 | 243 | * @{ |
| Kojto | 96:487b796308b0 | 244 | */ |
| Kojto | 96:487b796308b0 | 245 | |
| Kojto | 96:487b796308b0 | 246 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| Kojto | 96:487b796308b0 | 247 | /** |
| Kojto | 96:487b796308b0 | 248 | * @} |
| Kojto | 96:487b796308b0 | 249 | */ |
| Kojto | 96:487b796308b0 | 250 | |
| Kojto | 96:487b796308b0 | 251 | /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration |
| Kojto | 96:487b796308b0 | 252 | * @{ |
| Kojto | 96:487b796308b0 | 253 | */ |
| Kojto | 96:487b796308b0 | 254 | |
| Kojto | 96:487b796308b0 | 255 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| Kojto | 96:487b796308b0 | 256 | /** |
| Kojto | 96:487b796308b0 | 257 | * @} |
| Kojto | 96:487b796308b0 | 258 | */ |
| Kojto | 96:487b796308b0 | 259 | |
| Kojto | 96:487b796308b0 | 260 | /** |
| Kojto | 96:487b796308b0 | 261 | * @} |
| Kojto | 96:487b796308b0 | 262 | */ |
| Kojto | 96:487b796308b0 | 263 | |
| Kojto | 96:487b796308b0 | 264 | /* Exported typedef ----------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 265 | |
| Kojto | 96:487b796308b0 | 266 | /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types |
| Kojto | 96:487b796308b0 | 267 | * @{ |
| Kojto | 96:487b796308b0 | 268 | */ |
| Kojto | 96:487b796308b0 | 269 | |
| Kojto | 96:487b796308b0 | 270 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| Kojto | 96:487b796308b0 | 271 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| Kojto | 96:487b796308b0 | 272 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| Kojto | 96:487b796308b0 | 273 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| Kojto | 96:487b796308b0 | 274 | |
| Kojto | 96:487b796308b0 | 275 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| Kojto | 96:487b796308b0 | 276 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| Kojto | 96:487b796308b0 | 277 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| Kojto | 96:487b796308b0 | 278 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| Kojto | 96:487b796308b0 | 279 | |
| Kojto | 96:487b796308b0 | 280 | /** |
| Kojto | 96:487b796308b0 | 281 | * @brief FSMC_NORSRAM Configuration Structure definition |
| Kojto | 96:487b796308b0 | 282 | */ |
| Kojto | 96:487b796308b0 | 283 | typedef struct |
| Kojto | 96:487b796308b0 | 284 | { |
| Kojto | 96:487b796308b0 | 285 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| Kojto | 96:487b796308b0 | 286 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| Kojto | 96:487b796308b0 | 287 | |
| Kojto | 96:487b796308b0 | 288 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| Kojto | 96:487b796308b0 | 289 | multiplexed on the data bus or not. |
| Kojto | 96:487b796308b0 | 290 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| Kojto | 96:487b796308b0 | 291 | |
| Kojto | 96:487b796308b0 | 292 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| Kojto | 96:487b796308b0 | 293 | the corresponding memory device. |
| Kojto | 96:487b796308b0 | 294 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| Kojto | 96:487b796308b0 | 295 | |
| Kojto | 96:487b796308b0 | 296 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| Kojto | 96:487b796308b0 | 297 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| Kojto | 96:487b796308b0 | 298 | |
| Kojto | 96:487b796308b0 | 299 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| Kojto | 96:487b796308b0 | 300 | valid only with synchronous burst Flash memories. |
| Kojto | 96:487b796308b0 | 301 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| Kojto | 96:487b796308b0 | 302 | |
| Kojto | 96:487b796308b0 | 303 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| Kojto | 96:487b796308b0 | 304 | the Flash memory in burst mode. |
| Kojto | 96:487b796308b0 | 305 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| Kojto | 96:487b796308b0 | 306 | |
| Kojto | 96:487b796308b0 | 307 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| Kojto | 96:487b796308b0 | 308 | memory, valid only when accessing Flash memories in burst mode. |
| Kojto | 96:487b796308b0 | 309 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| Kojto | 96:487b796308b0 | 310 | |
| Kojto | 96:487b796308b0 | 311 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| Kojto | 96:487b796308b0 | 312 | clock cycle before the wait state or during the wait state, |
| Kojto | 96:487b796308b0 | 313 | valid only when accessing memories in burst mode. |
| Kojto | 96:487b796308b0 | 314 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| Kojto | 96:487b796308b0 | 315 | |
| Kojto | 96:487b796308b0 | 316 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| Kojto | 96:487b796308b0 | 317 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| Kojto | 96:487b796308b0 | 318 | |
| Kojto | 96:487b796308b0 | 319 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| Kojto | 96:487b796308b0 | 320 | signal, valid for Flash memory access in burst mode. |
| Kojto | 96:487b796308b0 | 321 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| Kojto | 96:487b796308b0 | 322 | |
| Kojto | 96:487b796308b0 | 323 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| Kojto | 96:487b796308b0 | 324 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| Kojto | 96:487b796308b0 | 325 | |
| Kojto | 96:487b796308b0 | 326 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| Kojto | 96:487b796308b0 | 327 | valid only with asynchronous Flash memories. |
| Kojto | 96:487b796308b0 | 328 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| Kojto | 96:487b796308b0 | 329 | |
| Kojto | 96:487b796308b0 | 330 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| Kojto | 96:487b796308b0 | 331 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| Kojto | 96:487b796308b0 | 332 | |
| Kojto | 96:487b796308b0 | 333 | }FSMC_NORSRAM_InitTypeDef; |
| Kojto | 96:487b796308b0 | 334 | |
| Kojto | 96:487b796308b0 | 335 | |
| Kojto | 96:487b796308b0 | 336 | /** |
| Kojto | 96:487b796308b0 | 337 | * @brief FSMC_NORSRAM Timing parameters structure definition |
| Kojto | 96:487b796308b0 | 338 | */ |
| Kojto | 96:487b796308b0 | 339 | typedef struct |
| Kojto | 96:487b796308b0 | 340 | { |
| Kojto | 96:487b796308b0 | 341 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| Kojto | 96:487b796308b0 | 342 | the duration of the address setup time. |
| Kojto | 96:487b796308b0 | 343 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| Kojto | 96:487b796308b0 | 344 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| Kojto | 96:487b796308b0 | 345 | |
| Kojto | 96:487b796308b0 | 346 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| Kojto | 96:487b796308b0 | 347 | the duration of the address hold time. |
| Kojto | 96:487b796308b0 | 348 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| Kojto | 96:487b796308b0 | 349 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| Kojto | 96:487b796308b0 | 350 | |
| Kojto | 96:487b796308b0 | 351 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| Kojto | 96:487b796308b0 | 352 | the duration of the data setup time. |
| Kojto | 96:487b796308b0 | 353 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| Kojto | 96:487b796308b0 | 354 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| Kojto | 96:487b796308b0 | 355 | NOR Flash memories. */ |
| Kojto | 96:487b796308b0 | 356 | |
| Kojto | 96:487b796308b0 | 357 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| Kojto | 96:487b796308b0 | 358 | the duration of the bus turnaround. |
| Kojto | 96:487b796308b0 | 359 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| Kojto | 96:487b796308b0 | 360 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| Kojto | 96:487b796308b0 | 361 | |
| Kojto | 96:487b796308b0 | 362 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| Kojto | 96:487b796308b0 | 363 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| Kojto | 96:487b796308b0 | 364 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| Kojto | 96:487b796308b0 | 365 | accesses. */ |
| Kojto | 96:487b796308b0 | 366 | |
| Kojto | 96:487b796308b0 | 367 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| Kojto | 96:487b796308b0 | 368 | to the memory before getting the first data. |
| Kojto | 96:487b796308b0 | 369 | The parameter value depends on the memory type as shown below: |
| Kojto | 96:487b796308b0 | 370 | - It must be set to 0 in case of a CRAM |
| Kojto | 96:487b796308b0 | 371 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| Kojto | 96:487b796308b0 | 372 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| Kojto | 96:487b796308b0 | 373 | with synchronous burst mode enable */ |
| Kojto | 96:487b796308b0 | 374 | |
| Kojto | 96:487b796308b0 | 375 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| Kojto | 96:487b796308b0 | 376 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| Kojto | 96:487b796308b0 | 377 | |
| Kojto | 96:487b796308b0 | 378 | }FSMC_NORSRAM_TimingTypeDef; |
| Kojto | 96:487b796308b0 | 379 | |
| Kojto | 96:487b796308b0 | 380 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| Kojto | 96:487b796308b0 | 381 | /** |
| Kojto | 96:487b796308b0 | 382 | * @brief FSMC_NAND Configuration Structure definition |
| Kojto | 96:487b796308b0 | 383 | */ |
| Kojto | 96:487b796308b0 | 384 | typedef struct |
| Kojto | 96:487b796308b0 | 385 | { |
| Kojto | 96:487b796308b0 | 386 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| Kojto | 96:487b796308b0 | 387 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| Kojto | 96:487b796308b0 | 388 | |
| Kojto | 96:487b796308b0 | 389 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| Kojto | 96:487b796308b0 | 390 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| Kojto | 96:487b796308b0 | 391 | |
| Kojto | 96:487b796308b0 | 392 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| Kojto | 96:487b796308b0 | 393 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| Kojto | 96:487b796308b0 | 394 | |
| Kojto | 96:487b796308b0 | 395 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| Kojto | 96:487b796308b0 | 396 | This parameter can be any value of @ref FSMC_ECC */ |
| Kojto | 96:487b796308b0 | 397 | |
| Kojto | 96:487b796308b0 | 398 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| Kojto | 96:487b796308b0 | 399 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| Kojto | 96:487b796308b0 | 400 | |
| Kojto | 96:487b796308b0 | 401 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| Kojto | 96:487b796308b0 | 402 | delay between CLE low and RE low. |
| Kojto | 96:487b796308b0 | 403 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 404 | |
| Kojto | 96:487b796308b0 | 405 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| Kojto | 96:487b796308b0 | 406 | delay between ALE low and RE low. |
| Kojto | 96:487b796308b0 | 407 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 408 | |
| Kojto | 96:487b796308b0 | 409 | }FSMC_NAND_InitTypeDef; |
| Kojto | 96:487b796308b0 | 410 | |
| Kojto | 96:487b796308b0 | 411 | /** |
| Kojto | 96:487b796308b0 | 412 | * @brief FSMC_NAND_PCCARD Timing parameters structure definition |
| Kojto | 96:487b796308b0 | 413 | */ |
| Kojto | 96:487b796308b0 | 414 | typedef struct |
| Kojto | 96:487b796308b0 | 415 | { |
| Kojto | 96:487b796308b0 | 416 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| Kojto | 96:487b796308b0 | 417 | the command assertion for NAND-Flash read or write access |
| Kojto | 96:487b796308b0 | 418 | to common/Attribute or I/O memory space (depending on |
| Kojto | 96:487b796308b0 | 419 | the memory space timing to be configured). |
| Kojto | 96:487b796308b0 | 420 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 421 | |
| Kojto | 96:487b796308b0 | 422 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| Kojto | 96:487b796308b0 | 423 | command for NAND-Flash read or write access to |
| Kojto | 96:487b796308b0 | 424 | common/Attribute or I/O memory space (depending on the |
| Kojto | 96:487b796308b0 | 425 | memory space timing to be configured). |
| Kojto | 96:487b796308b0 | 426 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 427 | |
| Kojto | 96:487b796308b0 | 428 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| Kojto | 96:487b796308b0 | 429 | (and data for write access) after the command de-assertion |
| Kojto | 96:487b796308b0 | 430 | for NAND-Flash read or write access to common/Attribute |
| Kojto | 96:487b796308b0 | 431 | or I/O memory space (depending on the memory space timing |
| Kojto | 96:487b796308b0 | 432 | to be configured). |
| Kojto | 96:487b796308b0 | 433 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 434 | |
| Kojto | 96:487b796308b0 | 435 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| Kojto | 96:487b796308b0 | 436 | data bus is kept in HiZ after the start of a NAND-Flash |
| Kojto | 96:487b796308b0 | 437 | write access to common/Attribute or I/O memory space (depending |
| Kojto | 96:487b796308b0 | 438 | on the memory space timing to be configured). |
| Kojto | 96:487b796308b0 | 439 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 440 | |
| Kojto | 96:487b796308b0 | 441 | }FSMC_NAND_PCC_TimingTypeDef; |
| Kojto | 96:487b796308b0 | 442 | |
| Kojto | 96:487b796308b0 | 443 | /** |
| Kojto | 96:487b796308b0 | 444 | * @brief FSMC_NAND Configuration Structure definition |
| Kojto | 96:487b796308b0 | 445 | */ |
| Kojto | 96:487b796308b0 | 446 | typedef struct |
| Kojto | 96:487b796308b0 | 447 | { |
| Kojto | 96:487b796308b0 | 448 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| Kojto | 96:487b796308b0 | 449 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| Kojto | 96:487b796308b0 | 450 | |
| Kojto | 96:487b796308b0 | 451 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| Kojto | 96:487b796308b0 | 452 | delay between CLE low and RE low. |
| Kojto | 96:487b796308b0 | 453 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 454 | |
| Kojto | 96:487b796308b0 | 455 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| Kojto | 96:487b796308b0 | 456 | delay between ALE low and RE low. |
| Kojto | 96:487b796308b0 | 457 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 458 | |
| Kojto | 96:487b796308b0 | 459 | }FSMC_PCCARD_InitTypeDef; |
| Kojto | 96:487b796308b0 | 460 | |
| Kojto | 96:487b796308b0 | 461 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| Kojto | 96:487b796308b0 | 462 | /** |
| Kojto | 96:487b796308b0 | 463 | * @} |
| Kojto | 96:487b796308b0 | 464 | */ |
| Kojto | 96:487b796308b0 | 465 | |
| Kojto | 96:487b796308b0 | 466 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 467 | |
| Kojto | 96:487b796308b0 | 468 | /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants |
| Kojto | 96:487b796308b0 | 469 | * @{ |
| Kojto | 96:487b796308b0 | 470 | */ |
| Kojto | 96:487b796308b0 | 471 | |
| Kojto | 96:487b796308b0 | 472 | /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants |
| Kojto | 96:487b796308b0 | 473 | * @{ |
| Kojto | 96:487b796308b0 | 474 | */ |
| Kojto | 96:487b796308b0 | 475 | |
| Kojto | 96:487b796308b0 | 476 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| Kojto | 96:487b796308b0 | 477 | * @{ |
| Kojto | 96:487b796308b0 | 478 | */ |
| Kojto | 96:487b796308b0 | 479 | #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 480 | #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| Kojto | 96:487b796308b0 | 481 | #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| Kojto | 96:487b796308b0 | 482 | #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| Kojto | 96:487b796308b0 | 483 | |
| Kojto | 96:487b796308b0 | 484 | /** |
| Kojto | 96:487b796308b0 | 485 | * @} |
| Kojto | 96:487b796308b0 | 486 | */ |
| Kojto | 96:487b796308b0 | 487 | |
| Kojto | 96:487b796308b0 | 488 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| Kojto | 96:487b796308b0 | 489 | * @{ |
| Kojto | 96:487b796308b0 | 490 | */ |
| Kojto | 96:487b796308b0 | 491 | |
| Kojto | 96:487b796308b0 | 492 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 493 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) |
| Kojto | 96:487b796308b0 | 494 | |
| Kojto | 96:487b796308b0 | 495 | /** |
| Kojto | 96:487b796308b0 | 496 | * @} |
| Kojto | 96:487b796308b0 | 497 | */ |
| Kojto | 96:487b796308b0 | 498 | |
| Kojto | 96:487b796308b0 | 499 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| Kojto | 96:487b796308b0 | 500 | * @{ |
| Kojto | 96:487b796308b0 | 501 | */ |
| Kojto | 96:487b796308b0 | 502 | |
| Kojto | 96:487b796308b0 | 503 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 504 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) |
| Kojto | 96:487b796308b0 | 505 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) |
| Kojto | 96:487b796308b0 | 506 | |
| Kojto | 96:487b796308b0 | 507 | |
| Kojto | 96:487b796308b0 | 508 | /** |
| Kojto | 96:487b796308b0 | 509 | * @} |
| Kojto | 96:487b796308b0 | 510 | */ |
| Kojto | 96:487b796308b0 | 511 | |
| Kojto | 96:487b796308b0 | 512 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| Kojto | 96:487b796308b0 | 513 | * @{ |
| Kojto | 96:487b796308b0 | 514 | */ |
| Kojto | 96:487b796308b0 | 515 | |
| Kojto | 96:487b796308b0 | 516 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 517 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) |
| Kojto | 96:487b796308b0 | 518 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) |
| Kojto | 96:487b796308b0 | 519 | |
| Kojto | 96:487b796308b0 | 520 | /** |
| Kojto | 96:487b796308b0 | 521 | * @} |
| Kojto | 96:487b796308b0 | 522 | */ |
| Kojto | 96:487b796308b0 | 523 | |
| Kojto | 96:487b796308b0 | 524 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| Kojto | 96:487b796308b0 | 525 | * @{ |
| Kojto | 96:487b796308b0 | 526 | */ |
| Kojto | 96:487b796308b0 | 527 | |
| Kojto | 96:487b796308b0 | 528 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) |
| Kojto | 96:487b796308b0 | 529 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 530 | /** |
| Kojto | 96:487b796308b0 | 531 | * @} |
| Kojto | 96:487b796308b0 | 532 | */ |
| Kojto | 96:487b796308b0 | 533 | |
| Kojto | 96:487b796308b0 | 534 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| Kojto | 96:487b796308b0 | 535 | * @{ |
| Kojto | 96:487b796308b0 | 536 | */ |
| Kojto | 96:487b796308b0 | 537 | |
| Kojto | 96:487b796308b0 | 538 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 539 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) |
| Kojto | 96:487b796308b0 | 540 | |
| Kojto | 96:487b796308b0 | 541 | /** |
| Kojto | 96:487b796308b0 | 542 | * @} |
| Kojto | 96:487b796308b0 | 543 | */ |
| Kojto | 96:487b796308b0 | 544 | |
| Kojto | 96:487b796308b0 | 545 | |
| Kojto | 96:487b796308b0 | 546 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| Kojto | 96:487b796308b0 | 547 | * @{ |
| Kojto | 96:487b796308b0 | 548 | */ |
| Kojto | 96:487b796308b0 | 549 | |
| Kojto | 96:487b796308b0 | 550 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 551 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) |
| Kojto | 96:487b796308b0 | 552 | |
| Kojto | 96:487b796308b0 | 553 | /** |
| Kojto | 96:487b796308b0 | 554 | * @} |
| Kojto | 96:487b796308b0 | 555 | */ |
| Kojto | 96:487b796308b0 | 556 | |
| Kojto | 96:487b796308b0 | 557 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| Kojto | 96:487b796308b0 | 558 | * @{ |
| Kojto | 96:487b796308b0 | 559 | */ |
| Kojto | 96:487b796308b0 | 560 | |
| Kojto | 96:487b796308b0 | 561 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 562 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) |
| Kojto | 96:487b796308b0 | 563 | |
| Kojto | 96:487b796308b0 | 564 | /** |
| Kojto | 96:487b796308b0 | 565 | * @} |
| Kojto | 96:487b796308b0 | 566 | */ |
| Kojto | 96:487b796308b0 | 567 | |
| Kojto | 96:487b796308b0 | 568 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| Kojto | 96:487b796308b0 | 569 | * @{ |
| Kojto | 96:487b796308b0 | 570 | */ |
| Kojto | 96:487b796308b0 | 571 | |
| Kojto | 96:487b796308b0 | 572 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 573 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) |
| Kojto | 96:487b796308b0 | 574 | |
| Kojto | 96:487b796308b0 | 575 | /** |
| Kojto | 96:487b796308b0 | 576 | * @} |
| Kojto | 96:487b796308b0 | 577 | */ |
| Kojto | 96:487b796308b0 | 578 | |
| Kojto | 96:487b796308b0 | 579 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| Kojto | 96:487b796308b0 | 580 | * @{ |
| Kojto | 96:487b796308b0 | 581 | */ |
| Kojto | 96:487b796308b0 | 582 | |
| Kojto | 96:487b796308b0 | 583 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 584 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) |
| Kojto | 96:487b796308b0 | 585 | |
| Kojto | 96:487b796308b0 | 586 | /** |
| Kojto | 96:487b796308b0 | 587 | * @} |
| Kojto | 96:487b796308b0 | 588 | */ |
| Kojto | 96:487b796308b0 | 589 | |
| Kojto | 96:487b796308b0 | 590 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| Kojto | 96:487b796308b0 | 591 | * @{ |
| Kojto | 96:487b796308b0 | 592 | */ |
| Kojto | 96:487b796308b0 | 593 | |
| Kojto | 96:487b796308b0 | 594 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 595 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) |
| Kojto | 96:487b796308b0 | 596 | |
| Kojto | 96:487b796308b0 | 597 | /** |
| Kojto | 96:487b796308b0 | 598 | * @} |
| Kojto | 96:487b796308b0 | 599 | */ |
| Kojto | 96:487b796308b0 | 600 | |
| Kojto | 96:487b796308b0 | 601 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| Kojto | 96:487b796308b0 | 602 | * @{ |
| Kojto | 96:487b796308b0 | 603 | */ |
| Kojto | 96:487b796308b0 | 604 | |
| Kojto | 96:487b796308b0 | 605 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 606 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) |
| Kojto | 96:487b796308b0 | 607 | |
| Kojto | 96:487b796308b0 | 608 | /** |
| Kojto | 96:487b796308b0 | 609 | * @} |
| Kojto | 96:487b796308b0 | 610 | */ |
| Kojto | 96:487b796308b0 | 611 | |
| Kojto | 96:487b796308b0 | 612 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| Kojto | 96:487b796308b0 | 613 | * @{ |
| Kojto | 96:487b796308b0 | 614 | */ |
| Kojto | 96:487b796308b0 | 615 | |
| Kojto | 96:487b796308b0 | 616 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 617 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) |
| Kojto | 96:487b796308b0 | 618 | |
| Kojto | 96:487b796308b0 | 619 | /** |
| Kojto | 96:487b796308b0 | 620 | * @} |
| Kojto | 96:487b796308b0 | 621 | */ |
| Kojto | 96:487b796308b0 | 622 | |
| Kojto | 96:487b796308b0 | 623 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| Kojto | 96:487b796308b0 | 624 | * @{ |
| Kojto | 96:487b796308b0 | 625 | */ |
| Kojto | 96:487b796308b0 | 626 | |
| Kojto | 96:487b796308b0 | 627 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 628 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) |
| Kojto | 96:487b796308b0 | 629 | |
| Kojto | 96:487b796308b0 | 630 | /** |
| Kojto | 96:487b796308b0 | 631 | * @} |
| Kojto | 96:487b796308b0 | 632 | */ |
| Kojto | 96:487b796308b0 | 633 | |
| Kojto | 96:487b796308b0 | 634 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| Kojto | 96:487b796308b0 | 635 | * @{ |
| Kojto | 96:487b796308b0 | 636 | */ |
| Kojto | 96:487b796308b0 | 637 | |
| Kojto | 96:487b796308b0 | 638 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 639 | #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) |
| Kojto | 96:487b796308b0 | 640 | #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) |
| Kojto | 96:487b796308b0 | 641 | #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) |
| Kojto | 96:487b796308b0 | 642 | |
| Kojto | 96:487b796308b0 | 643 | /** |
| Kojto | 96:487b796308b0 | 644 | * @} |
| Kojto | 96:487b796308b0 | 645 | */ |
| Kojto | 96:487b796308b0 | 646 | |
| Kojto | 96:487b796308b0 | 647 | |
| Kojto | 96:487b796308b0 | 648 | /** |
| Kojto | 96:487b796308b0 | 649 | * @} |
| Kojto | 96:487b796308b0 | 650 | */ |
| Kojto | 96:487b796308b0 | 651 | |
| Kojto | 96:487b796308b0 | 652 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| Kojto | 96:487b796308b0 | 653 | /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller |
| Kojto | 96:487b796308b0 | 654 | * @{ |
| Kojto | 96:487b796308b0 | 655 | */ |
| Kojto | 96:487b796308b0 | 656 | |
| Kojto | 96:487b796308b0 | 657 | /** @defgroup FSMC_NAND_Bank FSMC_NAND_Bank |
| Kojto | 96:487b796308b0 | 658 | * @{ |
| Kojto | 96:487b796308b0 | 659 | */ |
| Kojto | 96:487b796308b0 | 660 | #define FSMC_NAND_BANK2 ((uint32_t)0x00000010) |
| Kojto | 96:487b796308b0 | 661 | #define FSMC_NAND_BANK3 ((uint32_t)0x00000100) |
| Kojto | 96:487b796308b0 | 662 | |
| Kojto | 96:487b796308b0 | 663 | /** |
| Kojto | 96:487b796308b0 | 664 | * @} |
| Kojto | 96:487b796308b0 | 665 | */ |
| Kojto | 96:487b796308b0 | 666 | |
| Kojto | 96:487b796308b0 | 667 | /** @defgroup FSMC_Wait_feature FSMC_Wait_feature |
| Kojto | 96:487b796308b0 | 668 | * @{ |
| Kojto | 96:487b796308b0 | 669 | */ |
| Kojto | 96:487b796308b0 | 670 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 671 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) |
| Kojto | 96:487b796308b0 | 672 | |
| Kojto | 96:487b796308b0 | 673 | /** |
| Kojto | 96:487b796308b0 | 674 | * @} |
| Kojto | 96:487b796308b0 | 675 | */ |
| Kojto | 96:487b796308b0 | 676 | |
| Kojto | 96:487b796308b0 | 677 | /** @defgroup FSMC_PCR_Memory_Type FSMC_PCR_Memory_Type |
| Kojto | 96:487b796308b0 | 678 | * @{ |
| Kojto | 96:487b796308b0 | 679 | */ |
| Kojto | 96:487b796308b0 | 680 | #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 681 | #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP) |
| Kojto | 96:487b796308b0 | 682 | /** |
| Kojto | 96:487b796308b0 | 683 | * @} |
| Kojto | 96:487b796308b0 | 684 | */ |
| Kojto | 96:487b796308b0 | 685 | |
| Kojto | 96:487b796308b0 | 686 | /** @defgroup FSMC_NAND_Data_Width FSMC_NAND_Data_Width |
| Kojto | 96:487b796308b0 | 687 | * @{ |
| Kojto | 96:487b796308b0 | 688 | */ |
| Kojto | 96:487b796308b0 | 689 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 690 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0) |
| Kojto | 96:487b796308b0 | 691 | |
| Kojto | 96:487b796308b0 | 692 | /** |
| Kojto | 96:487b796308b0 | 693 | * @} |
| Kojto | 96:487b796308b0 | 694 | */ |
| Kojto | 96:487b796308b0 | 695 | |
| Kojto | 96:487b796308b0 | 696 | /** @defgroup FSMC_ECC FSMC_ECC |
| Kojto | 96:487b796308b0 | 697 | * @{ |
| Kojto | 96:487b796308b0 | 698 | */ |
| Kojto | 96:487b796308b0 | 699 | #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 700 | #define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN) |
| Kojto | 96:487b796308b0 | 701 | |
| Kojto | 96:487b796308b0 | 702 | /** |
| Kojto | 96:487b796308b0 | 703 | * @} |
| Kojto | 96:487b796308b0 | 704 | */ |
| Kojto | 96:487b796308b0 | 705 | |
| Kojto | 96:487b796308b0 | 706 | /** @defgroup FSMC_ECC_Page_Size FSMC_ECC_Page_Size |
| Kojto | 96:487b796308b0 | 707 | * @{ |
| Kojto | 96:487b796308b0 | 708 | */ |
| Kojto | 96:487b796308b0 | 709 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 710 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0) |
| Kojto | 96:487b796308b0 | 711 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1) |
| Kojto | 96:487b796308b0 | 712 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1) |
| Kojto | 96:487b796308b0 | 713 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2) |
| Kojto | 96:487b796308b0 | 714 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2) |
| Kojto | 96:487b796308b0 | 715 | |
| Kojto | 96:487b796308b0 | 716 | /** |
| Kojto | 96:487b796308b0 | 717 | * @} |
| Kojto | 96:487b796308b0 | 718 | */ |
| Kojto | 96:487b796308b0 | 719 | |
| Kojto | 96:487b796308b0 | 720 | /** @defgroup FSMC_Interrupt_definition FSMC_Interrupt_definition |
| Kojto | 96:487b796308b0 | 721 | * @brief FSMC Interrupt definition |
| Kojto | 96:487b796308b0 | 722 | * @{ |
| Kojto | 96:487b796308b0 | 723 | */ |
| Kojto | 96:487b796308b0 | 724 | #define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN) |
| Kojto | 96:487b796308b0 | 725 | #define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN) |
| Kojto | 96:487b796308b0 | 726 | #define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN) |
| Kojto | 96:487b796308b0 | 727 | |
| Kojto | 96:487b796308b0 | 728 | /** |
| Kojto | 96:487b796308b0 | 729 | * @} |
| Kojto | 96:487b796308b0 | 730 | */ |
| Kojto | 96:487b796308b0 | 731 | |
| Kojto | 96:487b796308b0 | 732 | /** @defgroup FSMC_Flag_definition FSMC_Flag_definition |
| Kojto | 96:487b796308b0 | 733 | * @brief FSMC Flag definition |
| Kojto | 96:487b796308b0 | 734 | * @{ |
| Kojto | 96:487b796308b0 | 735 | */ |
| Kojto | 96:487b796308b0 | 736 | #define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS) |
| Kojto | 96:487b796308b0 | 737 | #define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS) |
| Kojto | 96:487b796308b0 | 738 | #define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS) |
| Kojto | 96:487b796308b0 | 739 | #define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT) |
| Kojto | 96:487b796308b0 | 740 | |
| Kojto | 96:487b796308b0 | 741 | /** |
| Kojto | 96:487b796308b0 | 742 | * @} |
| Kojto | 96:487b796308b0 | 743 | */ |
| Kojto | 96:487b796308b0 | 744 | |
| Kojto | 96:487b796308b0 | 745 | /** |
| Kojto | 96:487b796308b0 | 746 | * @} |
| Kojto | 96:487b796308b0 | 747 | */ |
| Kojto | 96:487b796308b0 | 748 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| Kojto | 96:487b796308b0 | 749 | |
| Kojto | 96:487b796308b0 | 750 | /** |
| Kojto | 96:487b796308b0 | 751 | * @} |
| Kojto | 96:487b796308b0 | 752 | */ |
| Kojto | 96:487b796308b0 | 753 | |
| Kojto | 96:487b796308b0 | 754 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 755 | |
| Kojto | 96:487b796308b0 | 756 | /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros |
| Kojto | 96:487b796308b0 | 757 | * @{ |
| Kojto | 96:487b796308b0 | 758 | */ |
| Kojto | 96:487b796308b0 | 759 | |
| Kojto | 96:487b796308b0 | 760 | /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros |
| Kojto | 96:487b796308b0 | 761 | * @brief macros to handle NOR device enable/disable and read/write operations |
| Kojto | 96:487b796308b0 | 762 | * @{ |
| Kojto | 96:487b796308b0 | 763 | */ |
| Kojto | 96:487b796308b0 | 764 | |
| Kojto | 96:487b796308b0 | 765 | /** |
| Kojto | 96:487b796308b0 | 766 | * @brief Enable the NORSRAM device access. |
| Kojto | 96:487b796308b0 | 767 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| Kojto | 96:487b796308b0 | 768 | * @param __BANK__: FSMC_NORSRAM Bank |
| Kojto | 96:487b796308b0 | 769 | * @retval none |
| Kojto | 96:487b796308b0 | 770 | */ |
| Kojto | 96:487b796308b0 | 771 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| Kojto | 96:487b796308b0 | 772 | |
| Kojto | 96:487b796308b0 | 773 | /** |
| Kojto | 96:487b796308b0 | 774 | * @brief Disable the NORSRAM device access. |
| Kojto | 96:487b796308b0 | 775 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| Kojto | 96:487b796308b0 | 776 | * @param __BANK__: FSMC_NORSRAM Bank |
| Kojto | 96:487b796308b0 | 777 | * @retval none |
| Kojto | 96:487b796308b0 | 778 | */ |
| Kojto | 96:487b796308b0 | 779 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| Kojto | 96:487b796308b0 | 780 | |
| Kojto | 96:487b796308b0 | 781 | /** |
| Kojto | 96:487b796308b0 | 782 | * @} |
| Kojto | 96:487b796308b0 | 783 | */ |
| Kojto | 96:487b796308b0 | 784 | |
| Kojto | 96:487b796308b0 | 785 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| Kojto | 96:487b796308b0 | 786 | /** @defgroup FSMC_NAND_Macros FSMC_NAND_Macros |
| Kojto | 96:487b796308b0 | 787 | * @brief macros to handle NAND device enable/disable |
| Kojto | 96:487b796308b0 | 788 | * @{ |
| Kojto | 96:487b796308b0 | 789 | */ |
| Kojto | 96:487b796308b0 | 790 | |
| Kojto | 96:487b796308b0 | 791 | /** |
| Kojto | 96:487b796308b0 | 792 | * @brief Enable the NAND device access. |
| Kojto | 96:487b796308b0 | 793 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 794 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 795 | * @retval None |
| Kojto | 96:487b796308b0 | 796 | */ |
| Kojto | 96:487b796308b0 | 797 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
| Kojto | 96:487b796308b0 | 798 | SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
| Kojto | 96:487b796308b0 | 799 | |
| Kojto | 96:487b796308b0 | 800 | /** |
| Kojto | 96:487b796308b0 | 801 | * @brief Disable the NAND device access. |
| Kojto | 96:487b796308b0 | 802 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 803 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 804 | * @retval None |
| Kojto | 96:487b796308b0 | 805 | */ |
| Kojto | 96:487b796308b0 | 806 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
| Kojto | 96:487b796308b0 | 807 | CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
| Kojto | 96:487b796308b0 | 808 | /** |
| Kojto | 96:487b796308b0 | 809 | * @} |
| Kojto | 96:487b796308b0 | 810 | */ |
| Kojto | 96:487b796308b0 | 811 | |
| Kojto | 96:487b796308b0 | 812 | /** @defgroup FSMC_PCCARD_Macros FSMC_PCCARD_Macros |
| Kojto | 96:487b796308b0 | 813 | * @brief macros to handle SRAM read/write operations |
| Kojto | 96:487b796308b0 | 814 | * @{ |
| Kojto | 96:487b796308b0 | 815 | */ |
| Kojto | 96:487b796308b0 | 816 | |
| Kojto | 96:487b796308b0 | 817 | /** |
| Kojto | 96:487b796308b0 | 818 | * @brief Enable the PCCARD device access. |
| Kojto | 96:487b796308b0 | 819 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 820 | * @retval None |
| Kojto | 96:487b796308b0 | 821 | */ |
| Kojto | 96:487b796308b0 | 822 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) |
| Kojto | 96:487b796308b0 | 823 | |
| Kojto | 96:487b796308b0 | 824 | /** |
| Kojto | 96:487b796308b0 | 825 | * @brief Disable the PCCARD device access. |
| Kojto | 96:487b796308b0 | 826 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 827 | * @retval None |
| Kojto | 96:487b796308b0 | 828 | */ |
| Kojto | 96:487b796308b0 | 829 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) |
| Kojto | 96:487b796308b0 | 830 | /** |
| Kojto | 96:487b796308b0 | 831 | * @} |
| Kojto | 96:487b796308b0 | 832 | */ |
| Kojto | 96:487b796308b0 | 833 | |
| Kojto | 96:487b796308b0 | 834 | /** @defgroup FSMC_Interrupt FSMC_Interrupt |
| Kojto | 96:487b796308b0 | 835 | * @brief macros to handle FSMC interrupts |
| Kojto | 96:487b796308b0 | 836 | * @{ |
| Kojto | 96:487b796308b0 | 837 | */ |
| Kojto | 96:487b796308b0 | 838 | |
| Kojto | 96:487b796308b0 | 839 | /** |
| Kojto | 96:487b796308b0 | 840 | * @brief Enable the NAND device interrupt. |
| Kojto | 96:487b796308b0 | 841 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 842 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 843 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| Kojto | 96:487b796308b0 | 844 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 845 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 96:487b796308b0 | 846 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 96:487b796308b0 | 847 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 96:487b796308b0 | 848 | * @retval None |
| Kojto | 96:487b796308b0 | 849 | */ |
| Kojto | 96:487b796308b0 | 850 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| Kojto | 96:487b796308b0 | 851 | SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| Kojto | 96:487b796308b0 | 852 | |
| Kojto | 96:487b796308b0 | 853 | /** |
| Kojto | 96:487b796308b0 | 854 | * @brief Disable the NAND device interrupt. |
| Kojto | 96:487b796308b0 | 855 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 856 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 857 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| Kojto | 96:487b796308b0 | 858 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 859 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 96:487b796308b0 | 860 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 96:487b796308b0 | 861 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 96:487b796308b0 | 862 | * @retval None |
| Kojto | 96:487b796308b0 | 863 | */ |
| Kojto | 96:487b796308b0 | 864 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| Kojto | 96:487b796308b0 | 865 | CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| Kojto | 96:487b796308b0 | 866 | |
| Kojto | 96:487b796308b0 | 867 | /** |
| Kojto | 96:487b796308b0 | 868 | * @brief Get flag status of the NAND device. |
| Kojto | 96:487b796308b0 | 869 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 870 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 871 | * @param __FLAG__: FSMC_NAND flag |
| Kojto | 96:487b796308b0 | 872 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 873 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 96:487b796308b0 | 874 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 96:487b796308b0 | 875 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 96:487b796308b0 | 876 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 96:487b796308b0 | 877 | * @retval The state of FLAG (SET or RESET). |
| Kojto | 96:487b796308b0 | 878 | */ |
| Kojto | 96:487b796308b0 | 879 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| Kojto | 96:487b796308b0 | 880 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| Kojto | 96:487b796308b0 | 881 | /** |
| Kojto | 96:487b796308b0 | 882 | * @brief Clear flag status of the NAND device. |
| Kojto | 96:487b796308b0 | 883 | * @param __INSTANCE__: FSMC_NAND Instance |
| Kojto | 96:487b796308b0 | 884 | * @param __BANK__: FSMC_NAND Bank |
| Kojto | 96:487b796308b0 | 885 | * @param __FLAG__: FSMC_NAND flag |
| Kojto | 96:487b796308b0 | 886 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 887 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 96:487b796308b0 | 888 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 96:487b796308b0 | 889 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 96:487b796308b0 | 890 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 96:487b796308b0 | 891 | * @retval None |
| Kojto | 96:487b796308b0 | 892 | */ |
| Kojto | 96:487b796308b0 | 893 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \ |
| Kojto | 96:487b796308b0 | 894 | CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__))) |
| Kojto | 96:487b796308b0 | 895 | /** |
| Kojto | 96:487b796308b0 | 896 | * @brief Enable the PCCARD device interrupt. |
| Kojto | 96:487b796308b0 | 897 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 898 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| Kojto | 96:487b796308b0 | 899 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 900 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 96:487b796308b0 | 901 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 96:487b796308b0 | 902 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 96:487b796308b0 | 903 | * @retval None |
| Kojto | 96:487b796308b0 | 904 | */ |
| Kojto | 96:487b796308b0 | 905 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 906 | |
| Kojto | 96:487b796308b0 | 907 | /** |
| Kojto | 96:487b796308b0 | 908 | * @brief Disable the PCCARD device interrupt. |
| Kojto | 96:487b796308b0 | 909 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 910 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| Kojto | 96:487b796308b0 | 911 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 912 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| Kojto | 96:487b796308b0 | 913 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| Kojto | 96:487b796308b0 | 914 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| Kojto | 96:487b796308b0 | 915 | * @retval None |
| Kojto | 96:487b796308b0 | 916 | */ |
| Kojto | 96:487b796308b0 | 917 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 918 | |
| Kojto | 96:487b796308b0 | 919 | /** |
| Kojto | 96:487b796308b0 | 920 | * @brief Get flag status of the PCCARD device. |
| Kojto | 96:487b796308b0 | 921 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 922 | * @param __FLAG__: FSMC_PCCARD flag |
| Kojto | 96:487b796308b0 | 923 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 924 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 96:487b796308b0 | 925 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 96:487b796308b0 | 926 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 96:487b796308b0 | 927 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 96:487b796308b0 | 928 | * @retval The state of FLAG (SET or RESET). |
| Kojto | 96:487b796308b0 | 929 | */ |
| Kojto | 96:487b796308b0 | 930 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| Kojto | 96:487b796308b0 | 931 | |
| Kojto | 96:487b796308b0 | 932 | /** |
| Kojto | 96:487b796308b0 | 933 | * @brief Clear flag status of the PCCARD device. |
| Kojto | 96:487b796308b0 | 934 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| Kojto | 96:487b796308b0 | 935 | * @param __FLAG__: FSMC_PCCARD flag |
| Kojto | 96:487b796308b0 | 936 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 937 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| Kojto | 96:487b796308b0 | 938 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| Kojto | 96:487b796308b0 | 939 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| Kojto | 96:487b796308b0 | 940 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| Kojto | 96:487b796308b0 | 941 | * @retval None |
| Kojto | 96:487b796308b0 | 942 | */ |
| Kojto | 96:487b796308b0 | 943 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__)) |
| Kojto | 96:487b796308b0 | 944 | |
| Kojto | 96:487b796308b0 | 945 | /** |
| Kojto | 96:487b796308b0 | 946 | * @} |
| Kojto | 96:487b796308b0 | 947 | */ |
| Kojto | 96:487b796308b0 | 948 | |
| Kojto | 96:487b796308b0 | 949 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| Kojto | 96:487b796308b0 | 950 | |
| Kojto | 96:487b796308b0 | 951 | /** |
| Kojto | 96:487b796308b0 | 952 | * @} |
| Kojto | 96:487b796308b0 | 953 | */ |
| Kojto | 96:487b796308b0 | 954 | |
| Kojto | 96:487b796308b0 | 955 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 956 | |
| Kojto | 96:487b796308b0 | 957 | /** @addtogroup FSMC_LL_Exported_Functions |
| Kojto | 96:487b796308b0 | 958 | * @{ |
| Kojto | 96:487b796308b0 | 959 | */ |
| Kojto | 96:487b796308b0 | 960 | |
| Kojto | 96:487b796308b0 | 961 | /** @addtogroup FSMC_NORSRAM |
| Kojto | 96:487b796308b0 | 962 | * @{ |
| Kojto | 96:487b796308b0 | 963 | */ |
| Kojto | 96:487b796308b0 | 964 | |
| Kojto | 96:487b796308b0 | 965 | /** @addtogroup FSMC_NORSRAM_Group1 |
| Kojto | 96:487b796308b0 | 966 | * @{ |
| Kojto | 96:487b796308b0 | 967 | */ |
| Kojto | 96:487b796308b0 | 968 | |
| Kojto | 96:487b796308b0 | 969 | /* FSMC_NORSRAM Controller functions ******************************************/ |
| Kojto | 96:487b796308b0 | 970 | /* Initialization/de-initialization functions */ |
| Kojto | 96:487b796308b0 | 971 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| Kojto | 96:487b796308b0 | 972 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 973 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| Kojto | 96:487b796308b0 | 974 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 975 | |
| Kojto | 96:487b796308b0 | 976 | /** |
| Kojto | 96:487b796308b0 | 977 | * @} |
| Kojto | 96:487b796308b0 | 978 | */ |
| Kojto | 96:487b796308b0 | 979 | |
| Kojto | 96:487b796308b0 | 980 | /** @addtogroup FSMC_NORSRAM_Group2 |
| Kojto | 96:487b796308b0 | 981 | * @{ |
| Kojto | 96:487b796308b0 | 982 | */ |
| Kojto | 96:487b796308b0 | 983 | |
| Kojto | 96:487b796308b0 | 984 | /* FSMC_NORSRAM Control functions */ |
| Kojto | 96:487b796308b0 | 985 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 986 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 987 | |
| Kojto | 96:487b796308b0 | 988 | /** |
| Kojto | 96:487b796308b0 | 989 | * @} |
| Kojto | 96:487b796308b0 | 990 | */ |
| Kojto | 96:487b796308b0 | 991 | |
| Kojto | 96:487b796308b0 | 992 | /** |
| Kojto | 96:487b796308b0 | 993 | * @} |
| Kojto | 96:487b796308b0 | 994 | */ |
| Kojto | 96:487b796308b0 | 995 | |
| Kojto | 96:487b796308b0 | 996 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| Kojto | 96:487b796308b0 | 997 | /** @addtogroup FSMC_NAND |
| Kojto | 96:487b796308b0 | 998 | * @{ |
| Kojto | 96:487b796308b0 | 999 | */ |
| Kojto | 96:487b796308b0 | 1000 | |
| Kojto | 96:487b796308b0 | 1001 | /* FSMC_NAND Controller functions **********************************************/ |
| Kojto | 96:487b796308b0 | 1002 | /* Initialization/de-initialization functions */ |
| Kojto | 96:487b796308b0 | 1003 | /** @addtogroup FSMC_NAND_Exported_Functions_Group1 |
| Kojto | 96:487b796308b0 | 1004 | * @{ |
| Kojto | 96:487b796308b0 | 1005 | */ |
| Kojto | 96:487b796308b0 | 1006 | |
| Kojto | 96:487b796308b0 | 1007 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| Kojto | 96:487b796308b0 | 1008 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 1009 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 1010 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 1011 | |
| Kojto | 96:487b796308b0 | 1012 | /** |
| Kojto | 96:487b796308b0 | 1013 | * @} |
| Kojto | 96:487b796308b0 | 1014 | */ |
| Kojto | 96:487b796308b0 | 1015 | |
| Kojto | 96:487b796308b0 | 1016 | /* FSMC_NAND Control functions */ |
| Kojto | 96:487b796308b0 | 1017 | /** @addtogroup FSMC_NAND_Exported_Functions_Group2 |
| Kojto | 96:487b796308b0 | 1018 | * @{ |
| Kojto | 96:487b796308b0 | 1019 | */ |
| Kojto | 96:487b796308b0 | 1020 | |
| Kojto | 96:487b796308b0 | 1021 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 1022 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| Kojto | 96:487b796308b0 | 1023 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| Kojto | 96:487b796308b0 | 1024 | |
| Kojto | 96:487b796308b0 | 1025 | /** |
| Kojto | 96:487b796308b0 | 1026 | * @} |
| Kojto | 96:487b796308b0 | 1027 | */ |
| Kojto | 96:487b796308b0 | 1028 | |
| Kojto | 96:487b796308b0 | 1029 | /** |
| Kojto | 96:487b796308b0 | 1030 | * @} |
| Kojto | 96:487b796308b0 | 1031 | */ |
| Kojto | 96:487b796308b0 | 1032 | |
| Kojto | 96:487b796308b0 | 1033 | /** @addtogroup FSMC_PCCARD |
| Kojto | 96:487b796308b0 | 1034 | * @{ |
| Kojto | 96:487b796308b0 | 1035 | */ |
| Kojto | 96:487b796308b0 | 1036 | |
| Kojto | 96:487b796308b0 | 1037 | /* FSMC_PCCARD Controller functions ********************************************/ |
| Kojto | 96:487b796308b0 | 1038 | /* Initialization/de-initialization functions */ |
| Kojto | 96:487b796308b0 | 1039 | /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1 |
| Kojto | 96:487b796308b0 | 1040 | * @{ |
| Kojto | 96:487b796308b0 | 1041 | */ |
| Kojto | 96:487b796308b0 | 1042 | |
| Kojto | 96:487b796308b0 | 1043 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| Kojto | 96:487b796308b0 | 1044 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 96:487b796308b0 | 1045 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 96:487b796308b0 | 1046 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| Kojto | 96:487b796308b0 | 1047 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| Kojto | 96:487b796308b0 | 1048 | |
| Kojto | 96:487b796308b0 | 1049 | /** |
| Kojto | 96:487b796308b0 | 1050 | * @} |
| Kojto | 96:487b796308b0 | 1051 | */ |
| Kojto | 96:487b796308b0 | 1052 | |
| Kojto | 96:487b796308b0 | 1053 | /** |
| Kojto | 96:487b796308b0 | 1054 | * @} |
| Kojto | 96:487b796308b0 | 1055 | */ |
| Kojto | 96:487b796308b0 | 1056 | |
| Kojto | 96:487b796308b0 | 1057 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| Kojto | 96:487b796308b0 | 1058 | |
| Kojto | 96:487b796308b0 | 1059 | /** |
| Kojto | 96:487b796308b0 | 1060 | * @} |
| Kojto | 96:487b796308b0 | 1061 | */ |
| Kojto | 96:487b796308b0 | 1062 | |
| Kojto | 96:487b796308b0 | 1063 | /** |
| Kojto | 96:487b796308b0 | 1064 | * @} |
| Kojto | 96:487b796308b0 | 1065 | */ |
| Kojto | 96:487b796308b0 | 1066 | |
| Kojto | 96:487b796308b0 | 1067 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
| Kojto | 96:487b796308b0 | 1068 | |
| Kojto | 96:487b796308b0 | 1069 | /** |
| Kojto | 96:487b796308b0 | 1070 | * @} |
| Kojto | 96:487b796308b0 | 1071 | */ |
| Kojto | 96:487b796308b0 | 1072 | |
| Kojto | 96:487b796308b0 | 1073 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 1074 | } |
| Kojto | 96:487b796308b0 | 1075 | #endif |
| Kojto | 96:487b796308b0 | 1076 | |
| Kojto | 96:487b796308b0 | 1077 | #endif /* __STM32F1xx_LL_FSMC_H */ |
| Kojto | 96:487b796308b0 | 1078 | |
| Kojto | 96:487b796308b0 | 1079 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| Kojto | 96:487b796308b0 | 1080 |