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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:: Mikchel
Date:: Sun May 03 16:04:42 2015 +0000
Revision:: 99:7f6c6de930c0
Parent:: 96:487b796308b0

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	96:487b796308b0	1	/**
Kojto	96:487b796308b0	2	******************************************************************************
Kojto	96:487b796308b0	3	* @file stm32f1xx_hal_rcc.h
Kojto	96:487b796308b0	4	* @author MCD Application Team
Kojto	96:487b796308b0	5	* @version V1.0.0
Kojto	96:487b796308b0	6	* @date 15-December-2014
Kojto	96:487b796308b0	7	* @brief Header file of RCC HAL module.
Kojto	96:487b796308b0	8	******************************************************************************
Kojto	96:487b796308b0	9	* @attention
Kojto	96:487b796308b0	10	*
Kojto	96:487b796308b0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	96:487b796308b0	12	*
Kojto	96:487b796308b0	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	96:487b796308b0	14	* are permitted provided that the following conditions are met:
Kojto	96:487b796308b0	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	96:487b796308b0	16	* this list of conditions and the following disclaimer.
Kojto	96:487b796308b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	96:487b796308b0	18	* this list of conditions and the following disclaimer in the documentation
Kojto	96:487b796308b0	19	* and/or other materials provided with the distribution.
Kojto	96:487b796308b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	96:487b796308b0	21	* may be used to endorse or promote products derived from this software
Kojto	96:487b796308b0	22	* without specific prior written permission.
Kojto	96:487b796308b0	23	*
Kojto	96:487b796308b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	96:487b796308b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	96:487b796308b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	96:487b796308b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	96:487b796308b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	96:487b796308b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	96:487b796308b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	96:487b796308b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	96:487b796308b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	96:487b796308b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	96:487b796308b0	34	*
Kojto	96:487b796308b0	35	******************************************************************************
Kojto	96:487b796308b0	36	*/
Kojto	96:487b796308b0	37
Kojto	96:487b796308b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	96:487b796308b0	39	#ifndef __STM32F1xx_HAL_RCC_H
Kojto	96:487b796308b0	40	#define __STM32F1xx_HAL_RCC_H
Kojto	96:487b796308b0	41
Kojto	96:487b796308b0	42	#ifdef __cplusplus
Kojto	96:487b796308b0	43	extern "C" {
Kojto	96:487b796308b0	44	#endif
Kojto	96:487b796308b0	45
Kojto	96:487b796308b0	46	/* Includes ------------------------------------------------------------------*/
Kojto	96:487b796308b0	47	#include "stm32f1xx_hal_def.h"
Kojto	96:487b796308b0	48
Kojto	96:487b796308b0	49	/** @addtogroup STM32F1xx_HAL_Driver
Kojto	96:487b796308b0	50	* @{
Kojto	96:487b796308b0	51	*/
Kojto	96:487b796308b0	52
Kojto	96:487b796308b0	53	/** @addtogroup RCC
Kojto	96:487b796308b0	54	* @{
Kojto	96:487b796308b0	55	*/
Kojto	96:487b796308b0	56
Kojto	96:487b796308b0	57	/** @addtogroup RCC_Private_Constants
Kojto	96:487b796308b0	58	* @{
Kojto	96:487b796308b0	59	*/
Kojto	96:487b796308b0	60
Kojto	96:487b796308b0	61	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	96:487b796308b0	62	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	96:487b796308b0	63	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	96:487b796308b0	64	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	96:487b796308b0	65	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	96:487b796308b0	66	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	96:487b796308b0	67	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	96:487b796308b0	68	#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
Kojto	96:487b796308b0	69
Kojto	96:487b796308b0	70	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
Kojto	96:487b796308b0	71	* @brief RCC registers bit address in the alias region
Kojto	96:487b796308b0	72	* @{
Kojto	96:487b796308b0	73	*/
Kojto	96:487b796308b0	74	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	96:487b796308b0	75	#define RCC_CR_OFFSET 0x00
Kojto	96:487b796308b0	76	#define RCC_CFGR_OFFSET 0x04
Kojto	96:487b796308b0	77	#define RCC_CIR_OFFSET 0x08
Kojto	96:487b796308b0	78	#define RCC_BDCR_OFFSET 0x20
Kojto	96:487b796308b0	79	#define RCC_CSR_OFFSET 0x24
Kojto	96:487b796308b0	80	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
Kojto	96:487b796308b0	81	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
Kojto	96:487b796308b0	82	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
Kojto	96:487b796308b0	83	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
Kojto	96:487b796308b0	84	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
Kojto	96:487b796308b0	85
Kojto	96:487b796308b0	86	/* --- CR Register ---*/
Kojto	96:487b796308b0	87	/* Alias word address of HSION bit */
Kojto	96:487b796308b0	88	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
Kojto	96:487b796308b0	89	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
Kojto	96:487b796308b0	90	/* Alias word address of HSEON bit */
Kojto	96:487b796308b0	91	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
Kojto	96:487b796308b0	92	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
Kojto	96:487b796308b0	93	/* Alias word address of CSSON bit */
Kojto	96:487b796308b0	94	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
Kojto	96:487b796308b0	95	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
Kojto	96:487b796308b0	96	/* Alias word address of PLLON bit */
Kojto	96:487b796308b0	97	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
Kojto	96:487b796308b0	98	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
Kojto	96:487b796308b0	99
Kojto	96:487b796308b0	100	/* --- CSR Register ---*/
Kojto	96:487b796308b0	101	/* Alias word address of LSION bit */
Kojto	96:487b796308b0	102	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
Kojto	96:487b796308b0	103	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
Kojto	96:487b796308b0	104
Kojto	96:487b796308b0	105	/* --- BDCR Register ---*/
Kojto	96:487b796308b0	106	/* Alias word address of LSEON bit */
Kojto	96:487b796308b0	107	#define LSEON_BITNUMBER POSITION_VAL(RCC_BDCR_LSEON)
Kojto	96:487b796308b0	108	#define BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
Kojto	96:487b796308b0	109
Kojto	96:487b796308b0	110	/* Alias word address of LSEON bit */
Kojto	96:487b796308b0	111	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
Kojto	96:487b796308b0	112	#define BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
Kojto	96:487b796308b0	113
Kojto	96:487b796308b0	114	/* Alias word address of RTCEN bit */
Kojto	96:487b796308b0	115	#define RTCEN_BITNUMBER POSITION_VAL(RCC_BDCR_RTCEN)
Kojto	96:487b796308b0	116	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
Kojto	96:487b796308b0	117
Kojto	96:487b796308b0	118	/* Alias word address of BDRST bit */
Kojto	96:487b796308b0	119	#define BDRST_BITNUMBER POSITION_VAL(RCC_BDCR_BDRST)
Kojto	96:487b796308b0	120	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
Kojto	96:487b796308b0	121
Kojto	96:487b796308b0	122	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	96:487b796308b0	123	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
Kojto	96:487b796308b0	124
Kojto	96:487b796308b0	125	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	96:487b796308b0	126	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
Kojto	96:487b796308b0	127
Kojto	96:487b796308b0	128	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	96:487b796308b0	129	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
Kojto	96:487b796308b0	130
Kojto	96:487b796308b0	131	/* Defines used for Flags */
Kojto	96:487b796308b0	132	#define CR_REG_INDEX ((uint8_t)1)
Kojto	96:487b796308b0	133	#define BDCR_REG_INDEX ((uint8_t)2)
Kojto	96:487b796308b0	134	#define CSR_REG_INDEX ((uint8_t)3)
Kojto	96:487b796308b0	135
Kojto	96:487b796308b0	136	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	96:487b796308b0	137
Kojto	96:487b796308b0	138	/**
Kojto	96:487b796308b0	139	* @}
Kojto	96:487b796308b0	140	*/
Kojto	96:487b796308b0	141
Kojto	96:487b796308b0	142	/** @addtogroup RCC_Private_Macros
Kojto	96:487b796308b0	143	* @{
Kojto	96:487b796308b0	144	*/
Kojto	96:487b796308b0	145
Kojto	96:487b796308b0	146	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
Kojto	96:487b796308b0	147	* @{
Kojto	96:487b796308b0	148	*/
Kojto	96:487b796308b0	149	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto	96:487b796308b0	150	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto	96:487b796308b0	151	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto	96:487b796308b0	152	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto	96:487b796308b0	153	/**
Kojto	96:487b796308b0	154	* @}
Kojto	96:487b796308b0	155	*/
Kojto	96:487b796308b0	156
Kojto	96:487b796308b0	157	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
Kojto	96:487b796308b0	158
Kojto	96:487b796308b0	159	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	96:487b796308b0	160
Kojto	96:487b796308b0	161	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	96:487b796308b0	162
Kojto	96:487b796308b0	163	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	96:487b796308b0	164	((__HSE__) == RCC_HSE_BYPASS))
Kojto	96:487b796308b0	165
Kojto	96:487b796308b0	166	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	96:487b796308b0	167	((__LSE__) == RCC_LSE_BYPASS))
Kojto	96:487b796308b0	168
Kojto	96:487b796308b0	169	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
Kojto	96:487b796308b0	170	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	96:487b796308b0	171
Kojto	96:487b796308b0	172	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	96:487b796308b0	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	96:487b796308b0	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	96:487b796308b0	175	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	96:487b796308b0	176	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto	96:487b796308b0	177
Kojto	96:487b796308b0	178	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	96:487b796308b0	179
Kojto	96:487b796308b0	180	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	96:487b796308b0	181	((__PLL__) == RCC_PLL_ON))
Kojto	96:487b796308b0	182
Kojto	96:487b796308b0	183	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	96:487b796308b0	184	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	96:487b796308b0	185	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	96:487b796308b0	186
Kojto	96:487b796308b0	187	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	96:487b796308b0	188	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	96:487b796308b0	189	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	96:487b796308b0	190	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	96:487b796308b0	191	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	96:487b796308b0	192
Kojto	96:487b796308b0	193	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	96:487b796308b0	194	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	96:487b796308b0	195	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	96:487b796308b0	196
Kojto	96:487b796308b0	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
Kojto	96:487b796308b0	198
Kojto	96:487b796308b0	199	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
Kojto	96:487b796308b0	200
Kojto	96:487b796308b0	201	/**
Kojto	96:487b796308b0	202	* @}
Kojto	96:487b796308b0	203	*/
Kojto	96:487b796308b0	204
Kojto	96:487b796308b0	205	/* Exported types ------------------------------------------------------------*/
Kojto	96:487b796308b0	206
Kojto	96:487b796308b0	207	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	96:487b796308b0	208	* @{
Kojto	96:487b796308b0	209	*/
Kojto	96:487b796308b0	210
Kojto	96:487b796308b0	211	/**
Kojto	96:487b796308b0	212	* @brief RCC PLL configuration structure definition
Kojto	96:487b796308b0	213	*/
Kojto	96:487b796308b0	214	typedef struct
Kojto	96:487b796308b0	215	{
Kojto	96:487b796308b0	216	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	96:487b796308b0	217	This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
Kojto	96:487b796308b0	218
Kojto	96:487b796308b0	219	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	96:487b796308b0	220	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	96:487b796308b0	221
Kojto	96:487b796308b0	222	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	96:487b796308b0	223	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
Kojto	96:487b796308b0	224	} RCC_PLLInitTypeDef;
Kojto	96:487b796308b0	225
Kojto	96:487b796308b0	226	/**
Kojto	96:487b796308b0	227	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	96:487b796308b0	228	*/
Kojto	96:487b796308b0	229	typedef struct
Kojto	96:487b796308b0	230	{
Kojto	96:487b796308b0	231	uint32_t ClockType; /*!< The clock to be configured.
Kojto	96:487b796308b0	232	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	96:487b796308b0	233
Kojto	96:487b796308b0	234	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	96:487b796308b0	235	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	96:487b796308b0	236
Kojto	96:487b796308b0	237	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	96:487b796308b0	238	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	96:487b796308b0	239
Kojto	96:487b796308b0	240	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	96:487b796308b0	241	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	96:487b796308b0	242
Kojto	96:487b796308b0	243	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	96:487b796308b0	244	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	96:487b796308b0	245
Kojto	96:487b796308b0	246	} RCC_ClkInitTypeDef;
Kojto	96:487b796308b0	247
Kojto	96:487b796308b0	248	/**
Kojto	96:487b796308b0	249	* @}
Kojto	96:487b796308b0	250	*/
Kojto	96:487b796308b0	251
Kojto	96:487b796308b0	252	/**
Kojto	96:487b796308b0	253	* @}
Kojto	96:487b796308b0	254	*/
Kojto	96:487b796308b0	255
Kojto	96:487b796308b0	256	/* Exported constants --------------------------------------------------------*/
Kojto	96:487b796308b0	257	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	96:487b796308b0	258	* @{
Kojto	96:487b796308b0	259	*/
Kojto	96:487b796308b0	260
Kojto	96:487b796308b0	261	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto	96:487b796308b0	262	* @{
Kojto	96:487b796308b0	263	*/
Kojto	96:487b796308b0	264
Kojto	96:487b796308b0	265	#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Kojto	96:487b796308b0	266	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
Kojto	96:487b796308b0	267
Kojto	96:487b796308b0	268	/**
Kojto	96:487b796308b0	269	* @}
Kojto	96:487b796308b0	270	*/
Kojto	96:487b796308b0	271
Kojto	96:487b796308b0	272	/** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto	96:487b796308b0	273	* @{
Kojto	96:487b796308b0	274	*/
Kojto	96:487b796308b0	275	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	276	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	96:487b796308b0	277	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	96:487b796308b0	278	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	96:487b796308b0	279	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	96:487b796308b0	280
Kojto	96:487b796308b0	281	/**
Kojto	96:487b796308b0	282	* @}
Kojto	96:487b796308b0	283	*/
Kojto	96:487b796308b0	284
Kojto	96:487b796308b0	285	/** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
Kojto	96:487b796308b0	286	* @{
Kojto	96:487b796308b0	287	*/
Kojto	96:487b796308b0	288	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
Kojto	96:487b796308b0	289	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
Kojto	96:487b796308b0	290	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
Kojto	96:487b796308b0	291
Kojto	96:487b796308b0	292	/**
Kojto	96:487b796308b0	293	* @}
Kojto	96:487b796308b0	294	*/
Kojto	96:487b796308b0	295
Kojto	96:487b796308b0	296	/** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
Kojto	96:487b796308b0	297	* @{
Kojto	96:487b796308b0	298	*/
Kojto	96:487b796308b0	299	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
Kojto	96:487b796308b0	300	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
Kojto	96:487b796308b0	301	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
Kojto	96:487b796308b0	302
Kojto	96:487b796308b0	303	/**
Kojto	96:487b796308b0	304	* @}
Kojto	96:487b796308b0	305	*/
Kojto	96:487b796308b0	306
Kojto	96:487b796308b0	307	/** @defgroup RCC_HSI_Config HSI Config
Kojto	96:487b796308b0	308	* @{
Kojto	96:487b796308b0	309	*/
Kojto	96:487b796308b0	310	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
Kojto	96:487b796308b0	311	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
Kojto	96:487b796308b0	312
Kojto	96:487b796308b0	313	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	96:487b796308b0	314
Kojto	96:487b796308b0	315	/**
Kojto	96:487b796308b0	316	* @}
Kojto	96:487b796308b0	317	*/
Kojto	96:487b796308b0	318
Kojto	96:487b796308b0	319	/** @defgroup RCC_LSI_Config LSI Config
Kojto	96:487b796308b0	320	* @{
Kojto	96:487b796308b0	321	*/
Kojto	96:487b796308b0	322	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
Kojto	96:487b796308b0	323	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
Kojto	96:487b796308b0	324
Kojto	96:487b796308b0	325	/**
Kojto	96:487b796308b0	326	* @}
Kojto	96:487b796308b0	327	*/
Kojto	96:487b796308b0	328
Kojto	96:487b796308b0	329	/** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
Kojto	96:487b796308b0	330	* @{
Kojto	96:487b796308b0	331	*/
Kojto	96:487b796308b0	332	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
Kojto	96:487b796308b0	333	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
Kojto	96:487b796308b0	334	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
Kojto	96:487b796308b0	335
Kojto	96:487b796308b0	336	/**
Kojto	96:487b796308b0	337	* @}
Kojto	96:487b796308b0	338	*/
Kojto	96:487b796308b0	339
Kojto	96:487b796308b0	340	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	96:487b796308b0	341	* @{
Kojto	96:487b796308b0	342	*/
Kojto	96:487b796308b0	343	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
Kojto	96:487b796308b0	344	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
Kojto	96:487b796308b0	345	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
Kojto	96:487b796308b0	346	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
Kojto	96:487b796308b0	347
Kojto	96:487b796308b0	348	/**
Kojto	96:487b796308b0	349	* @}
Kojto	96:487b796308b0	350	*/
Kojto	96:487b796308b0	351
Kojto	96:487b796308b0	352	/** @defgroup RCC_System_Clock_Source System Clock Source
Kojto	96:487b796308b0	353	* @{
Kojto	96:487b796308b0	354	*/
Kojto	96:487b796308b0	355	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
Kojto	96:487b796308b0	356	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
Kojto	96:487b796308b0	357	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
Kojto	96:487b796308b0	358
Kojto	96:487b796308b0	359	/**
Kojto	96:487b796308b0	360	* @}
Kojto	96:487b796308b0	361	*/
Kojto	96:487b796308b0	362
Kojto	96:487b796308b0	363	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	96:487b796308b0	364	* @{
Kojto	96:487b796308b0	365	*/
Kojto	96:487b796308b0	366	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto	96:487b796308b0	367	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto	96:487b796308b0	368	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto	96:487b796308b0	369
Kojto	96:487b796308b0	370	/**
Kojto	96:487b796308b0	371	* @}
Kojto	96:487b796308b0	372	*/
Kojto	96:487b796308b0	373
Kojto	96:487b796308b0	374	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto	96:487b796308b0	375	* @{
Kojto	96:487b796308b0	376	*/
Kojto	96:487b796308b0	377	#define RCC_SYSCLK_DIV1 (RCC_CFGR_HPRE_DIV1) /!< SYSCLK not divided /
Kojto	96:487b796308b0	378	#define RCC_SYSCLK_DIV2 (RCC_CFGR_HPRE_DIV2) /!< SYSCLK divided by 2 /
Kojto	96:487b796308b0	379	#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_DIV4) /!< SYSCLK divided by 4 /
Kojto	96:487b796308b0	380	#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_DIV8) /!< SYSCLK divided by 8 /
Kojto	96:487b796308b0	381	#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_DIV16) /!< SYSCLK divided by 16 /
Kojto	96:487b796308b0	382	#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_DIV64) /!< SYSCLK divided by 64 /
Kojto	96:487b796308b0	383	#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_DIV128) /!< SYSCLK divided by 128 /
Kojto	96:487b796308b0	384	#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_DIV256) /!< SYSCLK divided by 256 /
Kojto	96:487b796308b0	385	#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_DIV512) /!< SYSCLK divided by 512 /
Kojto	96:487b796308b0	386
Kojto	96:487b796308b0	387	/**
Kojto	96:487b796308b0	388	* @}
Kojto	96:487b796308b0	389	*/
Kojto	96:487b796308b0	390
Kojto	96:487b796308b0	391	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
Kojto	96:487b796308b0	392	* @{
Kojto	96:487b796308b0	393	*/
Kojto	96:487b796308b0	394	#define RCC_HCLK_DIV1 (RCC_CFGR_PPRE1_DIV1) /!< HCLK not divided /
Kojto	96:487b796308b0	395	#define RCC_HCLK_DIV2 (RCC_CFGR_PPRE1_DIV2) /!< HCLK divided by 2 /
Kojto	96:487b796308b0	396	#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_DIV4) /!< HCLK divided by 4 /
Kojto	96:487b796308b0	397	#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_DIV8) /!< HCLK divided by 8 /
Kojto	96:487b796308b0	398	#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE1_DIV16) /!< HCLK divided by 16 /
Kojto	96:487b796308b0	399
Kojto	96:487b796308b0	400	/**
Kojto	96:487b796308b0	401	* @}
Kojto	96:487b796308b0	402	*/
Kojto	96:487b796308b0	403
Kojto	96:487b796308b0	404	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto	96:487b796308b0	405	* @{
Kojto	96:487b796308b0	406	*/
Kojto	96:487b796308b0	407	#define RCC_RTCCLKSOURCE_LSE (RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
Kojto	96:487b796308b0	408	#define RCC_RTCCLKSOURCE_LSI (RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
Kojto	96:487b796308b0	409	#define RCC_RTCCLKSOURCE_HSE_DIV128 (RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 128 used as RTC clock /
Kojto	96:487b796308b0	410	/**
Kojto	96:487b796308b0	411	* @}
Kojto	96:487b796308b0	412	*/
Kojto	96:487b796308b0	413
Kojto	96:487b796308b0	414	/** @defgroup RCC_MCO_Index MCO Index
Kojto	96:487b796308b0	415	* @{
Kojto	96:487b796308b0	416	*/
Kojto	96:487b796308b0	417	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	418	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
Kojto	96:487b796308b0	419
Kojto	96:487b796308b0	420	/**
Kojto	96:487b796308b0	421	* @}
Kojto	96:487b796308b0	422	*/
Kojto	96:487b796308b0	423
Kojto	96:487b796308b0	424	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
Kojto	96:487b796308b0	425	* @{
Kojto	96:487b796308b0	426	*/
Kojto	96:487b796308b0	427	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	428
Kojto	96:487b796308b0	429	/**
Kojto	96:487b796308b0	430	* @}
Kojto	96:487b796308b0	431	*/
Kojto	96:487b796308b0	432
Kojto	96:487b796308b0	433	/** @defgroup RCC_Interrupt Interrupts
Kojto	96:487b796308b0	434	* @{
Kojto	96:487b796308b0	435	*/
Kojto	96:487b796308b0	436	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
Kojto	96:487b796308b0	437	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
Kojto	96:487b796308b0	438	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
Kojto	96:487b796308b0	439	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
Kojto	96:487b796308b0	440	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
Kojto	96:487b796308b0	441	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
Kojto	96:487b796308b0	442	/**
Kojto	96:487b796308b0	443	* @}
Kojto	96:487b796308b0	444	*/
Kojto	96:487b796308b0	445
Kojto	96:487b796308b0	446	/** @defgroup RCC_Flag Flags
Kojto	96:487b796308b0	447	* Elements values convention: 0XXYYYYYb
Kojto	96:487b796308b0	448	* - YYYYY : Flag position in the register
Kojto	96:487b796308b0	449	* - XX : Register index
Kojto	96:487b796308b0	450	* - 01: CR register
Kojto	96:487b796308b0	451	* - 10: BDCR register
Kojto	96:487b796308b0	452	* - 11: CSR register
Kojto	96:487b796308b0	453	* @{
Kojto	96:487b796308b0	454	*/
Kojto	96:487b796308b0	455	/* Flags in the CR register */
Kojto	96:487b796308b0	456	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
Kojto	96:487b796308b0	457	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
Kojto	96:487b796308b0	458	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
Kojto	96:487b796308b0	459
Kojto	96:487b796308b0	460	/* Flags in the BDCR register */
Kojto	96:487b796308b0	461	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
Kojto	96:487b796308b0	462
Kojto	96:487b796308b0	463	/* Flags in the CSR register */
Kojto	96:487b796308b0	464	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
Kojto	96:487b796308b0	465	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
Kojto	96:487b796308b0	466	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
Kojto	96:487b796308b0	467	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
Kojto	96:487b796308b0	468	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
Kojto	96:487b796308b0	469	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
Kojto	96:487b796308b0	470	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
Kojto	96:487b796308b0	471	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
Kojto	96:487b796308b0	472
Kojto	96:487b796308b0	473	/**
Kojto	96:487b796308b0	474	* @}
Kojto	96:487b796308b0	475	*/
Kojto	96:487b796308b0	476
Kojto	96:487b796308b0	477	/**
Kojto	96:487b796308b0	478	* @}
Kojto	96:487b796308b0	479	*/
Kojto	96:487b796308b0	480
Kojto	96:487b796308b0	481	/* Exported macro ------------------------------------------------------------*/
Kojto	96:487b796308b0	482
Kojto	96:487b796308b0	483	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	96:487b796308b0	484	* @{
Kojto	96:487b796308b0	485	*/
Kojto	96:487b796308b0	486
Kojto	96:487b796308b0	487	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
Kojto	96:487b796308b0	488	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	96:487b796308b0	489	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	490	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	491	* using it.
Kojto	96:487b796308b0	492	* @{
Kojto	96:487b796308b0	493	*/
Kojto	96:487b796308b0	494	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	495	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	496	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	96:487b796308b0	497	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	498	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	96:487b796308b0	499	UNUSED(tmpreg); \
Kojto	96:487b796308b0	500	} while(0)
Kojto	96:487b796308b0	501
Kojto	96:487b796308b0	502	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
Kojto	96:487b796308b0	503	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	504	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	96:487b796308b0	505	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	506	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto	96:487b796308b0	507	UNUSED(tmpreg); \
Kojto	96:487b796308b0	508	} while(0)
Kojto	96:487b796308b0	509
Kojto	96:487b796308b0	510	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
Kojto	96:487b796308b0	511	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	512	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	96:487b796308b0	513	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	514	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto	96:487b796308b0	515	UNUSED(tmpreg); \
Kojto	96:487b796308b0	516	} while(0)
Kojto	96:487b796308b0	517
Kojto	96:487b796308b0	518	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	96:487b796308b0	519	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	520	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	96:487b796308b0	521	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	522	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	96:487b796308b0	523	UNUSED(tmpreg); \
Kojto	96:487b796308b0	524	} while(0)
Kojto	96:487b796308b0	525
Kojto	96:487b796308b0	526	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	96:487b796308b0	527	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto	96:487b796308b0	528	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	96:487b796308b0	529	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	96:487b796308b0	530
Kojto	96:487b796308b0	531	/**
Kojto	96:487b796308b0	532	* @}
Kojto	96:487b796308b0	533	*/
Kojto	96:487b796308b0	534
Kojto	96:487b796308b0	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
Kojto	96:487b796308b0	536	* @brief Get the enable or disable status of the AHB peripheral clock.
Kojto	96:487b796308b0	537	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	538	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	539	* using it.
Kojto	96:487b796308b0	540	* @{
Kojto	96:487b796308b0	541	*/
Kojto	96:487b796308b0	542
Kojto	96:487b796308b0	543	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
Kojto	96:487b796308b0	544	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Kojto	96:487b796308b0	545	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
Kojto	96:487b796308b0	546	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
Kojto	96:487b796308b0	547	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
Kojto	96:487b796308b0	548	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
Kojto	96:487b796308b0	549	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
Kojto	96:487b796308b0	550	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Kojto	96:487b796308b0	551
Kojto	96:487b796308b0	552	/**
Kojto	96:487b796308b0	553	* @}
Kojto	96:487b796308b0	554	*/
Kojto	96:487b796308b0	555
Kojto	96:487b796308b0	556	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
Kojto	96:487b796308b0	557	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	96:487b796308b0	558	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	559	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	560	* using it.
Kojto	96:487b796308b0	561	* @{
Kojto	96:487b796308b0	562	*/
Kojto	96:487b796308b0	563	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	96:487b796308b0	564	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	565	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	96:487b796308b0	566	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	567	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	96:487b796308b0	568	UNUSED(tmpreg); \
Kojto	96:487b796308b0	569	} while(0)
Kojto	96:487b796308b0	570
Kojto	96:487b796308b0	571	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	96:487b796308b0	572	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	573	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	96:487b796308b0	574	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	575	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	96:487b796308b0	576	UNUSED(tmpreg); \
Kojto	96:487b796308b0	577	} while(0)
Kojto	96:487b796308b0	578
Kojto	96:487b796308b0	579	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	96:487b796308b0	580	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	581	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	96:487b796308b0	582	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	583	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	96:487b796308b0	584	UNUSED(tmpreg); \
Kojto	96:487b796308b0	585	} while(0)
Kojto	96:487b796308b0	586
Kojto	96:487b796308b0	587	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	96:487b796308b0	588	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	589	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	96:487b796308b0	590	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	591	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	96:487b796308b0	592	UNUSED(tmpreg); \
Kojto	96:487b796308b0	593	} while(0)
Kojto	96:487b796308b0	594
Kojto	96:487b796308b0	595	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	596	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	597	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	96:487b796308b0	598	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	599	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	96:487b796308b0	600	UNUSED(tmpreg); \
Kojto	96:487b796308b0	601	} while(0)
Kojto	96:487b796308b0	602
Kojto	96:487b796308b0	603	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
Kojto	96:487b796308b0	604	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
Kojto	96:487b796308b0	606	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
Kojto	96:487b796308b0	608	UNUSED(tmpreg); \
Kojto	96:487b796308b0	609	} while(0)
Kojto	96:487b796308b0	610
Kojto	96:487b796308b0	611	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	96:487b796308b0	612	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	613	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	96:487b796308b0	614	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	615	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	96:487b796308b0	616	UNUSED(tmpreg); \
Kojto	96:487b796308b0	617	} while(0)
Kojto	96:487b796308b0	618
Kojto	96:487b796308b0	619	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	620	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	96:487b796308b0	621	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	96:487b796308b0	622	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	623	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	624
Kojto	96:487b796308b0	625	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
Kojto	96:487b796308b0	626	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	96:487b796308b0	627
Kojto	96:487b796308b0	628	/**
Kojto	96:487b796308b0	629	* @}
Kojto	96:487b796308b0	630	*/
Kojto	96:487b796308b0	631
Kojto	96:487b796308b0	632	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	96:487b796308b0	633	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	96:487b796308b0	634	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	635	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	636	* using it.
Kojto	96:487b796308b0	637	* @{
Kojto	96:487b796308b0	638	*/
Kojto	96:487b796308b0	639
Kojto	96:487b796308b0	640	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	96:487b796308b0	641	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	96:487b796308b0	642	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	96:487b796308b0	643	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	96:487b796308b0	644	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto	96:487b796308b0	645	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto	96:487b796308b0	646	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	96:487b796308b0	647	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	96:487b796308b0	648	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto	96:487b796308b0	649	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto	96:487b796308b0	650	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
Kojto	96:487b796308b0	651	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
Kojto	96:487b796308b0	652	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto	96:487b796308b0	653	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto	96:487b796308b0	654
Kojto	96:487b796308b0	655	/**
Kojto	96:487b796308b0	656	* @}
Kojto	96:487b796308b0	657	*/
Kojto	96:487b796308b0	658
Kojto	96:487b796308b0	659	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
Kojto	96:487b796308b0	660	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	96:487b796308b0	661	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	662	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	663	* using it.
Kojto	96:487b796308b0	664	* @{
Kojto	96:487b796308b0	665	*/
Kojto	96:487b796308b0	666	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
Kojto	96:487b796308b0	667	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	668	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
Kojto	96:487b796308b0	669	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	670	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
Kojto	96:487b796308b0	671	UNUSED(tmpreg); \
Kojto	96:487b796308b0	672	} while(0)
Kojto	96:487b796308b0	673
Kojto	96:487b796308b0	674	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	96:487b796308b0	675	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	676	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
Kojto	96:487b796308b0	677	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	678	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
Kojto	96:487b796308b0	679	UNUSED(tmpreg); \
Kojto	96:487b796308b0	680	} while(0)
Kojto	96:487b796308b0	681
Kojto	96:487b796308b0	682	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	96:487b796308b0	683	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
Kojto	96:487b796308b0	685	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
Kojto	96:487b796308b0	687	UNUSED(tmpreg); \
Kojto	96:487b796308b0	688	} while(0)
Kojto	96:487b796308b0	689
Kojto	96:487b796308b0	690	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	96:487b796308b0	691	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	692	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
Kojto	96:487b796308b0	693	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	694	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
Kojto	96:487b796308b0	695	UNUSED(tmpreg); \
Kojto	96:487b796308b0	696	} while(0)
Kojto	96:487b796308b0	697
Kojto	96:487b796308b0	698	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	96:487b796308b0	699	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	700	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
Kojto	96:487b796308b0	701	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	702	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
Kojto	96:487b796308b0	703	UNUSED(tmpreg); \
Kojto	96:487b796308b0	704	} while(0)
Kojto	96:487b796308b0	705
Kojto	96:487b796308b0	706	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	707	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	708	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	96:487b796308b0	709	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	710	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	96:487b796308b0	711	UNUSED(tmpreg); \
Kojto	96:487b796308b0	712	} while(0)
Kojto	96:487b796308b0	713
Kojto	96:487b796308b0	714	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	715	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	96:487b796308b0	717	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	96:487b796308b0	719	UNUSED(tmpreg); \
Kojto	96:487b796308b0	720	} while(0)
Kojto	96:487b796308b0	721
Kojto	96:487b796308b0	722	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	723	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	96:487b796308b0	725	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	96:487b796308b0	727	UNUSED(tmpreg); \
Kojto	96:487b796308b0	728	} while(0)
Kojto	96:487b796308b0	729
Kojto	96:487b796308b0	730	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	96:487b796308b0	731	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	732	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	96:487b796308b0	733	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	734	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	96:487b796308b0	735	UNUSED(tmpreg); \
Kojto	96:487b796308b0	736	} while(0)
Kojto	96:487b796308b0	737
Kojto	96:487b796308b0	738	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
Kojto	96:487b796308b0	739	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
Kojto	96:487b796308b0	740	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
Kojto	96:487b796308b0	741	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
Kojto	96:487b796308b0	742	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
Kojto	96:487b796308b0	743	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	96:487b796308b0	744
Kojto	96:487b796308b0	745	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	96:487b796308b0	746	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	96:487b796308b0	747	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	96:487b796308b0	748
Kojto	96:487b796308b0	749	/**
Kojto	96:487b796308b0	750	* @}
Kojto	96:487b796308b0	751	*/
Kojto	96:487b796308b0	752
Kojto	96:487b796308b0	753	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	96:487b796308b0	754	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	96:487b796308b0	755	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	756	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	757	* using it.
Kojto	96:487b796308b0	758	* @{
Kojto	96:487b796308b0	759	*/
Kojto	96:487b796308b0	760
Kojto	96:487b796308b0	761	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
Kojto	96:487b796308b0	762	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
Kojto	96:487b796308b0	763	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
Kojto	96:487b796308b0	764	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
Kojto	96:487b796308b0	765	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
Kojto	96:487b796308b0	766	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
Kojto	96:487b796308b0	767	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
Kojto	96:487b796308b0	768	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
Kojto	96:487b796308b0	769	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
Kojto	96:487b796308b0	770	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
Kojto	96:487b796308b0	771	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto	96:487b796308b0	772	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto	96:487b796308b0	773	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto	96:487b796308b0	774	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto	96:487b796308b0	775	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto	96:487b796308b0	776	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto	96:487b796308b0	777	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto	96:487b796308b0	778	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto	96:487b796308b0	779
Kojto	96:487b796308b0	780	/**
Kojto	96:487b796308b0	781	* @}
Kojto	96:487b796308b0	782	*/
Kojto	96:487b796308b0	783
Kojto	96:487b796308b0	784	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	96:487b796308b0	785	* @brief Force or release APB1 peripheral reset.
Kojto	96:487b796308b0	786	* @{
Kojto	96:487b796308b0	787	*/
Kojto	96:487b796308b0	788	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	96:487b796308b0	789	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	790	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	96:487b796308b0	791	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	96:487b796308b0	792	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	793	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	794
Kojto	96:487b796308b0	795	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
Kojto	96:487b796308b0	796	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	96:487b796308b0	797
Kojto	96:487b796308b0	798	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	96:487b796308b0	799	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	800	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	96:487b796308b0	801	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	96:487b796308b0	802	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	803	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	804
Kojto	96:487b796308b0	805	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
Kojto	96:487b796308b0	806	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	96:487b796308b0	807
Kojto	96:487b796308b0	808	/**
Kojto	96:487b796308b0	809	* @}
Kojto	96:487b796308b0	810	*/
Kojto	96:487b796308b0	811
Kojto	96:487b796308b0	812	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	96:487b796308b0	813	* @brief Force or release APB2 peripheral reset.
Kojto	96:487b796308b0	814	* @{
Kojto	96:487b796308b0	815	*/
Kojto	96:487b796308b0	816	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	96:487b796308b0	817	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
Kojto	96:487b796308b0	818	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
Kojto	96:487b796308b0	819	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
Kojto	96:487b796308b0	820	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
Kojto	96:487b796308b0	821	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
Kojto	96:487b796308b0	822	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	96:487b796308b0	823
Kojto	96:487b796308b0	824	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	96:487b796308b0	825	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	96:487b796308b0	826	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	96:487b796308b0	827
Kojto	96:487b796308b0	828	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	96:487b796308b0	829	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
Kojto	96:487b796308b0	830	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
Kojto	96:487b796308b0	831	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
Kojto	96:487b796308b0	832	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
Kojto	96:487b796308b0	833	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
Kojto	96:487b796308b0	834	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	96:487b796308b0	835
Kojto	96:487b796308b0	836	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	96:487b796308b0	837	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	96:487b796308b0	838	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	96:487b796308b0	839
Kojto	96:487b796308b0	840	/**
Kojto	96:487b796308b0	841	* @}
Kojto	96:487b796308b0	842	*/
Kojto	96:487b796308b0	843
Kojto	96:487b796308b0	844	/** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto	96:487b796308b0	845	* @{
Kojto	96:487b796308b0	846	*/
Kojto	96:487b796308b0	847
Kojto	96:487b796308b0	848	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	96:487b796308b0	849	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	96:487b796308b0	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	96:487b796308b0	851	* you have to select another source of the system clock then stop the HSI.
Kojto	96:487b796308b0	852	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	96:487b796308b0	853	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	96:487b796308b0	854	* system clock source.
Kojto	96:487b796308b0	855	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	96:487b796308b0	856	* clock cycles.
Kojto	96:487b796308b0	857	*/
Kojto	96:487b796308b0	858	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
Kojto	96:487b796308b0	859	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
Kojto	96:487b796308b0	860
Kojto	96:487b796308b0	861	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	96:487b796308b0	862	* @note The calibration is used to compensate for the variations in voltage
Kojto	96:487b796308b0	863	* and temperature that influence the frequency of the internal HSI RC.
Kojto	96:487b796308b0	864	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	96:487b796308b0	865	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	96:487b796308b0	866	* This parameter must be a number between 0 and 0x1F.
Kojto	96:487b796308b0	867	*/
Kojto	96:487b796308b0	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto	96:487b796308b0	869	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto	96:487b796308b0	870
Kojto	96:487b796308b0	871	/**
Kojto	96:487b796308b0	872	* @}
Kojto	96:487b796308b0	873	*/
Kojto	96:487b796308b0	874
Kojto	96:487b796308b0	875	/** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto	96:487b796308b0	876	* @{
Kojto	96:487b796308b0	877	*/
Kojto	96:487b796308b0	878
Kojto	96:487b796308b0	879	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	96:487b796308b0	880	* @note After enabling the LSI, the application software should wait on
Kojto	96:487b796308b0	881	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	96:487b796308b0	882	* be used to clock the IWDG and/or the RTC.
Kojto	96:487b796308b0	883	* @note LSI can not be disabled if the IWDG is running.
Kojto	96:487b796308b0	884	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	96:487b796308b0	885	* clock cycles.
Kojto	96:487b796308b0	886	*/
Kojto	96:487b796308b0	887	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
Kojto	96:487b796308b0	888	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
Kojto	96:487b796308b0	889
Kojto	96:487b796308b0	890	/**
Kojto	96:487b796308b0	891	* @}
Kojto	96:487b796308b0	892	*/
Kojto	96:487b796308b0	893
Kojto	96:487b796308b0	894	/** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto	96:487b796308b0	895	* @{
Kojto	96:487b796308b0	896	*/
Kojto	96:487b796308b0	897
Kojto	96:487b796308b0	898	/**
Kojto	96:487b796308b0	899	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	96:487b796308b0	900	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	96:487b796308b0	901	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	96:487b796308b0	902	* is stable and can be used to clock the PLL and/or system clock.
Kojto	96:487b796308b0	903	* @note HSE state can not be changed if it is used directly or through the
Kojto	96:487b796308b0	904	* PLL as system clock. In this case, you have to select another source
Kojto	96:487b796308b0	905	* of the system clock then change the HSE state (ex. disable it).
Kojto	96:487b796308b0	906	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	96:487b796308b0	907	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto	96:487b796308b0	908	* was previously enabled you have to enable it again after calling this
Kojto	96:487b796308b0	909	* function.
Kojto	96:487b796308b0	910	* @param __STATE__: specifies the new state of the HSE.
Kojto	96:487b796308b0	911	* This parameter can be one of the following values:
Kojto	96:487b796308b0	912	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	96:487b796308b0	913	* 6 HSE oscillator clock cycles.
Kojto	96:487b796308b0	914	* @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto	96:487b796308b0	915	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto	96:487b796308b0	916	*/
Kojto	96:487b796308b0	917	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	96:487b796308b0	918	do { \
Kojto	96:487b796308b0	919	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	96:487b796308b0	920	if((__STATE__) == RCC_HSE_ON) \
Kojto	96:487b796308b0	921	{ \
Kojto	96:487b796308b0	922	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	96:487b796308b0	923	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	96:487b796308b0	924	} \
Kojto	96:487b796308b0	925	else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto	96:487b796308b0	926	{ \
Kojto	96:487b796308b0	927	((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
Kojto	96:487b796308b0	928	} \
Kojto	96:487b796308b0	929	else \
Kojto	96:487b796308b0	930	{ \
Kojto	96:487b796308b0	931	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	96:487b796308b0	932	} \
Kojto	96:487b796308b0	933	} while(0)
Kojto	96:487b796308b0	934
Kojto	96:487b796308b0	935	/**
Kojto	96:487b796308b0	936	* @}
Kojto	96:487b796308b0	937	*/
Kojto	96:487b796308b0	938
Kojto	96:487b796308b0	939	/** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto	96:487b796308b0	940	* @{
Kojto	96:487b796308b0	941	*/
Kojto	96:487b796308b0	942
Kojto	96:487b796308b0	943	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
Kojto	96:487b796308b0	944	*/
Kojto	96:487b796308b0	945	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
Kojto	96:487b796308b0	946	do{ \
Kojto	96:487b796308b0	947	if ((__LSE_STATE__) == RCC_LSE_OFF) \
Kojto	96:487b796308b0	948	{ \
Kojto	96:487b796308b0	949	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
Kojto	96:487b796308b0	950	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
Kojto	96:487b796308b0	951	} \
Kojto	96:487b796308b0	952	else if ((__LSE_STATE__) == RCC_LSE_ON) \
Kojto	96:487b796308b0	953	{ \
Kojto	96:487b796308b0	954	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
Kojto	96:487b796308b0	955	(__IO uint32_t ) BDCR_LSEON_BB = ENABLE; \
Kojto	96:487b796308b0	956	} \
Kojto	96:487b796308b0	957	else \
Kojto	96:487b796308b0	958	{ \
Kojto	96:487b796308b0	959	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
Kojto	96:487b796308b0	960	(__IO uint32_t ) BDCR_LSEBYP_BB = ENABLE; \
Kojto	96:487b796308b0	961	} \
Kojto	96:487b796308b0	962	}while(0)
Kojto	96:487b796308b0	963
Kojto	96:487b796308b0	964
Kojto	96:487b796308b0	965	/**
Kojto	96:487b796308b0	966	* @}
Kojto	96:487b796308b0	967	*/
Kojto	96:487b796308b0	968
Kojto	96:487b796308b0	969	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	96:487b796308b0	970	* @{
Kojto	96:487b796308b0	971	*/
Kojto	96:487b796308b0	972
Kojto	96:487b796308b0	973	/** @brief Macros to enable the main PLL.
Kojto	96:487b796308b0	974	* @note After enabling the main PLL, the application software should wait on
Kojto	96:487b796308b0	975	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	96:487b796308b0	976	* be used as system clock source.
Kojto	96:487b796308b0	977	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	96:487b796308b0	978	*/
Kojto	96:487b796308b0	979	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
Kojto	96:487b796308b0	980
Kojto	96:487b796308b0	981	/** @brief Macros to disable the main PLL.
Kojto	96:487b796308b0	982	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	96:487b796308b0	983	*/
Kojto	96:487b796308b0	984	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
Kojto	96:487b796308b0	985
Kojto	96:487b796308b0	986	/** @brief macros to configure the main PLL clock source and multiplication factors.
Kojto	96:487b796308b0	987	* @note This function must be used only when the main PLL is disabled.
Kojto	96:487b796308b0	988	*
Kojto	96:487b796308b0	989	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
Kojto	96:487b796308b0	990	* This parameter can be one of the following values:
Kojto	96:487b796308b0	991	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
Kojto	96:487b796308b0	992	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	96:487b796308b0	993	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
Kojto	96:487b796308b0	994	* This parameter can be one of the following values:
Kojto	96:487b796308b0	995	* @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
Kojto	96:487b796308b0	996	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
Kojto	96:487b796308b0	997	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
Kojto	96:487b796308b0	998	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
Kojto	96:487b796308b0	999	* @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
Kojto	96:487b796308b0	1000	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
Kojto	96:487b796308b0	1001	* @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
Kojto	96:487b796308b0	1002	* @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
Kojto	96:487b796308b0	1003	* @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
Kojto	96:487b796308b0	1004	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
Kojto	96:487b796308b0	1005	* @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
Kojto	96:487b796308b0	1006	* @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
Kojto	96:487b796308b0	1007	* @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
Kojto	96:487b796308b0	1008	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
Kojto	96:487b796308b0	1009	* @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
Kojto	96:487b796308b0	1010	* @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1011	*
Kojto	96:487b796308b0	1012	*/
Kojto	96:487b796308b0	1013	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
Kojto	96:487b796308b0	1014	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
Kojto	96:487b796308b0	1015	/**
Kojto	96:487b796308b0	1016	* @}
Kojto	96:487b796308b0	1017	*/
Kojto	96:487b796308b0	1018
Kojto	96:487b796308b0	1019	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	96:487b796308b0	1020	* @{
Kojto	96:487b796308b0	1021	*/
Kojto	96:487b796308b0	1022
Kojto	96:487b796308b0	1023	/** @brief Macro to get the clock source used as system clock.
Kojto	96:487b796308b0	1024	* @retval The clock source used as system clock. The returned value can be one
Kojto	96:487b796308b0	1025	* of the following:
Kojto	96:487b796308b0	1026	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto	96:487b796308b0	1027	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto	96:487b796308b0	1028	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto	96:487b796308b0	1029	*/
Kojto	96:487b796308b0	1030	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto	96:487b796308b0	1031
Kojto	96:487b796308b0	1032	/** @brief Get oscillator clock selected as PLL input clock
Kojto	96:487b796308b0	1033	* @retval The clock source used for PLL entry. The returned value can be one
Kojto	96:487b796308b0	1034	* of the following:
Kojto	96:487b796308b0	1035	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
Kojto	96:487b796308b0	1036	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
Kojto	96:487b796308b0	1037	*/
Kojto	96:487b796308b0	1038	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	96:487b796308b0	1039
Kojto	96:487b796308b0	1040	/**
Kojto	96:487b796308b0	1041	* @}
Kojto	96:487b796308b0	1042	*/
Kojto	96:487b796308b0	1043	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto	96:487b796308b0	1044	* @{
Kojto	96:487b796308b0	1045	*/
Kojto	96:487b796308b0	1046
Kojto	96:487b796308b0	1047	/** @brief Macro to configures the RTC clock (RTCCLK).
Kojto	96:487b796308b0	1048	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	96:487b796308b0	1049	* access is denied to this domain after reset, you have to enable write
Kojto	96:487b796308b0	1050	* access using the Power Backup Access macro before to configure
Kojto	96:487b796308b0	1051	* the RTC clock source (to be done once after reset).
Kojto	96:487b796308b0	1052	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	96:487b796308b0	1053	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto	96:487b796308b0	1054	* a Power On Reset (POR).
Kojto	96:487b796308b0	1055	*
Kojto	96:487b796308b0	1056	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto	96:487b796308b0	1057	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1058	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	96:487b796308b0	1059	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	96:487b796308b0	1060	* @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
Kojto	96:487b796308b0	1061	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	96:487b796308b0	1062	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	96:487b796308b0	1063	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	96:487b796308b0	1064	* cannot be used in STOP and STANDBY modes.
Kojto	96:487b796308b0	1065	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	96:487b796308b0	1066	* RTC clock source).
Kojto	96:487b796308b0	1067	*/
Kojto	96:487b796308b0	1068	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto	96:487b796308b0	1069
Kojto	96:487b796308b0	1070
Kojto	96:487b796308b0	1071	/** @brief macros to get the RTC clock source.
Kojto	96:487b796308b0	1072	*/
Kojto	96:487b796308b0	1073	#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
Kojto	96:487b796308b0	1074
Kojto	96:487b796308b0	1075	/** @brief Macros to enable the the RTC clock.
Kojto	96:487b796308b0	1076	* @note These macros must be used only after the RTC clock source was selected.
Kojto	96:487b796308b0	1077	*/
Kojto	96:487b796308b0	1078	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto	96:487b796308b0	1079
Kojto	96:487b796308b0	1080	/** @brief Macros to disable the the RTC clock.
Kojto	96:487b796308b0	1081	* @note These macros must be used only after the RTC clock source was selected.
Kojto	96:487b796308b0	1082	*/
Kojto	96:487b796308b0	1083	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto	96:487b796308b0	1084
Kojto	96:487b796308b0	1085	/** @brief Macros to force the Backup domain reset.
Kojto	96:487b796308b0	1086	* @note This function resets the entire Backup domain.
Kojto	96:487b796308b0	1087	*/
Kojto	96:487b796308b0	1088	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
Kojto	96:487b796308b0	1089
Kojto	96:487b796308b0	1090	/** @brief Macros to release the Backup domain reset.
Kojto	96:487b796308b0	1091	*/
Kojto	96:487b796308b0	1092	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
Kojto	96:487b796308b0	1093
Kojto	96:487b796308b0	1094
Kojto	96:487b796308b0	1095	/**
Kojto	96:487b796308b0	1096	* @}
Kojto	96:487b796308b0	1097	*/
Kojto	96:487b796308b0	1098
Kojto	96:487b796308b0	1099	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto	96:487b796308b0	1100	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	96:487b796308b0	1101	* @{
Kojto	96:487b796308b0	1102	*/
Kojto	96:487b796308b0	1103
Kojto	96:487b796308b0	1104	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	96:487b796308b0	1105	* the selected interrupts.).
Kojto	96:487b796308b0	1106	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	96:487b796308b0	1107	* This parameter can be any combination of the following values:
Kojto	96:487b796308b0	1108	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	96:487b796308b0	1109	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	96:487b796308b0	1110	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	96:487b796308b0	1111	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	96:487b796308b0	1112	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	96:487b796308b0	1113	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
Kojto	96:487b796308b0	1114	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
Kojto	96:487b796308b0	1115	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1116	*/
Kojto	96:487b796308b0	1117	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	96:487b796308b0	1118
Kojto	96:487b796308b0	1119	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	96:487b796308b0	1120	* the selected interrupts).
Kojto	96:487b796308b0	1121	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	96:487b796308b0	1122	* This parameter can be any combination of the following values:
Kojto	96:487b796308b0	1123	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	96:487b796308b0	1124	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	96:487b796308b0	1125	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	96:487b796308b0	1126	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	96:487b796308b0	1127	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	96:487b796308b0	1128	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
Kojto	96:487b796308b0	1129	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
Kojto	96:487b796308b0	1130	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1131	*/
Kojto	96:487b796308b0	1132	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	96:487b796308b0	1133
Kojto	96:487b796308b0	1134	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto	96:487b796308b0	1135	* bits to clear the selected interrupt pending bits.
Kojto	96:487b796308b0	1136	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	96:487b796308b0	1137	* This parameter can be any combination of the following values:
Kojto	96:487b796308b0	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	96:487b796308b0	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	96:487b796308b0	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	96:487b796308b0	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	96:487b796308b0	1142	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	96:487b796308b0	1143	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
Kojto	96:487b796308b0	1144	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
Kojto	96:487b796308b0	1145	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1146	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	96:487b796308b0	1147	*/
Kojto	96:487b796308b0	1148	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	96:487b796308b0	1149
Kojto	96:487b796308b0	1150	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	96:487b796308b0	1151	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	96:487b796308b0	1152	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1153	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	96:487b796308b0	1154	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	96:487b796308b0	1155	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	96:487b796308b0	1156	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	96:487b796308b0	1157	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	96:487b796308b0	1158	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
Kojto	96:487b796308b0	1159	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
Kojto	96:487b796308b0	1160	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	96:487b796308b0	1161	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1162	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	96:487b796308b0	1163	*/
Kojto	96:487b796308b0	1164	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	96:487b796308b0	1165
Kojto	96:487b796308b0	1166	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	96:487b796308b0	1167	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto	96:487b796308b0	1168	*/
Kojto	96:487b796308b0	1169	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	96:487b796308b0	1170
Kojto	96:487b796308b0	1171	/** @brief Check RCC flag is set or not.
Kojto	96:487b796308b0	1172	* @param __FLAG__: specifies the flag to check.
Kojto	96:487b796308b0	1173	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1174	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	96:487b796308b0	1175	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	96:487b796308b0	1176	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	96:487b796308b0	1177	* @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
Kojto	96:487b796308b0	1178	* @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
Kojto	96:487b796308b0	1179	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	96:487b796308b0	1180	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	96:487b796308b0	1181	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	96:487b796308b0	1182	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	96:487b796308b0	1183	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	96:487b796308b0	1184	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	96:487b796308b0	1185	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	96:487b796308b0	1186	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	96:487b796308b0	1187	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
Kojto	96:487b796308b0	1188	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	96:487b796308b0	1189	*/
Kojto	96:487b796308b0	1190	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto	96:487b796308b0	1191	/**
Kojto	96:487b796308b0	1192	* @}
Kojto	96:487b796308b0	1193	*/
Kojto	96:487b796308b0	1194
Kojto	96:487b796308b0	1195	/**
Kojto	96:487b796308b0	1196	* @}
Kojto	96:487b796308b0	1197	*/
Kojto	96:487b796308b0	1198
Kojto	96:487b796308b0	1199	/* Include RCC HAL Extension module */
Kojto	96:487b796308b0	1200	#include "stm32f1xx_hal_rcc_ex.h"
Kojto	96:487b796308b0	1201
Kojto	96:487b796308b0	1202	/* Exported functions --------------------------------------------------------*/
Kojto	96:487b796308b0	1203	/** @addtogroup RCC_Exported_Functions
Kojto	96:487b796308b0	1204	* @{
Kojto	96:487b796308b0	1205	*/
Kojto	96:487b796308b0	1206
Kojto	96:487b796308b0	1207	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	96:487b796308b0	1208	* @{
Kojto	96:487b796308b0	1209	*/
Kojto	96:487b796308b0	1210
Kojto	96:487b796308b0	1211	/* Initialization and de-initialization functions ******************************/
Kojto	96:487b796308b0	1212	void HAL_RCC_DeInit(void);
Kojto	96:487b796308b0	1213	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	96:487b796308b0	1214	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	96:487b796308b0	1215
Kojto	96:487b796308b0	1216	/**
Kojto	96:487b796308b0	1217	* @}
Kojto	96:487b796308b0	1218	*/
Kojto	96:487b796308b0	1219
Kojto	96:487b796308b0	1220	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	96:487b796308b0	1221	* @{
Kojto	96:487b796308b0	1222	*/
Kojto	96:487b796308b0	1223
Kojto	96:487b796308b0	1224	/* Peripheral Control functions ************************************************/
Kojto	96:487b796308b0	1225	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	96:487b796308b0	1226	void HAL_RCC_EnableCSS(void);
Kojto	96:487b796308b0	1227	void HAL_RCC_DisableCSS(void);
Kojto	96:487b796308b0	1228	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	96:487b796308b0	1229	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	96:487b796308b0	1230	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	96:487b796308b0	1231	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	96:487b796308b0	1232	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	96:487b796308b0	1233	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	96:487b796308b0	1234
Kojto	96:487b796308b0	1235	/* CSS NMI IRQ handler */
Kojto	96:487b796308b0	1236	void HAL_RCC_NMI_IRQHandler(void);
Kojto	96:487b796308b0	1237
Kojto	96:487b796308b0	1238	/* User Callbacks in non blocking mode (IT mode) */
Kojto	96:487b796308b0	1239	void HAL_RCC_CSSCallback(void);
Kojto	96:487b796308b0	1240
Kojto	96:487b796308b0	1241	/**
Kojto	96:487b796308b0	1242	* @}
Kojto	96:487b796308b0	1243	*/
Kojto	96:487b796308b0	1244
Kojto	96:487b796308b0	1245	/**
Kojto	96:487b796308b0	1246	* @}
Kojto	96:487b796308b0	1247	*/
Kojto	96:487b796308b0	1248
Kojto	96:487b796308b0	1249	/**
Kojto	96:487b796308b0	1250	* @}
Kojto	96:487b796308b0	1251	*/
Kojto	96:487b796308b0	1252
Kojto	96:487b796308b0	1253	/**
Kojto	96:487b796308b0	1254	* @}
Kojto	96:487b796308b0	1255	*/
Kojto	96:487b796308b0	1256
Kojto	96:487b796308b0	1257	#ifdef __cplusplus
Kojto	96:487b796308b0	1258	}
Kojto	96:487b796308b0	1259	#endif
Kojto	96:487b796308b0	1260
Kojto	96:487b796308b0	1261	#endif /* __STM32F1xx_HAL_RCC_H */
Kojto	96:487b796308b0	1262
Kojto	96:487b796308b0	1263	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	03 May 2015
Imports:	4
Forks:	0
Commits:	100
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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc.h@99:7f6c6de930c0, 2015-05-03 (annotated)

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