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TARGET_EFM32LG_STK3600/efm32lg990f256.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
98:8ab26030e058 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 98:8ab26030e058 1 /**************************************************************************//**
Kojto 98:8ab26030e058 2 * @file efm32lg990f256.h
Kojto 98:8ab26030e058 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
Kojto 98:8ab26030e058 4 * for EFM32LG990F256
Kojto 98:8ab26030e058 5 * @version 3.20.6
Kojto 98:8ab26030e058 6 ******************************************************************************
Kojto 98:8ab26030e058 7 * @section License
Kojto 98:8ab26030e058 8 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
Kojto 98:8ab26030e058 9 ******************************************************************************
Kojto 98:8ab26030e058 10 *
Kojto 98:8ab26030e058 11 * Permission is granted to anyone to use this software for any purpose,
Kojto 98:8ab26030e058 12 * including commercial applications, and to alter it and redistribute it
Kojto 98:8ab26030e058 13 * freely, subject to the following restrictions:
Kojto 98:8ab26030e058 14 *
Kojto 98:8ab26030e058 15 * 1. The origin of this software must not be misrepresented; you must not
Kojto 98:8ab26030e058 16 * claim that you wrote the original software.@n
Kojto 98:8ab26030e058 17 * 2. Altered source versions must be plainly marked as such, and must not be
Kojto 98:8ab26030e058 18 * misrepresented as being the original software.@n
Kojto 98:8ab26030e058 19 * 3. This notice may not be removed or altered from any source distribution.
Kojto 98:8ab26030e058 20 *
Kojto 98:8ab26030e058 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Kojto 98:8ab26030e058 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Kojto 98:8ab26030e058 23 * providing the Software "AS IS", with no express or implied warranties of any
Kojto 98:8ab26030e058 24 * kind, including, but not limited to, any implied warranties of
Kojto 98:8ab26030e058 25 * merchantability or fitness for any particular purpose or warranties against
Kojto 98:8ab26030e058 26 * infringement of any proprietary rights of a third party.
Kojto 98:8ab26030e058 27 *
Kojto 98:8ab26030e058 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
Kojto 98:8ab26030e058 29 * incidental, or special damages, or any other relief, or for any claim by
Kojto 98:8ab26030e058 30 * any third party, arising from your use of this Software.
Kojto 98:8ab26030e058 31 *
Kojto 98:8ab26030e058 32 *****************************************************************************/
Kojto 98:8ab26030e058 33
Kojto 98:8ab26030e058 34 #ifndef __EFM32LG990F256_H
Kojto 98:8ab26030e058 35 #define __EFM32LG990F256_H
Kojto 98:8ab26030e058 36
Kojto 98:8ab26030e058 37 #ifdef __cplusplus
Kojto 98:8ab26030e058 38 extern "C" {
Kojto 98:8ab26030e058 39 #endif
Kojto 98:8ab26030e058 40
Kojto 98:8ab26030e058 41 /**************************************************************************//**
Kojto 98:8ab26030e058 42 * @addtogroup Parts
Kojto 98:8ab26030e058 43 * @{
Kojto 98:8ab26030e058 44 *****************************************************************************/
Kojto 98:8ab26030e058 45
Kojto 98:8ab26030e058 46 /**************************************************************************//**
Kojto 98:8ab26030e058 47 * @defgroup EFM32LG990F256 EFM32LG990F256
Kojto 98:8ab26030e058 48 * @{
Kojto 98:8ab26030e058 49 *****************************************************************************/
Kojto 98:8ab26030e058 50
Kojto 98:8ab26030e058 51 /** Interrupt Number Definition */
Kojto 98:8ab26030e058 52 typedef enum IRQn
Kojto 98:8ab26030e058 53 {
Kojto 98:8ab26030e058 54 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/
Kojto 98:8ab26030e058 55 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 98:8ab26030e058 56 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
Kojto 98:8ab26030e058 57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Kojto 98:8ab26030e058 58 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Kojto 98:8ab26030e058 59 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Kojto 98:8ab26030e058 60 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Kojto 98:8ab26030e058 61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Kojto 98:8ab26030e058 62 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Kojto 98:8ab26030e058 63 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Kojto 98:8ab26030e058 64
Kojto 98:8ab26030e058 65 /****** EFM32LG Peripheral Interrupt Numbers *********************************************/
Kojto 98:8ab26030e058 66 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
Kojto 98:8ab26030e058 67 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
Kojto 98:8ab26030e058 68 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
Kojto 98:8ab26030e058 69 USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
Kojto 98:8ab26030e058 70 USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
Kojto 98:8ab26030e058 71 USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
Kojto 98:8ab26030e058 72 ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
Kojto 98:8ab26030e058 73 ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
Kojto 98:8ab26030e058 74 DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
Kojto 98:8ab26030e058 75 I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
Kojto 98:8ab26030e058 76 I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
Kojto 98:8ab26030e058 77 GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
Kojto 98:8ab26030e058 78 TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
Kojto 98:8ab26030e058 79 TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
Kojto 98:8ab26030e058 80 TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
Kojto 98:8ab26030e058 81 USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
Kojto 98:8ab26030e058 82 USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
Kojto 98:8ab26030e058 83 LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
Kojto 98:8ab26030e058 84 USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
Kojto 98:8ab26030e058 85 USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
Kojto 98:8ab26030e058 86 UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
Kojto 98:8ab26030e058 87 UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
Kojto 98:8ab26030e058 88 UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
Kojto 98:8ab26030e058 89 UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
Kojto 98:8ab26030e058 90 LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
Kojto 98:8ab26030e058 91 LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
Kojto 98:8ab26030e058 92 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
Kojto 98:8ab26030e058 93 PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
Kojto 98:8ab26030e058 94 PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
Kojto 98:8ab26030e058 95 PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
Kojto 98:8ab26030e058 96 RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
Kojto 98:8ab26030e058 97 BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
Kojto 98:8ab26030e058 98 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
Kojto 98:8ab26030e058 99 VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
Kojto 98:8ab26030e058 100 LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
Kojto 98:8ab26030e058 101 MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
Kojto 98:8ab26030e058 102 AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
Kojto 98:8ab26030e058 103 EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
Kojto 98:8ab26030e058 104 EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
Kojto 98:8ab26030e058 105 } IRQn_Type;
Kojto 98:8ab26030e058 106
Kojto 98:8ab26030e058 107 /**************************************************************************//**
Kojto 98:8ab26030e058 108 * @defgroup EFM32LG990F256_Core EFM32LG990F256 Core
Kojto 98:8ab26030e058 109 * @{
Kojto 98:8ab26030e058 110 * @brief Processor and Core Peripheral Section
Kojto 98:8ab26030e058 111 *****************************************************************************/
Kojto 98:8ab26030e058 112 #define __MPU_PRESENT 1 /**< Presence of MPU */
Kojto 98:8ab26030e058 113 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
Kojto 98:8ab26030e058 114 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
Kojto 98:8ab26030e058 115
Kojto 98:8ab26030e058 116 /** @} End of group EFM32LG990F256_Core */
Kojto 98:8ab26030e058 117
Kojto 98:8ab26030e058 118 /**************************************************************************//**
Kojto 98:8ab26030e058 119 * @defgroup EFM32LG990F256_Part EFM32LG990F256 Part
Kojto 98:8ab26030e058 120 * @{
Kojto 98:8ab26030e058 121 ******************************************************************************/
Kojto 98:8ab26030e058 122
Kojto 98:8ab26030e058 123 /** Part family */
Kojto 98:8ab26030e058 124 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
Kojto 98:8ab26030e058 125 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
Kojto 98:8ab26030e058 126
Kojto 98:8ab26030e058 127 /* If part number is not defined as compiler option, define it */
Kojto 98:8ab26030e058 128 #if !defined(EFM32LG990F256)
Kojto 98:8ab26030e058 129 #define EFM32LG990F256 1 /**< Giant/Leopard Gecko Part */
Kojto 98:8ab26030e058 130 #endif
Kojto 98:8ab26030e058 131
Kojto 98:8ab26030e058 132 /** Configure part number */
Kojto 98:8ab26030e058 133 #define PART_NUMBER "EFM32LG990F256" /**< Part Number */
Kojto 98:8ab26030e058 134
Kojto 98:8ab26030e058 135 /** Memory Base addresses and limits */
Kojto 98:8ab26030e058 136 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
Kojto 98:8ab26030e058 137 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
Kojto 98:8ab26030e058 138 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
Kojto 98:8ab26030e058 139 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
Kojto 98:8ab26030e058 140 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
Kojto 98:8ab26030e058 141 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
Kojto 98:8ab26030e058 142 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
Kojto 98:8ab26030e058 143 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
Kojto 98:8ab26030e058 144 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
Kojto 98:8ab26030e058 145 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
Kojto 98:8ab26030e058 146 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
Kojto 98:8ab26030e058 147 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
Kojto 98:8ab26030e058 148 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
Kojto 98:8ab26030e058 149 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
Kojto 98:8ab26030e058 150 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
Kojto 98:8ab26030e058 151 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
Kojto 98:8ab26030e058 152 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
Kojto 98:8ab26030e058 153 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
Kojto 98:8ab26030e058 154 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
Kojto 98:8ab26030e058 155 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
Kojto 98:8ab26030e058 156 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
Kojto 98:8ab26030e058 157 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
Kojto 98:8ab26030e058 158 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
Kojto 98:8ab26030e058 159 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
Kojto 98:8ab26030e058 160 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
Kojto 98:8ab26030e058 161 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
Kojto 98:8ab26030e058 162 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
Kojto 98:8ab26030e058 163 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
Kojto 98:8ab26030e058 164 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
Kojto 98:8ab26030e058 165 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
Kojto 98:8ab26030e058 166 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
Kojto 98:8ab26030e058 167 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
Kojto 98:8ab26030e058 168
Kojto 98:8ab26030e058 169 /** Bit banding area */
Kojto 98:8ab26030e058 170 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
Kojto 98:8ab26030e058 171 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
Kojto 98:8ab26030e058 172
Kojto 98:8ab26030e058 173 /** Flash and SRAM limits for EFM32LG990F256 */
Kojto 98:8ab26030e058 174 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
Kojto 98:8ab26030e058 175 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
Kojto 98:8ab26030e058 176 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
Kojto 98:8ab26030e058 177 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
Kojto 98:8ab26030e058 178 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
Kojto 98:8ab26030e058 179 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
Kojto 98:8ab26030e058 180 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
Kojto 98:8ab26030e058 181 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
Kojto 98:8ab26030e058 182
Kojto 98:8ab26030e058 183 /** AF channels connect the different on-chip peripherals with the af-mux */
Kojto 98:8ab26030e058 184 #define AFCHAN_MAX 163
Kojto 98:8ab26030e058 185 #define AFCHANLOC_MAX 7
Kojto 98:8ab26030e058 186 /** Analog AF channels */
Kojto 98:8ab26030e058 187 #define AFACHAN_MAX 53
Kojto 98:8ab26030e058 188
Kojto 98:8ab26030e058 189 /* Part number capabilities */
Kojto 98:8ab26030e058 190
Kojto 98:8ab26030e058 191 #define USART_PRESENT /**< USART is available in this part */
Kojto 98:8ab26030e058 192 #define USART_COUNT 3 /**< 3 USARTs available */
Kojto 98:8ab26030e058 193 #define UART_PRESENT /**< UART is available in this part */
Kojto 98:8ab26030e058 194 #define UART_COUNT 2 /**< 2 UARTs available */
Kojto 98:8ab26030e058 195 #define TIMER_PRESENT /**< TIMER is available in this part */
Kojto 98:8ab26030e058 196 #define TIMER_COUNT 4 /**< 4 TIMERs available */
Kojto 98:8ab26030e058 197 #define ACMP_PRESENT /**< ACMP is available in this part */
Kojto 98:8ab26030e058 198 #define ACMP_COUNT 2 /**< 2 ACMPs available */
Kojto 98:8ab26030e058 199 #define LEUART_PRESENT /**< LEUART is available in this part */
Kojto 98:8ab26030e058 200 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
Kojto 98:8ab26030e058 201 #define LETIMER_PRESENT /**< LETIMER is available in this part */
Kojto 98:8ab26030e058 202 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
Kojto 98:8ab26030e058 203 #define PCNT_PRESENT /**< PCNT is available in this part */
Kojto 98:8ab26030e058 204 #define PCNT_COUNT 3 /**< 3 PCNTs available */
Kojto 98:8ab26030e058 205 #define I2C_PRESENT /**< I2C is available in this part */
Kojto 98:8ab26030e058 206 #define I2C_COUNT 2 /**< 2 I2Cs available */
Kojto 98:8ab26030e058 207 #define ADC_PRESENT /**< ADC is available in this part */
Kojto 98:8ab26030e058 208 #define ADC_COUNT 1 /**< 1 ADCs available */
Kojto 98:8ab26030e058 209 #define DAC_PRESENT /**< DAC is available in this part */
Kojto 98:8ab26030e058 210 #define DAC_COUNT 1 /**< 1 DACs available */
Kojto 98:8ab26030e058 211 #define DMA_PRESENT
Kojto 98:8ab26030e058 212 #define DMA_COUNT 1
Kojto 98:8ab26030e058 213 #define AES_PRESENT
Kojto 98:8ab26030e058 214 #define AES_COUNT 1
Kojto 98:8ab26030e058 215 #define USBC_PRESENT
Kojto 98:8ab26030e058 216 #define USBC_COUNT 1
Kojto 98:8ab26030e058 217 #define USB_PRESENT
Kojto 98:8ab26030e058 218 #define USB_COUNT 1
Kojto 98:8ab26030e058 219 #define LE_PRESENT
Kojto 98:8ab26030e058 220 #define LE_COUNT 1
Kojto 98:8ab26030e058 221 #define MSC_PRESENT
Kojto 98:8ab26030e058 222 #define MSC_COUNT 1
Kojto 98:8ab26030e058 223 #define EMU_PRESENT
Kojto 98:8ab26030e058 224 #define EMU_COUNT 1
Kojto 98:8ab26030e058 225 #define RMU_PRESENT
Kojto 98:8ab26030e058 226 #define RMU_COUNT 1
Kojto 98:8ab26030e058 227 #define CMU_PRESENT
Kojto 98:8ab26030e058 228 #define CMU_COUNT 1
Kojto 98:8ab26030e058 229 #define LESENSE_PRESENT
Kojto 98:8ab26030e058 230 #define LESENSE_COUNT 1
Kojto 98:8ab26030e058 231 #define EBI_PRESENT
Kojto 98:8ab26030e058 232 #define EBI_COUNT 1
Kojto 98:8ab26030e058 233 #define RTC_PRESENT
Kojto 98:8ab26030e058 234 #define RTC_COUNT 1
Kojto 98:8ab26030e058 235 #define GPIO_PRESENT
Kojto 98:8ab26030e058 236 #define GPIO_COUNT 1
Kojto 98:8ab26030e058 237 #define VCMP_PRESENT
Kojto 98:8ab26030e058 238 #define VCMP_COUNT 1
Kojto 98:8ab26030e058 239 #define PRS_PRESENT
Kojto 98:8ab26030e058 240 #define PRS_COUNT 1
Kojto 98:8ab26030e058 241 #define OPAMP_PRESENT
Kojto 98:8ab26030e058 242 #define OPAMP_COUNT 1
Kojto 98:8ab26030e058 243 #define BU_PRESENT
Kojto 98:8ab26030e058 244 #define BU_COUNT 1
Kojto 98:8ab26030e058 245 #define LCD_PRESENT
Kojto 98:8ab26030e058 246 #define LCD_COUNT 1
Kojto 98:8ab26030e058 247 #define BURTC_PRESENT
Kojto 98:8ab26030e058 248 #define BURTC_COUNT 1
Kojto 98:8ab26030e058 249 #define HFXTAL_PRESENT
Kojto 98:8ab26030e058 250 #define HFXTAL_COUNT 1
Kojto 98:8ab26030e058 251 #define LFXTAL_PRESENT
Kojto 98:8ab26030e058 252 #define LFXTAL_COUNT 1
Kojto 98:8ab26030e058 253 #define WDOG_PRESENT
Kojto 98:8ab26030e058 254 #define WDOG_COUNT 1
Kojto 98:8ab26030e058 255 #define DBG_PRESENT
Kojto 98:8ab26030e058 256 #define DBG_COUNT 1
Kojto 98:8ab26030e058 257 #define ETM_PRESENT
Kojto 98:8ab26030e058 258 #define ETM_COUNT 1
Kojto 98:8ab26030e058 259 #define BOOTLOADER_PRESENT
Kojto 98:8ab26030e058 260 #define BOOTLOADER_COUNT 1
Kojto 98:8ab26030e058 261 #define ANALOG_PRESENT
Kojto 98:8ab26030e058 262 #define ANALOG_COUNT 1
Kojto 98:8ab26030e058 263
Kojto 98:8ab26030e058 264 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
Kojto 98:8ab26030e058 265 #include "system_efm32lg.h" /* System Header */
Kojto 98:8ab26030e058 266
Kojto 98:8ab26030e058 267 /** @} End of group EFM32LG990F256_Part */
Kojto 98:8ab26030e058 268
Kojto 98:8ab26030e058 269 /**************************************************************************//**
Kojto 98:8ab26030e058 270 * @defgroup EFM32LG990F256_Peripheral_TypeDefs EFM32LG990F256 Peripheral TypeDefs
Kojto 98:8ab26030e058 271 * @{
Kojto 98:8ab26030e058 272 * @brief Device Specific Peripheral Register Structures
Kojto 98:8ab26030e058 273 *****************************************************************************/
Kojto 98:8ab26030e058 274
Kojto 98:8ab26030e058 275 #include "efm32lg_dma_ch.h"
Kojto 98:8ab26030e058 276 #include "efm32lg_dma.h"
Kojto 98:8ab26030e058 277 #include "efm32lg_aes.h"
Kojto 98:8ab26030e058 278 #include "efm32lg_usb_hc.h"
Kojto 98:8ab26030e058 279 #include "efm32lg_usb_diep.h"
Kojto 98:8ab26030e058 280 #include "efm32lg_usb_doep.h"
Kojto 98:8ab26030e058 281 #include "efm32lg_usb.h"
Kojto 98:8ab26030e058 282 #include "efm32lg_msc.h"
Kojto 98:8ab26030e058 283 #include "efm32lg_emu.h"
Kojto 98:8ab26030e058 284 #include "efm32lg_rmu.h"
Kojto 98:8ab26030e058 285
Kojto 98:8ab26030e058 286 /**************************************************************************//**
Kojto 98:8ab26030e058 287 * @defgroup EFM32LG990F256_CMU EFM32LG990F256 CMU
Kojto 98:8ab26030e058 288 * @{
Kojto 98:8ab26030e058 289 * @brief EFM32LG990F256_CMU Register Declaration
Kojto 98:8ab26030e058 290 *****************************************************************************/
Kojto 98:8ab26030e058 291 typedef struct
Kojto 98:8ab26030e058 292 {
Kojto 98:8ab26030e058 293 __IO uint32_t CTRL; /**< CMU Control Register */
Kojto 98:8ab26030e058 294 __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
Kojto 98:8ab26030e058 295 __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
Kojto 98:8ab26030e058 296 __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */
Kojto 98:8ab26030e058 297 __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */
Kojto 98:8ab26030e058 298 __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
Kojto 98:8ab26030e058 299 __IO uint32_t CALCTRL; /**< Calibration Control Register */
Kojto 98:8ab26030e058 300 __IO uint32_t CALCNT; /**< Calibration Counter Register */
Kojto 98:8ab26030e058 301 __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
Kojto 98:8ab26030e058 302 __IO uint32_t CMD; /**< Command Register */
Kojto 98:8ab26030e058 303 __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
Kojto 98:8ab26030e058 304 __I uint32_t STATUS; /**< Status Register */
Kojto 98:8ab26030e058 305 __I uint32_t IF; /**< Interrupt Flag Register */
Kojto 98:8ab26030e058 306 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
Kojto 98:8ab26030e058 307 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
Kojto 98:8ab26030e058 308 __IO uint32_t IEN; /**< Interrupt Enable Register */
Kojto 98:8ab26030e058 309 __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
Kojto 98:8ab26030e058 310 __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
Kojto 98:8ab26030e058 311 uint32_t RESERVED0[2]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 312 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
Kojto 98:8ab26030e058 313 __IO uint32_t FREEZE; /**< Freeze Register */
Kojto 98:8ab26030e058 314 __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
Kojto 98:8ab26030e058 315 uint32_t RESERVED1[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 316 __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
Kojto 98:8ab26030e058 317 uint32_t RESERVED2[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 318 __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
Kojto 98:8ab26030e058 319 uint32_t RESERVED3[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 320 __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
Kojto 98:8ab26030e058 321 uint32_t RESERVED4[1]; /**< Reserved for future use **/
Kojto 98:8ab26030e058 322 __IO uint32_t PCNTCTRL; /**< PCNT Control Register */
Kojto 98:8ab26030e058 323 __IO uint32_t LCDCTRL; /**< LCD Control Register */
Kojto 98:8ab26030e058 324 __IO uint32_t ROUTE; /**< I/O Routing Register */
Kojto 98:8ab26030e058 325 __IO uint32_t LOCK; /**< Configuration Lock Register */
Kojto 98:8ab26030e058 326 } CMU_TypeDef; /** @} */
Kojto 98:8ab26030e058 327
Kojto 98:8ab26030e058 328 #include "efm32lg_lesense_st.h"
Kojto 98:8ab26030e058 329 #include "efm32lg_lesense_buf.h"
Kojto 98:8ab26030e058 330 #include "efm32lg_lesense_ch.h"
Kojto 98:8ab26030e058 331 #include "efm32lg_lesense.h"
Kojto 98:8ab26030e058 332 #include "efm32lg_ebi.h"
Kojto 98:8ab26030e058 333 #include "efm32lg_usart.h"
Kojto 98:8ab26030e058 334 #include "efm32lg_timer_cc.h"
Kojto 98:8ab26030e058 335 #include "efm32lg_timer.h"
Kojto 98:8ab26030e058 336 #include "efm32lg_acmp.h"
Kojto 98:8ab26030e058 337 #include "efm32lg_leuart.h"
Kojto 98:8ab26030e058 338 #include "efm32lg_rtc.h"
Kojto 98:8ab26030e058 339 #include "efm32lg_letimer.h"
Kojto 98:8ab26030e058 340 #include "efm32lg_pcnt.h"
Kojto 98:8ab26030e058 341 #include "efm32lg_i2c.h"
Kojto 98:8ab26030e058 342 #include "efm32lg_gpio_p.h"
Kojto 98:8ab26030e058 343 #include "efm32lg_gpio.h"
Kojto 98:8ab26030e058 344 #include "efm32lg_vcmp.h"
Kojto 98:8ab26030e058 345 #include "efm32lg_prs_ch.h"
Kojto 98:8ab26030e058 346 #include "efm32lg_prs.h"
Kojto 98:8ab26030e058 347 #include "efm32lg_adc.h"
Kojto 98:8ab26030e058 348 #include "efm32lg_dac.h"
Kojto 98:8ab26030e058 349 #include "efm32lg_lcd.h"
Kojto 98:8ab26030e058 350 #include "efm32lg_burtc_ret.h"
Kojto 98:8ab26030e058 351 #include "efm32lg_burtc.h"
Kojto 98:8ab26030e058 352 #include "efm32lg_wdog.h"
Kojto 98:8ab26030e058 353 #include "efm32lg_etm.h"
Kojto 98:8ab26030e058 354 #include "efm32lg_dma_descriptor.h"
Kojto 98:8ab26030e058 355 #include "efm32lg_devinfo.h"
Kojto 98:8ab26030e058 356 #include "efm32lg_romtable.h"
Kojto 98:8ab26030e058 357 #include "efm32lg_calibrate.h"
Kojto 98:8ab26030e058 358
Kojto 98:8ab26030e058 359 /** @} End of group EFM32LG990F256_Peripheral_TypeDefs */
Kojto 98:8ab26030e058 360
Kojto 98:8ab26030e058 361 /**************************************************************************//**
Kojto 98:8ab26030e058 362 * @defgroup EFM32LG990F256_Peripheral_Base EFM32LG990F256 Peripheral Memory Map
Kojto 98:8ab26030e058 363 * @{
Kojto 98:8ab26030e058 364 *****************************************************************************/
Kojto 98:8ab26030e058 365
Kojto 98:8ab26030e058 366 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
Kojto 98:8ab26030e058 367 #define AES_BASE (0x400E0000UL) /**< AES base address */
Kojto 98:8ab26030e058 368 #define USB_BASE (0x400C4000UL) /**< USB base address */
Kojto 98:8ab26030e058 369 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
Kojto 98:8ab26030e058 370 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
Kojto 98:8ab26030e058 371 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
Kojto 98:8ab26030e058 372 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
Kojto 98:8ab26030e058 373 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
Kojto 98:8ab26030e058 374 #define EBI_BASE (0x40008000UL) /**< EBI base address */
Kojto 98:8ab26030e058 375 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
Kojto 98:8ab26030e058 376 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
Kojto 98:8ab26030e058 377 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
Kojto 98:8ab26030e058 378 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
Kojto 98:8ab26030e058 379 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
Kojto 98:8ab26030e058 380 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
Kojto 98:8ab26030e058 381 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
Kojto 98:8ab26030e058 382 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
Kojto 98:8ab26030e058 383 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
Kojto 98:8ab26030e058 384 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
Kojto 98:8ab26030e058 385 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
Kojto 98:8ab26030e058 386 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
Kojto 98:8ab26030e058 387 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
Kojto 98:8ab26030e058 388 #define RTC_BASE (0x40080000UL) /**< RTC base address */
Kojto 98:8ab26030e058 389 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
Kojto 98:8ab26030e058 390 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
Kojto 98:8ab26030e058 391 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
Kojto 98:8ab26030e058 392 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
Kojto 98:8ab26030e058 393 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
Kojto 98:8ab26030e058 394 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
Kojto 98:8ab26030e058 395 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
Kojto 98:8ab26030e058 396 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
Kojto 98:8ab26030e058 397 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
Kojto 98:8ab26030e058 398 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
Kojto 98:8ab26030e058 399 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
Kojto 98:8ab26030e058 400 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
Kojto 98:8ab26030e058 401 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
Kojto 98:8ab26030e058 402 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
Kojto 98:8ab26030e058 403 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
Kojto 98:8ab26030e058 404 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
Kojto 98:8ab26030e058 405 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
Kojto 98:8ab26030e058 406 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
Kojto 98:8ab26030e058 407 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
Kojto 98:8ab26030e058 408 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
Kojto 98:8ab26030e058 409
Kojto 98:8ab26030e058 410 /** @} End of group EFM32LG990F256_Peripheral_Base */
Kojto 98:8ab26030e058 411
Kojto 98:8ab26030e058 412 /**************************************************************************//**
Kojto 98:8ab26030e058 413 * @defgroup EFM32LG990F256_Peripheral_Declaration EFM32LG990F256 Peripheral Declarations
Kojto 98:8ab26030e058 414 * @{
Kojto 98:8ab26030e058 415 *****************************************************************************/
Kojto 98:8ab26030e058 416
Kojto 98:8ab26030e058 417 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
Kojto 98:8ab26030e058 418 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
Kojto 98:8ab26030e058 419 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
Kojto 98:8ab26030e058 420 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
Kojto 98:8ab26030e058 421 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
Kojto 98:8ab26030e058 422 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
Kojto 98:8ab26030e058 423 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
Kojto 98:8ab26030e058 424 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
Kojto 98:8ab26030e058 425 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
Kojto 98:8ab26030e058 426 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
Kojto 98:8ab26030e058 427 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
Kojto 98:8ab26030e058 428 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
Kojto 98:8ab26030e058 429 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
Kojto 98:8ab26030e058 430 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
Kojto 98:8ab26030e058 431 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
Kojto 98:8ab26030e058 432 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
Kojto 98:8ab26030e058 433 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
Kojto 98:8ab26030e058 434 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
Kojto 98:8ab26030e058 435 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
Kojto 98:8ab26030e058 436 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
Kojto 98:8ab26030e058 437 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
Kojto 98:8ab26030e058 438 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
Kojto 98:8ab26030e058 439 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
Kojto 98:8ab26030e058 440 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
Kojto 98:8ab26030e058 441 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
Kojto 98:8ab26030e058 442 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
Kojto 98:8ab26030e058 443 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
Kojto 98:8ab26030e058 444 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
Kojto 98:8ab26030e058 445 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
Kojto 98:8ab26030e058 446 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
Kojto 98:8ab26030e058 447 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
Kojto 98:8ab26030e058 448 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
Kojto 98:8ab26030e058 449 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
Kojto 98:8ab26030e058 450 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
Kojto 98:8ab26030e058 451 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
Kojto 98:8ab26030e058 452 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
Kojto 98:8ab26030e058 453 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
Kojto 98:8ab26030e058 454 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
Kojto 98:8ab26030e058 455 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
Kojto 98:8ab26030e058 456 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
Kojto 98:8ab26030e058 457 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
Kojto 98:8ab26030e058 458
Kojto 98:8ab26030e058 459 /** @} End of group EFM32LG990F256_Peripheral_Declaration */
Kojto 98:8ab26030e058 460
Kojto 98:8ab26030e058 461 /**************************************************************************//**
Kojto 98:8ab26030e058 462 * @defgroup EFM32LG990F256_BitFields EFM32LG990F256 Bit Fields
Kojto 98:8ab26030e058 463 * @{
Kojto 98:8ab26030e058 464 *****************************************************************************/
Kojto 98:8ab26030e058 465
Kojto 98:8ab26030e058 466 #include "efm32lg_prs_signals.h"
Kojto 98:8ab26030e058 467 #include "efm32lg_dmareq.h"
Kojto 98:8ab26030e058 468 #include "efm32lg_dmactrl.h"
Kojto 98:8ab26030e058 469 #include "efm32lg_uart.h"
Kojto 98:8ab26030e058 470
Kojto 98:8ab26030e058 471 /**************************************************************************//**
Kojto 98:8ab26030e058 472 * @defgroup EFM32LG990F256_CMU_BitFields EFM32LG990F256_CMU Bit Fields
Kojto 98:8ab26030e058 473 * @{
Kojto 98:8ab26030e058 474 *****************************************************************************/
Kojto 98:8ab26030e058 475
Kojto 98:8ab26030e058 476 /* Bit fields for CMU CTRL */
Kojto 98:8ab26030e058 477 #define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
Kojto 98:8ab26030e058 478 #define _CMU_CTRL_MASK 0x53FFFEEFUL /**< Mask for CMU_CTRL */
Kojto 98:8ab26030e058 479 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
Kojto 98:8ab26030e058 480 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
Kojto 98:8ab26030e058 481 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 482 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 483 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 484 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 485 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 486 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 487 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 488 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 489 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
Kojto 98:8ab26030e058 490 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
Kojto 98:8ab26030e058 491 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 492 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 493 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 494 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 495 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 496 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 497 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 498 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 499 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 500 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 501 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
Kojto 98:8ab26030e058 502 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
Kojto 98:8ab26030e058 503 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 504 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
Kojto 98:8ab26030e058 505 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
Kojto 98:8ab26030e058 506 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 507 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
Kojto 98:8ab26030e058 508 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
Kojto 98:8ab26030e058 509 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
Kojto 98:8ab26030e058 510 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
Kojto 98:8ab26030e058 511 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
Kojto 98:8ab26030e058 512 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 513 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 514 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
Kojto 98:8ab26030e058 515 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
Kojto 98:8ab26030e058 516 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 517 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 518 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 519 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 520 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 521 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 522 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 523 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 524 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 525 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 526 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
Kojto 98:8ab26030e058 527 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
Kojto 98:8ab26030e058 528 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 529 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 530 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 531 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 532 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 533 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
Kojto 98:8ab26030e058 534 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 535 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
Kojto 98:8ab26030e058 536 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
Kojto 98:8ab26030e058 537 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
Kojto 98:8ab26030e058 538 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
Kojto 98:8ab26030e058 539 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 540 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 541 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 542 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 543 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 544 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
Kojto 98:8ab26030e058 545 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
Kojto 98:8ab26030e058 546 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
Kojto 98:8ab26030e058 547 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 548 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 549 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
Kojto 98:8ab26030e058 550 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
Kojto 98:8ab26030e058 551 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
Kojto 98:8ab26030e058 552 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 553 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 554 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
Kojto 98:8ab26030e058 555 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
Kojto 98:8ab26030e058 556 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 557 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 558 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 559 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 560 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 561 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 562 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 563 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 564 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 565 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
Kojto 98:8ab26030e058 566 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
Kojto 98:8ab26030e058 567 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
Kojto 98:8ab26030e058 568 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 569 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 570 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
Kojto 98:8ab26030e058 571 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
Kojto 98:8ab26030e058 572 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
Kojto 98:8ab26030e058 573 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
Kojto 98:8ab26030e058 574 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
Kojto 98:8ab26030e058 575 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 576 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 577 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 578 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 579 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
Kojto 98:8ab26030e058 580 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
Kojto 98:8ab26030e058 581 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
Kojto 98:8ab26030e058 582 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
Kojto 98:8ab26030e058 583 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
Kojto 98:8ab26030e058 584 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 585 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 586 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
Kojto 98:8ab26030e058 587 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
Kojto 98:8ab26030e058 588 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 589 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 590 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
Kojto 98:8ab26030e058 591 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 592 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 593 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 594 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 595 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 596 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 597 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 598 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 599 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
Kojto 98:8ab26030e058 600 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 601 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 602 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
Kojto 98:8ab26030e058 603 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 604 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 605 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
Kojto 98:8ab26030e058 606 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
Kojto 98:8ab26030e058 607 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
Kojto 98:8ab26030e058 608 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
Kojto 98:8ab26030e058 609 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 610 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 611 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 612 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 613 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
Kojto 98:8ab26030e058 614 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
Kojto 98:8ab26030e058 615 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
Kojto 98:8ab26030e058 616 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
Kojto 98:8ab26030e058 617 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
Kojto 98:8ab26030e058 618 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 619 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
Kojto 98:8ab26030e058 620
Kojto 98:8ab26030e058 621 /* Bit fields for CMU HFCORECLKDIV */
Kojto 98:8ab26030e058 622 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 623 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 624 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 625 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 626 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 627 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 628 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 629 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 630 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 631 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 632 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 633 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 634 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 635 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 636 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 637 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 638 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 639 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 640 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 641 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 642 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 643 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 644 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 645 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 646 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 647 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 648 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
Kojto 98:8ab26030e058 649 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
Kojto 98:8ab26030e058 650 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
Kojto 98:8ab26030e058 651 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 652 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 653 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 654 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 655 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 656 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
Kojto 98:8ab26030e058 657
Kojto 98:8ab26030e058 658 /* Bit fields for CMU HFPERCLKDIV */
Kojto 98:8ab26030e058 659 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 660 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 661 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 662 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 663 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 664 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 665 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 666 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 667 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 668 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 669 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 670 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 671 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 672 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 673 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 674 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 675 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 676 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 677 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 678 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 679 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 680 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 681 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 682 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 683 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 684 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 685 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
Kojto 98:8ab26030e058 686 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
Kojto 98:8ab26030e058 687 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
Kojto 98:8ab26030e058 688 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 689 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
Kojto 98:8ab26030e058 690
Kojto 98:8ab26030e058 691 /* Bit fields for CMU HFRCOCTRL */
Kojto 98:8ab26030e058 692 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 693 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 694 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 695 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 696 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 697 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 698 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
Kojto 98:8ab26030e058 699 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
Kojto 98:8ab26030e058 700 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 701 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 702 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 703 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 704 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 705 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 706 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 707 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 708 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 709 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 710 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 711 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 712 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 713 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 714 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
Kojto 98:8ab26030e058 715 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
Kojto 98:8ab26030e058 716 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 717 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
Kojto 98:8ab26030e058 718
Kojto 98:8ab26030e058 719 /* Bit fields for CMU LFRCOCTRL */
Kojto 98:8ab26030e058 720 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 721 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 722 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 723 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 724 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 725 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
Kojto 98:8ab26030e058 726
Kojto 98:8ab26030e058 727 /* Bit fields for CMU AUXHFRCOCTRL */
Kojto 98:8ab26030e058 728 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 729 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 730 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
Kojto 98:8ab26030e058 731 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
Kojto 98:8ab26030e058 732 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 733 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 734 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
Kojto 98:8ab26030e058 735 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
Kojto 98:8ab26030e058 736 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 737 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 738 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 739 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 740 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 741 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 742 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 743 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 744 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 745 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 746 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 747 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 748 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 749 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
Kojto 98:8ab26030e058 750
Kojto 98:8ab26030e058 751 /* Bit fields for CMU CALCTRL */
Kojto 98:8ab26030e058 752 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
Kojto 98:8ab26030e058 753 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
Kojto 98:8ab26030e058 754 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
Kojto 98:8ab26030e058 755 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
Kojto 98:8ab26030e058 756 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 757 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 758 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 759 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 760 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 761 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 762 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 763 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 764 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 765 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 766 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 767 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 768 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
Kojto 98:8ab26030e058 769 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
Kojto 98:8ab26030e058 770 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 771 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
Kojto 98:8ab26030e058 772 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 773 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 774 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 775 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 776 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 777 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 778 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
Kojto 98:8ab26030e058 779 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 780 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
Kojto 98:8ab26030e058 781 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 782 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 783 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
Kojto 98:8ab26030e058 784 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
Kojto 98:8ab26030e058 785 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
Kojto 98:8ab26030e058 786 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
Kojto 98:8ab26030e058 787 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 788 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
Kojto 98:8ab26030e058 789
Kojto 98:8ab26030e058 790 /* Bit fields for CMU CALCNT */
Kojto 98:8ab26030e058 791 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
Kojto 98:8ab26030e058 792 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
Kojto 98:8ab26030e058 793 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
Kojto 98:8ab26030e058 794 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
Kojto 98:8ab26030e058 795 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
Kojto 98:8ab26030e058 796 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
Kojto 98:8ab26030e058 797
Kojto 98:8ab26030e058 798 /* Bit fields for CMU OSCENCMD */
Kojto 98:8ab26030e058 799 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
Kojto 98:8ab26030e058 800 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
Kojto 98:8ab26030e058 801 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
Kojto 98:8ab26030e058 802 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
Kojto 98:8ab26030e058 803 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
Kojto 98:8ab26030e058 804 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 805 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 806 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
Kojto 98:8ab26030e058 807 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
Kojto 98:8ab26030e058 808 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
Kojto 98:8ab26030e058 809 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 810 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 811 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
Kojto 98:8ab26030e058 812 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
Kojto 98:8ab26030e058 813 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
Kojto 98:8ab26030e058 814 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 815 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 816 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
Kojto 98:8ab26030e058 817 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
Kojto 98:8ab26030e058 818 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
Kojto 98:8ab26030e058 819 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 820 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 821 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
Kojto 98:8ab26030e058 822 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
Kojto 98:8ab26030e058 823 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
Kojto 98:8ab26030e058 824 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 825 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 826 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
Kojto 98:8ab26030e058 827 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
Kojto 98:8ab26030e058 828 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
Kojto 98:8ab26030e058 829 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 830 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 831 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
Kojto 98:8ab26030e058 832 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
Kojto 98:8ab26030e058 833 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
Kojto 98:8ab26030e058 834 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 835 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 836 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
Kojto 98:8ab26030e058 837 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
Kojto 98:8ab26030e058 838 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
Kojto 98:8ab26030e058 839 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 840 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 841 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
Kojto 98:8ab26030e058 842 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
Kojto 98:8ab26030e058 843 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
Kojto 98:8ab26030e058 844 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 845 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 846 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
Kojto 98:8ab26030e058 847 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
Kojto 98:8ab26030e058 848 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
Kojto 98:8ab26030e058 849 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 850 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
Kojto 98:8ab26030e058 851
Kojto 98:8ab26030e058 852 /* Bit fields for CMU CMD */
Kojto 98:8ab26030e058 853 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
Kojto 98:8ab26030e058 854 #define _CMU_CMD_MASK 0x0000007FUL /**< Mask for CMU_CMD */
Kojto 98:8ab26030e058 855 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
Kojto 98:8ab26030e058 856 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
Kojto 98:8ab26030e058 857 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 858 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
Kojto 98:8ab26030e058 859 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
Kojto 98:8ab26030e058 860 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 861 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 862 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 863 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
Kojto 98:8ab26030e058 864 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
Kojto 98:8ab26030e058 865 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 866 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 867 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
Kojto 98:8ab26030e058 868 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
Kojto 98:8ab26030e058 869 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
Kojto 98:8ab26030e058 870 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 871 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 872 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
Kojto 98:8ab26030e058 873 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
Kojto 98:8ab26030e058 874 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
Kojto 98:8ab26030e058 875 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 876 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 877 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
Kojto 98:8ab26030e058 878 #define _CMU_CMD_USBCCLKSEL_MASK 0x60UL /**< Bit mask for CMU_USBCCLKSEL */
Kojto 98:8ab26030e058 879 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 880 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */
Kojto 98:8ab26030e058 881 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 882 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 883 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
Kojto 98:8ab26030e058 884 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */
Kojto 98:8ab26030e058 885 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
Kojto 98:8ab26030e058 886 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
Kojto 98:8ab26030e058 887
Kojto 98:8ab26030e058 888 /* Bit fields for CMU LFCLKSEL */
Kojto 98:8ab26030e058 889 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 890 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 891 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
Kojto 98:8ab26030e058 892 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
Kojto 98:8ab26030e058 893 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 894 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 895 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 896 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 897 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 898 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 899 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 900 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 901 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 902 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 903 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
Kojto 98:8ab26030e058 904 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
Kojto 98:8ab26030e058 905 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 906 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 907 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 908 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 909 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 910 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 911 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 912 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 913 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 914 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 915 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
Kojto 98:8ab26030e058 916 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
Kojto 98:8ab26030e058 917 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
Kojto 98:8ab26030e058 918 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 919 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 920 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 921 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 922 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 923 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 924 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
Kojto 98:8ab26030e058 925 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
Kojto 98:8ab26030e058 926 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
Kojto 98:8ab26030e058 927 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 928 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 929 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 930 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 931 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 932 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
Kojto 98:8ab26030e058 933
Kojto 98:8ab26030e058 934 /* Bit fields for CMU STATUS */
Kojto 98:8ab26030e058 935 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
Kojto 98:8ab26030e058 936 #define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */
Kojto 98:8ab26030e058 937 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
Kojto 98:8ab26030e058 938 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
Kojto 98:8ab26030e058 939 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
Kojto 98:8ab26030e058 940 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 941 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 942 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
Kojto 98:8ab26030e058 943 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 944 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 945 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 946 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 947 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
Kojto 98:8ab26030e058 948 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
Kojto 98:8ab26030e058 949 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
Kojto 98:8ab26030e058 950 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 951 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 952 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
Kojto 98:8ab26030e058 953 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 954 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 955 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 956 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 957 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
Kojto 98:8ab26030e058 958 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
Kojto 98:8ab26030e058 959 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
Kojto 98:8ab26030e058 960 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 961 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 962 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
Kojto 98:8ab26030e058 963 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 964 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 965 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 966 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 967 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
Kojto 98:8ab26030e058 968 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
Kojto 98:8ab26030e058 969 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
Kojto 98:8ab26030e058 970 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 971 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 972 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
Kojto 98:8ab26030e058 973 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 974 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 975 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 976 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 977 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
Kojto 98:8ab26030e058 978 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
Kojto 98:8ab26030e058 979 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
Kojto 98:8ab26030e058 980 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 981 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 982 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
Kojto 98:8ab26030e058 983 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 984 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 985 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 986 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 987 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
Kojto 98:8ab26030e058 988 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
Kojto 98:8ab26030e058 989 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
Kojto 98:8ab26030e058 990 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 991 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 992 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
Kojto 98:8ab26030e058 993 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
Kojto 98:8ab26030e058 994 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
Kojto 98:8ab26030e058 995 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 996 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 997 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
Kojto 98:8ab26030e058 998 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
Kojto 98:8ab26030e058 999 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
Kojto 98:8ab26030e058 1000 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1001 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1002 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
Kojto 98:8ab26030e058 1003 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
Kojto 98:8ab26030e058 1004 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
Kojto 98:8ab26030e058 1005 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1006 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1007 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
Kojto 98:8ab26030e058 1008 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
Kojto 98:8ab26030e058 1009 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
Kojto 98:8ab26030e058 1010 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1011 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1012 #define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */
Kojto 98:8ab26030e058 1013 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1014 #define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1015 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1016 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1017 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
Kojto 98:8ab26030e058 1018 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
Kojto 98:8ab26030e058 1019 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
Kojto 98:8ab26030e058 1020 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1021 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1022 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
Kojto 98:8ab26030e058 1023 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
Kojto 98:8ab26030e058 1024 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
Kojto 98:8ab26030e058 1025 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1026 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
Kojto 98:8ab26030e058 1027
Kojto 98:8ab26030e058 1028 /* Bit fields for CMU IF */
Kojto 98:8ab26030e058 1029 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
Kojto 98:8ab26030e058 1030 #define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */
Kojto 98:8ab26030e058 1031 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 1032 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1033 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1034 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1035 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1036 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
Kojto 98:8ab26030e058 1037 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 1038 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 1039 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1040 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1041 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 1042 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1043 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1044 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1045 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1046 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
Kojto 98:8ab26030e058 1047 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 1048 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 1049 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1050 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1051 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
Kojto 98:8ab26030e058 1052 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1053 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1054 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1055 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1056 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
Kojto 98:8ab26030e058 1057 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 1058 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 1059 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1060 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1061 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
Kojto 98:8ab26030e058 1062 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 1063 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 1064 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1065 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1066 #define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */
Kojto 98:8ab26030e058 1067 #define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1068 #define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1069 #define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1070 #define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */
Kojto 98:8ab26030e058 1071
Kojto 98:8ab26030e058 1072 /* Bit fields for CMU IFS */
Kojto 98:8ab26030e058 1073 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
Kojto 98:8ab26030e058 1074 #define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */
Kojto 98:8ab26030e058 1075 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1076 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1077 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1078 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1079 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1080 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1081 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 1082 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 1083 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1084 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1085 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1086 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1087 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1088 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1089 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1090 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1091 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 1092 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 1093 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1094 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1095 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1096 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1097 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1098 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1099 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1100 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
Kojto 98:8ab26030e058 1101 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 1102 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 1103 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1104 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1105 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
Kojto 98:8ab26030e058 1106 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 1107 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 1108 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1109 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1110 #define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */
Kojto 98:8ab26030e058 1111 #define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1112 #define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1113 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1114 #define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */
Kojto 98:8ab26030e058 1115
Kojto 98:8ab26030e058 1116 /* Bit fields for CMU IFC */
Kojto 98:8ab26030e058 1117 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
Kojto 98:8ab26030e058 1118 #define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */
Kojto 98:8ab26030e058 1119 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1120 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1121 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1122 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1123 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1124 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1125 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 1126 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 1127 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1128 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1129 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1130 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1131 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1132 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1133 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1134 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1135 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 1136 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 1137 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1138 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1139 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1140 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1141 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1142 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1143 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1144 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
Kojto 98:8ab26030e058 1145 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 1146 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 1147 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1148 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1149 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
Kojto 98:8ab26030e058 1150 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 1151 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 1152 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1153 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1154 #define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */
Kojto 98:8ab26030e058 1155 #define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1156 #define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1157 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1158 #define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */
Kojto 98:8ab26030e058 1159
Kojto 98:8ab26030e058 1160 /* Bit fields for CMU IEN */
Kojto 98:8ab26030e058 1161 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
Kojto 98:8ab26030e058 1162 #define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */
Kojto 98:8ab26030e058 1163 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 1164 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1165 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
Kojto 98:8ab26030e058 1166 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1167 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1168 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
Kojto 98:8ab26030e058 1169 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
Kojto 98:8ab26030e058 1170 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
Kojto 98:8ab26030e058 1171 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1172 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1173 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 1174 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1175 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
Kojto 98:8ab26030e058 1176 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1177 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1178 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
Kojto 98:8ab26030e058 1179 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
Kojto 98:8ab26030e058 1180 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
Kojto 98:8ab26030e058 1181 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1182 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1183 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
Kojto 98:8ab26030e058 1184 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1185 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
Kojto 98:8ab26030e058 1186 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1187 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1188 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
Kojto 98:8ab26030e058 1189 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
Kojto 98:8ab26030e058 1190 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
Kojto 98:8ab26030e058 1191 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1192 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1193 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
Kojto 98:8ab26030e058 1194 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
Kojto 98:8ab26030e058 1195 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
Kojto 98:8ab26030e058 1196 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1197 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1198 #define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */
Kojto 98:8ab26030e058 1199 #define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1200 #define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
Kojto 98:8ab26030e058 1201 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1202 #define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */
Kojto 98:8ab26030e058 1203
Kojto 98:8ab26030e058 1204 /* Bit fields for CMU HFCORECLKEN0 */
Kojto 98:8ab26030e058 1205 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1206 #define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1207 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
Kojto 98:8ab26030e058 1208 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
Kojto 98:8ab26030e058 1209 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
Kojto 98:8ab26030e058 1210 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1211 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1212 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
Kojto 98:8ab26030e058 1213 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
Kojto 98:8ab26030e058 1214 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
Kojto 98:8ab26030e058 1215 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1216 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1217 #define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */
Kojto 98:8ab26030e058 1218 #define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */
Kojto 98:8ab26030e058 1219 #define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */
Kojto 98:8ab26030e058 1220 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1221 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1222 #define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */
Kojto 98:8ab26030e058 1223 #define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */
Kojto 98:8ab26030e058 1224 #define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */
Kojto 98:8ab26030e058 1225 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1226 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1227 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
Kojto 98:8ab26030e058 1228 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
Kojto 98:8ab26030e058 1229 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
Kojto 98:8ab26030e058 1230 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1231 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1232 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */
Kojto 98:8ab26030e058 1233 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */
Kojto 98:8ab26030e058 1234 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */
Kojto 98:8ab26030e058 1235 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1236 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
Kojto 98:8ab26030e058 1237
Kojto 98:8ab26030e058 1238 /* Bit fields for CMU HFPERCLKEN0 */
Kojto 98:8ab26030e058 1239 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1240 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1241 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
Kojto 98:8ab26030e058 1242 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
Kojto 98:8ab26030e058 1243 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
Kojto 98:8ab26030e058 1244 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1245 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1246 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
Kojto 98:8ab26030e058 1247 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
Kojto 98:8ab26030e058 1248 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
Kojto 98:8ab26030e058 1249 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1250 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1251 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
Kojto 98:8ab26030e058 1252 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
Kojto 98:8ab26030e058 1253 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
Kojto 98:8ab26030e058 1254 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1255 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1256 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
Kojto 98:8ab26030e058 1257 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */
Kojto 98:8ab26030e058 1258 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */
Kojto 98:8ab26030e058 1259 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1260 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1261 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
Kojto 98:8ab26030e058 1262 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */
Kojto 98:8ab26030e058 1263 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */
Kojto 98:8ab26030e058 1264 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1265 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1266 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
Kojto 98:8ab26030e058 1267 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
Kojto 98:8ab26030e058 1268 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
Kojto 98:8ab26030e058 1269 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1270 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1271 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
Kojto 98:8ab26030e058 1272 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
Kojto 98:8ab26030e058 1273 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
Kojto 98:8ab26030e058 1274 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1275 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1276 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
Kojto 98:8ab26030e058 1277 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
Kojto 98:8ab26030e058 1278 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
Kojto 98:8ab26030e058 1279 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1280 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1281 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
Kojto 98:8ab26030e058 1282 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
Kojto 98:8ab26030e058 1283 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
Kojto 98:8ab26030e058 1284 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1285 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1286 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
Kojto 98:8ab26030e058 1287 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
Kojto 98:8ab26030e058 1288 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
Kojto 98:8ab26030e058 1289 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1290 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1291 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
Kojto 98:8ab26030e058 1292 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
Kojto 98:8ab26030e058 1293 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
Kojto 98:8ab26030e058 1294 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1295 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1296 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
Kojto 98:8ab26030e058 1297 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
Kojto 98:8ab26030e058 1298 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
Kojto 98:8ab26030e058 1299 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1300 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1301 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
Kojto 98:8ab26030e058 1302 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
Kojto 98:8ab26030e058 1303 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
Kojto 98:8ab26030e058 1304 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1305 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1306 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
Kojto 98:8ab26030e058 1307 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
Kojto 98:8ab26030e058 1308 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
Kojto 98:8ab26030e058 1309 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1310 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1311 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
Kojto 98:8ab26030e058 1312 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
Kojto 98:8ab26030e058 1313 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
Kojto 98:8ab26030e058 1314 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1315 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1316 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
Kojto 98:8ab26030e058 1317 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
Kojto 98:8ab26030e058 1318 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
Kojto 98:8ab26030e058 1319 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1320 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1321 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
Kojto 98:8ab26030e058 1322 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
Kojto 98:8ab26030e058 1323 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
Kojto 98:8ab26030e058 1324 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1325 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1326 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
Kojto 98:8ab26030e058 1327 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
Kojto 98:8ab26030e058 1328 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
Kojto 98:8ab26030e058 1329 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1330 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
Kojto 98:8ab26030e058 1331
Kojto 98:8ab26030e058 1332 /* Bit fields for CMU SYNCBUSY */
Kojto 98:8ab26030e058 1333 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1334 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1335 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
Kojto 98:8ab26030e058 1336 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1337 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1338 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1339 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1340 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
Kojto 98:8ab26030e058 1341 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1342 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1343 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1344 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1345 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
Kojto 98:8ab26030e058 1346 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1347 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1348 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1349 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1350 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
Kojto 98:8ab26030e058 1351 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1352 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1353 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1354 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
Kojto 98:8ab26030e058 1355
Kojto 98:8ab26030e058 1356 /* Bit fields for CMU FREEZE */
Kojto 98:8ab26030e058 1357 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
Kojto 98:8ab26030e058 1358 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
Kojto 98:8ab26030e058 1359 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
Kojto 98:8ab26030e058 1360 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
Kojto 98:8ab26030e058 1361 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
Kojto 98:8ab26030e058 1362 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
Kojto 98:8ab26030e058 1363 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
Kojto 98:8ab26030e058 1364 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
Kojto 98:8ab26030e058 1365 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
Kojto 98:8ab26030e058 1366 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
Kojto 98:8ab26030e058 1367 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
Kojto 98:8ab26030e058 1368
Kojto 98:8ab26030e058 1369 /* Bit fields for CMU LFACLKEN0 */
Kojto 98:8ab26030e058 1370 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1371 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1372 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
Kojto 98:8ab26030e058 1373 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
Kojto 98:8ab26030e058 1374 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
Kojto 98:8ab26030e058 1375 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1376 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1377 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
Kojto 98:8ab26030e058 1378 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
Kojto 98:8ab26030e058 1379 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
Kojto 98:8ab26030e058 1380 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1381 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1382 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
Kojto 98:8ab26030e058 1383 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
Kojto 98:8ab26030e058 1384 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
Kojto 98:8ab26030e058 1385 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1386 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1387 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */
Kojto 98:8ab26030e058 1388 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */
Kojto 98:8ab26030e058 1389 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */
Kojto 98:8ab26030e058 1390 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1391 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
Kojto 98:8ab26030e058 1392
Kojto 98:8ab26030e058 1393 /* Bit fields for CMU LFBCLKEN0 */
Kojto 98:8ab26030e058 1394 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1395 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1396 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
Kojto 98:8ab26030e058 1397 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Kojto 98:8ab26030e058 1398 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
Kojto 98:8ab26030e058 1399 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1400 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1401 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
Kojto 98:8ab26030e058 1402 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
Kojto 98:8ab26030e058 1403 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
Kojto 98:8ab26030e058 1404 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1405 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
Kojto 98:8ab26030e058 1406
Kojto 98:8ab26030e058 1407 /* Bit fields for CMU LFAPRESC0 */
Kojto 98:8ab26030e058 1408 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1409 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1410 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
Kojto 98:8ab26030e058 1411 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
Kojto 98:8ab26030e058 1412 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1413 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1414 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1415 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1416 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1417 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1418 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1419 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1420 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
Kojto 98:8ab26030e058 1421 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
Kojto 98:8ab26030e058 1422 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1423 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1424 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1425 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1426 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1427 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1428 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1429 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1430 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1431 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1432 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1433 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1434 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1435 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1436 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1437 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1438 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1439 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1440 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1441 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1442 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1443 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1444 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1445 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1446 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1447 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1448 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1449 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1450 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1451 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1452 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1453 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1454 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
Kojto 98:8ab26030e058 1455 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
Kojto 98:8ab26030e058 1456 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1457 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1458 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1459 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1460 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1461 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1462 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1463 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1464 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1465 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1466 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1467 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1468 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1469 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1470 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1471 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1472 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1473 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1474 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1475 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1476 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1477 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1478 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1479 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1480 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1481 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1482 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1483 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1484 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1485 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1486 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1487 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1488 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */
Kojto 98:8ab26030e058 1489 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */
Kojto 98:8ab26030e058 1490 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1491 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1492 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1493 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1494 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1495 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1496 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1497 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
Kojto 98:8ab26030e058 1498
Kojto 98:8ab26030e058 1499 /* Bit fields for CMU LFBPRESC0 */
Kojto 98:8ab26030e058 1500 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1501 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1502 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
Kojto 98:8ab26030e058 1503 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
Kojto 98:8ab26030e058 1504 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1505 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1506 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1507 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1508 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1509 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1510 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1511 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1512 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
Kojto 98:8ab26030e058 1513 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
Kojto 98:8ab26030e058 1514 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1515 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1516 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1517 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1518 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1519 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1520 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1521 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
Kojto 98:8ab26030e058 1522
Kojto 98:8ab26030e058 1523 /* Bit fields for CMU PCNTCTRL */
Kojto 98:8ab26030e058 1524 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1525 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1526 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
Kojto 98:8ab26030e058 1527 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
Kojto 98:8ab26030e058 1528 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
Kojto 98:8ab26030e058 1529 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1530 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1531 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
Kojto 98:8ab26030e058 1532 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
Kojto 98:8ab26030e058 1533 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
Kojto 98:8ab26030e058 1534 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1535 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1536 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1537 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1538 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1539 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1540 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
Kojto 98:8ab26030e058 1541 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
Kojto 98:8ab26030e058 1542 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
Kojto 98:8ab26030e058 1543 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1544 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1545 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
Kojto 98:8ab26030e058 1546 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
Kojto 98:8ab26030e058 1547 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
Kojto 98:8ab26030e058 1548 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1549 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1550 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1551 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1552 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1553 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1554 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
Kojto 98:8ab26030e058 1555 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
Kojto 98:8ab26030e058 1556 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
Kojto 98:8ab26030e058 1557 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1558 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1559 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
Kojto 98:8ab26030e058 1560 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
Kojto 98:8ab26030e058 1561 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
Kojto 98:8ab26030e058 1562 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1563 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1564 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1565 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1566 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1567 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
Kojto 98:8ab26030e058 1568
Kojto 98:8ab26030e058 1569 /* Bit fields for CMU LCDCTRL */
Kojto 98:8ab26030e058 1570 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1571 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1572 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */
Kojto 98:8ab26030e058 1573 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */
Kojto 98:8ab26030e058 1574 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1575 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1576 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */
Kojto 98:8ab26030e058 1577 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */
Kojto 98:8ab26030e058 1578 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */
Kojto 98:8ab26030e058 1579 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1580 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1581 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */
Kojto 98:8ab26030e058 1582 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */
Kojto 98:8ab26030e058 1583 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1584 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1585 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1586 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1587 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1588 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1589 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1590 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1591 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1592 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1593 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1594 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1595 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1596 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1597 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1598 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1599 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1600 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */
Kojto 98:8ab26030e058 1601
Kojto 98:8ab26030e058 1602 /* Bit fields for CMU ROUTE */
Kojto 98:8ab26030e058 1603 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
Kojto 98:8ab26030e058 1604 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
Kojto 98:8ab26030e058 1605 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
Kojto 98:8ab26030e058 1606 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
Kojto 98:8ab26030e058 1607 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
Kojto 98:8ab26030e058 1608 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1609 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1610 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
Kojto 98:8ab26030e058 1611 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
Kojto 98:8ab26030e058 1612 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
Kojto 98:8ab26030e058 1613 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1614 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1615 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
Kojto 98:8ab26030e058 1616 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
Kojto 98:8ab26030e058 1617 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
Kojto 98:8ab26030e058 1618 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1619 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
Kojto 98:8ab26030e058 1620 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
Kojto 98:8ab26030e058 1621 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
Kojto 98:8ab26030e058 1622 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
Kojto 98:8ab26030e058 1623 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
Kojto 98:8ab26030e058 1624 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
Kojto 98:8ab26030e058 1625
Kojto 98:8ab26030e058 1626 /* Bit fields for CMU LOCK */
Kojto 98:8ab26030e058 1627 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
Kojto 98:8ab26030e058 1628 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
Kojto 98:8ab26030e058 1629 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
Kojto 98:8ab26030e058 1630 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
Kojto 98:8ab26030e058 1631 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
Kojto 98:8ab26030e058 1632 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
Kojto 98:8ab26030e058 1633 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 1634 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 1635 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
Kojto 98:8ab26030e058 1636 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
Kojto 98:8ab26030e058 1637 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
Kojto 98:8ab26030e058 1638 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 1639 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
Kojto 98:8ab26030e058 1640 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
Kojto 98:8ab26030e058 1641
Kojto 98:8ab26030e058 1642 /** @} End of group EFM32LG990F256_CMU */
Kojto 98:8ab26030e058 1643
Kojto 98:8ab26030e058 1644
Kojto 98:8ab26030e058 1645
Kojto 98:8ab26030e058 1646 /**************************************************************************//**
Kojto 98:8ab26030e058 1647 * @defgroup EFM32LG990F256_UNLOCK EFM32LG990F256 Unlock Codes
Kojto 98:8ab26030e058 1648 * @{
Kojto 98:8ab26030e058 1649 *****************************************************************************/
Kojto 98:8ab26030e058 1650 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
Kojto 98:8ab26030e058 1651 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
Kojto 98:8ab26030e058 1652 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
Kojto 98:8ab26030e058 1653 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
Kojto 98:8ab26030e058 1654 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
Kojto 98:8ab26030e058 1655 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
Kojto 98:8ab26030e058 1656
Kojto 98:8ab26030e058 1657 /** @} End of group EFM32LG990F256_UNLOCK */
Kojto 98:8ab26030e058 1658
Kojto 98:8ab26030e058 1659 /** @} End of group EFM32LG990F256_BitFields */
Kojto 98:8ab26030e058 1660
Kojto 98:8ab26030e058 1661 /**************************************************************************//**
Kojto 98:8ab26030e058 1662 * @defgroup EFM32LG990F256_Alternate_Function EFM32LG990F256 Alternate Function
Kojto 98:8ab26030e058 1663 * @{
Kojto 98:8ab26030e058 1664 *****************************************************************************/
Kojto 98:8ab26030e058 1665
Kojto 98:8ab26030e058 1666 #include "efm32lg_af_ports.h"
Kojto 98:8ab26030e058 1667 #include "efm32lg_af_pins.h"
Kojto 98:8ab26030e058 1668
Kojto 98:8ab26030e058 1669 /** @} End of group EFM32LG990F256_Alternate_Function */
Kojto 98:8ab26030e058 1670
Kojto 98:8ab26030e058 1671 /**************************************************************************//**
Kojto 98:8ab26030e058 1672 * @brief Set the value of a bit field within a register.
Kojto 98:8ab26030e058 1673 *
Kojto 98:8ab26030e058 1674 * @param REG
Kojto 98:8ab26030e058 1675 * The register to update
Kojto 98:8ab26030e058 1676 * @param MASK
Kojto 98:8ab26030e058 1677 * The mask for the bit field to update
Kojto 98:8ab26030e058 1678 * @param VALUE
Kojto 98:8ab26030e058 1679 * The value to write to the bit field
Kojto 98:8ab26030e058 1680 * @param OFFSET
Kojto 98:8ab26030e058 1681 * The number of bits that the field is offset within the register.
Kojto 98:8ab26030e058 1682 * 0 (zero) means LSB.
Kojto 98:8ab26030e058 1683 *****************************************************************************/
Kojto 98:8ab26030e058 1684 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
Kojto 98:8ab26030e058 1685 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Kojto 98:8ab26030e058 1686
Kojto 98:8ab26030e058 1687 /** @} End of group EFM32LG990F256 */
Kojto 98:8ab26030e058 1688
Kojto 98:8ab26030e058 1689 /** @} End of group Parts */
Kojto 98:8ab26030e058 1690
Kojto 98:8ab26030e058 1691 #ifdef __cplusplus
Kojto 98:8ab26030e058 1692 }
Kojto 98:8ab26030e058 1693 #endif
Kojto 98:8ab26030e058 1694 #endif /* __EFM32LG990F256_H */