Meindert Kuipers / Mbed 2 deprecated MMEx_Challenge

MMEx with SPI Slave to allow legacy devices to communicate with modern media such as USB, SD cards, the internet and all of the mbed\'s other interfaces

Dependencies:   NetServices MSCUsbHost mbed TMP102 SDFileSystem

lpc17xx_ssp.h@0:67a55a82ce06, 2011-02-27 (annotated)

Committer:
DeMein
Date:
Sun Feb 27 18:54:40 2011 +0000
Revision:
0:67a55a82ce06
Version as submitted to the NXP Design Challenge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DeMein 0:67a55a82ce06 1 /* MMEx for MBED - LPC17xx SSP Interface definitions
DeMein 0:67a55a82ce06 2 * Copyright (c) 2011 MK
DeMein 0:67a55a82ce06 3 *
DeMein 0:67a55a82ce06 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
DeMein 0:67a55a82ce06 5 * of this software and associated documentation files (the "Software"), to deal
DeMein 0:67a55a82ce06 6 * in the Software without restriction, including without limitation the rights
DeMein 0:67a55a82ce06 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
DeMein 0:67a55a82ce06 8 * copies of the Software, and to permit persons to whom the Software is
DeMein 0:67a55a82ce06 9 * furnished to do so, subject to the following conditions:
DeMein 0:67a55a82ce06 10 *
DeMein 0:67a55a82ce06 11 * The above copyright notice and this permission notice shall be included in
DeMein 0:67a55a82ce06 12 * all copies or substantial portions of the Software.
DeMein 0:67a55a82ce06 13 *
DeMein 0:67a55a82ce06 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
DeMein 0:67a55a82ce06 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
DeMein 0:67a55a82ce06 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
DeMein 0:67a55a82ce06 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
DeMein 0:67a55a82ce06 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
DeMein 0:67a55a82ce06 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
DeMein 0:67a55a82ce06 20 * THE SOFTWARE.
DeMein 0:67a55a82ce06 21 *
DeMein 0:67a55a82ce06 22 * This file is slightly modified from the original NXP source
DeMein 0:67a55a82ce06 23 */
DeMein 0:67a55a82ce06 24
DeMein 0:67a55a82ce06 25 /**
DeMein 0:67a55a82ce06 26 \file lpc17xx_ssp.h
DeMein 0:67a55a82ce06 27 \brief LPC17xx SSP Interface definitions
DeMein 0:67a55a82ce06 28 */
DeMein 0:67a55a82ce06 29
DeMein 0:67a55a82ce06 30
DeMein 0:67a55a82ce06 31 /* Peripheral group ----------------------------------------------------------- */
DeMein 0:67a55a82ce06 32 #ifndef LPC17XX_SSP_H_
DeMein 0:67a55a82ce06 33 #define LPC17XX_SSP_H_
DeMein 0:67a55a82ce06 34
DeMein 0:67a55a82ce06 35 #include "mbed.h"
DeMein 0:67a55a82ce06 36
DeMein 0:67a55a82ce06 37 /*********************************************************************//**
DeMein 0:67a55a82ce06 38 * Macro defines for CR0 register
DeMein 0:67a55a82ce06 39 **********************************************************************/
DeMein 0:67a55a82ce06 40
DeMein 0:67a55a82ce06 41 /** SSP data size select, must be 4 bits to 16 bits */
DeMein 0:67a55a82ce06 42 #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
DeMein 0:67a55a82ce06 43 /** SSP control 0 Motorola SPI mode */
DeMein 0:67a55a82ce06 44 #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
DeMein 0:67a55a82ce06 45 /** SSP control 0 TI synchronous serial mode */
DeMein 0:67a55a82ce06 46 #define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
DeMein 0:67a55a82ce06 47 /** SSP control 0 National Micro-wire mode */
DeMein 0:67a55a82ce06 48 #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
DeMein 0:67a55a82ce06 49 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
DeMein 0:67a55a82ce06 50 bus clock high between frames, (0) = low */
DeMein 0:67a55a82ce06 51 #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
DeMein 0:67a55a82ce06 52 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
DeMein 0:67a55a82ce06 53 on the second clock transition of the frame, (0) = first */
DeMein 0:67a55a82ce06 54 #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
DeMein 0:67a55a82ce06 55 /** SSP serial clock rate value load macro, divider rate is
DeMein 0:67a55a82ce06 56 PERIPH_CLK / (cpsr * (SCR + 1)) */
DeMein 0:67a55a82ce06 57 #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
DeMein 0:67a55a82ce06 58 /** SSP CR0 bit mask */
DeMein 0:67a55a82ce06 59 #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
DeMein 0:67a55a82ce06 60
DeMein 0:67a55a82ce06 61
DeMein 0:67a55a82ce06 62 /*********************************************************************//**
DeMein 0:67a55a82ce06 63 * Macro defines for CR1 register
DeMein 0:67a55a82ce06 64 **********************************************************************/
DeMein 0:67a55a82ce06 65 /** SSP control 1 loopback mode enable bit */
DeMein 0:67a55a82ce06 66 #define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 67 /** SSP control 1 enable bit */
DeMein 0:67a55a82ce06 68 #define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 69 /** SSP control 1 slave enable */
DeMein 0:67a55a82ce06 70 #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
DeMein 0:67a55a82ce06 71 /** SSP control 1 slave out disable bit, disables transmit line in slave
DeMein 0:67a55a82ce06 72 mode */
DeMein 0:67a55a82ce06 73 #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
DeMein 0:67a55a82ce06 74 /** SSP CR1 bit mask */
DeMein 0:67a55a82ce06 75 #define SSP_CR1_BITMASK ((uint32_t)(0x0F))
DeMein 0:67a55a82ce06 76
DeMein 0:67a55a82ce06 77
DeMein 0:67a55a82ce06 78 /*********************************************************************//**
DeMein 0:67a55a82ce06 79 * Macro defines for DR register
DeMein 0:67a55a82ce06 80 **********************************************************************/
DeMein 0:67a55a82ce06 81 /** SSP data bit mask */
DeMein 0:67a55a82ce06 82 #define SSP_DR_BITMASK(n) ((n)&0xFFFF)
DeMein 0:67a55a82ce06 83
DeMein 0:67a55a82ce06 84 /*********************************************************************//**
DeMein 0:67a55a82ce06 85 * Macro defines for SR register
DeMein 0:67a55a82ce06 86 **********************************************************************/
DeMein 0:67a55a82ce06 87 /** SSP status TX FIFO Empty bit */
DeMein 0:67a55a82ce06 88 #define SSP_SR_TFE ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 89 /** SSP status TX FIFO not full bit */
DeMein 0:67a55a82ce06 90 #define SSP_SR_TNF ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 91 /** SSP status RX FIFO not empty bit */
DeMein 0:67a55a82ce06 92 #define SSP_SR_RNE ((uint32_t)(1<<2))
DeMein 0:67a55a82ce06 93 /** SSP status RX FIFO full bit */
DeMein 0:67a55a82ce06 94 #define SSP_SR_RFF ((uint32_t)(1<<3))
DeMein 0:67a55a82ce06 95 /** SSP status SSP Busy bit */
DeMein 0:67a55a82ce06 96 #define SSP_SR_BSY ((uint32_t)(1<<4))
DeMein 0:67a55a82ce06 97 /** SSP SR bit mask */
DeMein 0:67a55a82ce06 98 #define SSP_SR_BITMASK ((uint32_t)(0x1F))
DeMein 0:67a55a82ce06 99
DeMein 0:67a55a82ce06 100
DeMein 0:67a55a82ce06 101 /*********************************************************************//**
DeMein 0:67a55a82ce06 102 * Macro defines for CPSR register
DeMein 0:67a55a82ce06 103 **********************************************************************/
DeMein 0:67a55a82ce06 104 /** SSP clock prescaler */
DeMein 0:67a55a82ce06 105 #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
DeMein 0:67a55a82ce06 106 /** SSP CPSR bit mask */
DeMein 0:67a55a82ce06 107 #define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
DeMein 0:67a55a82ce06 108
DeMein 0:67a55a82ce06 109
DeMein 0:67a55a82ce06 110 /*********************************************************************//**
DeMein 0:67a55a82ce06 111 * Macro define for (IMSC) Interrupt Mask Set/Clear registers
DeMein 0:67a55a82ce06 112 **********************************************************************/
DeMein 0:67a55a82ce06 113 /** Receive Overrun */
DeMein 0:67a55a82ce06 114 #define SSP_IMSC_ROR ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 115 /** Receive TimeOut */
DeMein 0:67a55a82ce06 116 #define SSP_IMSC_RT ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 117 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 118 #define SSP_IMSC_RX ((uint32_t)(1<<2))
DeMein 0:67a55a82ce06 119 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 120 #define SSP_IMSC_TX ((uint32_t)(1<<3))
DeMein 0:67a55a82ce06 121 /** IMSC bit mask */
DeMein 0:67a55a82ce06 122 #define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
DeMein 0:67a55a82ce06 123
DeMein 0:67a55a82ce06 124 /*********************************************************************//**
DeMein 0:67a55a82ce06 125 * Macro define for (RIS) Raw Interrupt Status registers
DeMein 0:67a55a82ce06 126 **********************************************************************/
DeMein 0:67a55a82ce06 127 /** Receive Overrun */
DeMein 0:67a55a82ce06 128 #define SSP_RIS_ROR ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 129 /** Receive TimeOut */
DeMein 0:67a55a82ce06 130 #define SSP_RIS_RT ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 131 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 132 #define SSP_RIS_RX ((uint32_t)(1<<2))
DeMein 0:67a55a82ce06 133 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 134 #define SSP_RIS_TX ((uint32_t)(1<<3))
DeMein 0:67a55a82ce06 135 /** RIS bit mask */
DeMein 0:67a55a82ce06 136 #define SSP_RIS_BITMASK ((uint32_t)(0x0F))
DeMein 0:67a55a82ce06 137
DeMein 0:67a55a82ce06 138
DeMein 0:67a55a82ce06 139 /*********************************************************************//**
DeMein 0:67a55a82ce06 140 * Macro define for (MIS) Masked Interrupt Status registers
DeMein 0:67a55a82ce06 141 **********************************************************************/
DeMein 0:67a55a82ce06 142 /** Receive Overrun */
DeMein 0:67a55a82ce06 143 #define SSP_MIS_ROR ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 144 /** Receive TimeOut */
DeMein 0:67a55a82ce06 145 #define SSP_MIS_RT ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 146 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 147 #define SSP_MIS_RX ((uint32_t)(1<<2))
DeMein 0:67a55a82ce06 148 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 149 #define SSP_MIS_TX ((uint32_t)(1<<3))
DeMein 0:67a55a82ce06 150 /** MIS bit mask */
DeMein 0:67a55a82ce06 151 #define SSP_MIS_BITMASK ((uint32_t)(0x0F))
DeMein 0:67a55a82ce06 152
DeMein 0:67a55a82ce06 153
DeMein 0:67a55a82ce06 154 /*********************************************************************//**
DeMein 0:67a55a82ce06 155 * Macro define for (ICR) Interrupt Clear registers
DeMein 0:67a55a82ce06 156 **********************************************************************/
DeMein 0:67a55a82ce06 157 /** Writing a 1 to this bit clears the "frame was received when
DeMein 0:67a55a82ce06 158 * RxFIFO was full" interrupt */
DeMein 0:67a55a82ce06 159 #define SSP_ICR_ROR ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 160 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
DeMein 0:67a55a82ce06 161 * has not been read for a timeout period" interrupt */
DeMein 0:67a55a82ce06 162 #define SSP_ICR_RT ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 163 /** ICR bit mask */
DeMein 0:67a55a82ce06 164 #define SSP_ICR_BITMASK ((uint32_t)(0x03))
DeMein 0:67a55a82ce06 165
DeMein 0:67a55a82ce06 166
DeMein 0:67a55a82ce06 167 /*********************************************************************//**
DeMein 0:67a55a82ce06 168 * Macro defines for DMACR register
DeMein 0:67a55a82ce06 169 **********************************************************************/
DeMein 0:67a55a82ce06 170 /** SSP bit for enabling RX DMA */
DeMein 0:67a55a82ce06 171 #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
DeMein 0:67a55a82ce06 172 /** SSP bit for enabling TX DMA */
DeMein 0:67a55a82ce06 173 #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
DeMein 0:67a55a82ce06 174 /** DMACR bit mask */
DeMein 0:67a55a82ce06 175 #define SSP_DMA_BITMASK ((uint32_t)(0x03))
DeMein 0:67a55a82ce06 176
DeMein 0:67a55a82ce06 177 /**
DeMein 0:67a55a82ce06 178 * @}
DeMein 0:67a55a82ce06 179 */
DeMein 0:67a55a82ce06 180
DeMein 0:67a55a82ce06 181 /**
DeMein 0:67a55a82ce06 182 * @}
DeMein 0:67a55a82ce06 183 */
DeMein 0:67a55a82ce06 184
DeMein 0:67a55a82ce06 185
DeMein 0:67a55a82ce06 186 /* Public Types --------------------------------------------------------------- */
DeMein 0:67a55a82ce06 187 /** @defgroup SSP_Public_Types
DeMein 0:67a55a82ce06 188 * @{
DeMein 0:67a55a82ce06 189 */
DeMein 0:67a55a82ce06 190
DeMein 0:67a55a82ce06 191 /** @brief SSP configuration structure */
DeMein 0:67a55a82ce06 192 typedef struct {
DeMein 0:67a55a82ce06 193 uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
DeMein 0:67a55a82ce06 194 where x is in range from 4 - 16 */
DeMein 0:67a55a82ce06 195 uint32_t CPHA; /** Clock phase, should be:
DeMein 0:67a55a82ce06 196 - SSP_CPHA_FIRST: first clock edge
DeMein 0:67a55a82ce06 197 - SSP_CPHA_SECOND: second clock edge */
DeMein 0:67a55a82ce06 198 uint32_t CPOL; /** Clock polarity, should be:
DeMein 0:67a55a82ce06 199 - SSP_CPOL_HI: high level
DeMein 0:67a55a82ce06 200 - SSP_CPOL_LO: low level */
DeMein 0:67a55a82ce06 201 uint32_t Mode; /** SSP mode, should be:
DeMein 0:67a55a82ce06 202 - SSP_MASTER_MODE: Master mode
DeMein 0:67a55a82ce06 203 - SSP_SLAVE_MODE: Slave mode */
DeMein 0:67a55a82ce06 204 uint32_t FrameFormat; /** Frame Format:
DeMein 0:67a55a82ce06 205 - SSP_FRAME_SPI: Motorola SPI frame format
DeMein 0:67a55a82ce06 206 - SSP_FRAME_TI: TI frame format
DeMein 0:67a55a82ce06 207 - SSP_FRAME_MICROWIRE: National Microwire frame format */
DeMein 0:67a55a82ce06 208 uint32_t ClockRate; /** Clock rate,in Hz */
DeMein 0:67a55a82ce06 209 } SSP_CFG_Type;
DeMein 0:67a55a82ce06 210
DeMein 0:67a55a82ce06 211 /**
DeMein 0:67a55a82ce06 212 * @brief SSP Transfer Type definitions
DeMein 0:67a55a82ce06 213 */
DeMein 0:67a55a82ce06 214 typedef enum {
DeMein 0:67a55a82ce06 215 SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
DeMein 0:67a55a82ce06 216 SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
DeMein 0:67a55a82ce06 217 } SSP_TRANSFER_Type;
DeMein 0:67a55a82ce06 218
DeMein 0:67a55a82ce06 219 /**
DeMein 0:67a55a82ce06 220 * @brief SPI Data configuration structure definitions
DeMein 0:67a55a82ce06 221 */
DeMein 0:67a55a82ce06 222 typedef struct {
DeMein 0:67a55a82ce06 223 void *tx_data; /**< Pointer to transmit data */
DeMein 0:67a55a82ce06 224 uint32_t tx_cnt; /**< Transmit counter */
DeMein 0:67a55a82ce06 225 void *rx_data; /**< Pointer to transmit data */
DeMein 0:67a55a82ce06 226 uint32_t rx_cnt; /**< Receive counter */
DeMein 0:67a55a82ce06 227 uint32_t length; /**< Length of transfer data */
DeMein 0:67a55a82ce06 228 uint32_t status; /**< Current status of SSP activity */
DeMein 0:67a55a82ce06 229 void (*callback)(void); /**< Pointer to Call back function when transmission complete
DeMein 0:67a55a82ce06 230 used in interrupt transfer mode */
DeMein 0:67a55a82ce06 231 } SSP_DATA_SETUP_Type;
DeMein 0:67a55a82ce06 232
DeMein 0:67a55a82ce06 233
DeMein 0:67a55a82ce06 234
DeMein 0:67a55a82ce06 235 /* Public Macros -------------------------------------------------------------- */
DeMein 0:67a55a82ce06 236
DeMein 0:67a55a82ce06 237
DeMein 0:67a55a82ce06 238 /** Macro to determine if it is valid SSP port number */
DeMein 0:67a55a82ce06 239 #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
DeMein 0:67a55a82ce06 240 || (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
DeMein 0:67a55a82ce06 241
DeMein 0:67a55a82ce06 242 /*********************************************************************//**
DeMein 0:67a55a82ce06 243 * SSP configuration parameter defines
DeMein 0:67a55a82ce06 244 **********************************************************************/
DeMein 0:67a55a82ce06 245 /** Clock phase control bit */
DeMein 0:67a55a82ce06 246 #define SSP_CPHA_FIRST ((uint32_t)(0))
DeMein 0:67a55a82ce06 247 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
DeMein 0:67a55a82ce06 248 #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
DeMein 0:67a55a82ce06 249
DeMein 0:67a55a82ce06 250 /** Clock polarity control bit */
DeMein 0:67a55a82ce06 251 /* There's no bug here!!!
DeMein 0:67a55a82ce06 252 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
DeMein 0:67a55a82ce06 253 * That means the active clock is in HI state.
DeMein 0:67a55a82ce06 254 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
DeMein 0:67a55a82ce06 255 * high between frames. That means the active clock is in LO state.
DeMein 0:67a55a82ce06 256 */
DeMein 0:67a55a82ce06 257 #define SSP_CPOL_HI ((uint32_t)(0))
DeMein 0:67a55a82ce06 258 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
DeMein 0:67a55a82ce06 259 #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
DeMein 0:67a55a82ce06 260
DeMein 0:67a55a82ce06 261 /** SSP master mode enable */
DeMein 0:67a55a82ce06 262 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
DeMein 0:67a55a82ce06 263 #define SSP_MASTER_MODE ((uint32_t)(0))
DeMein 0:67a55a82ce06 264 #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
DeMein 0:67a55a82ce06 265
DeMein 0:67a55a82ce06 266 /** SSP data bit number defines */
DeMein 0:67a55a82ce06 267 #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
DeMein 0:67a55a82ce06 268 #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
DeMein 0:67a55a82ce06 269 #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
DeMein 0:67a55a82ce06 270 #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
DeMein 0:67a55a82ce06 271 #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
DeMein 0:67a55a82ce06 272 #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
DeMein 0:67a55a82ce06 273 #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
DeMein 0:67a55a82ce06 274 #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
DeMein 0:67a55a82ce06 275 #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
DeMein 0:67a55a82ce06 276 #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
DeMein 0:67a55a82ce06 277 #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
DeMein 0:67a55a82ce06 278 #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
DeMein 0:67a55a82ce06 279 #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
DeMein 0:67a55a82ce06 280 #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
DeMein 0:67a55a82ce06 281 || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
DeMein 0:67a55a82ce06 282 || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
DeMein 0:67a55a82ce06 283 || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
DeMein 0:67a55a82ce06 284 || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
DeMein 0:67a55a82ce06 285 || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
DeMein 0:67a55a82ce06 286 || (n==SSP_DATABIT_15))
DeMein 0:67a55a82ce06 287
DeMein 0:67a55a82ce06 288 /** SSP Frame Format definition */
DeMein 0:67a55a82ce06 289 /** Motorola SPI mode */
DeMein 0:67a55a82ce06 290 #define SSP_FRAME_SPI SSP_CR0_FRF_SPI
DeMein 0:67a55a82ce06 291 /** TI synchronous serial mode */
DeMein 0:67a55a82ce06 292 #define SSP_FRAME_TI SSP_CR0_FRF_TI
DeMein 0:67a55a82ce06 293 /** National Micro-wire mode */
DeMein 0:67a55a82ce06 294 #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
DeMein 0:67a55a82ce06 295
DeMein 0:67a55a82ce06 296 #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
DeMein 0:67a55a82ce06 297 || (n==SSP_FRAME_MICROWIRE))
DeMein 0:67a55a82ce06 298
DeMein 0:67a55a82ce06 299
DeMein 0:67a55a82ce06 300 /*********************************************************************//**
DeMein 0:67a55a82ce06 301 * SSP Status defines
DeMein 0:67a55a82ce06 302 **********************************************************************/
DeMein 0:67a55a82ce06 303 /** SSP status TX FIFO Empty bit */
DeMein 0:67a55a82ce06 304 #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
DeMein 0:67a55a82ce06 305 /** SSP status TX FIFO not full bit */
DeMein 0:67a55a82ce06 306 #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
DeMein 0:67a55a82ce06 307 /** SSP status RX FIFO not empty bit */
DeMein 0:67a55a82ce06 308 #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
DeMein 0:67a55a82ce06 309 /** SSP status RX FIFO full bit */
DeMein 0:67a55a82ce06 310 #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
DeMein 0:67a55a82ce06 311 /** SSP status SSP Busy bit */
DeMein 0:67a55a82ce06 312 #define SSP_STAT_BUSY SSP_SR_BSY
DeMein 0:67a55a82ce06 313
DeMein 0:67a55a82ce06 314 #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
DeMein 0:67a55a82ce06 315 || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
DeMein 0:67a55a82ce06 316 || (n==SSP_STAT_BUSY))
DeMein 0:67a55a82ce06 317
DeMein 0:67a55a82ce06 318
DeMein 0:67a55a82ce06 319 /*********************************************************************//**
DeMein 0:67a55a82ce06 320 * SSP Interrupt Configuration defines
DeMein 0:67a55a82ce06 321 **********************************************************************/
DeMein 0:67a55a82ce06 322 /** Receive Overrun */
DeMein 0:67a55a82ce06 323 #define SSP_INTCFG_ROR SSP_IMSC_ROR
DeMein 0:67a55a82ce06 324 /** Receive TimeOut */
DeMein 0:67a55a82ce06 325 #define SSP_INTCFG_RT SSP_IMSC_RT
DeMein 0:67a55a82ce06 326 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 327 #define SSP_INTCFG_RX SSP_IMSC_RX
DeMein 0:67a55a82ce06 328 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 329 #define SSP_INTCFG_TX SSP_IMSC_TX
DeMein 0:67a55a82ce06 330
DeMein 0:67a55a82ce06 331 #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
DeMein 0:67a55a82ce06 332 || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
DeMein 0:67a55a82ce06 333
DeMein 0:67a55a82ce06 334
DeMein 0:67a55a82ce06 335 /*********************************************************************//**
DeMein 0:67a55a82ce06 336 * SSP Configured Interrupt Status defines
DeMein 0:67a55a82ce06 337 **********************************************************************/
DeMein 0:67a55a82ce06 338 /** Receive Overrun */
DeMein 0:67a55a82ce06 339 #define SSP_INTSTAT_ROR SSP_MIS_ROR
DeMein 0:67a55a82ce06 340 /** Receive TimeOut */
DeMein 0:67a55a82ce06 341 #define SSP_INTSTAT_RT SSP_MIS_RT
DeMein 0:67a55a82ce06 342 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 343 #define SSP_INTSTAT_RX SSP_MIS_RX
DeMein 0:67a55a82ce06 344 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 345 #define SSP_INTSTAT_TX SSP_MIS_TX
DeMein 0:67a55a82ce06 346
DeMein 0:67a55a82ce06 347 #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
DeMein 0:67a55a82ce06 348 || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
DeMein 0:67a55a82ce06 349
DeMein 0:67a55a82ce06 350
DeMein 0:67a55a82ce06 351 /*********************************************************************//**
DeMein 0:67a55a82ce06 352 * SSP Raw Interrupt Status defines
DeMein 0:67a55a82ce06 353 **********************************************************************/
DeMein 0:67a55a82ce06 354 /** Receive Overrun */
DeMein 0:67a55a82ce06 355 #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
DeMein 0:67a55a82ce06 356 /** Receive TimeOut */
DeMein 0:67a55a82ce06 357 #define SSP_INTSTAT_RAW_RT SSP_RIS_RT
DeMein 0:67a55a82ce06 358 /** Rx FIFO is at least half full */
DeMein 0:67a55a82ce06 359 #define SSP_INTSTAT_RAW_RX SSP_RIS_RX
DeMein 0:67a55a82ce06 360 /** Tx FIFO is at least half empty */
DeMein 0:67a55a82ce06 361 #define SSP_INTSTAT_RAW_TX SSP_RIS_TX
DeMein 0:67a55a82ce06 362
DeMein 0:67a55a82ce06 363 #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
DeMein 0:67a55a82ce06 364 || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
DeMein 0:67a55a82ce06 365
DeMein 0:67a55a82ce06 366
DeMein 0:67a55a82ce06 367 /*********************************************************************//**
DeMein 0:67a55a82ce06 368 * SSP Interrupt Clear defines
DeMein 0:67a55a82ce06 369 **********************************************************************/
DeMein 0:67a55a82ce06 370 /** Writing a 1 to this bit clears the "frame was received when
DeMein 0:67a55a82ce06 371 * RxFIFO was full" interrupt */
DeMein 0:67a55a82ce06 372 #define SSP_INTCLR_ROR SSP_ICR_ROR
DeMein 0:67a55a82ce06 373 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
DeMein 0:67a55a82ce06 374 * has not been read for a timeout period" interrupt */
DeMein 0:67a55a82ce06 375 #define SSP_INTCLR_RT SSP_ICR_RT
DeMein 0:67a55a82ce06 376
DeMein 0:67a55a82ce06 377 #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
DeMein 0:67a55a82ce06 378
DeMein 0:67a55a82ce06 379
DeMein 0:67a55a82ce06 380 /*********************************************************************//**
DeMein 0:67a55a82ce06 381 * SSP DMA defines
DeMein 0:67a55a82ce06 382 **********************************************************************/
DeMein 0:67a55a82ce06 383 /** SSP bit for enabling RX DMA */
DeMein 0:67a55a82ce06 384 #define SSP_DMA_TX SSP_DMA_RXDMA_EN
DeMein 0:67a55a82ce06 385 /** SSP bit for enabling TX DMA */
DeMein 0:67a55a82ce06 386 #define SSP_DMA_RX SSP_DMA_TXDMA_EN
DeMein 0:67a55a82ce06 387
DeMein 0:67a55a82ce06 388 #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
DeMein 0:67a55a82ce06 389
DeMein 0:67a55a82ce06 390 /* SSP Status Implementation definitions */
DeMein 0:67a55a82ce06 391 #define SSP_STAT_DONE (1UL<<8) /**< Done */
DeMein 0:67a55a82ce06 392 #define SSP_STAT_ERROR (1UL<<9) /**< Error */
DeMein 0:67a55a82ce06 393
DeMein 0:67a55a82ce06 394 #endif /* LPC17XX_SSP_H_ */
DeMein 0:67a55a82ce06 395
DeMein 0:67a55a82ce06 396 /* --------------------------------- End Of File ------------------------------ */