Stuart Northfield
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Diff: targets/cmsis/TARGET_STM/TARGET_STM32F407VG/system_stm32f4xx.c
- Revision:
- 384:ef87175507f1
- Parent:
- 383:0564d9840d0d
- Child:
- 385:be64abf45658
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F407VG/system_stm32f4xx.c Mon Nov 03 11:00:07 2014 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,704 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V2.1.0RC2
- * @date 14-May-2014
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * This file configures the system clock as follows:
- *-----------------------------------------------------------------------------
- * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
- * | (external 8 MHz clock) | (internal 16 MHz)
- * | 2- PLL_HSE_XTAL |
- * | (external 8 MHz xtal) |
- *-----------------------------------------------------------------------------
- * SYSCLK(MHz) | 168 | 168
- *-----------------------------------------------------------------------------
- * AHBCLK (MHz) | 168 | 168
- *-----------------------------------------------------------------------------
- * APB1CLK (MHz) | 42 | 42
- *-----------------------------------------------------------------------------
- * APB2CLK (MHz) | 84 | 84
- *-----------------------------------------------------------------------------
- * USB capable (48 MHz precise clock) | YES | NO
- *-----------------------------------------------------------------------------
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f4xx.h"
-#include "hal_tick.h"
-
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
- on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* #define DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
- * @{
- */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
- uint32_t SystemCoreClock = 168000000; /* [CHANGED FOR MBED] */
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and External memory
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
- /* Configure the Cube driver */
- SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
- SystemCoreClockUpdate();
-
- /* Reset the timer to avoid issues after the RAM initialization */
- TIM_MST_RESET_ON;
- TIM_MST_RESET_OFF;
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
- * depends on the application requirements), user has to ensure that HSE_VALUE
- * is same as the real frequency of the crystal used. Otherwise, this function
- * may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external memories (SRAM/SDRAM)
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-#if defined (DATA_IN_ExtSDRAM)
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register uint32_t index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
- clock */
- RCC->AHB1ENR |= 0x000001F8;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xA02A000A;
- /* Configure PDx pins speed to 50 MHz */
- GPIOD->OSPEEDR = 0xA02A000A;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA800A;
- /* Configure PEx pins speed to 50 MHz */
- GPIOE->OSPEEDR = 0xAAAA800A;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0xCCCCCCCC;
- GPIOF->AFR[1] = 0xCCCCCCCC;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0xCCCCCCCC;
- GPIOG->AFR[1] = 0xCCCCCCCC;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xAAAAAAAA;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0xAAAAAAAA;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x00C0CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA08A0;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAA08A0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
- /* Configure and enable SDRAM bank1 */
- FMC_Bank5_6->SDCR[0] = 0x000019E0;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x00000073;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif /* DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-#if defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR |= 0x00000078;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CCC0CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAA0A8A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0FCF;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA828A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCC0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA000AAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFF000FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0x000000C0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00085AAA;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000CAFFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*-- FMC/FSMC Configuration --------------------------------------------------*/
- /* Enable the FMC/FSMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[2] = 0x00001011;
- FMC_Bank1->BTCR[3] = 0x00000201;
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001011;
- FSMC_Bank1->BTCR[3] = 0x00000201;
- FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-void SetSysClock(void)
-{
- /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
- if (SetSysClock_PLL_HSE(1) == 0)
-#endif
- {
- /* 2- If fail try to start with HSE and external xtal */
- #if USE_PLL_HSE_XTAL != 0
- if (SetSysClock_PLL_HSE(0) == 0)
- #endif
- {
- /* 3- If fail start with HSI clock */
- if (SetSysClock_PLL_HSI() == 0)
- {
- while(1)
- {
- // [TODO] Put something here to tell the user that a problem occured...
- }
- }
- }
- }
-
- /* Output clock on MCO2 pin(PC9) for debugging purpose */
- //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
- regarding system frequency refer to product datasheet. */
- __PWR_CLK_ENABLE();
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-
- /* Enable HSE oscillator and activate PLL with HSE as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- if (bypass == 0)
- {
- RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
- }
- else
- {
- RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
- }
-RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
- RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
- RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Output clock on MCO1 pin(PA8) for debugging purpose */
- /*
- if (bypass == 0)
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
- else
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
- */
-
- return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/* PLL (clocked by HSI) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
- regarding system frequency refer to product datasheet. */
- __PWR_CLK_ENABLE();
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-
- /* Enable HSI oscillator and activate PLL with HSI as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
- RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
- RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Output clock on MCO1 pin(PA8) for debugging purpose */
- //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
- return 1; // OK
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
