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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h@394:83f921546702, 2014-11-07 (annotated)

Committer:
mbed_official
Date:
Fri Nov 07 15:45:07 2014 +0000
Revision:
394:83f921546702
Parent:
targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l152xe.h@354:e67efb2aab0e 
Synchronized with git revision aab52cb7ec5a665869e507dd988bbfd55b7e087e



Full URL: https://github.com/mbedmicro/mbed/commit/aab52cb7ec5a665869e507dd988bbfd55b7e087e/



Tests: Fix cpputest testrunner

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UserRevisionLine numberNew contents of line
mbed_official 354:e67efb2aab0e 1 /**
mbed_official 354:e67efb2aab0e 2 ******************************************************************************
mbed_official 354:e67efb2aab0e 3 * @file stm32l152xe.h
mbed_official 354:e67efb2aab0e 4 * @author MCD Application Team
mbed_official 354:e67efb2aab0e 5 * @version V2.0.0
mbed_official 354:e67efb2aab0e 6 * @date 5-September-2014
mbed_official 354:e67efb2aab0e 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
mbed_official 354:e67efb2aab0e 8 * This file contains all the peripheral register's definitions, bits
mbed_official 354:e67efb2aab0e 9 * definitions and memory mapping for STM32L1xx devices.
mbed_official 354:e67efb2aab0e 10 *
mbed_official 354:e67efb2aab0e 11 * This file contains:
mbed_official 354:e67efb2aab0e 12 * - Data structures and the address mapping for all peripherals
mbed_official 354:e67efb2aab0e 13 * - Peripheral's registers declarations and bits definition
mbed_official 354:e67efb2aab0e 14 * - Macros to access peripheral’s registers hardware
mbed_official 354:e67efb2aab0e 15 *
mbed_official 354:e67efb2aab0e 16 ******************************************************************************
mbed_official 354:e67efb2aab0e 17 * @attention
mbed_official 354:e67efb2aab0e 18 *
mbed_official 354:e67efb2aab0e 19 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 354:e67efb2aab0e 20 *
mbed_official 354:e67efb2aab0e 21 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 354:e67efb2aab0e 22 * are permitted provided that the following conditions are met:
mbed_official 354:e67efb2aab0e 23 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 354:e67efb2aab0e 24 * this list of conditions and the following disclaimer.
mbed_official 354:e67efb2aab0e 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 354:e67efb2aab0e 26 * this list of conditions and the following disclaimer in the documentation
mbed_official 354:e67efb2aab0e 27 * and/or other materials provided with the distribution.
mbed_official 354:e67efb2aab0e 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 354:e67efb2aab0e 29 * may be used to endorse or promote products derived from this software
mbed_official 354:e67efb2aab0e 30 * without specific prior written permission.
mbed_official 354:e67efb2aab0e 31 *
mbed_official 354:e67efb2aab0e 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 354:e67efb2aab0e 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 354:e67efb2aab0e 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 354:e67efb2aab0e 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 354:e67efb2aab0e 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 354:e67efb2aab0e 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 354:e67efb2aab0e 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 354:e67efb2aab0e 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 354:e67efb2aab0e 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 354:e67efb2aab0e 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 354:e67efb2aab0e 42 *
mbed_official 354:e67efb2aab0e 43 ******************************************************************************
mbed_official 354:e67efb2aab0e 44 */
mbed_official 354:e67efb2aab0e 45
mbed_official 354:e67efb2aab0e 46 /** @addtogroup CMSIS
mbed_official 354:e67efb2aab0e 47 * @{
mbed_official 354:e67efb2aab0e 48 */
mbed_official 354:e67efb2aab0e 49
mbed_official 354:e67efb2aab0e 50 /** @addtogroup stm32l152xe
mbed_official 354:e67efb2aab0e 51 * @{
mbed_official 354:e67efb2aab0e 52 */
mbed_official 354:e67efb2aab0e 53
mbed_official 354:e67efb2aab0e 54 #ifndef __STM32L152xE_H
mbed_official 354:e67efb2aab0e 55 #define __STM32L152xE_H
mbed_official 354:e67efb2aab0e 56
mbed_official 354:e67efb2aab0e 57 #ifdef __cplusplus
mbed_official 354:e67efb2aab0e 58 extern "C" {
mbed_official 354:e67efb2aab0e 59 #endif
mbed_official 354:e67efb2aab0e 60
mbed_official 354:e67efb2aab0e 61
mbed_official 354:e67efb2aab0e 62 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 354:e67efb2aab0e 63 * @{
mbed_official 354:e67efb2aab0e 64 */
mbed_official 354:e67efb2aab0e 65 /**
mbed_official 354:e67efb2aab0e 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
mbed_official 354:e67efb2aab0e 67 */
mbed_official 354:e67efb2aab0e 68 #define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
mbed_official 354:e67efb2aab0e 69 #define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */
mbed_official 354:e67efb2aab0e 70 #define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */
mbed_official 354:e67efb2aab0e 71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 354:e67efb2aab0e 72
mbed_official 354:e67efb2aab0e 73 /**
mbed_official 354:e67efb2aab0e 74 * @}
mbed_official 354:e67efb2aab0e 75 */
mbed_official 354:e67efb2aab0e 76
mbed_official 354:e67efb2aab0e 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 354:e67efb2aab0e 78 * @{
mbed_official 354:e67efb2aab0e 79 */
mbed_official 354:e67efb2aab0e 80
mbed_official 354:e67efb2aab0e 81 /**
mbed_official 354:e67efb2aab0e 82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
mbed_official 354:e67efb2aab0e 83 * in @ref Library_configuration_section
mbed_official 354:e67efb2aab0e 84 */
mbed_official 354:e67efb2aab0e 85
mbed_official 354:e67efb2aab0e 86 /*!< Interrupt Number Definition */
mbed_official 354:e67efb2aab0e 87 typedef enum
mbed_official 354:e67efb2aab0e 88 {
mbed_official 354:e67efb2aab0e 89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
mbed_official 354:e67efb2aab0e 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 354:e67efb2aab0e 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
mbed_official 354:e67efb2aab0e 92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
mbed_official 354:e67efb2aab0e 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
mbed_official 354:e67efb2aab0e 94 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
mbed_official 354:e67efb2aab0e 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
mbed_official 354:e67efb2aab0e 96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
mbed_official 354:e67efb2aab0e 97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
mbed_official 354:e67efb2aab0e 98
mbed_official 354:e67efb2aab0e 99 /****** STM32L specific Interrupt Numbers ***********************************************************/
mbed_official 354:e67efb2aab0e 100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 354:e67efb2aab0e 101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 354:e67efb2aab0e 102 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 354:e67efb2aab0e 103 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
mbed_official 354:e67efb2aab0e 104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 354:e67efb2aab0e 105 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 354:e67efb2aab0e 106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 354:e67efb2aab0e 107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 354:e67efb2aab0e 108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 354:e67efb2aab0e 109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 354:e67efb2aab0e 110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 354:e67efb2aab0e 111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
mbed_official 354:e67efb2aab0e 112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
mbed_official 354:e67efb2aab0e 113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
mbed_official 354:e67efb2aab0e 114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
mbed_official 354:e67efb2aab0e 115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
mbed_official 354:e67efb2aab0e 116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
mbed_official 354:e67efb2aab0e 117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
mbed_official 354:e67efb2aab0e 118 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
mbed_official 354:e67efb2aab0e 119 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
mbed_official 354:e67efb2aab0e 120 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
mbed_official 354:e67efb2aab0e 121 DAC_IRQn = 21, /*!< DAC Interrupt */
mbed_official 354:e67efb2aab0e 122 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
mbed_official 354:e67efb2aab0e 123 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 354:e67efb2aab0e 124 LCD_IRQn = 24, /*!< LCD Interrupt */
mbed_official 354:e67efb2aab0e 125 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
mbed_official 354:e67efb2aab0e 126 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
mbed_official 354:e67efb2aab0e 127 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
mbed_official 354:e67efb2aab0e 128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 354:e67efb2aab0e 129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 354:e67efb2aab0e 130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 354:e67efb2aab0e 131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 354:e67efb2aab0e 132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 354:e67efb2aab0e 133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 354:e67efb2aab0e 134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 354:e67efb2aab0e 135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 354:e67efb2aab0e 136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 354:e67efb2aab0e 137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 354:e67efb2aab0e 138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 354:e67efb2aab0e 139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 354:e67efb2aab0e 140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 354:e67efb2aab0e 141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
mbed_official 354:e67efb2aab0e 142 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
mbed_official 354:e67efb2aab0e 143 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
mbed_official 354:e67efb2aab0e 144 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
mbed_official 354:e67efb2aab0e 145 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
mbed_official 354:e67efb2aab0e 146 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
mbed_official 354:e67efb2aab0e 147 UART4_IRQn = 48, /*!< UART4 global Interrupt */
mbed_official 354:e67efb2aab0e 148 UART5_IRQn = 49, /*!< UART5 global Interrupt */
mbed_official 354:e67efb2aab0e 149 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 354:e67efb2aab0e 150 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 354:e67efb2aab0e 151 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 354:e67efb2aab0e 152 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 354:e67efb2aab0e 153 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 354:e67efb2aab0e 154 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
mbed_official 354:e67efb2aab0e 155 } IRQn_Type;
mbed_official 354:e67efb2aab0e 156
mbed_official 354:e67efb2aab0e 157 /**
mbed_official 354:e67efb2aab0e 158 * @}
mbed_official 354:e67efb2aab0e 159 */
mbed_official 354:e67efb2aab0e 160
mbed_official 354:e67efb2aab0e 161 #include "core_cm3.h"
mbed_official 354:e67efb2aab0e 162 #include "system_stm32l1xx.h"
mbed_official 354:e67efb2aab0e 163 #include <stdint.h>
mbed_official 354:e67efb2aab0e 164
mbed_official 354:e67efb2aab0e 165 /** @addtogroup Peripheral_registers_structures
mbed_official 354:e67efb2aab0e 166 * @{
mbed_official 354:e67efb2aab0e 167 */
mbed_official 354:e67efb2aab0e 168
mbed_official 354:e67efb2aab0e 169 /**
mbed_official 354:e67efb2aab0e 170 * @brief Analog to Digital Converter
mbed_official 354:e67efb2aab0e 171 */
mbed_official 354:e67efb2aab0e 172
mbed_official 354:e67efb2aab0e 173 typedef struct
mbed_official 354:e67efb2aab0e 174 {
mbed_official 354:e67efb2aab0e 175 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 177 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 178 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 179 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 180 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 181 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 182 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 183 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 184 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 185 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 186 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 187 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 354:e67efb2aab0e 188 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 189 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 354:e67efb2aab0e 190 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 354:e67efb2aab0e 191 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
mbed_official 354:e67efb2aab0e 192 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
mbed_official 354:e67efb2aab0e 193 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
mbed_official 354:e67efb2aab0e 194 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
mbed_official 354:e67efb2aab0e 195 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
mbed_official 354:e67efb2aab0e 196 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
mbed_official 354:e67efb2aab0e 197 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
mbed_official 354:e67efb2aab0e 198 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
mbed_official 354:e67efb2aab0e 199 } ADC_TypeDef;
mbed_official 354:e67efb2aab0e 200
mbed_official 354:e67efb2aab0e 201 typedef struct
mbed_official 354:e67efb2aab0e 202 {
mbed_official 354:e67efb2aab0e 203 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 354:e67efb2aab0e 204 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 354:e67efb2aab0e 205 } ADC_Common_TypeDef;
mbed_official 354:e67efb2aab0e 206
mbed_official 354:e67efb2aab0e 207 /**
mbed_official 354:e67efb2aab0e 208 * @brief Comparator
mbed_official 354:e67efb2aab0e 209 */
mbed_official 354:e67efb2aab0e 210
mbed_official 354:e67efb2aab0e 211 typedef struct
mbed_official 354:e67efb2aab0e 212 {
mbed_official 354:e67efb2aab0e 213 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 214 } COMP_TypeDef;
mbed_official 354:e67efb2aab0e 215
mbed_official 354:e67efb2aab0e 216 /**
mbed_official 354:e67efb2aab0e 217 * @brief CRC calculation unit
mbed_official 354:e67efb2aab0e 218 */
mbed_official 354:e67efb2aab0e 219
mbed_official 354:e67efb2aab0e 220 typedef struct
mbed_official 354:e67efb2aab0e 221 {
mbed_official 354:e67efb2aab0e 222 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 223 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 224 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 225 } CRC_TypeDef;
mbed_official 354:e67efb2aab0e 226
mbed_official 354:e67efb2aab0e 227 /**
mbed_official 354:e67efb2aab0e 228 * @brief Digital to Analog Converter
mbed_official 354:e67efb2aab0e 229 */
mbed_official 354:e67efb2aab0e 230
mbed_official 354:e67efb2aab0e 231 typedef struct
mbed_official 354:e67efb2aab0e 232 {
mbed_official 354:e67efb2aab0e 233 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 234 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 235 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 236 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 237 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 238 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 239 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 240 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 241 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 242 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 243 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 244 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 245 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 354:e67efb2aab0e 246 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 247 } DAC_TypeDef;
mbed_official 354:e67efb2aab0e 248
mbed_official 354:e67efb2aab0e 249 /**
mbed_official 354:e67efb2aab0e 250 * @brief Debug MCU
mbed_official 354:e67efb2aab0e 251 */
mbed_official 354:e67efb2aab0e 252
mbed_official 354:e67efb2aab0e 253 typedef struct
mbed_official 354:e67efb2aab0e 254 {
mbed_official 354:e67efb2aab0e 255 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 256 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 257 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 258 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 259 }DBGMCU_TypeDef;
mbed_official 354:e67efb2aab0e 260
mbed_official 354:e67efb2aab0e 261 /**
mbed_official 354:e67efb2aab0e 262 * @brief DMA Controller
mbed_official 354:e67efb2aab0e 263 */
mbed_official 354:e67efb2aab0e 264
mbed_official 354:e67efb2aab0e 265 typedef struct
mbed_official 354:e67efb2aab0e 266 {
mbed_official 354:e67efb2aab0e 267 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 354:e67efb2aab0e 268 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 354:e67efb2aab0e 269 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 354:e67efb2aab0e 270 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 354:e67efb2aab0e 271 } DMA_Channel_TypeDef;
mbed_official 354:e67efb2aab0e 272
mbed_official 354:e67efb2aab0e 273 typedef struct
mbed_official 354:e67efb2aab0e 274 {
mbed_official 354:e67efb2aab0e 275 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 276 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 277 } DMA_TypeDef;
mbed_official 354:e67efb2aab0e 278
mbed_official 354:e67efb2aab0e 279 /**
mbed_official 354:e67efb2aab0e 280 * @brief External Interrupt/Event Controller
mbed_official 354:e67efb2aab0e 281 */
mbed_official 354:e67efb2aab0e 282
mbed_official 354:e67efb2aab0e 283 typedef struct
mbed_official 354:e67efb2aab0e 284 {
mbed_official 354:e67efb2aab0e 285 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 286 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 287 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 288 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 289 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 290 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 291 } EXTI_TypeDef;
mbed_official 354:e67efb2aab0e 292
mbed_official 354:e67efb2aab0e 293 /**
mbed_official 354:e67efb2aab0e 294 * @brief FLASH Registers
mbed_official 354:e67efb2aab0e 295 */
mbed_official 354:e67efb2aab0e 296 typedef struct
mbed_official 354:e67efb2aab0e 297 {
mbed_official 354:e67efb2aab0e 298 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 299 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 300 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 301 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
mbed_official 354:e67efb2aab0e 302 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 303 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 304 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 305 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
mbed_official 354:e67efb2aab0e 306 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 307 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 308 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
mbed_official 354:e67efb2aab0e 309 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */
mbed_official 354:e67efb2aab0e 310 __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */
mbed_official 354:e67efb2aab0e 311 } FLASH_TypeDef;
mbed_official 354:e67efb2aab0e 312
mbed_official 354:e67efb2aab0e 313 /**
mbed_official 354:e67efb2aab0e 314 * @brief Option Bytes Registers
mbed_official 354:e67efb2aab0e 315 */
mbed_official 354:e67efb2aab0e 316 typedef struct
mbed_official 354:e67efb2aab0e 317 {
mbed_official 354:e67efb2aab0e 318 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 319 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 320 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 321 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 322 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 323 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 324 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 325 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 326 uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */
mbed_official 354:e67efb2aab0e 327 __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */
mbed_official 354:e67efb2aab0e 328 __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */
mbed_official 354:e67efb2aab0e 329 } OB_TypeDef;
mbed_official 354:e67efb2aab0e 330
mbed_official 354:e67efb2aab0e 331 /**
mbed_official 354:e67efb2aab0e 332 * @brief Operational Amplifier (OPAMP)
mbed_official 354:e67efb2aab0e 333 */
mbed_official 354:e67efb2aab0e 334 typedef struct
mbed_official 354:e67efb2aab0e 335 {
mbed_official 354:e67efb2aab0e 336 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 337 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 338 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 339 } OPAMP_TypeDef;
mbed_official 354:e67efb2aab0e 340
mbed_official 354:e67efb2aab0e 341 /**
mbed_official 354:e67efb2aab0e 342 * @brief General Purpose IO
mbed_official 354:e67efb2aab0e 343 */
mbed_official 354:e67efb2aab0e 344
mbed_official 354:e67efb2aab0e 345 typedef struct
mbed_official 354:e67efb2aab0e 346 {
mbed_official 354:e67efb2aab0e 347 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 348 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 349 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 350 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 351 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 352 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 353 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 354 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 355 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
mbed_official 354:e67efb2aab0e 356 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 357 } GPIO_TypeDef;
mbed_official 354:e67efb2aab0e 358
mbed_official 354:e67efb2aab0e 359 /**
mbed_official 354:e67efb2aab0e 360 * @brief SysTem Configuration
mbed_official 354:e67efb2aab0e 361 */
mbed_official 354:e67efb2aab0e 362
mbed_official 354:e67efb2aab0e 363 typedef struct
mbed_official 354:e67efb2aab0e 364 {
mbed_official 354:e67efb2aab0e 365 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 366 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 367 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 354:e67efb2aab0e 368 } SYSCFG_TypeDef;
mbed_official 354:e67efb2aab0e 369
mbed_official 354:e67efb2aab0e 370 /**
mbed_official 354:e67efb2aab0e 371 * @brief Inter-integrated Circuit Interface
mbed_official 354:e67efb2aab0e 372 */
mbed_official 354:e67efb2aab0e 373
mbed_official 354:e67efb2aab0e 374 typedef struct
mbed_official 354:e67efb2aab0e 375 {
mbed_official 354:e67efb2aab0e 376 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 377 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 378 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 379 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 380 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 381 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 382 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 383 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 384 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 385 } I2C_TypeDef;
mbed_official 354:e67efb2aab0e 386
mbed_official 354:e67efb2aab0e 387 /**
mbed_official 354:e67efb2aab0e 388 * @brief Independent WATCHDOG
mbed_official 354:e67efb2aab0e 389 */
mbed_official 354:e67efb2aab0e 390
mbed_official 354:e67efb2aab0e 391 typedef struct
mbed_official 354:e67efb2aab0e 392 {
mbed_official 354:e67efb2aab0e 393 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 394 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 395 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 396 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 397 } IWDG_TypeDef;
mbed_official 354:e67efb2aab0e 398
mbed_official 354:e67efb2aab0e 399 /**
mbed_official 354:e67efb2aab0e 400 * @brief LCD
mbed_official 354:e67efb2aab0e 401 */
mbed_official 354:e67efb2aab0e 402
mbed_official 354:e67efb2aab0e 403 typedef struct
mbed_official 354:e67efb2aab0e 404 {
mbed_official 354:e67efb2aab0e 405 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 406 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 407 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 408 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 409 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 410 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
mbed_official 354:e67efb2aab0e 411 } LCD_TypeDef;
mbed_official 354:e67efb2aab0e 412
mbed_official 354:e67efb2aab0e 413 /**
mbed_official 354:e67efb2aab0e 414 * @brief Power Control
mbed_official 354:e67efb2aab0e 415 */
mbed_official 354:e67efb2aab0e 416
mbed_official 354:e67efb2aab0e 417 typedef struct
mbed_official 354:e67efb2aab0e 418 {
mbed_official 354:e67efb2aab0e 419 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 420 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 421 } PWR_TypeDef;
mbed_official 354:e67efb2aab0e 422
mbed_official 354:e67efb2aab0e 423 /**
mbed_official 354:e67efb2aab0e 424 * @brief Reset and Clock Control
mbed_official 354:e67efb2aab0e 425 */
mbed_official 354:e67efb2aab0e 426
mbed_official 354:e67efb2aab0e 427 typedef struct
mbed_official 354:e67efb2aab0e 428 {
mbed_official 354:e67efb2aab0e 429 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 430 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 431 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 432 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 433 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 434 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 435 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 436 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 437 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 438 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 439 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 440 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 441 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
mbed_official 354:e67efb2aab0e 442 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 443 } RCC_TypeDef;
mbed_official 354:e67efb2aab0e 444
mbed_official 354:e67efb2aab0e 445 /**
mbed_official 354:e67efb2aab0e 446 * @brief Routing Interface
mbed_official 354:e67efb2aab0e 447 */
mbed_official 354:e67efb2aab0e 448
mbed_official 354:e67efb2aab0e 449 typedef struct
mbed_official 354:e67efb2aab0e 450 {
mbed_official 354:e67efb2aab0e 451 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 452 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 453 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 454 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 455 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 456 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 457 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 458 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 459 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 460 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 461 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 462 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 463 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
mbed_official 354:e67efb2aab0e 464 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 465 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
mbed_official 354:e67efb2aab0e 466 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
mbed_official 354:e67efb2aab0e 467 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
mbed_official 354:e67efb2aab0e 468 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
mbed_official 354:e67efb2aab0e 469 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
mbed_official 354:e67efb2aab0e 470 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
mbed_official 354:e67efb2aab0e 471 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
mbed_official 354:e67efb2aab0e 472 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
mbed_official 354:e67efb2aab0e 473 } RI_TypeDef;
mbed_official 354:e67efb2aab0e 474
mbed_official 354:e67efb2aab0e 475 /**
mbed_official 354:e67efb2aab0e 476 * @brief Real-Time Clock
mbed_official 354:e67efb2aab0e 477 */
mbed_official 354:e67efb2aab0e 478 typedef struct
mbed_official 354:e67efb2aab0e 479 {
mbed_official 354:e67efb2aab0e 480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 486 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 488 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 354:e67efb2aab0e 493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 354:e67efb2aab0e 495 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
mbed_official 354:e67efb2aab0e 496 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 354:e67efb2aab0e 497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 354:e67efb2aab0e 498 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 354:e67efb2aab0e 499 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 354:e67efb2aab0e 500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 354:e67efb2aab0e 501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 354:e67efb2aab0e 502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 354:e67efb2aab0e 503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 354:e67efb2aab0e 504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 354:e67efb2aab0e 505 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 354:e67efb2aab0e 506 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 354:e67efb2aab0e 507 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 354:e67efb2aab0e 508 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 354:e67efb2aab0e 509 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 354:e67efb2aab0e 510 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 354:e67efb2aab0e 511 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 354:e67efb2aab0e 512 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 354:e67efb2aab0e 513 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 354:e67efb2aab0e 514 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 354:e67efb2aab0e 515 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 354:e67efb2aab0e 516 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 354:e67efb2aab0e 517 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 354:e67efb2aab0e 518 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 354:e67efb2aab0e 519 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 354:e67efb2aab0e 520 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
mbed_official 354:e67efb2aab0e 521 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
mbed_official 354:e67efb2aab0e 522 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
mbed_official 354:e67efb2aab0e 523 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
mbed_official 354:e67efb2aab0e 524 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
mbed_official 354:e67efb2aab0e 525 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
mbed_official 354:e67efb2aab0e 526 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
mbed_official 354:e67efb2aab0e 527 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
mbed_official 354:e67efb2aab0e 528 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
mbed_official 354:e67efb2aab0e 529 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
mbed_official 354:e67efb2aab0e 530 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
mbed_official 354:e67efb2aab0e 531 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
mbed_official 354:e67efb2aab0e 532 } RTC_TypeDef;
mbed_official 354:e67efb2aab0e 533
mbed_official 354:e67efb2aab0e 534 /**
mbed_official 354:e67efb2aab0e 535 * @brief Serial Peripheral Interface
mbed_official 354:e67efb2aab0e 536 */
mbed_official 354:e67efb2aab0e 537
mbed_official 354:e67efb2aab0e 538 typedef struct
mbed_official 354:e67efb2aab0e 539 {
mbed_official 354:e67efb2aab0e 540 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 541 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 542 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 543 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 544 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 545 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 546 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 547 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 548 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 549 } SPI_TypeDef;
mbed_official 354:e67efb2aab0e 550
mbed_official 354:e67efb2aab0e 551 /**
mbed_official 354:e67efb2aab0e 552 * @brief TIM
mbed_official 354:e67efb2aab0e 553 */
mbed_official 354:e67efb2aab0e 554 typedef struct
mbed_official 354:e67efb2aab0e 555 {
mbed_official 354:e67efb2aab0e 556 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 557 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 558 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 559 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 560 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 561 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 562 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 563 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 564 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 354:e67efb2aab0e 565 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 354:e67efb2aab0e 566 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 354:e67efb2aab0e 567 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 354:e67efb2aab0e 568 uint32_t RESERVED12; /*!< Reserved, 0x30 */
mbed_official 354:e67efb2aab0e 569 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 354:e67efb2aab0e 570 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 354:e67efb2aab0e 571 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 354:e67efb2aab0e 572 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 354:e67efb2aab0e 573 uint32_t RESERVED17; /*!< Reserved, 0x44 */
mbed_official 354:e67efb2aab0e 574 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 354:e67efb2aab0e 575 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 354:e67efb2aab0e 576 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 354:e67efb2aab0e 577 } TIM_TypeDef;
mbed_official 354:e67efb2aab0e 578 /**
mbed_official 354:e67efb2aab0e 579 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 354:e67efb2aab0e 580 */
mbed_official 354:e67efb2aab0e 581
mbed_official 354:e67efb2aab0e 582 typedef struct
mbed_official 354:e67efb2aab0e 583 {
mbed_official 354:e67efb2aab0e 584 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 585 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 586 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 587 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 588 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 589 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 590 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 591 } USART_TypeDef;
mbed_official 354:e67efb2aab0e 592
mbed_official 354:e67efb2aab0e 593 /**
mbed_official 354:e67efb2aab0e 594 * @brief Universal Serial Bus Full Speed Device
mbed_official 354:e67efb2aab0e 595 */
mbed_official 354:e67efb2aab0e 596
mbed_official 354:e67efb2aab0e 597 typedef struct
mbed_official 354:e67efb2aab0e 598 {
mbed_official 354:e67efb2aab0e 599 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 600 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 354:e67efb2aab0e 601 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 602 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 354:e67efb2aab0e 603 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 604 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 354:e67efb2aab0e 605 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 354:e67efb2aab0e 606 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 354:e67efb2aab0e 607 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 354:e67efb2aab0e 608 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 354:e67efb2aab0e 609 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 354:e67efb2aab0e 610 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 354:e67efb2aab0e 611 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 354:e67efb2aab0e 612 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 354:e67efb2aab0e 613 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 354:e67efb2aab0e 614 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 354:e67efb2aab0e 615 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 354:e67efb2aab0e 616 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 354:e67efb2aab0e 617 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 354:e67efb2aab0e 618 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 354:e67efb2aab0e 619 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 354:e67efb2aab0e 620 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 354:e67efb2aab0e 621 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 354:e67efb2aab0e 622 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 354:e67efb2aab0e 623 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 354:e67efb2aab0e 624 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 354:e67efb2aab0e 625 } USB_TypeDef;
mbed_official 354:e67efb2aab0e 626
mbed_official 354:e67efb2aab0e 627 /**
mbed_official 354:e67efb2aab0e 628 * @brief Window WATCHDOG
mbed_official 354:e67efb2aab0e 629 */
mbed_official 354:e67efb2aab0e 630 typedef struct
mbed_official 354:e67efb2aab0e 631 {
mbed_official 354:e67efb2aab0e 632 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 354:e67efb2aab0e 633 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 354:e67efb2aab0e 634 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 354:e67efb2aab0e 635 } WWDG_TypeDef;
mbed_official 354:e67efb2aab0e 636
mbed_official 354:e67efb2aab0e 637 /**
mbed_official 354:e67efb2aab0e 638 * @brief Universal Serial Bus Full Speed Device
mbed_official 354:e67efb2aab0e 639 */
mbed_official 354:e67efb2aab0e 640 /**
mbed_official 354:e67efb2aab0e 641 * @}
mbed_official 354:e67efb2aab0e 642 */
mbed_official 354:e67efb2aab0e 643
mbed_official 354:e67efb2aab0e 644 /** @addtogroup Peripheral_memory_map
mbed_official 354:e67efb2aab0e 645 * @{
mbed_official 354:e67efb2aab0e 646 */
mbed_official 354:e67efb2aab0e 647
mbed_official 354:e67efb2aab0e 648 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 354:e67efb2aab0e 649 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */
mbed_official 354:e67efb2aab0e 650 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 354:e67efb2aab0e 651 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 354:e67efb2aab0e 652 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
mbed_official 354:e67efb2aab0e 653 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 354:e67efb2aab0e 654 #define FLASH_BANK2_BASE ((uint32_t)0x08040000) /*!< FLASH BANK2 base address in the alias region */
mbed_official 354:e67efb2aab0e 655 #define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH BANK1 address */
mbed_official 354:e67efb2aab0e 656 #define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /*!< Program end FLASH BANK2 address */
mbed_official 354:e67efb2aab0e 657 #define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /*!< FLASH EEPROM end address (16KB) */
mbed_official 354:e67efb2aab0e 658
mbed_official 354:e67efb2aab0e 659 /*!< Peripheral memory map */
mbed_official 354:e67efb2aab0e 660 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 354:e67efb2aab0e 661 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 354:e67efb2aab0e 662 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 354:e67efb2aab0e 663
mbed_official 354:e67efb2aab0e 664 /*!< APB1 peripherals */
mbed_official 354:e67efb2aab0e 665 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 354:e67efb2aab0e 666 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 354:e67efb2aab0e 667 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
mbed_official 354:e67efb2aab0e 668 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
mbed_official 354:e67efb2aab0e 669 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 354:e67efb2aab0e 670 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 354:e67efb2aab0e 671 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400)
mbed_official 354:e67efb2aab0e 672 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 354:e67efb2aab0e 673 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 354:e67efb2aab0e 674 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 354:e67efb2aab0e 675 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
mbed_official 354:e67efb2aab0e 676 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
mbed_official 354:e67efb2aab0e 677 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 354:e67efb2aab0e 678 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 354:e67efb2aab0e 679 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
mbed_official 354:e67efb2aab0e 680 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
mbed_official 354:e67efb2aab0e 681 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 354:e67efb2aab0e 682 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
mbed_official 354:e67efb2aab0e 683
mbed_official 354:e67efb2aab0e 684 /* USB device FS */
mbed_official 354:e67efb2aab0e 685 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 354:e67efb2aab0e 686 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 354:e67efb2aab0e 687
mbed_official 354:e67efb2aab0e 688 /* USB device FS SRAM */
mbed_official 354:e67efb2aab0e 689 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 354:e67efb2aab0e 690 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 354:e67efb2aab0e 691 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
mbed_official 354:e67efb2aab0e 692 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
mbed_official 354:e67efb2aab0e 693 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
mbed_official 354:e67efb2aab0e 694
mbed_official 354:e67efb2aab0e 695 /*!< APB2 peripherals */
mbed_official 354:e67efb2aab0e 696 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 354:e67efb2aab0e 697 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 354:e67efb2aab0e 698 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
mbed_official 354:e67efb2aab0e 699 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
mbed_official 354:e67efb2aab0e 700 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
mbed_official 354:e67efb2aab0e 701 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
mbed_official 354:e67efb2aab0e 702 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
mbed_official 354:e67efb2aab0e 703 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 354:e67efb2aab0e 704 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 354:e67efb2aab0e 705
mbed_official 354:e67efb2aab0e 706 /*!< AHB peripherals */
mbed_official 354:e67efb2aab0e 707 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 354:e67efb2aab0e 708 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
mbed_official 354:e67efb2aab0e 709 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
mbed_official 354:e67efb2aab0e 710 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
mbed_official 354:e67efb2aab0e 711 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 354:e67efb2aab0e 712 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
mbed_official 354:e67efb2aab0e 713 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800)
mbed_official 354:e67efb2aab0e 714 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00)
mbed_official 354:e67efb2aab0e 715 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 354:e67efb2aab0e 716 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
mbed_official 354:e67efb2aab0e 717 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
mbed_official 354:e67efb2aab0e 718 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
mbed_official 354:e67efb2aab0e 719 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
mbed_official 354:e67efb2aab0e 720 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 354:e67efb2aab0e 721 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 354:e67efb2aab0e 722 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 354:e67efb2aab0e 723 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 354:e67efb2aab0e 724 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 354:e67efb2aab0e 725 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 354:e67efb2aab0e 726 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 354:e67efb2aab0e 727 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
mbed_official 354:e67efb2aab0e 728 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
mbed_official 354:e67efb2aab0e 729 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
mbed_official 354:e67efb2aab0e 730 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
mbed_official 354:e67efb2aab0e 731 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
mbed_official 354:e67efb2aab0e 732 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
mbed_official 354:e67efb2aab0e 733 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 354:e67efb2aab0e 734
mbed_official 354:e67efb2aab0e 735 /**
mbed_official 354:e67efb2aab0e 736 * @}
mbed_official 354:e67efb2aab0e 737 */
mbed_official 354:e67efb2aab0e 738
mbed_official 354:e67efb2aab0e 739 /** @addtogroup Peripheral_declaration
mbed_official 354:e67efb2aab0e 740 * @{
mbed_official 354:e67efb2aab0e 741 */
mbed_official 354:e67efb2aab0e 742
mbed_official 354:e67efb2aab0e 743 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 354:e67efb2aab0e 744 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 354:e67efb2aab0e 745 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 354:e67efb2aab0e 746 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 354:e67efb2aab0e 747 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 354:e67efb2aab0e 748 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 354:e67efb2aab0e 749 #define LCD ((LCD_TypeDef *) LCD_BASE)
mbed_official 354:e67efb2aab0e 750 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 354:e67efb2aab0e 751 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 354:e67efb2aab0e 752 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 354:e67efb2aab0e 753 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 354:e67efb2aab0e 754 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 354:e67efb2aab0e 755 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 354:e67efb2aab0e 756 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 354:e67efb2aab0e 757 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 354:e67efb2aab0e 758 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 354:e67efb2aab0e 759 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 354:e67efb2aab0e 760 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 354:e67efb2aab0e 761 /* USB device FS */
mbed_official 354:e67efb2aab0e 762 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 354:e67efb2aab0e 763 /* USB device FS SRAM */
mbed_official 354:e67efb2aab0e 764 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 354:e67efb2aab0e 765 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 354:e67efb2aab0e 766 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 354:e67efb2aab0e 767 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official 354:e67efb2aab0e 768 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
mbed_official 354:e67efb2aab0e 769 #define RI ((RI_TypeDef *) RI_BASE)
mbed_official 354:e67efb2aab0e 770 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 354:e67efb2aab0e 771 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 354:e67efb2aab0e 772 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
mbed_official 354:e67efb2aab0e 773 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 354:e67efb2aab0e 774 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 354:e67efb2aab0e 775 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 354:e67efb2aab0e 776 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 354:e67efb2aab0e 777 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 354:e67efb2aab0e 778 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 354:e67efb2aab0e 779 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 354:e67efb2aab0e 780 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 354:e67efb2aab0e 781 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 354:e67efb2aab0e 782 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 354:e67efb2aab0e 783 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 354:e67efb2aab0e 784 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 354:e67efb2aab0e 785 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 354:e67efb2aab0e 786 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 354:e67efb2aab0e 787 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 354:e67efb2aab0e 788 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 354:e67efb2aab0e 789 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 354:e67efb2aab0e 790 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 354:e67efb2aab0e 791 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 354:e67efb2aab0e 792 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 354:e67efb2aab0e 793 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 354:e67efb2aab0e 794 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 354:e67efb2aab0e 795 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 354:e67efb2aab0e 796 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 354:e67efb2aab0e 797 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 354:e67efb2aab0e 798 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 354:e67efb2aab0e 799 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 354:e67efb2aab0e 800 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 354:e67efb2aab0e 801 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 354:e67efb2aab0e 802 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 354:e67efb2aab0e 803 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 354:e67efb2aab0e 804 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 354:e67efb2aab0e 805 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 354:e67efb2aab0e 806 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 354:e67efb2aab0e 807 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 354:e67efb2aab0e 808 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 354:e67efb2aab0e 809
mbed_official 354:e67efb2aab0e 810 /**
mbed_official 354:e67efb2aab0e 811 * @}
mbed_official 354:e67efb2aab0e 812 */
mbed_official 354:e67efb2aab0e 813
mbed_official 354:e67efb2aab0e 814 /** @addtogroup Exported_constants
mbed_official 354:e67efb2aab0e 815 * @{
mbed_official 354:e67efb2aab0e 816 */
mbed_official 354:e67efb2aab0e 817
mbed_official 354:e67efb2aab0e 818 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 354:e67efb2aab0e 819 * @{
mbed_official 354:e67efb2aab0e 820 */
mbed_official 354:e67efb2aab0e 821
mbed_official 354:e67efb2aab0e 822 /******************************************************************************/
mbed_official 354:e67efb2aab0e 823 /* Peripheral Registers Bits Definition */
mbed_official 354:e67efb2aab0e 824 /******************************************************************************/
mbed_official 354:e67efb2aab0e 825 /******************************************************************************/
mbed_official 354:e67efb2aab0e 826 /* */
mbed_official 354:e67efb2aab0e 827 /* Analog to Digital Converter (ADC) */
mbed_official 354:e67efb2aab0e 828 /* */
mbed_official 354:e67efb2aab0e 829 /******************************************************************************/
mbed_official 354:e67efb2aab0e 830
mbed_official 354:e67efb2aab0e 831 /******************** Bit definition for ADC_SR register ********************/
mbed_official 354:e67efb2aab0e 832 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
mbed_official 354:e67efb2aab0e 833 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
mbed_official 354:e67efb2aab0e 834 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
mbed_official 354:e67efb2aab0e 835 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
mbed_official 354:e67efb2aab0e 836 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
mbed_official 354:e67efb2aab0e 837 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
mbed_official 354:e67efb2aab0e 838 #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
mbed_official 354:e67efb2aab0e 839 #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
mbed_official 354:e67efb2aab0e 840 #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
mbed_official 354:e67efb2aab0e 841
mbed_official 354:e67efb2aab0e 842 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 354:e67efb2aab0e 843 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 354:e67efb2aab0e 844 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 845 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 846 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 847 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 848 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 849
mbed_official 354:e67efb2aab0e 850 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
mbed_official 354:e67efb2aab0e 851 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
mbed_official 354:e67efb2aab0e 852 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
mbed_official 354:e67efb2aab0e 853 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
mbed_official 354:e67efb2aab0e 854 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
mbed_official 354:e67efb2aab0e 855 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
mbed_official 354:e67efb2aab0e 856 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
mbed_official 354:e67efb2aab0e 857 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
mbed_official 354:e67efb2aab0e 858
mbed_official 354:e67efb2aab0e 859 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 354:e67efb2aab0e 860 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 861 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 862 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 863
mbed_official 354:e67efb2aab0e 864 #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
mbed_official 354:e67efb2aab0e 865 #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
mbed_official 354:e67efb2aab0e 866
mbed_official 354:e67efb2aab0e 867 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
mbed_official 354:e67efb2aab0e 868 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 354:e67efb2aab0e 869
mbed_official 354:e67efb2aab0e 870 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
mbed_official 354:e67efb2aab0e 871 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 872 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 873
mbed_official 354:e67efb2aab0e 874 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
mbed_official 354:e67efb2aab0e 875
mbed_official 354:e67efb2aab0e 876 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 354:e67efb2aab0e 877 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
mbed_official 354:e67efb2aab0e 878 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
mbed_official 354:e67efb2aab0e 879 #define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
mbed_official 354:e67efb2aab0e 880
mbed_official 354:e67efb2aab0e 881 #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
mbed_official 354:e67efb2aab0e 882 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 883 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 884 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 885
mbed_official 354:e67efb2aab0e 886 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
mbed_official 354:e67efb2aab0e 887 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
mbed_official 354:e67efb2aab0e 888 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
mbed_official 354:e67efb2aab0e 889 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
mbed_official 354:e67efb2aab0e 890
mbed_official 354:e67efb2aab0e 891 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 354:e67efb2aab0e 892 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 893 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 894 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 895 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 896
mbed_official 354:e67efb2aab0e 897 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
mbed_official 354:e67efb2aab0e 898 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 899 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 900
mbed_official 354:e67efb2aab0e 901 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
mbed_official 354:e67efb2aab0e 902
mbed_official 354:e67efb2aab0e 903 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 354:e67efb2aab0e 904 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 905 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 906 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 907 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 908
mbed_official 354:e67efb2aab0e 909 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 354:e67efb2aab0e 910 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 911 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 912
mbed_official 354:e67efb2aab0e 913 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
mbed_official 354:e67efb2aab0e 914
mbed_official 354:e67efb2aab0e 915 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 354:e67efb2aab0e 916 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
mbed_official 354:e67efb2aab0e 917 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 918 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 919 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 920
mbed_official 354:e67efb2aab0e 921 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
mbed_official 354:e67efb2aab0e 922 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 923 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 924 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 925
mbed_official 354:e67efb2aab0e 926 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
mbed_official 354:e67efb2aab0e 927 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 928 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 929 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 930
mbed_official 354:e67efb2aab0e 931 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
mbed_official 354:e67efb2aab0e 932 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 933 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 934 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 935
mbed_official 354:e67efb2aab0e 936 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
mbed_official 354:e67efb2aab0e 937 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 938 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 939 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 940
mbed_official 354:e67efb2aab0e 941 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
mbed_official 354:e67efb2aab0e 942 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 943 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 944 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 945
mbed_official 354:e67efb2aab0e 946 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
mbed_official 354:e67efb2aab0e 947 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 948 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 949 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 950
mbed_official 354:e67efb2aab0e 951 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
mbed_official 354:e67efb2aab0e 952 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 953 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 954 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 955
mbed_official 354:e67efb2aab0e 956 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
mbed_official 354:e67efb2aab0e 957 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 958 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 959 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 960
mbed_official 354:e67efb2aab0e 961 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
mbed_official 354:e67efb2aab0e 962 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 963 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 964 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 965
mbed_official 354:e67efb2aab0e 966 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 354:e67efb2aab0e 967 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 354:e67efb2aab0e 968 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 969 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 970 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 971
mbed_official 354:e67efb2aab0e 972 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 354:e67efb2aab0e 973 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 974 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 975 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 976
mbed_official 354:e67efb2aab0e 977 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 354:e67efb2aab0e 978 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 979 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 980 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 981
mbed_official 354:e67efb2aab0e 982 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 354:e67efb2aab0e 983 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 984 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 985 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 986
mbed_official 354:e67efb2aab0e 987 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 354:e67efb2aab0e 988 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 989 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 990 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 991
mbed_official 354:e67efb2aab0e 992 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
mbed_official 354:e67efb2aab0e 993 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 994 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 995 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 996
mbed_official 354:e67efb2aab0e 997 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 354:e67efb2aab0e 998 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 999 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1000 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1001
mbed_official 354:e67efb2aab0e 1002 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 354:e67efb2aab0e 1003 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1004 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1005 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1006
mbed_official 354:e67efb2aab0e 1007 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 354:e67efb2aab0e 1008 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1009 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1010 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1011
mbed_official 354:e67efb2aab0e 1012 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
mbed_official 354:e67efb2aab0e 1013 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1014 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1015 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1016
mbed_official 354:e67efb2aab0e 1017 /****************** Bit definition for ADC_SMPR3 register *******************/
mbed_official 354:e67efb2aab0e 1018 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 354:e67efb2aab0e 1019 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1020 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1021 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1022
mbed_official 354:e67efb2aab0e 1023 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 354:e67efb2aab0e 1024 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1025 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1026 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1027
mbed_official 354:e67efb2aab0e 1028 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 354:e67efb2aab0e 1029 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1030 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1031 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1032
mbed_official 354:e67efb2aab0e 1033 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 354:e67efb2aab0e 1034 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1035 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1036 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1037
mbed_official 354:e67efb2aab0e 1038 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 354:e67efb2aab0e 1039 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1040 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1041 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1042
mbed_official 354:e67efb2aab0e 1043 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 354:e67efb2aab0e 1044 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1045 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1046 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1047
mbed_official 354:e67efb2aab0e 1048 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 354:e67efb2aab0e 1049 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1050 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1051 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1052
mbed_official 354:e67efb2aab0e 1053 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 354:e67efb2aab0e 1054 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1055 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1056 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1057
mbed_official 354:e67efb2aab0e 1058 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 354:e67efb2aab0e 1059 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1060 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1061 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1062
mbed_official 354:e67efb2aab0e 1063 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 354:e67efb2aab0e 1064 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1065 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1066 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1067
mbed_official 354:e67efb2aab0e 1068 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 354:e67efb2aab0e 1069 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
mbed_official 354:e67efb2aab0e 1070
mbed_official 354:e67efb2aab0e 1071 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 354:e67efb2aab0e 1072 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
mbed_official 354:e67efb2aab0e 1073
mbed_official 354:e67efb2aab0e 1074 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 354:e67efb2aab0e 1075 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
mbed_official 354:e67efb2aab0e 1076
mbed_official 354:e67efb2aab0e 1077 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 354:e67efb2aab0e 1078 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
mbed_official 354:e67efb2aab0e 1079
mbed_official 354:e67efb2aab0e 1080 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 354:e67efb2aab0e 1081 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
mbed_official 354:e67efb2aab0e 1082
mbed_official 354:e67efb2aab0e 1083 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 354:e67efb2aab0e 1084 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 354:e67efb2aab0e 1085
mbed_official 354:e67efb2aab0e 1086 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 354:e67efb2aab0e 1087 #define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */
mbed_official 354:e67efb2aab0e 1088 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1089 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1090 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1091 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1092 #define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1093
mbed_official 354:e67efb2aab0e 1094 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1095 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1096 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1097 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1098 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1099 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1100
mbed_official 354:e67efb2aab0e 1101 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1102 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1103 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1104 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1105 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1106 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1107
mbed_official 354:e67efb2aab0e 1108 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1109 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1110 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1111 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1112 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1113 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1114
mbed_official 354:e67efb2aab0e 1115 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1116 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1117 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1118 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1119 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1120 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1121
mbed_official 354:e67efb2aab0e 1122 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 354:e67efb2aab0e 1123 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1124 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1125 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1126 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1127 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1128 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1129
mbed_official 354:e67efb2aab0e 1130 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1131 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1132 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1133 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1134 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1135 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1136
mbed_official 354:e67efb2aab0e 1137 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1138 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1139 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1140 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1141 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1142 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1143
mbed_official 354:e67efb2aab0e 1144 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1145 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1146 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1147 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1148 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1149 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1150
mbed_official 354:e67efb2aab0e 1151 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1152 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1153 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1154 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1155 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1156 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1157
mbed_official 354:e67efb2aab0e 1158 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1159 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1160 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1161 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1162 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1163 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1164
mbed_official 354:e67efb2aab0e 1165 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 354:e67efb2aab0e 1166 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1167 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1168 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1169 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1170 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1171 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1172
mbed_official 354:e67efb2aab0e 1173 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1174 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1175 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1176 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1177 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1178 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1179
mbed_official 354:e67efb2aab0e 1180 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1181 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1182 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1183 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1184 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1185 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1186
mbed_official 354:e67efb2aab0e 1187 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1188 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1189 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1190 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1191 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1192 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1193
mbed_official 354:e67efb2aab0e 1194 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1195 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1196 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1197 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1198 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1199 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1200
mbed_official 354:e67efb2aab0e 1201 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1202 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1203 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1204 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1205 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1206 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1207
mbed_official 354:e67efb2aab0e 1208 /******************* Bit definition for ADC_SQR4 register *******************/
mbed_official 354:e67efb2aab0e 1209 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1210 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1211 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1212 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1213 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1214 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1215
mbed_official 354:e67efb2aab0e 1216 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1217 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1218 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1219 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1220 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1221 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1222
mbed_official 354:e67efb2aab0e 1223 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1224 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1225 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1226 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1227 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1228 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1229
mbed_official 354:e67efb2aab0e 1230 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1231 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1232 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1233 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1234 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1235 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1236
mbed_official 354:e67efb2aab0e 1237 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1238 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1239 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1240 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1241 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1242 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1243
mbed_official 354:e67efb2aab0e 1244 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1245 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1246 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1247 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1248 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1249 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1250
mbed_official 354:e67efb2aab0e 1251 /******************* Bit definition for ADC_SQR5 register *******************/
mbed_official 354:e67efb2aab0e 1252 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1253 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1254 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1255 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1256 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1257 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1258
mbed_official 354:e67efb2aab0e 1259 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1260 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1261 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1262 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1263 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1264 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1265
mbed_official 354:e67efb2aab0e 1266 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1267 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1268 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1269 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1270 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1271 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1272
mbed_official 354:e67efb2aab0e 1273 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1274 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1275 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1276 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1277 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1278 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1279
mbed_official 354:e67efb2aab0e 1280 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1281 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1282 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1283 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1284 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1285 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1286
mbed_official 354:e67efb2aab0e 1287 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 354:e67efb2aab0e 1288 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1289 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1290 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1291 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1292 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1293
mbed_official 354:e67efb2aab0e 1294
mbed_official 354:e67efb2aab0e 1295 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 354:e67efb2aab0e 1296 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 354:e67efb2aab0e 1297 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1298 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1299 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1300 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1301 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1302
mbed_official 354:e67efb2aab0e 1303 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 354:e67efb2aab0e 1304 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1305 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1306 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1307 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1308 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1309
mbed_official 354:e67efb2aab0e 1310 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 354:e67efb2aab0e 1311 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1312 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1313 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1314 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1315 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1316
mbed_official 354:e67efb2aab0e 1317 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 354:e67efb2aab0e 1318 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1319 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1320 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1321 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1322 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1323
mbed_official 354:e67efb2aab0e 1324 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
mbed_official 354:e67efb2aab0e 1325 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1326 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1327
mbed_official 354:e67efb2aab0e 1328 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 354:e67efb2aab0e 1329 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 354:e67efb2aab0e 1330
mbed_official 354:e67efb2aab0e 1331 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 354:e67efb2aab0e 1332 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 354:e67efb2aab0e 1333
mbed_official 354:e67efb2aab0e 1334 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 354:e67efb2aab0e 1335 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 354:e67efb2aab0e 1336
mbed_official 354:e67efb2aab0e 1337 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 354:e67efb2aab0e 1338 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 354:e67efb2aab0e 1339
mbed_official 354:e67efb2aab0e 1340 /******************** Bit definition for ADC_DR register ********************/
mbed_official 354:e67efb2aab0e 1341 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 354:e67efb2aab0e 1342
mbed_official 354:e67efb2aab0e 1343 /****************** Bit definition for ADC_SMPR0 register *******************/
mbed_official 354:e67efb2aab0e 1344 #define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
mbed_official 354:e67efb2aab0e 1345 #define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1346 #define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1347 #define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1348
mbed_official 354:e67efb2aab0e 1349 #define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
mbed_official 354:e67efb2aab0e 1350 #define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1351 #define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1352 #define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1353
mbed_official 354:e67efb2aab0e 1354 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 354:e67efb2aab0e 1355 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
mbed_official 354:e67efb2aab0e 1356 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
mbed_official 354:e67efb2aab0e 1357 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
mbed_official 354:e67efb2aab0e 1358 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
mbed_official 354:e67efb2aab0e 1359 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
mbed_official 354:e67efb2aab0e 1360 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
mbed_official 354:e67efb2aab0e 1361 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
mbed_official 354:e67efb2aab0e 1362
mbed_official 354:e67efb2aab0e 1363 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 354:e67efb2aab0e 1364 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
mbed_official 354:e67efb2aab0e 1365 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1366 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1367 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
mbed_official 354:e67efb2aab0e 1368
mbed_official 354:e67efb2aab0e 1369 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1370 /* */
mbed_official 354:e67efb2aab0e 1371 /* Analog Comparators (COMP) */
mbed_official 354:e67efb2aab0e 1372 /* */
mbed_official 354:e67efb2aab0e 1373 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1374
mbed_official 354:e67efb2aab0e 1375 /****************** Bit definition for COMP_CSR register ********************/
mbed_official 354:e67efb2aab0e 1376 #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
mbed_official 354:e67efb2aab0e 1377 #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
mbed_official 354:e67efb2aab0e 1378 #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
mbed_official 354:e67efb2aab0e 1379 #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
mbed_official 354:e67efb2aab0e 1380 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
mbed_official 354:e67efb2aab0e 1381 #define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
mbed_official 354:e67efb2aab0e 1382 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
mbed_official 354:e67efb2aab0e 1383
mbed_official 354:e67efb2aab0e 1384 #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
mbed_official 354:e67efb2aab0e 1385 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
mbed_official 354:e67efb2aab0e 1386 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
mbed_official 354:e67efb2aab0e 1387 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
mbed_official 354:e67efb2aab0e 1388 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
mbed_official 354:e67efb2aab0e 1389 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1390 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1391 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1392 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
mbed_official 354:e67efb2aab0e 1393 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1394 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1395 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1396
mbed_official 354:e67efb2aab0e 1397 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
mbed_official 354:e67efb2aab0e 1398 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
mbed_official 354:e67efb2aab0e 1399 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
mbed_official 354:e67efb2aab0e 1400
mbed_official 354:e67efb2aab0e 1401 #define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
mbed_official 354:e67efb2aab0e 1402 #define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
mbed_official 354:e67efb2aab0e 1403 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
mbed_official 354:e67efb2aab0e 1404
mbed_official 354:e67efb2aab0e 1405 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1406 /* */
mbed_official 354:e67efb2aab0e 1407 /* Operational Amplifier (OPAMP) */
mbed_official 354:e67efb2aab0e 1408 /* */
mbed_official 354:e67efb2aab0e 1409 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1410 /******************* Bit definition for OPAMP_CSR register ******************/
mbed_official 354:e67efb2aab0e 1411 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
mbed_official 354:e67efb2aab0e 1412 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
mbed_official 354:e67efb2aab0e 1413 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
mbed_official 354:e67efb2aab0e 1414 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
mbed_official 354:e67efb2aab0e 1415 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
mbed_official 354:e67efb2aab0e 1416 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
mbed_official 354:e67efb2aab0e 1417 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
mbed_official 354:e67efb2aab0e 1418 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
mbed_official 354:e67efb2aab0e 1419 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
mbed_official 354:e67efb2aab0e 1420 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
mbed_official 354:e67efb2aab0e 1421 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
mbed_official 354:e67efb2aab0e 1422 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
mbed_official 354:e67efb2aab0e 1423 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
mbed_official 354:e67efb2aab0e 1424 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
mbed_official 354:e67efb2aab0e 1425 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
mbed_official 354:e67efb2aab0e 1426 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
mbed_official 354:e67efb2aab0e 1427 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
mbed_official 354:e67efb2aab0e 1428 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
mbed_official 354:e67efb2aab0e 1429 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
mbed_official 354:e67efb2aab0e 1430 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
mbed_official 354:e67efb2aab0e 1431 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
mbed_official 354:e67efb2aab0e 1432 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
mbed_official 354:e67efb2aab0e 1433
mbed_official 354:e67efb2aab0e 1434 /******************* Bit definition for OPAMP_OTR register ******************/
mbed_official 354:e67efb2aab0e 1435 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
mbed_official 354:e67efb2aab0e 1436 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
mbed_official 354:e67efb2aab0e 1437 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
mbed_official 354:e67efb2aab0e 1438 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
mbed_official 354:e67efb2aab0e 1439 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
mbed_official 354:e67efb2aab0e 1440
mbed_official 354:e67efb2aab0e 1441 /******************* Bit definition for OPAMP_LPOTR register ****************/
mbed_official 354:e67efb2aab0e 1442 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
mbed_official 354:e67efb2aab0e 1443 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
mbed_official 354:e67efb2aab0e 1444 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
mbed_official 354:e67efb2aab0e 1445 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
mbed_official 354:e67efb2aab0e 1446
mbed_official 354:e67efb2aab0e 1447 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1448 /* */
mbed_official 354:e67efb2aab0e 1449 /* CRC calculation unit (CRC) */
mbed_official 354:e67efb2aab0e 1450 /* */
mbed_official 354:e67efb2aab0e 1451 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1452
mbed_official 354:e67efb2aab0e 1453 /******************* Bit definition for CRC_DR register *********************/
mbed_official 354:e67efb2aab0e 1454 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 354:e67efb2aab0e 1455
mbed_official 354:e67efb2aab0e 1456 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 354:e67efb2aab0e 1457 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
mbed_official 354:e67efb2aab0e 1458
mbed_official 354:e67efb2aab0e 1459 /******************** Bit definition for CRC_CR register ********************/
mbed_official 354:e67efb2aab0e 1460 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
mbed_official 354:e67efb2aab0e 1461
mbed_official 354:e67efb2aab0e 1462 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1463 /* */
mbed_official 354:e67efb2aab0e 1464 /* Digital to Analog Converter (DAC) */
mbed_official 354:e67efb2aab0e 1465 /* */
mbed_official 354:e67efb2aab0e 1466 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1467
mbed_official 354:e67efb2aab0e 1468 /******************** Bit definition for DAC_CR register ********************/
mbed_official 354:e67efb2aab0e 1469 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 354:e67efb2aab0e 1470 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 354:e67efb2aab0e 1471 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 354:e67efb2aab0e 1472
mbed_official 354:e67efb2aab0e 1473 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 354:e67efb2aab0e 1474 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1475 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1476 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 1477
mbed_official 354:e67efb2aab0e 1478 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 354:e67efb2aab0e 1479 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1480 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1481
mbed_official 354:e67efb2aab0e 1482 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 354:e67efb2aab0e 1483 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1484 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1485 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 1486 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 1487
mbed_official 354:e67efb2aab0e 1488 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 354:e67efb2aab0e 1489 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Interrupt enable */
mbed_official 354:e67efb2aab0e 1490 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 354:e67efb2aab0e 1491 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 354:e67efb2aab0e 1492 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 354:e67efb2aab0e 1493
mbed_official 354:e67efb2aab0e 1494 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 354:e67efb2aab0e 1495 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1496 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1497 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 1498
mbed_official 354:e67efb2aab0e 1499 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 354:e67efb2aab0e 1500 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1501 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1502
mbed_official 354:e67efb2aab0e 1503 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 354:e67efb2aab0e 1504 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 1505 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 1506 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 1507 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 1508
mbed_official 354:e67efb2aab0e 1509 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 354:e67efb2aab0e 1510 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
mbed_official 354:e67efb2aab0e 1511 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 354:e67efb2aab0e 1512 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
mbed_official 354:e67efb2aab0e 1513 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
mbed_official 354:e67efb2aab0e 1514
mbed_official 354:e67efb2aab0e 1515 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 354:e67efb2aab0e 1516 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1517
mbed_official 354:e67efb2aab0e 1518 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 354:e67efb2aab0e 1519 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 354:e67efb2aab0e 1520
mbed_official 354:e67efb2aab0e 1521 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 354:e67efb2aab0e 1522 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1523
mbed_official 354:e67efb2aab0e 1524 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 354:e67efb2aab0e 1525 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1526
mbed_official 354:e67efb2aab0e 1527 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 354:e67efb2aab0e 1528 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 354:e67efb2aab0e 1529
mbed_official 354:e67efb2aab0e 1530 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 354:e67efb2aab0e 1531 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1532
mbed_official 354:e67efb2aab0e 1533 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 354:e67efb2aab0e 1534 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1535 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1536
mbed_official 354:e67efb2aab0e 1537 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 354:e67efb2aab0e 1538 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 354:e67efb2aab0e 1539 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 354:e67efb2aab0e 1540
mbed_official 354:e67efb2aab0e 1541 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 354:e67efb2aab0e 1542 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1543 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 354:e67efb2aab0e 1544
mbed_official 354:e67efb2aab0e 1545 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 354:e67efb2aab0e 1546 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
mbed_official 354:e67efb2aab0e 1547
mbed_official 354:e67efb2aab0e 1548 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 354:e67efb2aab0e 1549 #define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /*!<DAC channel2 data output */
mbed_official 354:e67efb2aab0e 1550
mbed_official 354:e67efb2aab0e 1551 /******************** Bit definition for DAC_SR register ********************/
mbed_official 354:e67efb2aab0e 1552 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 354:e67efb2aab0e 1553 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 354:e67efb2aab0e 1554
mbed_official 354:e67efb2aab0e 1555 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1556 /* */
mbed_official 354:e67efb2aab0e 1557 /* Debug MCU (DBGMCU) */
mbed_official 354:e67efb2aab0e 1558 /* */
mbed_official 354:e67efb2aab0e 1559 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1560
mbed_official 354:e67efb2aab0e 1561 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 354:e67efb2aab0e 1562 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 354:e67efb2aab0e 1563
mbed_official 354:e67efb2aab0e 1564 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 354:e67efb2aab0e 1565 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1566 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1567 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 1568 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 1569 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 1570 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 1571 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 1572 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 1573 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 1574 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 1575 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 1576 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 1577 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 1578 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 1579 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 1580 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 1581
mbed_official 354:e67efb2aab0e 1582 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 354:e67efb2aab0e 1583 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
mbed_official 354:e67efb2aab0e 1584 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 354:e67efb2aab0e 1585 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 354:e67efb2aab0e 1586 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
mbed_official 354:e67efb2aab0e 1587
mbed_official 354:e67efb2aab0e 1588 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
mbed_official 354:e67efb2aab0e 1589 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1590 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1591
mbed_official 354:e67efb2aab0e 1592 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 354:e67efb2aab0e 1593
mbed_official 354:e67efb2aab0e 1594 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1595 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1596 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1597 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1598 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1599 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1600 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
mbed_official 354:e67efb2aab0e 1601 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 354:e67efb2aab0e 1602 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 354:e67efb2aab0e 1603 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 354:e67efb2aab0e 1604 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 354:e67efb2aab0e 1605
mbed_official 354:e67efb2aab0e 1606 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 354:e67efb2aab0e 1607
mbed_official 354:e67efb2aab0e 1608 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1609 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1610 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
mbed_official 354:e67efb2aab0e 1611
mbed_official 354:e67efb2aab0e 1612 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1613 /* */
mbed_official 354:e67efb2aab0e 1614 /* DMA Controller (DMA) */
mbed_official 354:e67efb2aab0e 1615 /* */
mbed_official 354:e67efb2aab0e 1616 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1617
mbed_official 354:e67efb2aab0e 1618 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 354:e67efb2aab0e 1619 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1620 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1621 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1622 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1623 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1624 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1625 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1626 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1627 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1628 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1629 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1630 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1631 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1632 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1633 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1634 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1635 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1636 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1637 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1638 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1639 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1640 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1641 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1642 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1643 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 354:e67efb2aab0e 1644 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 354:e67efb2aab0e 1645 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 354:e67efb2aab0e 1646 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 354:e67efb2aab0e 1647
mbed_official 354:e67efb2aab0e 1648 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 354:e67efb2aab0e 1649 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1650 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1651 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1652 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1653 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1654 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1655 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1656 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1657 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1658 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1659 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1660 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1661 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1662 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1663 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1664 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1665 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1666 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1667 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1668 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1669 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1670 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1671 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1672 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1673 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 354:e67efb2aab0e 1674 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 354:e67efb2aab0e 1675 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 354:e67efb2aab0e 1676 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 354:e67efb2aab0e 1677
mbed_official 354:e67efb2aab0e 1678 /******************* Bit definition for DMA_CCR register *******************/
mbed_official 354:e67efb2aab0e 1679 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable*/
mbed_official 354:e67efb2aab0e 1680 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 354:e67efb2aab0e 1681 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 354:e67efb2aab0e 1682 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 354:e67efb2aab0e 1683 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 354:e67efb2aab0e 1684 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 354:e67efb2aab0e 1685 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 354:e67efb2aab0e 1686 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 354:e67efb2aab0e 1687
mbed_official 354:e67efb2aab0e 1688 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 354:e67efb2aab0e 1689 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1690 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1691
mbed_official 354:e67efb2aab0e 1692 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 354:e67efb2aab0e 1693 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1694 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1695
mbed_official 354:e67efb2aab0e 1696 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
mbed_official 354:e67efb2aab0e 1697 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 1698 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 1699
mbed_official 354:e67efb2aab0e 1700 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 354:e67efb2aab0e 1701
mbed_official 354:e67efb2aab0e 1702 /****************** Bit definition for DMA_CNDTR1 register ******************/
mbed_official 354:e67efb2aab0e 1703 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1704
mbed_official 354:e67efb2aab0e 1705 /****************** Bit definition for DMA_CNDTR2 register ******************/
mbed_official 354:e67efb2aab0e 1706 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1707
mbed_official 354:e67efb2aab0e 1708 /****************** Bit definition for DMA_CNDTR3 register ******************/
mbed_official 354:e67efb2aab0e 1709 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1710
mbed_official 354:e67efb2aab0e 1711 /****************** Bit definition for DMA_CNDTR4 register ******************/
mbed_official 354:e67efb2aab0e 1712 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1713
mbed_official 354:e67efb2aab0e 1714 /****************** Bit definition for DMA_CNDTR5 register ******************/
mbed_official 354:e67efb2aab0e 1715 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1716
mbed_official 354:e67efb2aab0e 1717 /****************** Bit definition for DMA_CNDTR6 register ******************/
mbed_official 354:e67efb2aab0e 1718 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1719
mbed_official 354:e67efb2aab0e 1720 /****************** Bit definition for DMA_CNDTR7 register ******************/
mbed_official 354:e67efb2aab0e 1721 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 354:e67efb2aab0e 1722
mbed_official 354:e67efb2aab0e 1723 /****************** Bit definition for DMA_CPAR1 register *******************/
mbed_official 354:e67efb2aab0e 1724 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1725
mbed_official 354:e67efb2aab0e 1726 /****************** Bit definition for DMA_CPAR2 register *******************/
mbed_official 354:e67efb2aab0e 1727 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1728
mbed_official 354:e67efb2aab0e 1729 /****************** Bit definition for DMA_CPAR3 register *******************/
mbed_official 354:e67efb2aab0e 1730 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1731
mbed_official 354:e67efb2aab0e 1732
mbed_official 354:e67efb2aab0e 1733 /****************** Bit definition for DMA_CPAR4 register *******************/
mbed_official 354:e67efb2aab0e 1734 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1735
mbed_official 354:e67efb2aab0e 1736 /****************** Bit definition for DMA_CPAR5 register *******************/
mbed_official 354:e67efb2aab0e 1737 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1738
mbed_official 354:e67efb2aab0e 1739 /****************** Bit definition for DMA_CPAR6 register *******************/
mbed_official 354:e67efb2aab0e 1740 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1741
mbed_official 354:e67efb2aab0e 1742
mbed_official 354:e67efb2aab0e 1743 /****************** Bit definition for DMA_CPAR7 register *******************/
mbed_official 354:e67efb2aab0e 1744 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 354:e67efb2aab0e 1745
mbed_official 354:e67efb2aab0e 1746 /****************** Bit definition for DMA_CMAR1 register *******************/
mbed_official 354:e67efb2aab0e 1747 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1748
mbed_official 354:e67efb2aab0e 1749 /****************** Bit definition for DMA_CMAR2 register *******************/
mbed_official 354:e67efb2aab0e 1750 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1751
mbed_official 354:e67efb2aab0e 1752 /****************** Bit definition for DMA_CMAR3 register *******************/
mbed_official 354:e67efb2aab0e 1753 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1754
mbed_official 354:e67efb2aab0e 1755
mbed_official 354:e67efb2aab0e 1756 /****************** Bit definition for DMA_CMAR4 register *******************/
mbed_official 354:e67efb2aab0e 1757 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1758
mbed_official 354:e67efb2aab0e 1759 /****************** Bit definition for DMA_CMAR5 register *******************/
mbed_official 354:e67efb2aab0e 1760 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1761
mbed_official 354:e67efb2aab0e 1762 /****************** Bit definition for DMA_CMAR6 register *******************/
mbed_official 354:e67efb2aab0e 1763 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1764
mbed_official 354:e67efb2aab0e 1765 /****************** Bit definition for DMA_CMAR7 register *******************/
mbed_official 354:e67efb2aab0e 1766 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 354:e67efb2aab0e 1767
mbed_official 354:e67efb2aab0e 1768 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1769 /* */
mbed_official 354:e67efb2aab0e 1770 /* External Interrupt/Event Controller (EXTI) */
mbed_official 354:e67efb2aab0e 1771 /* */
mbed_official 354:e67efb2aab0e 1772 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1773
mbed_official 354:e67efb2aab0e 1774 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 354:e67efb2aab0e 1775 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 354:e67efb2aab0e 1776 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 354:e67efb2aab0e 1777 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 354:e67efb2aab0e 1778 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 354:e67efb2aab0e 1779 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 354:e67efb2aab0e 1780 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 354:e67efb2aab0e 1781 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 354:e67efb2aab0e 1782 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 354:e67efb2aab0e 1783 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 354:e67efb2aab0e 1784 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 354:e67efb2aab0e 1785 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 354:e67efb2aab0e 1786 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 354:e67efb2aab0e 1787 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 354:e67efb2aab0e 1788 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 354:e67efb2aab0e 1789 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 354:e67efb2aab0e 1790 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 354:e67efb2aab0e 1791 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 354:e67efb2aab0e 1792 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 354:e67efb2aab0e 1793 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 354:e67efb2aab0e 1794 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 354:e67efb2aab0e 1795 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 354:e67efb2aab0e 1796 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 354:e67efb2aab0e 1797 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 354:e67efb2aab0e 1798 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 354:e67efb2aab0e 1799
mbed_official 354:e67efb2aab0e 1800 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 354:e67efb2aab0e 1801 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 354:e67efb2aab0e 1802 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 354:e67efb2aab0e 1803 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 354:e67efb2aab0e 1804 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 354:e67efb2aab0e 1805 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 354:e67efb2aab0e 1806 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 354:e67efb2aab0e 1807 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 354:e67efb2aab0e 1808 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 354:e67efb2aab0e 1809 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 354:e67efb2aab0e 1810 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 354:e67efb2aab0e 1811 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 354:e67efb2aab0e 1812 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 354:e67efb2aab0e 1813 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 354:e67efb2aab0e 1814 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 354:e67efb2aab0e 1815 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 354:e67efb2aab0e 1816 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 354:e67efb2aab0e 1817 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 354:e67efb2aab0e 1818 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 354:e67efb2aab0e 1819 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 354:e67efb2aab0e 1820 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 354:e67efb2aab0e 1821 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 354:e67efb2aab0e 1822 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 354:e67efb2aab0e 1823 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 354:e67efb2aab0e 1824 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 354:e67efb2aab0e 1825
mbed_official 354:e67efb2aab0e 1826 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 354:e67efb2aab0e 1827 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 354:e67efb2aab0e 1828 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 354:e67efb2aab0e 1829 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 354:e67efb2aab0e 1830 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 354:e67efb2aab0e 1831 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 354:e67efb2aab0e 1832 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 354:e67efb2aab0e 1833 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 354:e67efb2aab0e 1834 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 354:e67efb2aab0e 1835 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 354:e67efb2aab0e 1836 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 354:e67efb2aab0e 1837 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 354:e67efb2aab0e 1838 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 354:e67efb2aab0e 1839 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 354:e67efb2aab0e 1840 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 354:e67efb2aab0e 1841 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 354:e67efb2aab0e 1842 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 354:e67efb2aab0e 1843 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 354:e67efb2aab0e 1844 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 354:e67efb2aab0e 1845 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 354:e67efb2aab0e 1846 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 354:e67efb2aab0e 1847 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 354:e67efb2aab0e 1848 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 354:e67efb2aab0e 1849 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 354:e67efb2aab0e 1850 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 354:e67efb2aab0e 1851
mbed_official 354:e67efb2aab0e 1852 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 354:e67efb2aab0e 1853 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 354:e67efb2aab0e 1854 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 354:e67efb2aab0e 1855 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 354:e67efb2aab0e 1856 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 354:e67efb2aab0e 1857 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 354:e67efb2aab0e 1858 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 354:e67efb2aab0e 1859 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 354:e67efb2aab0e 1860 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 354:e67efb2aab0e 1861 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 354:e67efb2aab0e 1862 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 354:e67efb2aab0e 1863 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 354:e67efb2aab0e 1864 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 354:e67efb2aab0e 1865 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 354:e67efb2aab0e 1866 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 354:e67efb2aab0e 1867 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 354:e67efb2aab0e 1868 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 354:e67efb2aab0e 1869 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 354:e67efb2aab0e 1870 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 354:e67efb2aab0e 1871 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 354:e67efb2aab0e 1872 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 354:e67efb2aab0e 1873 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 354:e67efb2aab0e 1874 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 354:e67efb2aab0e 1875 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 354:e67efb2aab0e 1876 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 354:e67efb2aab0e 1877
mbed_official 354:e67efb2aab0e 1878 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 354:e67efb2aab0e 1879 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 354:e67efb2aab0e 1880 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 354:e67efb2aab0e 1881 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 354:e67efb2aab0e 1882 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 354:e67efb2aab0e 1883 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 354:e67efb2aab0e 1884 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 354:e67efb2aab0e 1885 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 354:e67efb2aab0e 1886 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 354:e67efb2aab0e 1887 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 354:e67efb2aab0e 1888 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 354:e67efb2aab0e 1889 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 354:e67efb2aab0e 1890 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 354:e67efb2aab0e 1891 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 354:e67efb2aab0e 1892 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 354:e67efb2aab0e 1893 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 354:e67efb2aab0e 1894 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 354:e67efb2aab0e 1895 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 354:e67efb2aab0e 1896 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 354:e67efb2aab0e 1897 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 354:e67efb2aab0e 1898 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 354:e67efb2aab0e 1899 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 354:e67efb2aab0e 1900 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 354:e67efb2aab0e 1901 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 354:e67efb2aab0e 1902 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 354:e67efb2aab0e 1903
mbed_official 354:e67efb2aab0e 1904 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 354:e67efb2aab0e 1905 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 354:e67efb2aab0e 1906 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 354:e67efb2aab0e 1907 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 354:e67efb2aab0e 1908 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 354:e67efb2aab0e 1909 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 354:e67efb2aab0e 1910 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 354:e67efb2aab0e 1911 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 354:e67efb2aab0e 1912 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 354:e67efb2aab0e 1913 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 354:e67efb2aab0e 1914 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 354:e67efb2aab0e 1915 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 354:e67efb2aab0e 1916 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 354:e67efb2aab0e 1917 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 354:e67efb2aab0e 1918 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 354:e67efb2aab0e 1919 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 354:e67efb2aab0e 1920 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 354:e67efb2aab0e 1921 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 354:e67efb2aab0e 1922 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 354:e67efb2aab0e 1923 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
mbed_official 354:e67efb2aab0e 1924 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 354:e67efb2aab0e 1925 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
mbed_official 354:e67efb2aab0e 1926 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
mbed_official 354:e67efb2aab0e 1927 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
mbed_official 354:e67efb2aab0e 1928 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
mbed_official 354:e67efb2aab0e 1929
mbed_official 354:e67efb2aab0e 1930 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1931 /* */
mbed_official 354:e67efb2aab0e 1932 /* FLASH, DATA EEPROM and Option Bytes Registers */
mbed_official 354:e67efb2aab0e 1933 /* (FLASH, DATA_EEPROM, OB) */
mbed_official 354:e67efb2aab0e 1934 /* */
mbed_official 354:e67efb2aab0e 1935 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1936
mbed_official 354:e67efb2aab0e 1937 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 354:e67efb2aab0e 1938 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
mbed_official 354:e67efb2aab0e 1939 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
mbed_official 354:e67efb2aab0e 1940 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
mbed_official 354:e67efb2aab0e 1941 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
mbed_official 354:e67efb2aab0e 1942 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
mbed_official 354:e67efb2aab0e 1943
mbed_official 354:e67efb2aab0e 1944 /******************* Bit definition for FLASH_PECR register ******************/
mbed_official 354:e67efb2aab0e 1945 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
mbed_official 354:e67efb2aab0e 1946 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
mbed_official 354:e67efb2aab0e 1947 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
mbed_official 354:e67efb2aab0e 1948 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
mbed_official 354:e67efb2aab0e 1949 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
mbed_official 354:e67efb2aab0e 1950 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
mbed_official 354:e67efb2aab0e 1951 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
mbed_official 354:e67efb2aab0e 1952 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
mbed_official 354:e67efb2aab0e 1953 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
mbed_official 354:e67efb2aab0e 1954 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
mbed_official 354:e67efb2aab0e 1955 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
mbed_official 354:e67efb2aab0e 1956 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
mbed_official 354:e67efb2aab0e 1957
mbed_official 354:e67efb2aab0e 1958 /****************** Bit definition for FLASH_PDKEYR register ******************/
mbed_official 354:e67efb2aab0e 1959 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
mbed_official 354:e67efb2aab0e 1960
mbed_official 354:e67efb2aab0e 1961 /****************** Bit definition for FLASH_PEKEYR register ******************/
mbed_official 354:e67efb2aab0e 1962 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
mbed_official 354:e67efb2aab0e 1963
mbed_official 354:e67efb2aab0e 1964 /****************** Bit definition for FLASH_PRGKEYR register ******************/
mbed_official 354:e67efb2aab0e 1965 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
mbed_official 354:e67efb2aab0e 1966
mbed_official 354:e67efb2aab0e 1967 /****************** Bit definition for FLASH_OPTKEYR register ******************/
mbed_official 354:e67efb2aab0e 1968 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
mbed_official 354:e67efb2aab0e 1969
mbed_official 354:e67efb2aab0e 1970 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 354:e67efb2aab0e 1971 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 354:e67efb2aab0e 1972 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
mbed_official 354:e67efb2aab0e 1973 #define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
mbed_official 354:e67efb2aab0e 1974 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
mbed_official 354:e67efb2aab0e 1975
mbed_official 354:e67efb2aab0e 1976 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
mbed_official 354:e67efb2aab0e 1977 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
mbed_official 354:e67efb2aab0e 1978 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
mbed_official 354:e67efb2aab0e 1979 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
mbed_official 354:e67efb2aab0e 1980 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
mbed_official 354:e67efb2aab0e 1981
mbed_official 354:e67efb2aab0e 1982 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 354:e67efb2aab0e 1983 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /*!< Read Protection */
mbed_official 354:e67efb2aab0e 1984 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
mbed_official 354:e67efb2aab0e 1985 #define FLASH_OBR_USER ((uint32_t)0x00F00000) /*!< User Option Bytes */
mbed_official 354:e67efb2aab0e 1986 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
mbed_official 354:e67efb2aab0e 1987 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
mbed_official 354:e67efb2aab0e 1988 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
mbed_official 354:e67efb2aab0e 1989 #define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */
mbed_official 354:e67efb2aab0e 1990
mbed_official 354:e67efb2aab0e 1991 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 354:e67efb2aab0e 1992 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 354:e67efb2aab0e 1993 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 354:e67efb2aab0e 1994 #define FLASH_WRPR3_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 354:e67efb2aab0e 1995 #define FLASH_WRPR4_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 354:e67efb2aab0e 1996
mbed_official 354:e67efb2aab0e 1997 /******************************************************************************/
mbed_official 354:e67efb2aab0e 1998 /* */
mbed_official 354:e67efb2aab0e 1999 /* General Purpose I/O */
mbed_official 354:e67efb2aab0e 2000 /* */
mbed_official 354:e67efb2aab0e 2001 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2002 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 354:e67efb2aab0e 2003 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 354:e67efb2aab0e 2004 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2005 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2006
mbed_official 354:e67efb2aab0e 2007 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 354:e67efb2aab0e 2008 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2009 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2010
mbed_official 354:e67efb2aab0e 2011 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 2012 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2013 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2014
mbed_official 354:e67efb2aab0e 2015 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 354:e67efb2aab0e 2016 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2017 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2018
mbed_official 354:e67efb2aab0e 2019 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 354:e67efb2aab0e 2020 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2021 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2022
mbed_official 354:e67efb2aab0e 2023 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 354:e67efb2aab0e 2024 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2025 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2026
mbed_official 354:e67efb2aab0e 2027 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 354:e67efb2aab0e 2028 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2029 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2030
mbed_official 354:e67efb2aab0e 2031 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 354:e67efb2aab0e 2032 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2033 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2034
mbed_official 354:e67efb2aab0e 2035 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 354:e67efb2aab0e 2036 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2037 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2038
mbed_official 354:e67efb2aab0e 2039 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 354:e67efb2aab0e 2040 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2041 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2042
mbed_official 354:e67efb2aab0e 2043 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 2044 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2045 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2046
mbed_official 354:e67efb2aab0e 2047 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 354:e67efb2aab0e 2048 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2049 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 2050
mbed_official 354:e67efb2aab0e 2051 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 354:e67efb2aab0e 2052 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 2053 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 2054
mbed_official 354:e67efb2aab0e 2055 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 354:e67efb2aab0e 2056 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 2057 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 2058
mbed_official 354:e67efb2aab0e 2059 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 354:e67efb2aab0e 2060 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 2061 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 2062
mbed_official 354:e67efb2aab0e 2063 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 354:e67efb2aab0e 2064 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 2065 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 2066
mbed_official 354:e67efb2aab0e 2067 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 354:e67efb2aab0e 2068 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2069 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2070 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2071 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2072 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2073 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2074 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2075 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2076 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2077 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2078 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2079 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2080 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2081 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2082 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2083 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2084
mbed_official 354:e67efb2aab0e 2085 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 354:e67efb2aab0e 2086 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 354:e67efb2aab0e 2087 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2088 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2089
mbed_official 354:e67efb2aab0e 2090 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 354:e67efb2aab0e 2091 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2092 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2093
mbed_official 354:e67efb2aab0e 2094 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 2095 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2096 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2097
mbed_official 354:e67efb2aab0e 2098 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 354:e67efb2aab0e 2099 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2100 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2101
mbed_official 354:e67efb2aab0e 2102 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 354:e67efb2aab0e 2103 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2104 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2105
mbed_official 354:e67efb2aab0e 2106 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 354:e67efb2aab0e 2107 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2108 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2109
mbed_official 354:e67efb2aab0e 2110 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 354:e67efb2aab0e 2111 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2112 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2113
mbed_official 354:e67efb2aab0e 2114 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 354:e67efb2aab0e 2115 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2116 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2117
mbed_official 354:e67efb2aab0e 2118 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 354:e67efb2aab0e 2119 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2120 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2121
mbed_official 354:e67efb2aab0e 2122 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 354:e67efb2aab0e 2123 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2124 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2125
mbed_official 354:e67efb2aab0e 2126 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 2127 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2128 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2129
mbed_official 354:e67efb2aab0e 2130 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 354:e67efb2aab0e 2131 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2132 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 2133
mbed_official 354:e67efb2aab0e 2134 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 354:e67efb2aab0e 2135 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 2136 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 2137
mbed_official 354:e67efb2aab0e 2138 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 354:e67efb2aab0e 2139 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 2140 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 2141
mbed_official 354:e67efb2aab0e 2142 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 354:e67efb2aab0e 2143 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 2144 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 2145
mbed_official 354:e67efb2aab0e 2146 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 354:e67efb2aab0e 2147 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 2148 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 2149
mbed_official 354:e67efb2aab0e 2150 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 354:e67efb2aab0e 2151 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 354:e67efb2aab0e 2152 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2153 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2154
mbed_official 354:e67efb2aab0e 2155 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 354:e67efb2aab0e 2156 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2157 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2158
mbed_official 354:e67efb2aab0e 2159 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 2160 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2161 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2162
mbed_official 354:e67efb2aab0e 2163 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 354:e67efb2aab0e 2164 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2165 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2166
mbed_official 354:e67efb2aab0e 2167 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 354:e67efb2aab0e 2168 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2169 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2170
mbed_official 354:e67efb2aab0e 2171 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 354:e67efb2aab0e 2172 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2173 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2174
mbed_official 354:e67efb2aab0e 2175 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 354:e67efb2aab0e 2176 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2177 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2178
mbed_official 354:e67efb2aab0e 2179 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 354:e67efb2aab0e 2180 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2181 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2182
mbed_official 354:e67efb2aab0e 2183 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 354:e67efb2aab0e 2184 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2185 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2186
mbed_official 354:e67efb2aab0e 2187 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 354:e67efb2aab0e 2188 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2189 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2190
mbed_official 354:e67efb2aab0e 2191 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 2192 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2193 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2194
mbed_official 354:e67efb2aab0e 2195 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 354:e67efb2aab0e 2196 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2197 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 2198
mbed_official 354:e67efb2aab0e 2199 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 354:e67efb2aab0e 2200 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 2201 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 2202
mbed_official 354:e67efb2aab0e 2203 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 354:e67efb2aab0e 2204 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 2205 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 2206
mbed_official 354:e67efb2aab0e 2207 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 354:e67efb2aab0e 2208 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 2209 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 2210 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 354:e67efb2aab0e 2211 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 2212 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 2213
mbed_official 354:e67efb2aab0e 2214 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 354:e67efb2aab0e 2215 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2216 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2217 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2218 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2219 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2220 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2221 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2222 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2223 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2224 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2225 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2226 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2227 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2228 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2229 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2230 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2231
mbed_official 354:e67efb2aab0e 2232 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 354:e67efb2aab0e 2233 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2234 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2235 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2236 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2237 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2238 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2239 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2240 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2241 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2242 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2243 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2244 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2245 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2246 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2247 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2248 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2249
mbed_official 354:e67efb2aab0e 2250 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 354:e67efb2aab0e 2251 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2252 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2253 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2254 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2255 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2256 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2257 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2258 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2259 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2260 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2261 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2262 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2263 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2264 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2265 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2266 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2267 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2268 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2269 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2270 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2271 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2272 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2273 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2274 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 2275 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 2276 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 2277 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 2278 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 2279 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 2280 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 2281 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 2282 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 2283
mbed_official 354:e67efb2aab0e 2284 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 354:e67efb2aab0e 2285 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2286 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2287 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2288 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2289 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2290 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2291 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2292 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2293 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2294 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2295 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2296 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2297 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2298 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2299 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2300 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2301 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2302
mbed_official 354:e67efb2aab0e 2303 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 354:e67efb2aab0e 2304 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 2305 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 354:e67efb2aab0e 2306 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 2307 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 354:e67efb2aab0e 2308 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 2309 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 354:e67efb2aab0e 2310 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 2311 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 354:e67efb2aab0e 2312
mbed_official 354:e67efb2aab0e 2313 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 354:e67efb2aab0e 2314 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 2315 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 354:e67efb2aab0e 2316 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 2317 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 354:e67efb2aab0e 2318 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 2319 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 354:e67efb2aab0e 2320 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 2321 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 354:e67efb2aab0e 2322
mbed_official 354:e67efb2aab0e 2323 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 354:e67efb2aab0e 2324 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2325 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2326 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2327 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2328 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2329 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2330 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2331 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 2332 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2333 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2334 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2335 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2336 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2337 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2338 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2339 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2340
mbed_official 354:e67efb2aab0e 2341
mbed_official 354:e67efb2aab0e 2342 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2343 /* */
mbed_official 354:e67efb2aab0e 2344 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 354:e67efb2aab0e 2345 /* */
mbed_official 354:e67efb2aab0e 2346 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2347
mbed_official 354:e67efb2aab0e 2348 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 354:e67efb2aab0e 2349 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
mbed_official 354:e67efb2aab0e 2350 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
mbed_official 354:e67efb2aab0e 2351 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
mbed_official 354:e67efb2aab0e 2352 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
mbed_official 354:e67efb2aab0e 2353 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
mbed_official 354:e67efb2aab0e 2354 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
mbed_official 354:e67efb2aab0e 2355 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
mbed_official 354:e67efb2aab0e 2356 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
mbed_official 354:e67efb2aab0e 2357 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
mbed_official 354:e67efb2aab0e 2358 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
mbed_official 354:e67efb2aab0e 2359 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
mbed_official 354:e67efb2aab0e 2360 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
mbed_official 354:e67efb2aab0e 2361 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
mbed_official 354:e67efb2aab0e 2362 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
mbed_official 354:e67efb2aab0e 2363
mbed_official 354:e67efb2aab0e 2364 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 354:e67efb2aab0e 2365 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 354:e67efb2aab0e 2366 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2367 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2368 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2369 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 2370 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 2371 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 2372
mbed_official 354:e67efb2aab0e 2373 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
mbed_official 354:e67efb2aab0e 2374 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
mbed_official 354:e67efb2aab0e 2375 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
mbed_official 354:e67efb2aab0e 2376 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
mbed_official 354:e67efb2aab0e 2377 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
mbed_official 354:e67efb2aab0e 2378
mbed_official 354:e67efb2aab0e 2379 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 354:e67efb2aab0e 2380 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
mbed_official 354:e67efb2aab0e 2381 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
mbed_official 354:e67efb2aab0e 2382
mbed_official 354:e67efb2aab0e 2383 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2384 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2385 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2386 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 2387 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 2388 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 2389 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 2390 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 2391 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 2392 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 2393
mbed_official 354:e67efb2aab0e 2394 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
mbed_official 354:e67efb2aab0e 2395
mbed_official 354:e67efb2aab0e 2396 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 354:e67efb2aab0e 2397 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
mbed_official 354:e67efb2aab0e 2398 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
mbed_official 354:e67efb2aab0e 2399
mbed_official 354:e67efb2aab0e 2400 /******************** Bit definition for I2C_DR register ********************/
mbed_official 354:e67efb2aab0e 2401 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!< 8-bit Data Register */
mbed_official 354:e67efb2aab0e 2402
mbed_official 354:e67efb2aab0e 2403 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 354:e67efb2aab0e 2404 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
mbed_official 354:e67efb2aab0e 2405 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
mbed_official 354:e67efb2aab0e 2406 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
mbed_official 354:e67efb2aab0e 2407 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
mbed_official 354:e67efb2aab0e 2408 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
mbed_official 354:e67efb2aab0e 2409 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
mbed_official 354:e67efb2aab0e 2410 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
mbed_official 354:e67efb2aab0e 2411 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
mbed_official 354:e67efb2aab0e 2412 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
mbed_official 354:e67efb2aab0e 2413 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
mbed_official 354:e67efb2aab0e 2414 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
mbed_official 354:e67efb2aab0e 2415 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
mbed_official 354:e67efb2aab0e 2416 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
mbed_official 354:e67efb2aab0e 2417 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
mbed_official 354:e67efb2aab0e 2418
mbed_official 354:e67efb2aab0e 2419 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 354:e67efb2aab0e 2420 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
mbed_official 354:e67efb2aab0e 2421 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
mbed_official 354:e67efb2aab0e 2422 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
mbed_official 354:e67efb2aab0e 2423 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
mbed_official 354:e67efb2aab0e 2424 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
mbed_official 354:e67efb2aab0e 2425 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
mbed_official 354:e67efb2aab0e 2426 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
mbed_official 354:e67efb2aab0e 2427 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
mbed_official 354:e67efb2aab0e 2428
mbed_official 354:e67efb2aab0e 2429 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 354:e67efb2aab0e 2430 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 354:e67efb2aab0e 2431 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
mbed_official 354:e67efb2aab0e 2432 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
mbed_official 354:e67efb2aab0e 2433
mbed_official 354:e67efb2aab0e 2434 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 354:e67efb2aab0e 2435 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 354:e67efb2aab0e 2436
mbed_official 354:e67efb2aab0e 2437 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2438 /* */
mbed_official 354:e67efb2aab0e 2439 /* Independent WATCHDOG (IWDG) */
mbed_official 354:e67efb2aab0e 2440 /* */
mbed_official 354:e67efb2aab0e 2441 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2442
mbed_official 354:e67efb2aab0e 2443 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 354:e67efb2aab0e 2444 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 354:e67efb2aab0e 2445
mbed_official 354:e67efb2aab0e 2446 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 354:e67efb2aab0e 2447 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 354:e67efb2aab0e 2448 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2449 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2450 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2451
mbed_official 354:e67efb2aab0e 2452 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 354:e67efb2aab0e 2453 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 354:e67efb2aab0e 2454
mbed_official 354:e67efb2aab0e 2455 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 354:e67efb2aab0e 2456 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 354:e67efb2aab0e 2457 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 354:e67efb2aab0e 2458
mbed_official 354:e67efb2aab0e 2459 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2460 /* */
mbed_official 354:e67efb2aab0e 2461 /* LCD Controller (LCD) */
mbed_official 354:e67efb2aab0e 2462 /* */
mbed_official 354:e67efb2aab0e 2463 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2464
mbed_official 354:e67efb2aab0e 2465 /******************* Bit definition for LCD_CR register *********************/
mbed_official 354:e67efb2aab0e 2466 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
mbed_official 354:e67efb2aab0e 2467 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
mbed_official 354:e67efb2aab0e 2468
mbed_official 354:e67efb2aab0e 2469 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
mbed_official 354:e67efb2aab0e 2470 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
mbed_official 354:e67efb2aab0e 2471 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
mbed_official 354:e67efb2aab0e 2472 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
mbed_official 354:e67efb2aab0e 2473
mbed_official 354:e67efb2aab0e 2474 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
mbed_official 354:e67efb2aab0e 2475 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
mbed_official 354:e67efb2aab0e 2476 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
mbed_official 354:e67efb2aab0e 2477
mbed_official 354:e67efb2aab0e 2478 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
mbed_official 354:e67efb2aab0e 2479
mbed_official 354:e67efb2aab0e 2480 /******************* Bit definition for LCD_FCR register ********************/
mbed_official 354:e67efb2aab0e 2481 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
mbed_official 354:e67efb2aab0e 2482 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
mbed_official 354:e67efb2aab0e 2483 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
mbed_official 354:e67efb2aab0e 2484
mbed_official 354:e67efb2aab0e 2485 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
mbed_official 354:e67efb2aab0e 2486 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2487 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2488 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2489
mbed_official 354:e67efb2aab0e 2490 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
mbed_official 354:e67efb2aab0e 2491 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2492 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2493 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2494
mbed_official 354:e67efb2aab0e 2495 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
mbed_official 354:e67efb2aab0e 2496 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2497 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2498 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2499
mbed_official 354:e67efb2aab0e 2500 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
mbed_official 354:e67efb2aab0e 2501 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2502 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2503 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2504
mbed_official 354:e67efb2aab0e 2505 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
mbed_official 354:e67efb2aab0e 2506 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2507 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2508
mbed_official 354:e67efb2aab0e 2509 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
mbed_official 354:e67efb2aab0e 2510 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
mbed_official 354:e67efb2aab0e 2511
mbed_official 354:e67efb2aab0e 2512 /******************* Bit definition for LCD_SR register *********************/
mbed_official 354:e67efb2aab0e 2513 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
mbed_official 354:e67efb2aab0e 2514 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
mbed_official 354:e67efb2aab0e 2515 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
mbed_official 354:e67efb2aab0e 2516 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
mbed_official 354:e67efb2aab0e 2517 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
mbed_official 354:e67efb2aab0e 2518 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
mbed_official 354:e67efb2aab0e 2519
mbed_official 354:e67efb2aab0e 2520 /******************* Bit definition for LCD_CLR register ********************/
mbed_official 354:e67efb2aab0e 2521 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
mbed_official 354:e67efb2aab0e 2522 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
mbed_official 354:e67efb2aab0e 2523
mbed_official 354:e67efb2aab0e 2524 /******************* Bit definition for LCD_RAM register ********************/
mbed_official 354:e67efb2aab0e 2525 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
mbed_official 354:e67efb2aab0e 2526
mbed_official 354:e67efb2aab0e 2527 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2528 /* */
mbed_official 354:e67efb2aab0e 2529 /* Power Control (PWR) */
mbed_official 354:e67efb2aab0e 2530 /* */
mbed_official 354:e67efb2aab0e 2531 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2532
mbed_official 354:e67efb2aab0e 2533 /******************** Bit definition for PWR_CR register ********************/
mbed_official 354:e67efb2aab0e 2534 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
mbed_official 354:e67efb2aab0e 2535 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 354:e67efb2aab0e 2536 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 354:e67efb2aab0e 2537 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 354:e67efb2aab0e 2538 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 354:e67efb2aab0e 2539
mbed_official 354:e67efb2aab0e 2540 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 354:e67efb2aab0e 2541 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2542 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2543 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2544
mbed_official 354:e67efb2aab0e 2545 /*!< PVD level configuration */
mbed_official 354:e67efb2aab0e 2546 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 354:e67efb2aab0e 2547 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 354:e67efb2aab0e 2548 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 354:e67efb2aab0e 2549 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 354:e67efb2aab0e 2550 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 354:e67efb2aab0e 2551 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 354:e67efb2aab0e 2552 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 354:e67efb2aab0e 2553 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 354:e67efb2aab0e 2554
mbed_official 354:e67efb2aab0e 2555 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 354:e67efb2aab0e 2556 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
mbed_official 354:e67efb2aab0e 2557 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
mbed_official 354:e67efb2aab0e 2558
mbed_official 354:e67efb2aab0e 2559 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
mbed_official 354:e67efb2aab0e 2560 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2561 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2562 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
mbed_official 354:e67efb2aab0e 2563
mbed_official 354:e67efb2aab0e 2564 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 354:e67efb2aab0e 2565 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 354:e67efb2aab0e 2566 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 354:e67efb2aab0e 2567 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 354:e67efb2aab0e 2568 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 354:e67efb2aab0e 2569 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
mbed_official 354:e67efb2aab0e 2570 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
mbed_official 354:e67efb2aab0e 2571
mbed_official 354:e67efb2aab0e 2572 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 354:e67efb2aab0e 2573 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 354:e67efb2aab0e 2574 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 354:e67efb2aab0e 2575
mbed_official 354:e67efb2aab0e 2576 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2577 /* */
mbed_official 354:e67efb2aab0e 2578 /* Reset and Clock Control (RCC) */
mbed_official 354:e67efb2aab0e 2579 /* */
mbed_official 354:e67efb2aab0e 2580 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2581 /******************** Bit definition for RCC_CR register ********************/
mbed_official 354:e67efb2aab0e 2582 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 354:e67efb2aab0e 2583 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 354:e67efb2aab0e 2584
mbed_official 354:e67efb2aab0e 2585 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
mbed_official 354:e67efb2aab0e 2586 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
mbed_official 354:e67efb2aab0e 2587
mbed_official 354:e67efb2aab0e 2588 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 354:e67efb2aab0e 2589 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 354:e67efb2aab0e 2590 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 354:e67efb2aab0e 2591
mbed_official 354:e67efb2aab0e 2592 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 354:e67efb2aab0e 2593 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 354:e67efb2aab0e 2594 #define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
mbed_official 354:e67efb2aab0e 2595
mbed_official 354:e67efb2aab0e 2596 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
mbed_official 354:e67efb2aab0e 2597 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
mbed_official 354:e67efb2aab0e 2598 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
mbed_official 354:e67efb2aab0e 2599
mbed_official 354:e67efb2aab0e 2600 /******************** Bit definition for RCC_ICSCR register *****************/
mbed_official 354:e67efb2aab0e 2601 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
mbed_official 354:e67efb2aab0e 2602 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
mbed_official 354:e67efb2aab0e 2603
mbed_official 354:e67efb2aab0e 2604 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
mbed_official 354:e67efb2aab0e 2605 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
mbed_official 354:e67efb2aab0e 2606 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
mbed_official 354:e67efb2aab0e 2607 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
mbed_official 354:e67efb2aab0e 2608 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
mbed_official 354:e67efb2aab0e 2609 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
mbed_official 354:e67efb2aab0e 2610 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
mbed_official 354:e67efb2aab0e 2611 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
mbed_official 354:e67efb2aab0e 2612 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
mbed_official 354:e67efb2aab0e 2613 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
mbed_official 354:e67efb2aab0e 2614
mbed_official 354:e67efb2aab0e 2615 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 354:e67efb2aab0e 2616 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 354:e67efb2aab0e 2617 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2618 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2619
mbed_official 354:e67efb2aab0e 2620 /*!< SW configuration */
mbed_official 354:e67efb2aab0e 2621 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
mbed_official 354:e67efb2aab0e 2622 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
mbed_official 354:e67efb2aab0e 2623 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
mbed_official 354:e67efb2aab0e 2624 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
mbed_official 354:e67efb2aab0e 2625
mbed_official 354:e67efb2aab0e 2626 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 354:e67efb2aab0e 2627 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2628 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2629
mbed_official 354:e67efb2aab0e 2630 /*!< SWS configuration */
mbed_official 354:e67efb2aab0e 2631 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
mbed_official 354:e67efb2aab0e 2632 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
mbed_official 354:e67efb2aab0e 2633 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
mbed_official 354:e67efb2aab0e 2634 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
mbed_official 354:e67efb2aab0e 2635
mbed_official 354:e67efb2aab0e 2636 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 354:e67efb2aab0e 2637 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2638 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2639 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2640 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 2641
mbed_official 354:e67efb2aab0e 2642 /*!< HPRE configuration */
mbed_official 354:e67efb2aab0e 2643 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 354:e67efb2aab0e 2644 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 354:e67efb2aab0e 2645 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 354:e67efb2aab0e 2646 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 354:e67efb2aab0e 2647 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 354:e67efb2aab0e 2648 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 354:e67efb2aab0e 2649 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 354:e67efb2aab0e 2650 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 354:e67efb2aab0e 2651 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 354:e67efb2aab0e 2652
mbed_official 354:e67efb2aab0e 2653 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 354:e67efb2aab0e 2654 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2655 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2656 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2657
mbed_official 354:e67efb2aab0e 2658 /*!< PPRE1 configuration */
mbed_official 354:e67efb2aab0e 2659 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 354:e67efb2aab0e 2660 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 354:e67efb2aab0e 2661 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 354:e67efb2aab0e 2662 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 354:e67efb2aab0e 2663 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 354:e67efb2aab0e 2664
mbed_official 354:e67efb2aab0e 2665 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 354:e67efb2aab0e 2666 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2667 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2668 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2669
mbed_official 354:e67efb2aab0e 2670 /*!< PPRE2 configuration */
mbed_official 354:e67efb2aab0e 2671 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 354:e67efb2aab0e 2672 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 354:e67efb2aab0e 2673 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 354:e67efb2aab0e 2674 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 354:e67efb2aab0e 2675 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 354:e67efb2aab0e 2676
mbed_official 354:e67efb2aab0e 2677 /*!< PLL entry clock source*/
mbed_official 354:e67efb2aab0e 2678 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 354:e67efb2aab0e 2679
mbed_official 354:e67efb2aab0e 2680 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
mbed_official 354:e67efb2aab0e 2681 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
mbed_official 354:e67efb2aab0e 2682
mbed_official 354:e67efb2aab0e 2683
mbed_official 354:e67efb2aab0e 2684 /*!< PLLMUL configuration */
mbed_official 354:e67efb2aab0e 2685 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 354:e67efb2aab0e 2686 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2687 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2688 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2689 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 2690
mbed_official 354:e67efb2aab0e 2691 /*!< PLLMUL configuration */
mbed_official 354:e67efb2aab0e 2692 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
mbed_official 354:e67efb2aab0e 2693 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
mbed_official 354:e67efb2aab0e 2694 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
mbed_official 354:e67efb2aab0e 2695 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
mbed_official 354:e67efb2aab0e 2696 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
mbed_official 354:e67efb2aab0e 2697 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
mbed_official 354:e67efb2aab0e 2698 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
mbed_official 354:e67efb2aab0e 2699 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
mbed_official 354:e67efb2aab0e 2700 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
mbed_official 354:e67efb2aab0e 2701
mbed_official 354:e67efb2aab0e 2702 /*!< PLLDIV configuration */
mbed_official 354:e67efb2aab0e 2703 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
mbed_official 354:e67efb2aab0e 2704 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
mbed_official 354:e67efb2aab0e 2705 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
mbed_official 354:e67efb2aab0e 2706
mbed_official 354:e67efb2aab0e 2707
mbed_official 354:e67efb2aab0e 2708 /*!< PLLDIV configuration */
mbed_official 354:e67efb2aab0e 2709 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
mbed_official 354:e67efb2aab0e 2710 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
mbed_official 354:e67efb2aab0e 2711 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
mbed_official 354:e67efb2aab0e 2712 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
mbed_official 354:e67efb2aab0e 2713
mbed_official 354:e67efb2aab0e 2714
mbed_official 354:e67efb2aab0e 2715 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 354:e67efb2aab0e 2716 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2717 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2718 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2719
mbed_official 354:e67efb2aab0e 2720 /*!< MCO configuration */
mbed_official 354:e67efb2aab0e 2721 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 354:e67efb2aab0e 2722 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
mbed_official 354:e67efb2aab0e 2723 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
mbed_official 354:e67efb2aab0e 2724 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
mbed_official 354:e67efb2aab0e 2725 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
mbed_official 354:e67efb2aab0e 2726 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
mbed_official 354:e67efb2aab0e 2727 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
mbed_official 354:e67efb2aab0e 2728 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
mbed_official 354:e67efb2aab0e 2729
mbed_official 354:e67efb2aab0e 2730 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
mbed_official 354:e67efb2aab0e 2731 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2732 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2733 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 2734
mbed_official 354:e67efb2aab0e 2735 /*!< MCO Prescaler configuration */
mbed_official 354:e67efb2aab0e 2736 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
mbed_official 354:e67efb2aab0e 2737 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
mbed_official 354:e67efb2aab0e 2738 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
mbed_official 354:e67efb2aab0e 2739 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
mbed_official 354:e67efb2aab0e 2740 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
mbed_official 354:e67efb2aab0e 2741
mbed_official 354:e67efb2aab0e 2742 /*!<****************** Bit definition for RCC_CIR register ********************/
mbed_official 354:e67efb2aab0e 2743 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2744 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2745 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2746 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2747 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2748 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
mbed_official 354:e67efb2aab0e 2749 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
mbed_official 354:e67efb2aab0e 2750 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 354:e67efb2aab0e 2751
mbed_official 354:e67efb2aab0e 2752 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2753 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2754 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2755 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2756 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2757 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
mbed_official 354:e67efb2aab0e 2758 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
mbed_official 354:e67efb2aab0e 2759
mbed_official 354:e67efb2aab0e 2760 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2761 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2762 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2763 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2764 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2765 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
mbed_official 354:e67efb2aab0e 2766 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
mbed_official 354:e67efb2aab0e 2767 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 354:e67efb2aab0e 2768
mbed_official 354:e67efb2aab0e 2769 /***************** Bit definition for RCC_AHBRSTR register ******************/
mbed_official 354:e67efb2aab0e 2770 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
mbed_official 354:e67efb2aab0e 2771 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
mbed_official 354:e67efb2aab0e 2772 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
mbed_official 354:e67efb2aab0e 2773 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
mbed_official 354:e67efb2aab0e 2774 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
mbed_official 354:e67efb2aab0e 2775 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
mbed_official 354:e67efb2aab0e 2776 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */
mbed_official 354:e67efb2aab0e 2777 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */
mbed_official 354:e67efb2aab0e 2778 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
mbed_official 354:e67efb2aab0e 2779 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
mbed_official 354:e67efb2aab0e 2780 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
mbed_official 354:e67efb2aab0e 2781 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
mbed_official 354:e67efb2aab0e 2782
mbed_official 354:e67efb2aab0e 2783 /***************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 354:e67efb2aab0e 2784 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
mbed_official 354:e67efb2aab0e 2785 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
mbed_official 354:e67efb2aab0e 2786 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
mbed_official 354:e67efb2aab0e 2787 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
mbed_official 354:e67efb2aab0e 2788 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
mbed_official 354:e67efb2aab0e 2789 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 354:e67efb2aab0e 2790 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 354:e67efb2aab0e 2791
mbed_official 354:e67efb2aab0e 2792 /***************** Bit definition for RCC_APB1RSTR register *****************/
mbed_official 354:e67efb2aab0e 2793 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 354:e67efb2aab0e 2794 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 354:e67efb2aab0e 2795 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 354:e67efb2aab0e 2796 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
mbed_official 354:e67efb2aab0e 2797 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 354:e67efb2aab0e 2798 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 354:e67efb2aab0e 2799 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
mbed_official 354:e67efb2aab0e 2800 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 354:e67efb2aab0e 2801 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
mbed_official 354:e67efb2aab0e 2802 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
mbed_official 354:e67efb2aab0e 2803 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 354:e67efb2aab0e 2804 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 354:e67efb2aab0e 2805 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
mbed_official 354:e67efb2aab0e 2806 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
mbed_official 354:e67efb2aab0e 2807 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 354:e67efb2aab0e 2808 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 354:e67efb2aab0e 2809 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
mbed_official 354:e67efb2aab0e 2810 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
mbed_official 354:e67efb2aab0e 2811 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
mbed_official 354:e67efb2aab0e 2812 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
mbed_official 354:e67efb2aab0e 2813
mbed_official 354:e67efb2aab0e 2814 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 354:e67efb2aab0e 2815 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
mbed_official 354:e67efb2aab0e 2816 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
mbed_official 354:e67efb2aab0e 2817 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
mbed_official 354:e67efb2aab0e 2818 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
mbed_official 354:e67efb2aab0e 2819 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
mbed_official 354:e67efb2aab0e 2820 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
mbed_official 354:e67efb2aab0e 2821 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */
mbed_official 354:e67efb2aab0e 2822 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */
mbed_official 354:e67efb2aab0e 2823 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
mbed_official 354:e67efb2aab0e 2824 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
mbed_official 354:e67efb2aab0e 2825 the Flash memory is in power down mode) */
mbed_official 354:e67efb2aab0e 2826 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
mbed_official 354:e67efb2aab0e 2827 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
mbed_official 354:e67efb2aab0e 2828
mbed_official 354:e67efb2aab0e 2829 /****************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 354:e67efb2aab0e 2830 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
mbed_official 354:e67efb2aab0e 2831 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
mbed_official 354:e67efb2aab0e 2832 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
mbed_official 354:e67efb2aab0e 2833 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
mbed_official 354:e67efb2aab0e 2834 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 354:e67efb2aab0e 2835 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 354:e67efb2aab0e 2836 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 354:e67efb2aab0e 2837
mbed_official 354:e67efb2aab0e 2838 /***************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 354:e67efb2aab0e 2839 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
mbed_official 354:e67efb2aab0e 2840 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 354:e67efb2aab0e 2841 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 354:e67efb2aab0e 2842 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
mbed_official 354:e67efb2aab0e 2843 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 354:e67efb2aab0e 2844 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 354:e67efb2aab0e 2845 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
mbed_official 354:e67efb2aab0e 2846 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 354:e67efb2aab0e 2847 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
mbed_official 354:e67efb2aab0e 2848 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
mbed_official 354:e67efb2aab0e 2849 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 354:e67efb2aab0e 2850 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 354:e67efb2aab0e 2851 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
mbed_official 354:e67efb2aab0e 2852 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
mbed_official 354:e67efb2aab0e 2853 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 354:e67efb2aab0e 2854 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 354:e67efb2aab0e 2855 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 354:e67efb2aab0e 2856 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
mbed_official 354:e67efb2aab0e 2857 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
mbed_official 354:e67efb2aab0e 2858 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
mbed_official 354:e67efb2aab0e 2859
mbed_official 354:e67efb2aab0e 2860 /****************** Bit definition for RCC_AHBLPENR register ****************/
mbed_official 354:e67efb2aab0e 2861 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2862 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2863 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2864 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2865 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2866 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2867 #define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2868 #define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2869 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2870 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
mbed_official 354:e67efb2aab0e 2871 (has effect only when the Flash memory is
mbed_official 354:e67efb2aab0e 2872 in power down mode) */
mbed_official 354:e67efb2aab0e 2873 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2874 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2875 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2876
mbed_official 354:e67efb2aab0e 2877 /****************** Bit definition for RCC_APB2LPENR register ***************/
mbed_official 354:e67efb2aab0e 2878 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2879 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2880 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2881 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2882 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2883 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2884 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2885
mbed_official 354:e67efb2aab0e 2886 /***************** Bit definition for RCC_APB1LPENR register ****************/
mbed_official 354:e67efb2aab0e 2887 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2888 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2889 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2890 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2891 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2892 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2893 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2894 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2895 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2896 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2897 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2898 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2899 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2900 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2901 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2902 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2903 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2904 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2905 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
mbed_official 354:e67efb2aab0e 2906 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
mbed_official 354:e67efb2aab0e 2907
mbed_official 354:e67efb2aab0e 2908 /******************* Bit definition for RCC_CSR register ********************/
mbed_official 354:e67efb2aab0e 2909 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 354:e67efb2aab0e 2910 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 354:e67efb2aab0e 2911
mbed_official 354:e67efb2aab0e 2912 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
mbed_official 354:e67efb2aab0e 2913 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
mbed_official 354:e67efb2aab0e 2914 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
mbed_official 354:e67efb2aab0e 2915
mbed_official 354:e67efb2aab0e 2916 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
mbed_official 354:e67efb2aab0e 2917 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
mbed_official 354:e67efb2aab0e 2918
mbed_official 354:e67efb2aab0e 2919 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 354:e67efb2aab0e 2920 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 2921 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 2922
mbed_official 354:e67efb2aab0e 2923 /*!< RTC congiguration */
mbed_official 354:e67efb2aab0e 2924 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 354:e67efb2aab0e 2925 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
mbed_official 354:e67efb2aab0e 2926 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
mbed_official 354:e67efb2aab0e 2927 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
mbed_official 354:e67efb2aab0e 2928
mbed_official 354:e67efb2aab0e 2929 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
mbed_official 354:e67efb2aab0e 2930 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
mbed_official 354:e67efb2aab0e 2931
mbed_official 354:e67efb2aab0e 2932 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 354:e67efb2aab0e 2933 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
mbed_official 354:e67efb2aab0e 2934 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 354:e67efb2aab0e 2935 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 354:e67efb2aab0e 2936 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 354:e67efb2aab0e 2937 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 354:e67efb2aab0e 2938 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 354:e67efb2aab0e 2939 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 354:e67efb2aab0e 2940
mbed_official 354:e67efb2aab0e 2941 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2942 /* */
mbed_official 354:e67efb2aab0e 2943 /* Real-Time Clock (RTC) */
mbed_official 354:e67efb2aab0e 2944 /* */
mbed_official 354:e67efb2aab0e 2945 /******************************************************************************/
mbed_official 354:e67efb2aab0e 2946 /******************** Bits definition for RTC_TR register *******************/
mbed_official 354:e67efb2aab0e 2947 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2948 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 2949 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2950 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2951 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 2952 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2953 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2954 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2955 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2956 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 354:e67efb2aab0e 2957 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2958 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2959 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2960 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 2961 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2962 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2963 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2964 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2965 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 354:e67efb2aab0e 2966 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2967 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2968 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 2969 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 2970 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 2971 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 2972 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 2973 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 2974
mbed_official 354:e67efb2aab0e 2975 /******************** Bits definition for RTC_DR register *******************/
mbed_official 354:e67efb2aab0e 2976 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 354:e67efb2aab0e 2977 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 2978 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 2979 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 2980 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 2981 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 2982 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 2983 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 2984 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 2985 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 2986 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 354:e67efb2aab0e 2987 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 2988 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 2989 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 2990 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 2991 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 2992 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 2993 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 2994 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 2995 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 2996 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 2997 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 2998 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 2999 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 3000 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3001 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3002 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3003 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3004
mbed_official 354:e67efb2aab0e 3005 /******************** Bits definition for RTC_CR register *******************/
mbed_official 354:e67efb2aab0e 3006 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 3007 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 354:e67efb2aab0e 3008 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 3009 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 3010 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 3011 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 3012 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 3013 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 3014 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 3015 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3016 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3017 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3018 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3019 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3020 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3021 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3022 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3023 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3024 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3025 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3026 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3027 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3028 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 354:e67efb2aab0e 3029 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3030 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3031 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3032
mbed_official 354:e67efb2aab0e 3033 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 354:e67efb2aab0e 3034 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 3035 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3036 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3037 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3038 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3039 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3040 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3041 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3042 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3043 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3044 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3045 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3046 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3047 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3048 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3049 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3050 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3051
mbed_official 354:e67efb2aab0e 3052 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 354:e67efb2aab0e 3053 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 354:e67efb2aab0e 3054 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 354:e67efb2aab0e 3055
mbed_official 354:e67efb2aab0e 3056 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 354:e67efb2aab0e 3057 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 354:e67efb2aab0e 3058
mbed_official 354:e67efb2aab0e 3059 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 354:e67efb2aab0e 3060 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3061 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 354:e67efb2aab0e 3062
mbed_official 354:e67efb2aab0e 3063 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 354:e67efb2aab0e 3064 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 3065 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 3066 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 354:e67efb2aab0e 3067 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 3068 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 3069 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 3070 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 3071 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 3072 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 3073 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 3074 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 3075 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 3076 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 3077 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 3078 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 3079 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 3080 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 3081 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 3082 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 3083 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 3084 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3085 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 354:e67efb2aab0e 3086 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3087 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3088 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3089 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 3090 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3091 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3092 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3093 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3094 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3095 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 354:e67efb2aab0e 3096 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3097 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3098 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3099 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 3100 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3101 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3102 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3103 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3104
mbed_official 354:e67efb2aab0e 3105 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 354:e67efb2aab0e 3106 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 3107 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 354:e67efb2aab0e 3108 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 354:e67efb2aab0e 3109 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 354:e67efb2aab0e 3110 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 354:e67efb2aab0e 3111 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 3112 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 3113 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 3114 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 3115 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 3116 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 354:e67efb2aab0e 3117 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 3118 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 3119 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 3120 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 3121 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 3122 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 3123 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 3124 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 3125 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 3126 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3127 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 354:e67efb2aab0e 3128 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3129 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3130 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3131 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 3132 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3133 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3134 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3135 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3136 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3137 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 354:e67efb2aab0e 3138 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3139 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3140 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3141 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 3142 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3143 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3144 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3145 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3146
mbed_official 354:e67efb2aab0e 3147 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 354:e67efb2aab0e 3148 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 354:e67efb2aab0e 3149
mbed_official 354:e67efb2aab0e 3150 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 354:e67efb2aab0e 3151 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 354:e67efb2aab0e 3152
mbed_official 354:e67efb2aab0e 3153 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 354:e67efb2aab0e 3154 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 354:e67efb2aab0e 3155 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 354:e67efb2aab0e 3156
mbed_official 354:e67efb2aab0e 3157 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 354:e67efb2aab0e 3158 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 354:e67efb2aab0e 3159 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 354:e67efb2aab0e 3160 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 354:e67efb2aab0e 3161 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 354:e67efb2aab0e 3162 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 354:e67efb2aab0e 3163 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 354:e67efb2aab0e 3164 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 354:e67efb2aab0e 3165 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 3166 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 354:e67efb2aab0e 3167 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 354:e67efb2aab0e 3168 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3169 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3170 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3171 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 3172 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3173 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3174 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3175 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3176 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 354:e67efb2aab0e 3177 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3178 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3179 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3180 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 3181 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3182 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3183 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3184 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3185
mbed_official 354:e67efb2aab0e 3186 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 354:e67efb2aab0e 3187 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 354:e67efb2aab0e 3188 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3189 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3190 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3191 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3192 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 354:e67efb2aab0e 3193 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3194 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3195 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3196 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3197 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 354:e67efb2aab0e 3198 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3199 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3200 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 354:e67efb2aab0e 3201 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3202 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3203 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3204 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3205
mbed_official 354:e67efb2aab0e 3206 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 354:e67efb2aab0e 3207 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 354:e67efb2aab0e 3208
mbed_official 354:e67efb2aab0e 3209 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 354:e67efb2aab0e 3210 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3211 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3212 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3213 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 354:e67efb2aab0e 3214 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3215 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3216 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3217 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3218 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3219 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3220 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3221 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3222 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3223
mbed_official 354:e67efb2aab0e 3224 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 354:e67efb2aab0e 3225 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 354:e67efb2aab0e 3226 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 354:e67efb2aab0e 3227 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 354:e67efb2aab0e 3228 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 354:e67efb2aab0e 3229 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 354:e67efb2aab0e 3230 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 354:e67efb2aab0e 3231 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 354:e67efb2aab0e 3232 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 354:e67efb2aab0e 3233 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 354:e67efb2aab0e 3234 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 354:e67efb2aab0e 3235 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 354:e67efb2aab0e 3236 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 354:e67efb2aab0e 3237 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 354:e67efb2aab0e 3238 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 354:e67efb2aab0e 3239 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 354:e67efb2aab0e 3240 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 354:e67efb2aab0e 3241 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 354:e67efb2aab0e 3242 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 354:e67efb2aab0e 3243 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 354:e67efb2aab0e 3244 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 354:e67efb2aab0e 3245
mbed_official 354:e67efb2aab0e 3246 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 354:e67efb2aab0e 3247 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 3248 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 3249 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 3250 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 3251 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 3252 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 354:e67efb2aab0e 3253
mbed_official 354:e67efb2aab0e 3254 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 354:e67efb2aab0e 3255 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 354:e67efb2aab0e 3256 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 354:e67efb2aab0e 3257 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 354:e67efb2aab0e 3258 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 354:e67efb2aab0e 3259 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 354:e67efb2aab0e 3260 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 354:e67efb2aab0e 3261
mbed_official 354:e67efb2aab0e 3262 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 354:e67efb2aab0e 3263 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3264
mbed_official 354:e67efb2aab0e 3265 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 354:e67efb2aab0e 3266 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3267
mbed_official 354:e67efb2aab0e 3268 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 354:e67efb2aab0e 3269 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3270
mbed_official 354:e67efb2aab0e 3271 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 354:e67efb2aab0e 3272 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3273
mbed_official 354:e67efb2aab0e 3274 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 354:e67efb2aab0e 3275 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3276
mbed_official 354:e67efb2aab0e 3277 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 354:e67efb2aab0e 3278 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3279
mbed_official 354:e67efb2aab0e 3280 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 354:e67efb2aab0e 3281 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3282
mbed_official 354:e67efb2aab0e 3283 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 354:e67efb2aab0e 3284 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3285
mbed_official 354:e67efb2aab0e 3286 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 354:e67efb2aab0e 3287 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3288
mbed_official 354:e67efb2aab0e 3289 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 354:e67efb2aab0e 3290 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3291
mbed_official 354:e67efb2aab0e 3292 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 354:e67efb2aab0e 3293 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3294
mbed_official 354:e67efb2aab0e 3295 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 354:e67efb2aab0e 3296 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3297
mbed_official 354:e67efb2aab0e 3298 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 354:e67efb2aab0e 3299 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3300
mbed_official 354:e67efb2aab0e 3301 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 354:e67efb2aab0e 3302 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3303
mbed_official 354:e67efb2aab0e 3304 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 354:e67efb2aab0e 3305 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3306
mbed_official 354:e67efb2aab0e 3307 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 354:e67efb2aab0e 3308 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3309
mbed_official 354:e67efb2aab0e 3310 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 354:e67efb2aab0e 3311 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3312
mbed_official 354:e67efb2aab0e 3313 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 354:e67efb2aab0e 3314 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3315
mbed_official 354:e67efb2aab0e 3316 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 354:e67efb2aab0e 3317 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3318
mbed_official 354:e67efb2aab0e 3319 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 354:e67efb2aab0e 3320 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3321
mbed_official 354:e67efb2aab0e 3322 /******************** Bits definition for RTC_BKP20R register ***************/
mbed_official 354:e67efb2aab0e 3323 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3324
mbed_official 354:e67efb2aab0e 3325 /******************** Bits definition for RTC_BKP21R register ***************/
mbed_official 354:e67efb2aab0e 3326 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3327
mbed_official 354:e67efb2aab0e 3328 /******************** Bits definition for RTC_BKP22R register ***************/
mbed_official 354:e67efb2aab0e 3329 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3330
mbed_official 354:e67efb2aab0e 3331 /******************** Bits definition for RTC_BKP23R register ***************/
mbed_official 354:e67efb2aab0e 3332 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3333
mbed_official 354:e67efb2aab0e 3334 /******************** Bits definition for RTC_BKP24R register ***************/
mbed_official 354:e67efb2aab0e 3335 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3336
mbed_official 354:e67efb2aab0e 3337 /******************** Bits definition for RTC_BKP25R register ***************/
mbed_official 354:e67efb2aab0e 3338 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3339
mbed_official 354:e67efb2aab0e 3340 /******************** Bits definition for RTC_BKP26R register ***************/
mbed_official 354:e67efb2aab0e 3341 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3342
mbed_official 354:e67efb2aab0e 3343 /******************** Bits definition for RTC_BKP27R register ***************/
mbed_official 354:e67efb2aab0e 3344 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3345
mbed_official 354:e67efb2aab0e 3346 /******************** Bits definition for RTC_BKP28R register ***************/
mbed_official 354:e67efb2aab0e 3347 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3348
mbed_official 354:e67efb2aab0e 3349 /******************** Bits definition for RTC_BKP29R register ***************/
mbed_official 354:e67efb2aab0e 3350 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3351
mbed_official 354:e67efb2aab0e 3352 /******************** Bits definition for RTC_BKP30R register ***************/
mbed_official 354:e67efb2aab0e 3353 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3354
mbed_official 354:e67efb2aab0e 3355 /******************** Bits definition for RTC_BKP31R register ***************/
mbed_official 354:e67efb2aab0e 3356 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
mbed_official 354:e67efb2aab0e 3357
mbed_official 354:e67efb2aab0e 3358 /******************** Number of backup registers ******************************/
mbed_official 354:e67efb2aab0e 3359 #define RTC_BKP_NUMBER 32
mbed_official 354:e67efb2aab0e 3360
mbed_official 354:e67efb2aab0e 3361 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3362 /* */
mbed_official 354:e67efb2aab0e 3363 /* Serial Peripheral Interface (SPI) */
mbed_official 354:e67efb2aab0e 3364 /* */
mbed_official 354:e67efb2aab0e 3365 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3366
mbed_official 354:e67efb2aab0e 3367 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 354:e67efb2aab0e 3368 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 354:e67efb2aab0e 3369 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 354:e67efb2aab0e 3370 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 354:e67efb2aab0e 3371
mbed_official 354:e67efb2aab0e 3372 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 354:e67efb2aab0e 3373 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3374 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3375 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3376
mbed_official 354:e67efb2aab0e 3377 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 354:e67efb2aab0e 3378 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 354:e67efb2aab0e 3379 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 354:e67efb2aab0e 3380 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 354:e67efb2aab0e 3381 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 354:e67efb2aab0e 3382 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
mbed_official 354:e67efb2aab0e 3383 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 354:e67efb2aab0e 3384 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 354:e67efb2aab0e 3385 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 354:e67efb2aab0e 3386 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 354:e67efb2aab0e 3387
mbed_official 354:e67efb2aab0e 3388 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 354:e67efb2aab0e 3389 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 354:e67efb2aab0e 3390 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 354:e67efb2aab0e 3391 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 354:e67efb2aab0e 3392 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame format */
mbed_official 354:e67efb2aab0e 3393 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 354:e67efb2aab0e 3394 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 354:e67efb2aab0e 3395 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 354:e67efb2aab0e 3396
mbed_official 354:e67efb2aab0e 3397 /******************** Bit definition for SPI_SR register ********************/
mbed_official 354:e67efb2aab0e 3398 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 354:e67efb2aab0e 3399 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 354:e67efb2aab0e 3400 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 354:e67efb2aab0e 3401 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 354:e67efb2aab0e 3402 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 354:e67efb2aab0e 3403 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 354:e67efb2aab0e 3404 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 354:e67efb2aab0e 3405 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 354:e67efb2aab0e 3406 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 354:e67efb2aab0e 3407
mbed_official 354:e67efb2aab0e 3408 /******************** Bit definition for SPI_DR register ********************/
mbed_official 354:e67efb2aab0e 3409 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 354:e67efb2aab0e 3410
mbed_official 354:e67efb2aab0e 3411 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 354:e67efb2aab0e 3412 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 354:e67efb2aab0e 3413
mbed_official 354:e67efb2aab0e 3414 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 354:e67efb2aab0e 3415 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 354:e67efb2aab0e 3416
mbed_official 354:e67efb2aab0e 3417 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 354:e67efb2aab0e 3418 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 354:e67efb2aab0e 3419
mbed_official 354:e67efb2aab0e 3420 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 354:e67efb2aab0e 3421 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 354:e67efb2aab0e 3422
mbed_official 354:e67efb2aab0e 3423 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 354:e67efb2aab0e 3424 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 3425 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 3426
mbed_official 354:e67efb2aab0e 3427 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 354:e67efb2aab0e 3428
mbed_official 354:e67efb2aab0e 3429 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 354:e67efb2aab0e 3430 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 3431 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 3432
mbed_official 354:e67efb2aab0e 3433 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 354:e67efb2aab0e 3434
mbed_official 354:e67efb2aab0e 3435 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 354:e67efb2aab0e 3436 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 3437 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 3438
mbed_official 354:e67efb2aab0e 3439 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 354:e67efb2aab0e 3440 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 354:e67efb2aab0e 3441
mbed_official 354:e67efb2aab0e 3442 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 354:e67efb2aab0e 3443 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 354:e67efb2aab0e 3444 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 354:e67efb2aab0e 3445 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 354:e67efb2aab0e 3446
mbed_official 354:e67efb2aab0e 3447 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3448 /* */
mbed_official 354:e67efb2aab0e 3449 /* System Configuration (SYSCFG) */
mbed_official 354:e67efb2aab0e 3450 /* */
mbed_official 354:e67efb2aab0e 3451 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3452 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
mbed_official 354:e67efb2aab0e 3453 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 354:e67efb2aab0e 3454 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3455 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3456 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
mbed_official 354:e67efb2aab0e 3457 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3458 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3459
mbed_official 354:e67efb2aab0e 3460 /***************** Bit definition for SYSCFG_PMC register *******************/
mbed_official 354:e67efb2aab0e 3461 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
mbed_official 354:e67efb2aab0e 3462
mbed_official 354:e67efb2aab0e 3463 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 354:e67efb2aab0e 3464 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 354:e67efb2aab0e 3465 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 354:e67efb2aab0e 3466 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 354:e67efb2aab0e 3467 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 354:e67efb2aab0e 3468
mbed_official 354:e67efb2aab0e 3469 /**
mbed_official 354:e67efb2aab0e 3470 * @brief EXTI0 configuration
mbed_official 354:e67efb2aab0e 3471 */
mbed_official 354:e67efb2aab0e 3472 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 354:e67efb2aab0e 3473 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 354:e67efb2aab0e 3474 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 354:e67efb2aab0e 3475 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 354:e67efb2aab0e 3476 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 354:e67efb2aab0e 3477 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
mbed_official 354:e67efb2aab0e 3478 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /*!< PF[0] pin */
mbed_official 354:e67efb2aab0e 3479 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /*!< PG[0] pin */
mbed_official 354:e67efb2aab0e 3480
mbed_official 354:e67efb2aab0e 3481 /**
mbed_official 354:e67efb2aab0e 3482 * @brief EXTI1 configuration
mbed_official 354:e67efb2aab0e 3483 */
mbed_official 354:e67efb2aab0e 3484 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 354:e67efb2aab0e 3485 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 354:e67efb2aab0e 3486 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 354:e67efb2aab0e 3487 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 354:e67efb2aab0e 3488 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 354:e67efb2aab0e 3489 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
mbed_official 354:e67efb2aab0e 3490 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /*!< PF[1] pin */
mbed_official 354:e67efb2aab0e 3491 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /*!< PG[1] pin */
mbed_official 354:e67efb2aab0e 3492
mbed_official 354:e67efb2aab0e 3493 /**
mbed_official 354:e67efb2aab0e 3494 * @brief EXTI2 configuration
mbed_official 354:e67efb2aab0e 3495 */
mbed_official 354:e67efb2aab0e 3496 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 354:e67efb2aab0e 3497 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 354:e67efb2aab0e 3498 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 354:e67efb2aab0e 3499 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 354:e67efb2aab0e 3500 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 354:e67efb2aab0e 3501 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /*!< PH[2] pin */
mbed_official 354:e67efb2aab0e 3502 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /*!< PF[2] pin */
mbed_official 354:e67efb2aab0e 3503 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /*!< PG[2] pin */
mbed_official 354:e67efb2aab0e 3504
mbed_official 354:e67efb2aab0e 3505 /**
mbed_official 354:e67efb2aab0e 3506 * @brief EXTI3 configuration
mbed_official 354:e67efb2aab0e 3507 */
mbed_official 354:e67efb2aab0e 3508 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 354:e67efb2aab0e 3509 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 354:e67efb2aab0e 3510 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 354:e67efb2aab0e 3511 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 354:e67efb2aab0e 3512 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 354:e67efb2aab0e 3513 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /*!< PF[3] pin */
mbed_official 354:e67efb2aab0e 3514 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /*!< PG[3] pin */
mbed_official 354:e67efb2aab0e 3515
mbed_official 354:e67efb2aab0e 3516 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
mbed_official 354:e67efb2aab0e 3517 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 354:e67efb2aab0e 3518 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 354:e67efb2aab0e 3519 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 354:e67efb2aab0e 3520 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 354:e67efb2aab0e 3521
mbed_official 354:e67efb2aab0e 3522 /**
mbed_official 354:e67efb2aab0e 3523 * @brief EXTI4 configuration
mbed_official 354:e67efb2aab0e 3524 */
mbed_official 354:e67efb2aab0e 3525 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 354:e67efb2aab0e 3526 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 354:e67efb2aab0e 3527 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 354:e67efb2aab0e 3528 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 354:e67efb2aab0e 3529 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 354:e67efb2aab0e 3530 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /*!< PF[4] pin */
mbed_official 354:e67efb2aab0e 3531 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /*!< PG[4] pin */
mbed_official 354:e67efb2aab0e 3532
mbed_official 354:e67efb2aab0e 3533 /**
mbed_official 354:e67efb2aab0e 3534 * @brief EXTI5 configuration
mbed_official 354:e67efb2aab0e 3535 */
mbed_official 354:e67efb2aab0e 3536 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 354:e67efb2aab0e 3537 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 354:e67efb2aab0e 3538 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 354:e67efb2aab0e 3539 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 354:e67efb2aab0e 3540 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 354:e67efb2aab0e 3541 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /*!< PF[5] pin */
mbed_official 354:e67efb2aab0e 3542 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /*!< PG[5] pin */
mbed_official 354:e67efb2aab0e 3543
mbed_official 354:e67efb2aab0e 3544 /**
mbed_official 354:e67efb2aab0e 3545 * @brief EXTI6 configuration
mbed_official 354:e67efb2aab0e 3546 */
mbed_official 354:e67efb2aab0e 3547 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 354:e67efb2aab0e 3548 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 354:e67efb2aab0e 3549 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 354:e67efb2aab0e 3550 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 354:e67efb2aab0e 3551 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 354:e67efb2aab0e 3552 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /*!< PF[6] pin */
mbed_official 354:e67efb2aab0e 3553 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /*!< PG[6] pin */
mbed_official 354:e67efb2aab0e 3554
mbed_official 354:e67efb2aab0e 3555 /**
mbed_official 354:e67efb2aab0e 3556 * @brief EXTI7 configuration
mbed_official 354:e67efb2aab0e 3557 */
mbed_official 354:e67efb2aab0e 3558 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 354:e67efb2aab0e 3559 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 354:e67efb2aab0e 3560 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 354:e67efb2aab0e 3561 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 354:e67efb2aab0e 3562 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 354:e67efb2aab0e 3563 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /*!< PF[7] pin */
mbed_official 354:e67efb2aab0e 3564 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /*!< PG[7] pin */
mbed_official 354:e67efb2aab0e 3565
mbed_official 354:e67efb2aab0e 3566 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
mbed_official 354:e67efb2aab0e 3567 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 354:e67efb2aab0e 3568 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 354:e67efb2aab0e 3569 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 354:e67efb2aab0e 3570 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 354:e67efb2aab0e 3571
mbed_official 354:e67efb2aab0e 3572 /**
mbed_official 354:e67efb2aab0e 3573 * @brief EXTI8 configuration
mbed_official 354:e67efb2aab0e 3574 */
mbed_official 354:e67efb2aab0e 3575 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 354:e67efb2aab0e 3576 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 354:e67efb2aab0e 3577 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 354:e67efb2aab0e 3578 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 354:e67efb2aab0e 3579 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 354:e67efb2aab0e 3580 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /*!< PF[8] pin */
mbed_official 354:e67efb2aab0e 3581 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /*!< PG[8] pin */
mbed_official 354:e67efb2aab0e 3582
mbed_official 354:e67efb2aab0e 3583 /**
mbed_official 354:e67efb2aab0e 3584 * @brief EXTI9 configuration
mbed_official 354:e67efb2aab0e 3585 */
mbed_official 354:e67efb2aab0e 3586 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 354:e67efb2aab0e 3587 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 354:e67efb2aab0e 3588 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 354:e67efb2aab0e 3589 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 354:e67efb2aab0e 3590 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 354:e67efb2aab0e 3591 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /*!< PF[9] pin */
mbed_official 354:e67efb2aab0e 3592 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /*!< PG[9] pin */
mbed_official 354:e67efb2aab0e 3593
mbed_official 354:e67efb2aab0e 3594 /**
mbed_official 354:e67efb2aab0e 3595 * @brief EXTI10 configuration
mbed_official 354:e67efb2aab0e 3596 */
mbed_official 354:e67efb2aab0e 3597 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 354:e67efb2aab0e 3598 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 354:e67efb2aab0e 3599 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 354:e67efb2aab0e 3600 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 354:e67efb2aab0e 3601 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 354:e67efb2aab0e 3602 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /*!< PF[10] pin */
mbed_official 354:e67efb2aab0e 3603 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /*!< PG[10] pin */
mbed_official 354:e67efb2aab0e 3604
mbed_official 354:e67efb2aab0e 3605 /**
mbed_official 354:e67efb2aab0e 3606 * @brief EXTI11 configuration
mbed_official 354:e67efb2aab0e 3607 */
mbed_official 354:e67efb2aab0e 3608 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 354:e67efb2aab0e 3609 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 354:e67efb2aab0e 3610 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 354:e67efb2aab0e 3611 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 354:e67efb2aab0e 3612 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 354:e67efb2aab0e 3613 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /*!< PF[11] pin */
mbed_official 354:e67efb2aab0e 3614 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /*!< PG[11] pin */
mbed_official 354:e67efb2aab0e 3615
mbed_official 354:e67efb2aab0e 3616 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 354:e67efb2aab0e 3617 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 354:e67efb2aab0e 3618 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 354:e67efb2aab0e 3619 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 354:e67efb2aab0e 3620 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 354:e67efb2aab0e 3621
mbed_official 354:e67efb2aab0e 3622 /**
mbed_official 354:e67efb2aab0e 3623 * @brief EXTI12 configuration
mbed_official 354:e67efb2aab0e 3624 */
mbed_official 354:e67efb2aab0e 3625 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 354:e67efb2aab0e 3626 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 354:e67efb2aab0e 3627 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 354:e67efb2aab0e 3628 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 354:e67efb2aab0e 3629 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 354:e67efb2aab0e 3630 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /*!< PF[12] pin */
mbed_official 354:e67efb2aab0e 3631 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /*!< PG[12] pin */
mbed_official 354:e67efb2aab0e 3632
mbed_official 354:e67efb2aab0e 3633 /**
mbed_official 354:e67efb2aab0e 3634 * @brief EXTI13 configuration
mbed_official 354:e67efb2aab0e 3635 */
mbed_official 354:e67efb2aab0e 3636 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 354:e67efb2aab0e 3637 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 354:e67efb2aab0e 3638 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 354:e67efb2aab0e 3639 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 354:e67efb2aab0e 3640 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 354:e67efb2aab0e 3641 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /*!< PF[13] pin */
mbed_official 354:e67efb2aab0e 3642 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /*!< PG[13] pin */
mbed_official 354:e67efb2aab0e 3643
mbed_official 354:e67efb2aab0e 3644 /**
mbed_official 354:e67efb2aab0e 3645 * @brief EXTI14 configuration
mbed_official 354:e67efb2aab0e 3646 */
mbed_official 354:e67efb2aab0e 3647 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 354:e67efb2aab0e 3648 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 354:e67efb2aab0e 3649 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 354:e67efb2aab0e 3650 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 354:e67efb2aab0e 3651 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 354:e67efb2aab0e 3652 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /*!< PF[14] pin */
mbed_official 354:e67efb2aab0e 3653 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /*!< PG[14] pin */
mbed_official 354:e67efb2aab0e 3654
mbed_official 354:e67efb2aab0e 3655 /**
mbed_official 354:e67efb2aab0e 3656 * @brief EXTI15 configuration
mbed_official 354:e67efb2aab0e 3657 */
mbed_official 354:e67efb2aab0e 3658 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 354:e67efb2aab0e 3659 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 354:e67efb2aab0e 3660 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 354:e67efb2aab0e 3661 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 354:e67efb2aab0e 3662 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 354:e67efb2aab0e 3663 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /*!< PF[15] pin */
mbed_official 354:e67efb2aab0e 3664 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /*!< PG[15] pin */
mbed_official 354:e67efb2aab0e 3665
mbed_official 354:e67efb2aab0e 3666 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3667 /* */
mbed_official 354:e67efb2aab0e 3668 /* Routing Interface (RI) */
mbed_official 354:e67efb2aab0e 3669 /* */
mbed_official 354:e67efb2aab0e 3670 /******************************************************************************/
mbed_official 354:e67efb2aab0e 3671
mbed_official 354:e67efb2aab0e 3672 /******************** Bit definition for RI_ICR register ********************/
mbed_official 354:e67efb2aab0e 3673 #define RI_ICR_IC1OS ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
mbed_official 354:e67efb2aab0e 3674 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3675 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3676 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3677 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3678
mbed_official 354:e67efb2aab0e 3679 #define RI_ICR_IC2OS ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
mbed_official 354:e67efb2aab0e 3680 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3681 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3682 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3683 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3684
mbed_official 354:e67efb2aab0e 3685 #define RI_ICR_IC3OS ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
mbed_official 354:e67efb2aab0e 3686 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3687 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3688 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3689 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3690
mbed_official 354:e67efb2aab0e 3691 #define RI_ICR_IC4OS ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
mbed_official 354:e67efb2aab0e 3692 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3693 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3694 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3695 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3696
mbed_official 354:e67efb2aab0e 3697 #define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
mbed_official 354:e67efb2aab0e 3698 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3699 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3700
mbed_official 354:e67efb2aab0e 3701 #define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
mbed_official 354:e67efb2aab0e 3702 #define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
mbed_official 354:e67efb2aab0e 3703 #define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
mbed_official 354:e67efb2aab0e 3704 #define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
mbed_official 354:e67efb2aab0e 3705
mbed_official 354:e67efb2aab0e 3706 /******************** Bit definition for RI_ASCR1 register ********************/
mbed_official 354:e67efb2aab0e 3707 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
mbed_official 354:e67efb2aab0e 3708 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3709 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3710 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3711 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3712 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3713 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3714 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3715 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3716 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3717 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3718 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3719 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3720 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3721 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3722 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3723 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3724 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
mbed_official 354:e67efb2aab0e 3725 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
mbed_official 354:e67efb2aab0e 3726 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
mbed_official 354:e67efb2aab0e 3727 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
mbed_official 354:e67efb2aab0e 3728 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
mbed_official 354:e67efb2aab0e 3729 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
mbed_official 354:e67efb2aab0e 3730 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
mbed_official 354:e67efb2aab0e 3731 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
mbed_official 354:e67efb2aab0e 3732 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
mbed_official 354:e67efb2aab0e 3733 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
mbed_official 354:e67efb2aab0e 3734 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
mbed_official 354:e67efb2aab0e 3735 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
mbed_official 354:e67efb2aab0e 3736 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
mbed_official 354:e67efb2aab0e 3737 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
mbed_official 354:e67efb2aab0e 3738 #define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
mbed_official 354:e67efb2aab0e 3739
mbed_official 354:e67efb2aab0e 3740 /******************** Bit definition for RI_ASCR2 register ********************/
mbed_official 354:e67efb2aab0e 3741 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
mbed_official 354:e67efb2aab0e 3742 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
mbed_official 354:e67efb2aab0e 3743 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
mbed_official 354:e67efb2aab0e 3744 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
mbed_official 354:e67efb2aab0e 3745 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
mbed_official 354:e67efb2aab0e 3746 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
mbed_official 354:e67efb2aab0e 3747 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
mbed_official 354:e67efb2aab0e 3748 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
mbed_official 354:e67efb2aab0e 3749 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
mbed_official 354:e67efb2aab0e 3750 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
mbed_official 354:e67efb2aab0e 3751 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
mbed_official 354:e67efb2aab0e 3752 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
mbed_official 354:e67efb2aab0e 3753 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
mbed_official 354:e67efb2aab0e 3754 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
mbed_official 354:e67efb2aab0e 3755 #define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */
mbed_official 354:e67efb2aab0e 3756 #define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */
mbed_official 354:e67efb2aab0e 3757 #define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */
mbed_official 354:e67efb2aab0e 3758 #define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */
mbed_official 354:e67efb2aab0e 3759 #define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */
mbed_official 354:e67efb2aab0e 3760 #define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */
mbed_official 354:e67efb2aab0e 3761 #define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */
mbed_official 354:e67efb2aab0e 3762 #define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */
mbed_official 354:e67efb2aab0e 3763 #define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */
mbed_official 354:e67efb2aab0e 3764 #define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */
mbed_official 354:e67efb2aab0e 3765 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
mbed_official 354:e67efb2aab0e 3766 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
mbed_official 354:e67efb2aab0e 3767
mbed_official 354:e67efb2aab0e 3768 /******************** Bit definition for RI_HYSCR1 register ********************/
mbed_official 354:e67efb2aab0e 3769 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
mbed_official 354:e67efb2aab0e 3770 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3771 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3772 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3773 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3774 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3775 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3776 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3777 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3778 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3779 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3780 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3781 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3782 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3783 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3784 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3785 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3786
mbed_official 354:e67efb2aab0e 3787 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
mbed_official 354:e67efb2aab0e 3788 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3789 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3790 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3791 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3792 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3793 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3794 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3795 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3796 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3797 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3798 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3799 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3800 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3801 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3802 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3803 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3804
mbed_official 354:e67efb2aab0e 3805 /******************** Bit definition for RI_HYSCR2 register ********************/
mbed_official 354:e67efb2aab0e 3806 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
mbed_official 354:e67efb2aab0e 3807 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3808 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3809 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3810 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3811 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3812 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3813 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3814 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3815 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3816 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3817 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3818 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3819 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3820 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3821 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3822 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3823
mbed_official 354:e67efb2aab0e 3824 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
mbed_official 354:e67efb2aab0e 3825 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3826 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3827 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3828 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3829 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3830 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3831 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3832 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3833 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3834 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3835 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3836 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3837 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3838 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3839 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3840 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3841
mbed_official 354:e67efb2aab0e 3842 /******************** Bit definition for RI_HYSCR3 register ********************/
mbed_official 354:e67efb2aab0e 3843 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
mbed_official 354:e67efb2aab0e 3844 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3845 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3846 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3847 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3848 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3849 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3850 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3851 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3852 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3853 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3854 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3855 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3856 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3857 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3858 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3859 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3860 #define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
mbed_official 354:e67efb2aab0e 3861 #define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3862 #define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3863 #define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3864 #define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3865 #define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3866 #define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3867 #define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3868 #define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3869 #define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3870 #define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3871 #define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3872 #define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3873 #define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3874 #define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3875 #define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3876 #define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3877
mbed_official 354:e67efb2aab0e 3878 /******************** Bit definition for RI_HYSCR4 register ********************/
mbed_official 354:e67efb2aab0e 3879 #define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
mbed_official 354:e67efb2aab0e 3880 #define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3881 #define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3882 #define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3883 #define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3884 #define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3885 #define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3886 #define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3887 #define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3888 #define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3889 #define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3890 #define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3891 #define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3892 #define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3893 #define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3894 #define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3895 #define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3896
mbed_official 354:e67efb2aab0e 3897 /******************** Bit definition for RI_ASMR1 register ********************/
mbed_official 354:e67efb2aab0e 3898 #define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 354:e67efb2aab0e 3899 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3900 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3901 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3902 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3903 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3904 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3905 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3906 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3907 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3908 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3909 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3910 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3911 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3912 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3913 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3914 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3915
mbed_official 354:e67efb2aab0e 3916 /******************** Bit definition for RI_CMR1 register ********************/
mbed_official 354:e67efb2aab0e 3917 #define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 354:e67efb2aab0e 3918 #define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3919 #define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3920 #define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3921 #define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3922 #define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3923 #define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3924 #define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3925 #define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3926 #define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3927 #define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3928 #define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3929 #define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3930 #define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3931 #define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3932 #define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3933 #define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3934
mbed_official 354:e67efb2aab0e 3935 /******************** Bit definition for RI_CICR1 register ********************/
mbed_official 354:e67efb2aab0e 3936 #define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 354:e67efb2aab0e 3937 #define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3938 #define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3939 #define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3940 #define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3941 #define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3942 #define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3943 #define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3944 #define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3945 #define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3946 #define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3947 #define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3948 #define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3949 #define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3950 #define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3951 #define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3952 #define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3953
mbed_official 354:e67efb2aab0e 3954 /******************** Bit definition for RI_ASMR2 register ********************/
mbed_official 354:e67efb2aab0e 3955 #define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 354:e67efb2aab0e 3956 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3957 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3958 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3959 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3960 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3961 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3962 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3963 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3964 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3965 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3966 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3967 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3968 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3969 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3970 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3971 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3972
mbed_official 354:e67efb2aab0e 3973 /******************** Bit definition for RI_CMR2 register ********************/
mbed_official 354:e67efb2aab0e 3974 #define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 354:e67efb2aab0e 3975 #define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3976 #define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3977 #define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3978 #define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3979 #define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3980 #define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 3981 #define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 3982 #define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 3983 #define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 3984 #define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 3985 #define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 3986 #define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 3987 #define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 3988 #define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 3989 #define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 3990 #define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 3991
mbed_official 354:e67efb2aab0e 3992 /******************** Bit definition for RI_CICR2 register ********************/
mbed_official 354:e67efb2aab0e 3993 #define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 354:e67efb2aab0e 3994 #define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 3995 #define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 3996 #define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 3997 #define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 3998 #define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 3999 #define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4000 #define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4001 #define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4002 #define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4003 #define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4004 #define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4005 #define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4006 #define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4007 #define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4008 #define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4009 #define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4010
mbed_official 354:e67efb2aab0e 4011 /******************** Bit definition for RI_ASMR3 register ********************/
mbed_official 354:e67efb2aab0e 4012 #define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 354:e67efb2aab0e 4013 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4014 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4015 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4016 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4017 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4018 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4019 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4020 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4021 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4022 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4023 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4024 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4025 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4026 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4027 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4028 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4029
mbed_official 354:e67efb2aab0e 4030 /******************** Bit definition for RI_CMR3 register ********************/
mbed_official 354:e67efb2aab0e 4031 #define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 354:e67efb2aab0e 4032 #define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4033 #define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4034 #define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4035 #define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4036 #define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4037 #define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4038 #define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4039 #define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4040 #define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4041 #define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4042 #define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4043 #define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4044 #define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4045 #define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4046 #define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4047 #define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4048
mbed_official 354:e67efb2aab0e 4049 /******************** Bit definition for RI_CICR3 register ********************/
mbed_official 354:e67efb2aab0e 4050 #define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 354:e67efb2aab0e 4051 #define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4052 #define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4053 #define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4054 #define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4055 #define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4056 #define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4057 #define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4058 #define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4059 #define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4060 #define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4061 #define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4062 #define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4063 #define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4064 #define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4065 #define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4066 #define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4067
mbed_official 354:e67efb2aab0e 4068 /******************** Bit definition for RI_ASMR4 register ********************/
mbed_official 354:e67efb2aab0e 4069 #define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
mbed_official 354:e67efb2aab0e 4070 #define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4071 #define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4072 #define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4073 #define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4074 #define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4075 #define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4076 #define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4077 #define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4078 #define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4079 #define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4080 #define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4081 #define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4082 #define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4083 #define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4084 #define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4085 #define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4086
mbed_official 354:e67efb2aab0e 4087 /******************** Bit definition for RI_CMR4 register ********************/
mbed_official 354:e67efb2aab0e 4088 #define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
mbed_official 354:e67efb2aab0e 4089 #define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4090 #define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4091 #define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4092 #define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4093 #define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4094 #define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4095 #define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4096 #define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4097 #define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4098 #define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4099 #define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4100 #define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4101 #define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4102 #define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4103 #define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4104 #define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4105
mbed_official 354:e67efb2aab0e 4106 /******************** Bit definition for RI_CICR4 register ********************/
mbed_official 354:e67efb2aab0e 4107 #define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
mbed_official 354:e67efb2aab0e 4108 #define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4109 #define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4110 #define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4111 #define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4112 #define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4113 #define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4114 #define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4115 #define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4116 #define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4117 #define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4118 #define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4119 #define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4120 #define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4121 #define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4122 #define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4123 #define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4124
mbed_official 354:e67efb2aab0e 4125 /******************** Bit definition for RI_ASMR5 register ********************/
mbed_official 354:e67efb2aab0e 4126 #define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
mbed_official 354:e67efb2aab0e 4127 #define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4128 #define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4129 #define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4130 #define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4131 #define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4132 #define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4133 #define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4134 #define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4135 #define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4136 #define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4137 #define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4138 #define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4139 #define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4140 #define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4141 #define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4142 #define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4143
mbed_official 354:e67efb2aab0e 4144 /******************** Bit definition for RI_CMR5 register ********************/
mbed_official 354:e67efb2aab0e 4145 #define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
mbed_official 354:e67efb2aab0e 4146 #define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4147 #define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4148 #define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4149 #define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4150 #define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4151 #define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4152 #define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4153 #define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4154 #define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4155 #define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4156 #define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4157 #define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4158 #define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4159 #define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4160 #define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4161 #define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4162
mbed_official 354:e67efb2aab0e 4163 /******************** Bit definition for RI_CICR5 register ********************/
mbed_official 354:e67efb2aab0e 4164 #define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
mbed_official 354:e67efb2aab0e 4165 #define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4166 #define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4167 #define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4168 #define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4169 #define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4170 #define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4171 #define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4172 #define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4173 #define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 354:e67efb2aab0e 4174 #define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 354:e67efb2aab0e 4175 #define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 354:e67efb2aab0e 4176 #define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 354:e67efb2aab0e 4177 #define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 354:e67efb2aab0e 4178 #define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 354:e67efb2aab0e 4179 #define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 354:e67efb2aab0e 4180 #define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 354:e67efb2aab0e 4181
mbed_official 354:e67efb2aab0e 4182 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4183 /* */
mbed_official 354:e67efb2aab0e 4184 /* Timers (TIM) */
mbed_official 354:e67efb2aab0e 4185 /* */
mbed_official 354:e67efb2aab0e 4186 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4187
mbed_official 354:e67efb2aab0e 4188 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 354:e67efb2aab0e 4189 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 354:e67efb2aab0e 4190 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 354:e67efb2aab0e 4191 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 354:e67efb2aab0e 4192 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 354:e67efb2aab0e 4193 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 354:e67efb2aab0e 4194
mbed_official 354:e67efb2aab0e 4195 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 354:e67efb2aab0e 4196 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4197 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4198
mbed_official 354:e67efb2aab0e 4199 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 354:e67efb2aab0e 4200
mbed_official 354:e67efb2aab0e 4201 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 354:e67efb2aab0e 4202 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4203 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4204
mbed_official 354:e67efb2aab0e 4205 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 354:e67efb2aab0e 4206 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 354:e67efb2aab0e 4207
mbed_official 354:e67efb2aab0e 4208 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 354:e67efb2aab0e 4209 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4210 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4211 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4212
mbed_official 354:e67efb2aab0e 4213 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 354:e67efb2aab0e 4214
mbed_official 354:e67efb2aab0e 4215 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 354:e67efb2aab0e 4216 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 354:e67efb2aab0e 4217 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4218 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4219 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4220
mbed_official 354:e67efb2aab0e 4221 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 354:e67efb2aab0e 4222
mbed_official 354:e67efb2aab0e 4223 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 354:e67efb2aab0e 4224 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4225 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4226 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4227
mbed_official 354:e67efb2aab0e 4228 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 354:e67efb2aab0e 4229
mbed_official 354:e67efb2aab0e 4230 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 354:e67efb2aab0e 4231 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4232 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4233 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4234 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4235
mbed_official 354:e67efb2aab0e 4236 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 354:e67efb2aab0e 4237 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4238 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4239
mbed_official 354:e67efb2aab0e 4240 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 354:e67efb2aab0e 4241 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 354:e67efb2aab0e 4242
mbed_official 354:e67efb2aab0e 4243 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 354:e67efb2aab0e 4244 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 354:e67efb2aab0e 4245 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 354:e67efb2aab0e 4246 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 354:e67efb2aab0e 4247 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 354:e67efb2aab0e 4248 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 354:e67efb2aab0e 4249 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 354:e67efb2aab0e 4250 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 354:e67efb2aab0e 4251 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 354:e67efb2aab0e 4252 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 354:e67efb2aab0e 4253 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 354:e67efb2aab0e 4254 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 354:e67efb2aab0e 4255 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
mbed_official 354:e67efb2aab0e 4256 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 354:e67efb2aab0e 4257
mbed_official 354:e67efb2aab0e 4258 /******************** Bit definition for TIM_SR register ********************/
mbed_official 354:e67efb2aab0e 4259 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 354:e67efb2aab0e 4260 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 354:e67efb2aab0e 4261 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 354:e67efb2aab0e 4262 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 354:e67efb2aab0e 4263 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 354:e67efb2aab0e 4264 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 354:e67efb2aab0e 4265 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 354:e67efb2aab0e 4266 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 354:e67efb2aab0e 4267 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 354:e67efb2aab0e 4268 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 354:e67efb2aab0e 4269
mbed_official 354:e67efb2aab0e 4270 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 354:e67efb2aab0e 4271 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 354:e67efb2aab0e 4272 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 354:e67efb2aab0e 4273 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 354:e67efb2aab0e 4274 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 354:e67efb2aab0e 4275 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 354:e67efb2aab0e 4276 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 354:e67efb2aab0e 4277
mbed_official 354:e67efb2aab0e 4278 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 354:e67efb2aab0e 4279 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 354:e67efb2aab0e 4280 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4281 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4282
mbed_official 354:e67efb2aab0e 4283 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 354:e67efb2aab0e 4284 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 354:e67efb2aab0e 4285
mbed_official 354:e67efb2aab0e 4286 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 354:e67efb2aab0e 4287 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4288 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4289 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4290
mbed_official 354:e67efb2aab0e 4291 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 354:e67efb2aab0e 4292
mbed_official 354:e67efb2aab0e 4293 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 354:e67efb2aab0e 4294 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4295 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4296
mbed_official 354:e67efb2aab0e 4297 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 354:e67efb2aab0e 4298 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 354:e67efb2aab0e 4299
mbed_official 354:e67efb2aab0e 4300 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 354:e67efb2aab0e 4301 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4302 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4303 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4304
mbed_official 354:e67efb2aab0e 4305 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 354:e67efb2aab0e 4306
mbed_official 354:e67efb2aab0e 4307 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4308
mbed_official 354:e67efb2aab0e 4309 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 354:e67efb2aab0e 4310 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4311 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4312
mbed_official 354:e67efb2aab0e 4313 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 354:e67efb2aab0e 4314 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4315 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4316 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4317 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4318
mbed_official 354:e67efb2aab0e 4319 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 354:e67efb2aab0e 4320 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4321 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4322
mbed_official 354:e67efb2aab0e 4323 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 354:e67efb2aab0e 4324 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4325 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4326 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4327 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4328
mbed_official 354:e67efb2aab0e 4329 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 354:e67efb2aab0e 4330 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 354:e67efb2aab0e 4331 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4332 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4333
mbed_official 354:e67efb2aab0e 4334 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 354:e67efb2aab0e 4335 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 354:e67efb2aab0e 4336
mbed_official 354:e67efb2aab0e 4337 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 354:e67efb2aab0e 4338 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4339 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4340 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4341
mbed_official 354:e67efb2aab0e 4342 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 354:e67efb2aab0e 4343
mbed_official 354:e67efb2aab0e 4344 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 354:e67efb2aab0e 4345 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4346 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4347
mbed_official 354:e67efb2aab0e 4348 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 354:e67efb2aab0e 4349 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 354:e67efb2aab0e 4350
mbed_official 354:e67efb2aab0e 4351 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 354:e67efb2aab0e 4352 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4353 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4354 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4355
mbed_official 354:e67efb2aab0e 4356 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 354:e67efb2aab0e 4357
mbed_official 354:e67efb2aab0e 4358 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4359
mbed_official 354:e67efb2aab0e 4360 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 354:e67efb2aab0e 4361 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4362 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4363
mbed_official 354:e67efb2aab0e 4364 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 354:e67efb2aab0e 4365 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4366 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4367 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4368 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4369
mbed_official 354:e67efb2aab0e 4370 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 354:e67efb2aab0e 4371 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4372 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4373
mbed_official 354:e67efb2aab0e 4374 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 354:e67efb2aab0e 4375 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4376 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4377 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4378 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4379
mbed_official 354:e67efb2aab0e 4380 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 354:e67efb2aab0e 4381 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 354:e67efb2aab0e 4382 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 354:e67efb2aab0e 4383 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 354:e67efb2aab0e 4384 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 354:e67efb2aab0e 4385 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 354:e67efb2aab0e 4386 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 354:e67efb2aab0e 4387 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 354:e67efb2aab0e 4388 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 354:e67efb2aab0e 4389 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 354:e67efb2aab0e 4390 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 354:e67efb2aab0e 4391 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 354:e67efb2aab0e 4392 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 354:e67efb2aab0e 4393
mbed_official 354:e67efb2aab0e 4394 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 354:e67efb2aab0e 4395 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
mbed_official 354:e67efb2aab0e 4396
mbed_official 354:e67efb2aab0e 4397 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 354:e67efb2aab0e 4398 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 354:e67efb2aab0e 4399
mbed_official 354:e67efb2aab0e 4400 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 354:e67efb2aab0e 4401 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
mbed_official 354:e67efb2aab0e 4402
mbed_official 354:e67efb2aab0e 4403 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 354:e67efb2aab0e 4404 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 354:e67efb2aab0e 4405
mbed_official 354:e67efb2aab0e 4406 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 354:e67efb2aab0e 4407 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 354:e67efb2aab0e 4408
mbed_official 354:e67efb2aab0e 4409 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 354:e67efb2aab0e 4410 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 354:e67efb2aab0e 4411
mbed_official 354:e67efb2aab0e 4412 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 354:e67efb2aab0e 4413 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 354:e67efb2aab0e 4414
mbed_official 354:e67efb2aab0e 4415 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 354:e67efb2aab0e 4416 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 354:e67efb2aab0e 4417 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4418 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4419 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4420 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4421 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 354:e67efb2aab0e 4422
mbed_official 354:e67efb2aab0e 4423 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 354:e67efb2aab0e 4424 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4425 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4426 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4427 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4428 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 354:e67efb2aab0e 4429
mbed_official 354:e67efb2aab0e 4430 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 354:e67efb2aab0e 4431 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 354:e67efb2aab0e 4432
mbed_official 354:e67efb2aab0e 4433 /******************* Bit definition for TIM_OR register *********************/
mbed_official 354:e67efb2aab0e 4434 #define TIM_OR_TI1RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
mbed_official 354:e67efb2aab0e 4435 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4436 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4437
mbed_official 354:e67efb2aab0e 4438 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
mbed_official 354:e67efb2aab0e 4439 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
mbed_official 354:e67efb2aab0e 4440
mbed_official 354:e67efb2aab0e 4441 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4442 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
mbed_official 354:e67efb2aab0e 4443
mbed_official 354:e67efb2aab0e 4444 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4445 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
mbed_official 354:e67efb2aab0e 4446
mbed_official 354:e67efb2aab0e 4447 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4448 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
mbed_official 354:e67efb2aab0e 4449
mbed_official 354:e67efb2aab0e 4450 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4451
mbed_official 354:e67efb2aab0e 4452
mbed_official 354:e67efb2aab0e 4453 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4454 /* */
mbed_official 354:e67efb2aab0e 4455 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 354:e67efb2aab0e 4456 /* */
mbed_official 354:e67efb2aab0e 4457 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4458
mbed_official 354:e67efb2aab0e 4459 /******************* Bit definition for USART_SR register *******************/
mbed_official 354:e67efb2aab0e 4460 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 354:e67efb2aab0e 4461 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 354:e67efb2aab0e 4462 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
mbed_official 354:e67efb2aab0e 4463 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 354:e67efb2aab0e 4464 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 354:e67efb2aab0e 4465 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 354:e67efb2aab0e 4466 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 354:e67efb2aab0e 4467 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 354:e67efb2aab0e 4468 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 354:e67efb2aab0e 4469 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
mbed_official 354:e67efb2aab0e 4470
mbed_official 354:e67efb2aab0e 4471 /******************* Bit definition for USART_DR register *******************/
mbed_official 354:e67efb2aab0e 4472 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
mbed_official 354:e67efb2aab0e 4473
mbed_official 354:e67efb2aab0e 4474 /****************** Bit definition for USART_BRR register *******************/
mbed_official 354:e67efb2aab0e 4475 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 354:e67efb2aab0e 4476 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 354:e67efb2aab0e 4477
mbed_official 354:e67efb2aab0e 4478 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 354:e67efb2aab0e 4479 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
mbed_official 354:e67efb2aab0e 4480 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
mbed_official 354:e67efb2aab0e 4481 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 354:e67efb2aab0e 4482 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 354:e67efb2aab0e 4483 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 354:e67efb2aab0e 4484 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 354:e67efb2aab0e 4485 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 354:e67efb2aab0e 4486 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
mbed_official 354:e67efb2aab0e 4487 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 354:e67efb2aab0e 4488 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 354:e67efb2aab0e 4489 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 354:e67efb2aab0e 4490 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
mbed_official 354:e67efb2aab0e 4491 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 354:e67efb2aab0e 4492 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
mbed_official 354:e67efb2aab0e 4493 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit mode */
mbed_official 354:e67efb2aab0e 4494
mbed_official 354:e67efb2aab0e 4495 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 354:e67efb2aab0e 4496 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
mbed_official 354:e67efb2aab0e 4497 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 354:e67efb2aab0e 4498 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 354:e67efb2aab0e 4499 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 354:e67efb2aab0e 4500 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 354:e67efb2aab0e 4501 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 354:e67efb2aab0e 4502 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 354:e67efb2aab0e 4503
mbed_official 354:e67efb2aab0e 4504 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 354:e67efb2aab0e 4505 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4506 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4507
mbed_official 354:e67efb2aab0e 4508 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 354:e67efb2aab0e 4509
mbed_official 354:e67efb2aab0e 4510 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 354:e67efb2aab0e 4511 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 354:e67efb2aab0e 4512 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 354:e67efb2aab0e 4513 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 354:e67efb2aab0e 4514 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 354:e67efb2aab0e 4515 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
mbed_official 354:e67efb2aab0e 4516 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
mbed_official 354:e67efb2aab0e 4517 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 354:e67efb2aab0e 4518 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 354:e67efb2aab0e 4519 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 354:e67efb2aab0e 4520 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 354:e67efb2aab0e 4521 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 354:e67efb2aab0e 4522 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 354:e67efb2aab0e 4523
mbed_official 354:e67efb2aab0e 4524 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 354:e67efb2aab0e 4525 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 354:e67efb2aab0e 4526 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4527 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4528 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4529 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4530 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4531 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 4532 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 4533 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 354:e67efb2aab0e 4534
mbed_official 354:e67efb2aab0e 4535 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
mbed_official 354:e67efb2aab0e 4536
mbed_official 354:e67efb2aab0e 4537 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4538 /* */
mbed_official 354:e67efb2aab0e 4539 /* Universal Serial Bus (USB) */
mbed_official 354:e67efb2aab0e 4540 /* */
mbed_official 354:e67efb2aab0e 4541 /******************************************************************************/
mbed_official 354:e67efb2aab0e 4542
mbed_official 354:e67efb2aab0e 4543 /*!<Endpoint-specific registers */
mbed_official 354:e67efb2aab0e 4544
mbed_official 354:e67efb2aab0e 4545 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 354:e67efb2aab0e 4546 #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
mbed_official 354:e67efb2aab0e 4547 #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
mbed_official 354:e67efb2aab0e 4548 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
mbed_official 354:e67efb2aab0e 4549 #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
mbed_official 354:e67efb2aab0e 4550 #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
mbed_official 354:e67efb2aab0e 4551 #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
mbed_official 354:e67efb2aab0e 4552 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
mbed_official 354:e67efb2aab0e 4553
mbed_official 354:e67efb2aab0e 4554 /* bit positions */
mbed_official 354:e67efb2aab0e 4555 #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
mbed_official 354:e67efb2aab0e 4556 #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
mbed_official 354:e67efb2aab0e 4557 #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
mbed_official 354:e67efb2aab0e 4558 #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
mbed_official 354:e67efb2aab0e 4559 #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
mbed_official 354:e67efb2aab0e 4560 #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
mbed_official 354:e67efb2aab0e 4561 #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
mbed_official 354:e67efb2aab0e 4562 #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
mbed_official 354:e67efb2aab0e 4563 #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
mbed_official 354:e67efb2aab0e 4564 #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
mbed_official 354:e67efb2aab0e 4565
mbed_official 354:e67efb2aab0e 4566 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 354:e67efb2aab0e 4567 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 354:e67efb2aab0e 4568 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 354:e67efb2aab0e 4569 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
mbed_official 354:e67efb2aab0e 4570 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
mbed_official 354:e67efb2aab0e 4571 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
mbed_official 354:e67efb2aab0e 4572 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
mbed_official 354:e67efb2aab0e 4573 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
mbed_official 354:e67efb2aab0e 4574 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 354:e67efb2aab0e 4575
mbed_official 354:e67efb2aab0e 4576 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 354:e67efb2aab0e 4577 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 354:e67efb2aab0e 4578 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
mbed_official 354:e67efb2aab0e 4579 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
mbed_official 354:e67efb2aab0e 4580 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
mbed_official 354:e67efb2aab0e 4581 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
mbed_official 354:e67efb2aab0e 4582 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 354:e67efb2aab0e 4583 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 354:e67efb2aab0e 4584 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 354:e67efb2aab0e 4585 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 354:e67efb2aab0e 4586 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
mbed_official 354:e67efb2aab0e 4587 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
mbed_official 354:e67efb2aab0e 4588 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
mbed_official 354:e67efb2aab0e 4589 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
mbed_official 354:e67efb2aab0e 4590 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 354:e67efb2aab0e 4591 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 354:e67efb2aab0e 4592 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 354:e67efb2aab0e 4593
mbed_official 354:e67efb2aab0e 4594 /******************* Bit definition for USB_EP0R register *******************/
mbed_official 354:e67efb2aab0e 4595 #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4596
mbed_official 354:e67efb2aab0e 4597 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4598 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4599 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4600
mbed_official 354:e67efb2aab0e 4601 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4602 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4603 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4604
mbed_official 354:e67efb2aab0e 4605 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4606 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4607 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4608
mbed_official 354:e67efb2aab0e 4609 #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4610
mbed_official 354:e67efb2aab0e 4611 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4612 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4613 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4614
mbed_official 354:e67efb2aab0e 4615 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4616 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4617
mbed_official 354:e67efb2aab0e 4618 /******************* Bit definition for USB_EP1R register *******************/
mbed_official 354:e67efb2aab0e 4619 #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4620
mbed_official 354:e67efb2aab0e 4621 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4622 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4623 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4624
mbed_official 354:e67efb2aab0e 4625 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4626 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4627 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4628
mbed_official 354:e67efb2aab0e 4629 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4630 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4631 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4632
mbed_official 354:e67efb2aab0e 4633 #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4634
mbed_official 354:e67efb2aab0e 4635 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4636 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4637 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4638
mbed_official 354:e67efb2aab0e 4639 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4640 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4641
mbed_official 354:e67efb2aab0e 4642 /******************* Bit definition for USB_EP2R register *******************/
mbed_official 354:e67efb2aab0e 4643 #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4644
mbed_official 354:e67efb2aab0e 4645 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4646 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4647 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4648
mbed_official 354:e67efb2aab0e 4649 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4650 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4651 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4652
mbed_official 354:e67efb2aab0e 4653 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4654 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4655 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4656
mbed_official 354:e67efb2aab0e 4657 #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4658
mbed_official 354:e67efb2aab0e 4659 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4660 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4661 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4662
mbed_official 354:e67efb2aab0e 4663 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4664 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4665
mbed_official 354:e67efb2aab0e 4666 /******************* Bit definition for USB_EP3R register *******************/
mbed_official 354:e67efb2aab0e 4667 #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4668
mbed_official 354:e67efb2aab0e 4669 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4670 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4671 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4672
mbed_official 354:e67efb2aab0e 4673 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4674 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4675 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4676
mbed_official 354:e67efb2aab0e 4677 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4678 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4679 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4680
mbed_official 354:e67efb2aab0e 4681 #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4682
mbed_official 354:e67efb2aab0e 4683 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4684 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4685 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4686
mbed_official 354:e67efb2aab0e 4687 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4688 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4689
mbed_official 354:e67efb2aab0e 4690 /******************* Bit definition for USB_EP4R register *******************/
mbed_official 354:e67efb2aab0e 4691 #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4692
mbed_official 354:e67efb2aab0e 4693 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4694 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4695 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4696
mbed_official 354:e67efb2aab0e 4697 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4698 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4699 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4700
mbed_official 354:e67efb2aab0e 4701 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4702 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4703 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4704
mbed_official 354:e67efb2aab0e 4705 #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4706
mbed_official 354:e67efb2aab0e 4707 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4708 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4709 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4710
mbed_official 354:e67efb2aab0e 4711 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4712 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4713
mbed_official 354:e67efb2aab0e 4714 /******************* Bit definition for USB_EP5R register *******************/
mbed_official 354:e67efb2aab0e 4715 #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4716
mbed_official 354:e67efb2aab0e 4717 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4718 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4719 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4720
mbed_official 354:e67efb2aab0e 4721 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4722 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4723 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4724
mbed_official 354:e67efb2aab0e 4725 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4726 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4727 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4728
mbed_official 354:e67efb2aab0e 4729 #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4730
mbed_official 354:e67efb2aab0e 4731 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4732 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4733 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4734
mbed_official 354:e67efb2aab0e 4735 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4736 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4737
mbed_official 354:e67efb2aab0e 4738 /******************* Bit definition for USB_EP6R register *******************/
mbed_official 354:e67efb2aab0e 4739 #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4740
mbed_official 354:e67efb2aab0e 4741 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4742 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4743 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4744
mbed_official 354:e67efb2aab0e 4745 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4746 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4747 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4748
mbed_official 354:e67efb2aab0e 4749 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4750 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4751 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4752
mbed_official 354:e67efb2aab0e 4753 #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4754
mbed_official 354:e67efb2aab0e 4755 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4756 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4757 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4758
mbed_official 354:e67efb2aab0e 4759 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4760 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4761
mbed_official 354:e67efb2aab0e 4762 /******************* Bit definition for USB_EP7R register *******************/
mbed_official 354:e67efb2aab0e 4763 #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 354:e67efb2aab0e 4764
mbed_official 354:e67efb2aab0e 4765 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 354:e67efb2aab0e 4766 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4767 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4768
mbed_official 354:e67efb2aab0e 4769 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 354:e67efb2aab0e 4770 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 354:e67efb2aab0e 4771 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 354:e67efb2aab0e 4772
mbed_official 354:e67efb2aab0e 4773 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 354:e67efb2aab0e 4774 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4775 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4776
mbed_official 354:e67efb2aab0e 4777 #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 354:e67efb2aab0e 4778
mbed_official 354:e67efb2aab0e 4779 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 354:e67efb2aab0e 4780 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4781 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4782
mbed_official 354:e67efb2aab0e 4783 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 354:e67efb2aab0e 4784 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 354:e67efb2aab0e 4785
mbed_official 354:e67efb2aab0e 4786 /*!<Common registers */
mbed_official 354:e67efb2aab0e 4787
mbed_official 354:e67efb2aab0e 4788 #define USB_CNTR (USB_BASE + 0x00000040) /*!< Control register */
mbed_official 354:e67efb2aab0e 4789 #define USB_ISTR (USB_BASE + 0x00000044) /*!< Interrupt status register */
mbed_official 354:e67efb2aab0e 4790 #define USB_FNR (USB_BASE + 0x00000048) /*!< Frame number register */
mbed_official 354:e67efb2aab0e 4791 #define USB_DADDR (USB_BASE + 0x0000004C) /*!< Device address register */
mbed_official 354:e67efb2aab0e 4792 #define USB_BTABLE (USB_BASE + 0x00000050) /*!< Buffer Table address register */
mbed_official 354:e67efb2aab0e 4793
mbed_official 354:e67efb2aab0e 4794
mbed_official 354:e67efb2aab0e 4795
mbed_official 354:e67efb2aab0e 4796 /******************* Bit definition for USB_CNTR register *******************/
mbed_official 354:e67efb2aab0e 4797 #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!<Force USB Reset */
mbed_official 354:e67efb2aab0e 4798 #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!<Power down */
mbed_official 354:e67efb2aab0e 4799 #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!<Low-power mode */
mbed_official 354:e67efb2aab0e 4800 #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!<Force suspend */
mbed_official 354:e67efb2aab0e 4801 #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!<Resume request */
mbed_official 354:e67efb2aab0e 4802 #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!<Expected Start Of Frame Interrupt Mask */
mbed_official 354:e67efb2aab0e 4803 #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!<Start Of Frame Interrupt Mask */
mbed_official 354:e67efb2aab0e 4804 #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!<RESET Interrupt Mask */
mbed_official 354:e67efb2aab0e 4805 #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!<Suspend mode Interrupt Mask */
mbed_official 354:e67efb2aab0e 4806 #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!<Wakeup Interrupt Mask */
mbed_official 354:e67efb2aab0e 4807 #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!<Error Interrupt Mask */
mbed_official 354:e67efb2aab0e 4808 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
mbed_official 354:e67efb2aab0e 4809 #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!<Correct Transfer Interrupt Mask */
mbed_official 354:e67efb2aab0e 4810
mbed_official 354:e67efb2aab0e 4811 /******************* Bit definition for USB_ISTR register *******************/
mbed_official 354:e67efb2aab0e 4812 #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!<Endpoint Identifier */
mbed_official 354:e67efb2aab0e 4813 #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!<Direction of transaction */
mbed_official 354:e67efb2aab0e 4814 #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!<Expected Start Of Frame */
mbed_official 354:e67efb2aab0e 4815 #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!<Start Of Frame */
mbed_official 354:e67efb2aab0e 4816 #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!<USB RESET request */
mbed_official 354:e67efb2aab0e 4817 #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!<Suspend mode request */
mbed_official 354:e67efb2aab0e 4818 #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!<Wake up */
mbed_official 354:e67efb2aab0e 4819 #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!<Error */
mbed_official 354:e67efb2aab0e 4820 #define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun */
mbed_official 354:e67efb2aab0e 4821 #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!<Correct Transfer */
mbed_official 354:e67efb2aab0e 4822
mbed_official 354:e67efb2aab0e 4823 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 354:e67efb2aab0e 4824 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 354:e67efb2aab0e 4825 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 354:e67efb2aab0e 4826 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 354:e67efb2aab0e 4827 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 354:e67efb2aab0e 4828 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 354:e67efb2aab0e 4829 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 354:e67efb2aab0e 4830 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 354:e67efb2aab0e 4831
mbed_official 354:e67efb2aab0e 4832
mbed_official 354:e67efb2aab0e 4833 /******************* Bit definition for USB_FNR register ********************/
mbed_official 354:e67efb2aab0e 4834 #define USB_FNR_FN ((uint32_t)0x000007FF) /*!<Frame Number */
mbed_official 354:e67efb2aab0e 4835 #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!<Lost SOF */
mbed_official 354:e67efb2aab0e 4836 #define USB_FNR_LCK ((uint32_t)0x00002000) /*!<Locked */
mbed_official 354:e67efb2aab0e 4837 #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!<Receive Data - Line Status */
mbed_official 354:e67efb2aab0e 4838 #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!<Receive Data + Line Status */
mbed_official 354:e67efb2aab0e 4839
mbed_official 354:e67efb2aab0e 4840 /****************** Bit definition for USB_DADDR register *******************/
mbed_official 354:e67efb2aab0e 4841 #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!<ADD[6:0] bits (Device Address) */
mbed_official 354:e67efb2aab0e 4842 #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 354:e67efb2aab0e 4843 #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 354:e67efb2aab0e 4844 #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 354:e67efb2aab0e 4845 #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 354:e67efb2aab0e 4846 #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 354:e67efb2aab0e 4847 #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 354:e67efb2aab0e 4848 #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 354:e67efb2aab0e 4849
mbed_official 354:e67efb2aab0e 4850 #define USB_DADDR_EF ((uint32_t)0x00000080) /*!<Enable Function */
mbed_official 354:e67efb2aab0e 4851
mbed_official 354:e67efb2aab0e 4852 /****************** Bit definition for USB_BTABLE register ******************/
mbed_official 354:e67efb2aab0e 4853 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!<Buffer Table */
mbed_official 354:e67efb2aab0e 4854
mbed_official 354:e67efb2aab0e 4855 /*!< Buffer descriptor table */
mbed_official 354:e67efb2aab0e 4856 /***************** Bit definition for USB_ADDR0_TX register *****************/
mbed_official 354:e67efb2aab0e 4857 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
mbed_official 354:e67efb2aab0e 4858
mbed_official 354:e67efb2aab0e 4859 /***************** Bit definition for USB_ADDR1_TX register *****************/
mbed_official 354:e67efb2aab0e 4860 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
mbed_official 354:e67efb2aab0e 4861
mbed_official 354:e67efb2aab0e 4862 /***************** Bit definition for USB_ADDR2_TX register *****************/
mbed_official 354:e67efb2aab0e 4863 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
mbed_official 354:e67efb2aab0e 4864
mbed_official 354:e67efb2aab0e 4865 /***************** Bit definition for USB_ADDR3_TX register *****************/
mbed_official 354:e67efb2aab0e 4866 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
mbed_official 354:e67efb2aab0e 4867
mbed_official 354:e67efb2aab0e 4868 /***************** Bit definition for USB_ADDR4_TX register *****************/
mbed_official 354:e67efb2aab0e 4869 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
mbed_official 354:e67efb2aab0e 4870
mbed_official 354:e67efb2aab0e 4871 /***************** Bit definition for USB_ADDR5_TX register *****************/
mbed_official 354:e67efb2aab0e 4872 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
mbed_official 354:e67efb2aab0e 4873
mbed_official 354:e67efb2aab0e 4874 /***************** Bit definition for USB_ADDR6_TX register *****************/
mbed_official 354:e67efb2aab0e 4875 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
mbed_official 354:e67efb2aab0e 4876
mbed_official 354:e67efb2aab0e 4877 /***************** Bit definition for USB_ADDR7_TX register *****************/
mbed_official 354:e67efb2aab0e 4878 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
mbed_official 354:e67efb2aab0e 4879
mbed_official 354:e67efb2aab0e 4880 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4881
mbed_official 354:e67efb2aab0e 4882 /***************** Bit definition for USB_COUNT0_TX register ****************/
mbed_official 354:e67efb2aab0e 4883 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
mbed_official 354:e67efb2aab0e 4884
mbed_official 354:e67efb2aab0e 4885 /***************** Bit definition for USB_COUNT1_TX register ****************/
mbed_official 354:e67efb2aab0e 4886 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
mbed_official 354:e67efb2aab0e 4887
mbed_official 354:e67efb2aab0e 4888 /***************** Bit definition for USB_COUNT2_TX register ****************/
mbed_official 354:e67efb2aab0e 4889 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
mbed_official 354:e67efb2aab0e 4890
mbed_official 354:e67efb2aab0e 4891 /***************** Bit definition for USB_COUNT3_TX register ****************/
mbed_official 354:e67efb2aab0e 4892 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
mbed_official 354:e67efb2aab0e 4893
mbed_official 354:e67efb2aab0e 4894 /***************** Bit definition for USB_COUNT4_TX register ****************/
mbed_official 354:e67efb2aab0e 4895 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
mbed_official 354:e67efb2aab0e 4896
mbed_official 354:e67efb2aab0e 4897 /***************** Bit definition for USB_COUNT5_TX register ****************/
mbed_official 354:e67efb2aab0e 4898 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
mbed_official 354:e67efb2aab0e 4899
mbed_official 354:e67efb2aab0e 4900 /***************** Bit definition for USB_COUNT6_TX register ****************/
mbed_official 354:e67efb2aab0e 4901 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
mbed_official 354:e67efb2aab0e 4902
mbed_official 354:e67efb2aab0e 4903 /***************** Bit definition for USB_COUNT7_TX register ****************/
mbed_official 354:e67efb2aab0e 4904 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
mbed_official 354:e67efb2aab0e 4905
mbed_official 354:e67efb2aab0e 4906 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4907
mbed_official 354:e67efb2aab0e 4908 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4909 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
mbed_official 354:e67efb2aab0e 4910
mbed_official 354:e67efb2aab0e 4911 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4912 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
mbed_official 354:e67efb2aab0e 4913
mbed_official 354:e67efb2aab0e 4914 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4915 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
mbed_official 354:e67efb2aab0e 4916
mbed_official 354:e67efb2aab0e 4917 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4918 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
mbed_official 354:e67efb2aab0e 4919
mbed_official 354:e67efb2aab0e 4920 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4921 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
mbed_official 354:e67efb2aab0e 4922
mbed_official 354:e67efb2aab0e 4923 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4924 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
mbed_official 354:e67efb2aab0e 4925
mbed_official 354:e67efb2aab0e 4926 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4927 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /*!< Transmission Byte Count 3 (low) */
mbed_official 354:e67efb2aab0e 4928
mbed_official 354:e67efb2aab0e 4929 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4930 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /*!< Transmission Byte Count 3 (high) */
mbed_official 354:e67efb2aab0e 4931
mbed_official 354:e67efb2aab0e 4932 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4933 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
mbed_official 354:e67efb2aab0e 4934
mbed_official 354:e67efb2aab0e 4935 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4936 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
mbed_official 354:e67efb2aab0e 4937
mbed_official 354:e67efb2aab0e 4938 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4939 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
mbed_official 354:e67efb2aab0e 4940
mbed_official 354:e67efb2aab0e 4941 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4942 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
mbed_official 354:e67efb2aab0e 4943
mbed_official 354:e67efb2aab0e 4944 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4945 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
mbed_official 354:e67efb2aab0e 4946
mbed_official 354:e67efb2aab0e 4947 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4948 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
mbed_official 354:e67efb2aab0e 4949
mbed_official 354:e67efb2aab0e 4950 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
mbed_official 354:e67efb2aab0e 4951 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
mbed_official 354:e67efb2aab0e 4952
mbed_official 354:e67efb2aab0e 4953 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
mbed_official 354:e67efb2aab0e 4954 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
mbed_official 354:e67efb2aab0e 4955
mbed_official 354:e67efb2aab0e 4956 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4957
mbed_official 354:e67efb2aab0e 4958 /***************** Bit definition for USB_ADDR0_RX register *****************/
mbed_official 354:e67efb2aab0e 4959 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
mbed_official 354:e67efb2aab0e 4960
mbed_official 354:e67efb2aab0e 4961 /***************** Bit definition for USB_ADDR1_RX register *****************/
mbed_official 354:e67efb2aab0e 4962 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
mbed_official 354:e67efb2aab0e 4963
mbed_official 354:e67efb2aab0e 4964 /***************** Bit definition for USB_ADDR2_RX register *****************/
mbed_official 354:e67efb2aab0e 4965 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
mbed_official 354:e67efb2aab0e 4966
mbed_official 354:e67efb2aab0e 4967 /***************** Bit definition for USB_ADDR3_RX register *****************/
mbed_official 354:e67efb2aab0e 4968 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
mbed_official 354:e67efb2aab0e 4969
mbed_official 354:e67efb2aab0e 4970 /***************** Bit definition for USB_ADDR4_RX register *****************/
mbed_official 354:e67efb2aab0e 4971 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
mbed_official 354:e67efb2aab0e 4972
mbed_official 354:e67efb2aab0e 4973 /***************** Bit definition for USB_ADDR5_RX register *****************/
mbed_official 354:e67efb2aab0e 4974 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
mbed_official 354:e67efb2aab0e 4975
mbed_official 354:e67efb2aab0e 4976 /***************** Bit definition for USB_ADDR6_RX register *****************/
mbed_official 354:e67efb2aab0e 4977 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
mbed_official 354:e67efb2aab0e 4978
mbed_official 354:e67efb2aab0e 4979 /***************** Bit definition for USB_ADDR7_RX register *****************/
mbed_official 354:e67efb2aab0e 4980 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
mbed_official 354:e67efb2aab0e 4981
mbed_official 354:e67efb2aab0e 4982 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 4983
mbed_official 354:e67efb2aab0e 4984 /***************** Bit definition for USB_COUNT0_RX register ****************/
mbed_official 354:e67efb2aab0e 4985 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 4986
mbed_official 354:e67efb2aab0e 4987 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 4988 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 4989 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 4990 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 4991 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 4992 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 4993
mbed_official 354:e67efb2aab0e 4994 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 4995
mbed_official 354:e67efb2aab0e 4996 /***************** Bit definition for USB_COUNT1_RX register ****************/
mbed_official 354:e67efb2aab0e 4997 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 4998
mbed_official 354:e67efb2aab0e 4999 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5000 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5001 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5002 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5003 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5004 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5005
mbed_official 354:e67efb2aab0e 5006 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5007
mbed_official 354:e67efb2aab0e 5008 /***************** Bit definition for USB_COUNT2_RX register ****************/
mbed_official 354:e67efb2aab0e 5009 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5010
mbed_official 354:e67efb2aab0e 5011 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5012 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5013 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5014 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5015 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5016 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5017
mbed_official 354:e67efb2aab0e 5018 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5019
mbed_official 354:e67efb2aab0e 5020 /***************** Bit definition for USB_COUNT3_RX register ****************/
mbed_official 354:e67efb2aab0e 5021 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5022
mbed_official 354:e67efb2aab0e 5023 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5024 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5025 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5026 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5027 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5028 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5029
mbed_official 354:e67efb2aab0e 5030 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5031
mbed_official 354:e67efb2aab0e 5032 /***************** Bit definition for USB_COUNT4_RX register ****************/
mbed_official 354:e67efb2aab0e 5033 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5034
mbed_official 354:e67efb2aab0e 5035 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5036 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5037 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5038 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5039 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5040 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5041
mbed_official 354:e67efb2aab0e 5042 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5043
mbed_official 354:e67efb2aab0e 5044 /***************** Bit definition for USB_COUNT5_RX register ****************/
mbed_official 354:e67efb2aab0e 5045 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5046
mbed_official 354:e67efb2aab0e 5047 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5048 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5049 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5050 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5051 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5052 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5053
mbed_official 354:e67efb2aab0e 5054 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5055
mbed_official 354:e67efb2aab0e 5056 /***************** Bit definition for USB_COUNT6_RX register ****************/
mbed_official 354:e67efb2aab0e 5057 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5058
mbed_official 354:e67efb2aab0e 5059 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5060 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5061 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5062 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5063 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5064 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5065
mbed_official 354:e67efb2aab0e 5066 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5067
mbed_official 354:e67efb2aab0e 5068 /***************** Bit definition for USB_COUNT7_RX register ****************/
mbed_official 354:e67efb2aab0e 5069 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 354:e67efb2aab0e 5070
mbed_official 354:e67efb2aab0e 5071 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 354:e67efb2aab0e 5072 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5073 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5074 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5075 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5076 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5077
mbed_official 354:e67efb2aab0e 5078 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 354:e67efb2aab0e 5079
mbed_official 354:e67efb2aab0e 5080 /*----------------------------------------------------------------------------*/
mbed_official 354:e67efb2aab0e 5081
mbed_official 354:e67efb2aab0e 5082 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5083 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5084
mbed_official 354:e67efb2aab0e 5085 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5086 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5087 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5088 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5089 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5090 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5091
mbed_official 354:e67efb2aab0e 5092 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5093
mbed_official 354:e67efb2aab0e 5094 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5095 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5096
mbed_official 354:e67efb2aab0e 5097 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5098 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5099 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5100 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5101 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5102 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5103
mbed_official 354:e67efb2aab0e 5104 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5105
mbed_official 354:e67efb2aab0e 5106 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5107 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5108
mbed_official 354:e67efb2aab0e 5109 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5110 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5111 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5112 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5113 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5114 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5115
mbed_official 354:e67efb2aab0e 5116 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5117
mbed_official 354:e67efb2aab0e 5118 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5119 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5120
mbed_official 354:e67efb2aab0e 5121 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5122 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5123 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5124 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5125 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5126 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5127
mbed_official 354:e67efb2aab0e 5128 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5129
mbed_official 354:e67efb2aab0e 5130 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5131 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5132
mbed_official 354:e67efb2aab0e 5133 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5134 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5135 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5136 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5137 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5138 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5139
mbed_official 354:e67efb2aab0e 5140 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5141
mbed_official 354:e67efb2aab0e 5142 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5143 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5144
mbed_official 354:e67efb2aab0e 5145 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5146 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5147 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5148 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5149 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5150 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5151
mbed_official 354:e67efb2aab0e 5152 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5153
mbed_official 354:e67efb2aab0e 5154 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5155 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5156
mbed_official 354:e67efb2aab0e 5157 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5158 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5159 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5160 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5161 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5162 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5163
mbed_official 354:e67efb2aab0e 5164 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5165
mbed_official 354:e67efb2aab0e 5166 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5167 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5168
mbed_official 354:e67efb2aab0e 5169 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5170 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5171 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5172 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5173 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5174 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5175
mbed_official 354:e67efb2aab0e 5176 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5177
mbed_official 354:e67efb2aab0e 5178 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5179 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5180
mbed_official 354:e67efb2aab0e 5181 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5182 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5183 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5184 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5185 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5186 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5187
mbed_official 354:e67efb2aab0e 5188 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5189
mbed_official 354:e67efb2aab0e 5190 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5191 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5192
mbed_official 354:e67efb2aab0e 5193 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5194 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5195 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5196 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5197 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5198 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5199
mbed_official 354:e67efb2aab0e 5200 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5201
mbed_official 354:e67efb2aab0e 5202 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5203 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5204
mbed_official 354:e67efb2aab0e 5205 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5206 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5207 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5208 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5209 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5210 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5211
mbed_official 354:e67efb2aab0e 5212 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5213
mbed_official 354:e67efb2aab0e 5214 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5215 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5216
mbed_official 354:e67efb2aab0e 5217 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5218 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5219 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5220 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5221 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5222 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5223
mbed_official 354:e67efb2aab0e 5224 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5225
mbed_official 354:e67efb2aab0e 5226 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
mbed_official 354:e67efb2aab0e 5227 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5228
mbed_official 354:e67efb2aab0e 5229 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5230 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5231 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5232 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5233 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5234 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5235
mbed_official 354:e67efb2aab0e 5236 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5237
mbed_official 354:e67efb2aab0e 5238 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
mbed_official 354:e67efb2aab0e 5239 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5240
mbed_official 354:e67efb2aab0e 5241 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5242 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5243 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5244 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5245 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5246 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5247
mbed_official 354:e67efb2aab0e 5248 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5249
mbed_official 354:e67efb2aab0e 5250 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
mbed_official 354:e67efb2aab0e 5251 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 354:e67efb2aab0e 5252
mbed_official 354:e67efb2aab0e 5253 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 354:e67efb2aab0e 5254 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5255 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5256 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5257 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5258 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5259
mbed_official 354:e67efb2aab0e 5260 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 354:e67efb2aab0e 5261
mbed_official 354:e67efb2aab0e 5262 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
mbed_official 354:e67efb2aab0e 5263 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 354:e67efb2aab0e 5264
mbed_official 354:e67efb2aab0e 5265 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 354:e67efb2aab0e 5266 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5267 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5268 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5269 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5270 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5271
mbed_official 354:e67efb2aab0e 5272 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 354:e67efb2aab0e 5273
mbed_official 354:e67efb2aab0e 5274 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5275 /* */
mbed_official 354:e67efb2aab0e 5276 /* Window WATCHDOG (WWDG) */
mbed_official 354:e67efb2aab0e 5277 /* */
mbed_official 354:e67efb2aab0e 5278 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5279
mbed_official 354:e67efb2aab0e 5280 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 354:e67efb2aab0e 5281 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 354:e67efb2aab0e 5282 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5283 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5284 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5285 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5286 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5287 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 5288 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 5289
mbed_official 354:e67efb2aab0e 5290 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
mbed_official 354:e67efb2aab0e 5291
mbed_official 354:e67efb2aab0e 5292 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 354:e67efb2aab0e 5293 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
mbed_official 354:e67efb2aab0e 5294 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5295 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5296 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5297 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 354:e67efb2aab0e 5298 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 354:e67efb2aab0e 5299 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 354:e67efb2aab0e 5300 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 354:e67efb2aab0e 5301
mbed_official 354:e67efb2aab0e 5302 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
mbed_official 354:e67efb2aab0e 5303 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5304 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5305
mbed_official 354:e67efb2aab0e 5306 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
mbed_official 354:e67efb2aab0e 5307
mbed_official 354:e67efb2aab0e 5308 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 354:e67efb2aab0e 5309 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
mbed_official 354:e67efb2aab0e 5310
mbed_official 354:e67efb2aab0e 5311 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5312 /* */
mbed_official 354:e67efb2aab0e 5313 /* SystemTick (SysTick) */
mbed_official 354:e67efb2aab0e 5314 /* */
mbed_official 354:e67efb2aab0e 5315 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5316
mbed_official 354:e67efb2aab0e 5317 /***************** Bit definition for SysTick_CTRL register *****************/
mbed_official 354:e67efb2aab0e 5318 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
mbed_official 354:e67efb2aab0e 5319 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
mbed_official 354:e67efb2aab0e 5320 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
mbed_official 354:e67efb2aab0e 5321 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
mbed_official 354:e67efb2aab0e 5322
mbed_official 354:e67efb2aab0e 5323 /***************** Bit definition for SysTick_LOAD register *****************/
mbed_official 354:e67efb2aab0e 5324 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
mbed_official 354:e67efb2aab0e 5325
mbed_official 354:e67efb2aab0e 5326 /***************** Bit definition for SysTick_VAL register ******************/
mbed_official 354:e67efb2aab0e 5327 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
mbed_official 354:e67efb2aab0e 5328
mbed_official 354:e67efb2aab0e 5329 /***************** Bit definition for SysTick_CALIB register ****************/
mbed_official 354:e67efb2aab0e 5330 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
mbed_official 354:e67efb2aab0e 5331 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
mbed_official 354:e67efb2aab0e 5332 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
mbed_official 354:e67efb2aab0e 5333
mbed_official 354:e67efb2aab0e 5334 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5335 /* */
mbed_official 354:e67efb2aab0e 5336 /* Nested Vectored Interrupt Controller (NVIC) */
mbed_official 354:e67efb2aab0e 5337 /* */
mbed_official 354:e67efb2aab0e 5338 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5339
mbed_official 354:e67efb2aab0e 5340 /****************** Bit definition for NVIC_ISER register *******************/
mbed_official 354:e67efb2aab0e 5341 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
mbed_official 354:e67efb2aab0e 5342 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 354:e67efb2aab0e 5343 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 354:e67efb2aab0e 5344 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 354:e67efb2aab0e 5345 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 354:e67efb2aab0e 5346 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 354:e67efb2aab0e 5347 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 354:e67efb2aab0e 5348 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 354:e67efb2aab0e 5349 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 354:e67efb2aab0e 5350 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 354:e67efb2aab0e 5351 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 354:e67efb2aab0e 5352 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 354:e67efb2aab0e 5353 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 354:e67efb2aab0e 5354 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 354:e67efb2aab0e 5355 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 354:e67efb2aab0e 5356 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 354:e67efb2aab0e 5357 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 354:e67efb2aab0e 5358 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 354:e67efb2aab0e 5359 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 354:e67efb2aab0e 5360 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 354:e67efb2aab0e 5361 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 354:e67efb2aab0e 5362 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 354:e67efb2aab0e 5363 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 354:e67efb2aab0e 5364 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 354:e67efb2aab0e 5365 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 354:e67efb2aab0e 5366 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 354:e67efb2aab0e 5367 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 354:e67efb2aab0e 5368 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 354:e67efb2aab0e 5369 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 354:e67efb2aab0e 5370 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 354:e67efb2aab0e 5371 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 354:e67efb2aab0e 5372 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 354:e67efb2aab0e 5373 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 354:e67efb2aab0e 5374
mbed_official 354:e67efb2aab0e 5375 /****************** Bit definition for NVIC_ICER register *******************/
mbed_official 354:e67efb2aab0e 5376 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
mbed_official 354:e67efb2aab0e 5377 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 354:e67efb2aab0e 5378 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 354:e67efb2aab0e 5379 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 354:e67efb2aab0e 5380 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 354:e67efb2aab0e 5381 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 354:e67efb2aab0e 5382 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 354:e67efb2aab0e 5383 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 354:e67efb2aab0e 5384 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 354:e67efb2aab0e 5385 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 354:e67efb2aab0e 5386 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 354:e67efb2aab0e 5387 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 354:e67efb2aab0e 5388 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 354:e67efb2aab0e 5389 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 354:e67efb2aab0e 5390 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 354:e67efb2aab0e 5391 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 354:e67efb2aab0e 5392 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 354:e67efb2aab0e 5393 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 354:e67efb2aab0e 5394 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 354:e67efb2aab0e 5395 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 354:e67efb2aab0e 5396 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 354:e67efb2aab0e 5397 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 354:e67efb2aab0e 5398 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 354:e67efb2aab0e 5399 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 354:e67efb2aab0e 5400 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 354:e67efb2aab0e 5401 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 354:e67efb2aab0e 5402 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 354:e67efb2aab0e 5403 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 354:e67efb2aab0e 5404 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 354:e67efb2aab0e 5405 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 354:e67efb2aab0e 5406 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 354:e67efb2aab0e 5407 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 354:e67efb2aab0e 5408 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 354:e67efb2aab0e 5409
mbed_official 354:e67efb2aab0e 5410 /****************** Bit definition for NVIC_ISPR register *******************/
mbed_official 354:e67efb2aab0e 5411 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
mbed_official 354:e67efb2aab0e 5412 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 354:e67efb2aab0e 5413 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 354:e67efb2aab0e 5414 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 354:e67efb2aab0e 5415 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 354:e67efb2aab0e 5416 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 354:e67efb2aab0e 5417 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 354:e67efb2aab0e 5418 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 354:e67efb2aab0e 5419 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 354:e67efb2aab0e 5420 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 354:e67efb2aab0e 5421 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 354:e67efb2aab0e 5422 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 354:e67efb2aab0e 5423 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 354:e67efb2aab0e 5424 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 354:e67efb2aab0e 5425 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 354:e67efb2aab0e 5426 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 354:e67efb2aab0e 5427 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 354:e67efb2aab0e 5428 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 354:e67efb2aab0e 5429 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 354:e67efb2aab0e 5430 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 354:e67efb2aab0e 5431 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 354:e67efb2aab0e 5432 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 354:e67efb2aab0e 5433 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 354:e67efb2aab0e 5434 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 354:e67efb2aab0e 5435 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 354:e67efb2aab0e 5436 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 354:e67efb2aab0e 5437 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 354:e67efb2aab0e 5438 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 354:e67efb2aab0e 5439 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 354:e67efb2aab0e 5440 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 354:e67efb2aab0e 5441 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 354:e67efb2aab0e 5442 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 354:e67efb2aab0e 5443 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 354:e67efb2aab0e 5444
mbed_official 354:e67efb2aab0e 5445 /****************** Bit definition for NVIC_ICPR register *******************/
mbed_official 354:e67efb2aab0e 5446 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
mbed_official 354:e67efb2aab0e 5447 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 354:e67efb2aab0e 5448 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 354:e67efb2aab0e 5449 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 354:e67efb2aab0e 5450 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 354:e67efb2aab0e 5451 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 354:e67efb2aab0e 5452 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 354:e67efb2aab0e 5453 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 354:e67efb2aab0e 5454 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 354:e67efb2aab0e 5455 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 354:e67efb2aab0e 5456 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 354:e67efb2aab0e 5457 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 354:e67efb2aab0e 5458 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 354:e67efb2aab0e 5459 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 354:e67efb2aab0e 5460 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 354:e67efb2aab0e 5461 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 354:e67efb2aab0e 5462 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 354:e67efb2aab0e 5463 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 354:e67efb2aab0e 5464 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 354:e67efb2aab0e 5465 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 354:e67efb2aab0e 5466 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 354:e67efb2aab0e 5467 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 354:e67efb2aab0e 5468 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 354:e67efb2aab0e 5469 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 354:e67efb2aab0e 5470 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 354:e67efb2aab0e 5471 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 354:e67efb2aab0e 5472 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 354:e67efb2aab0e 5473 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 354:e67efb2aab0e 5474 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 354:e67efb2aab0e 5475 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 354:e67efb2aab0e 5476 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 354:e67efb2aab0e 5477 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 354:e67efb2aab0e 5478 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 354:e67efb2aab0e 5479
mbed_official 354:e67efb2aab0e 5480 /****************** Bit definition for NVIC_IABR register *******************/
mbed_official 354:e67efb2aab0e 5481 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
mbed_official 354:e67efb2aab0e 5482 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 354:e67efb2aab0e 5483 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 354:e67efb2aab0e 5484 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 354:e67efb2aab0e 5485 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 354:e67efb2aab0e 5486 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 354:e67efb2aab0e 5487 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 354:e67efb2aab0e 5488 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 354:e67efb2aab0e 5489 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 354:e67efb2aab0e 5490 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 354:e67efb2aab0e 5491 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 354:e67efb2aab0e 5492 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 354:e67efb2aab0e 5493 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 354:e67efb2aab0e 5494 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 354:e67efb2aab0e 5495 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 354:e67efb2aab0e 5496 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 354:e67efb2aab0e 5497 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 354:e67efb2aab0e 5498 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 354:e67efb2aab0e 5499 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 354:e67efb2aab0e 5500 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 354:e67efb2aab0e 5501 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 354:e67efb2aab0e 5502 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 354:e67efb2aab0e 5503 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 354:e67efb2aab0e 5504 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 354:e67efb2aab0e 5505 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 354:e67efb2aab0e 5506 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 354:e67efb2aab0e 5507 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 354:e67efb2aab0e 5508 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 354:e67efb2aab0e 5509 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 354:e67efb2aab0e 5510 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 354:e67efb2aab0e 5511 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 354:e67efb2aab0e 5512 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 354:e67efb2aab0e 5513 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 354:e67efb2aab0e 5514
mbed_official 354:e67efb2aab0e 5515 /****************** Bit definition for NVIC_PRI0 register *******************/
mbed_official 354:e67efb2aab0e 5516 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
mbed_official 354:e67efb2aab0e 5517 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
mbed_official 354:e67efb2aab0e 5518 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
mbed_official 354:e67efb2aab0e 5519 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
mbed_official 354:e67efb2aab0e 5520
mbed_official 354:e67efb2aab0e 5521 /****************** Bit definition for NVIC_PRI1 register *******************/
mbed_official 354:e67efb2aab0e 5522 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
mbed_official 354:e67efb2aab0e 5523 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
mbed_official 354:e67efb2aab0e 5524 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
mbed_official 354:e67efb2aab0e 5525 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
mbed_official 354:e67efb2aab0e 5526
mbed_official 354:e67efb2aab0e 5527 /****************** Bit definition for NVIC_PRI2 register *******************/
mbed_official 354:e67efb2aab0e 5528 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
mbed_official 354:e67efb2aab0e 5529 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
mbed_official 354:e67efb2aab0e 5530 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
mbed_official 354:e67efb2aab0e 5531 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
mbed_official 354:e67efb2aab0e 5532
mbed_official 354:e67efb2aab0e 5533 /****************** Bit definition for NVIC_PRI3 register *******************/
mbed_official 354:e67efb2aab0e 5534 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
mbed_official 354:e67efb2aab0e 5535 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
mbed_official 354:e67efb2aab0e 5536 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
mbed_official 354:e67efb2aab0e 5537 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
mbed_official 354:e67efb2aab0e 5538
mbed_official 354:e67efb2aab0e 5539 /****************** Bit definition for NVIC_PRI4 register *******************/
mbed_official 354:e67efb2aab0e 5540 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
mbed_official 354:e67efb2aab0e 5541 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
mbed_official 354:e67efb2aab0e 5542 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
mbed_official 354:e67efb2aab0e 5543 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
mbed_official 354:e67efb2aab0e 5544
mbed_official 354:e67efb2aab0e 5545 /****************** Bit definition for NVIC_PRI5 register *******************/
mbed_official 354:e67efb2aab0e 5546 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
mbed_official 354:e67efb2aab0e 5547 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
mbed_official 354:e67efb2aab0e 5548 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
mbed_official 354:e67efb2aab0e 5549 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
mbed_official 354:e67efb2aab0e 5550
mbed_official 354:e67efb2aab0e 5551 /****************** Bit definition for NVIC_PRI6 register *******************/
mbed_official 354:e67efb2aab0e 5552 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
mbed_official 354:e67efb2aab0e 5553 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
mbed_official 354:e67efb2aab0e 5554 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
mbed_official 354:e67efb2aab0e 5555 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
mbed_official 354:e67efb2aab0e 5556
mbed_official 354:e67efb2aab0e 5557 /****************** Bit definition for NVIC_PRI7 register *******************/
mbed_official 354:e67efb2aab0e 5558 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
mbed_official 354:e67efb2aab0e 5559 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
mbed_official 354:e67efb2aab0e 5560 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
mbed_official 354:e67efb2aab0e 5561 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
mbed_official 354:e67efb2aab0e 5562
mbed_official 354:e67efb2aab0e 5563 /****************** Bit definition for SCB_CPUID register *******************/
mbed_official 354:e67efb2aab0e 5564 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
mbed_official 354:e67efb2aab0e 5565 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
mbed_official 354:e67efb2aab0e 5566 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
mbed_official 354:e67efb2aab0e 5567 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
mbed_official 354:e67efb2aab0e 5568 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
mbed_official 354:e67efb2aab0e 5569
mbed_official 354:e67efb2aab0e 5570 /******************* Bit definition for SCB_ICSR register *******************/
mbed_official 354:e67efb2aab0e 5571 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
mbed_official 354:e67efb2aab0e 5572 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
mbed_official 354:e67efb2aab0e 5573 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
mbed_official 354:e67efb2aab0e 5574 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
mbed_official 354:e67efb2aab0e 5575 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
mbed_official 354:e67efb2aab0e 5576 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
mbed_official 354:e67efb2aab0e 5577 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
mbed_official 354:e67efb2aab0e 5578 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
mbed_official 354:e67efb2aab0e 5579 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
mbed_official 354:e67efb2aab0e 5580 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
mbed_official 354:e67efb2aab0e 5581
mbed_official 354:e67efb2aab0e 5582 /******************* Bit definition for SCB_VTOR register *******************/
mbed_official 354:e67efb2aab0e 5583 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
mbed_official 354:e67efb2aab0e 5584 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
mbed_official 354:e67efb2aab0e 5585
mbed_official 354:e67efb2aab0e 5586 /*!<***************** Bit definition for SCB_AIRCR register *******************/
mbed_official 354:e67efb2aab0e 5587 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
mbed_official 354:e67efb2aab0e 5588 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
mbed_official 354:e67efb2aab0e 5589 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
mbed_official 354:e67efb2aab0e 5590
mbed_official 354:e67efb2aab0e 5591 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
mbed_official 354:e67efb2aab0e 5592 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 354:e67efb2aab0e 5593 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 354:e67efb2aab0e 5594 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 354:e67efb2aab0e 5595
mbed_official 354:e67efb2aab0e 5596 /* prority group configuration */
mbed_official 354:e67efb2aab0e 5597 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
mbed_official 354:e67efb2aab0e 5598 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5599 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5600 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5601 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5602 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5603 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5604 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
mbed_official 354:e67efb2aab0e 5605
mbed_official 354:e67efb2aab0e 5606 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
mbed_official 354:e67efb2aab0e 5607 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
mbed_official 354:e67efb2aab0e 5608
mbed_official 354:e67efb2aab0e 5609 /******************* Bit definition for SCB_SCR register ********************/
mbed_official 354:e67efb2aab0e 5610 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
mbed_official 354:e67efb2aab0e 5611 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
mbed_official 354:e67efb2aab0e 5612 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
mbed_official 354:e67efb2aab0e 5613
mbed_official 354:e67efb2aab0e 5614 /******************** Bit definition for SCB_CCR register *******************/
mbed_official 354:e67efb2aab0e 5615 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
mbed_official 354:e67efb2aab0e 5616 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
mbed_official 354:e67efb2aab0e 5617 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
mbed_official 354:e67efb2aab0e 5618 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
mbed_official 354:e67efb2aab0e 5619 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
mbed_official 354:e67efb2aab0e 5620 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
mbed_official 354:e67efb2aab0e 5621
mbed_official 354:e67efb2aab0e 5622 /******************* Bit definition for SCB_SHPR register ********************/
mbed_official 354:e67efb2aab0e 5623 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
mbed_official 354:e67efb2aab0e 5624 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
mbed_official 354:e67efb2aab0e 5625 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
mbed_official 354:e67efb2aab0e 5626 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
mbed_official 354:e67efb2aab0e 5627
mbed_official 354:e67efb2aab0e 5628 /****************** Bit definition for SCB_SHCSR register *******************/
mbed_official 354:e67efb2aab0e 5629 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
mbed_official 354:e67efb2aab0e 5630 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
mbed_official 354:e67efb2aab0e 5631 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
mbed_official 354:e67efb2aab0e 5632 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
mbed_official 354:e67efb2aab0e 5633 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
mbed_official 354:e67efb2aab0e 5634 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
mbed_official 354:e67efb2aab0e 5635 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
mbed_official 354:e67efb2aab0e 5636 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
mbed_official 354:e67efb2aab0e 5637 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
mbed_official 354:e67efb2aab0e 5638 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
mbed_official 354:e67efb2aab0e 5639 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
mbed_official 354:e67efb2aab0e 5640 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
mbed_official 354:e67efb2aab0e 5641 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
mbed_official 354:e67efb2aab0e 5642 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
mbed_official 354:e67efb2aab0e 5643
mbed_official 354:e67efb2aab0e 5644 /******************* Bit definition for SCB_CFSR register *******************/
mbed_official 354:e67efb2aab0e 5645 /*!< MFSR */
mbed_official 354:e67efb2aab0e 5646 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
mbed_official 354:e67efb2aab0e 5647 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
mbed_official 354:e67efb2aab0e 5648 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
mbed_official 354:e67efb2aab0e 5649 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
mbed_official 354:e67efb2aab0e 5650 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
mbed_official 354:e67efb2aab0e 5651 /*!< BFSR */
mbed_official 354:e67efb2aab0e 5652 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
mbed_official 354:e67efb2aab0e 5653 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
mbed_official 354:e67efb2aab0e 5654 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
mbed_official 354:e67efb2aab0e 5655 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
mbed_official 354:e67efb2aab0e 5656 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
mbed_official 354:e67efb2aab0e 5657 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
mbed_official 354:e67efb2aab0e 5658 /*!< UFSR */
mbed_official 354:e67efb2aab0e 5659 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
mbed_official 354:e67efb2aab0e 5660 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
mbed_official 354:e67efb2aab0e 5661 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
mbed_official 354:e67efb2aab0e 5662 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
mbed_official 354:e67efb2aab0e 5663 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
mbed_official 354:e67efb2aab0e 5664 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
mbed_official 354:e67efb2aab0e 5665
mbed_official 354:e67efb2aab0e 5666 /******************* Bit definition for SCB_HFSR register *******************/
mbed_official 354:e67efb2aab0e 5667 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
mbed_official 354:e67efb2aab0e 5668 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
mbed_official 354:e67efb2aab0e 5669 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
mbed_official 354:e67efb2aab0e 5670
mbed_official 354:e67efb2aab0e 5671 /******************* Bit definition for SCB_DFSR register *******************/
mbed_official 354:e67efb2aab0e 5672 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
mbed_official 354:e67efb2aab0e 5673 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
mbed_official 354:e67efb2aab0e 5674 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
mbed_official 354:e67efb2aab0e 5675 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
mbed_official 354:e67efb2aab0e 5676 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
mbed_official 354:e67efb2aab0e 5677
mbed_official 354:e67efb2aab0e 5678 /******************* Bit definition for SCB_MMFAR register ******************/
mbed_official 354:e67efb2aab0e 5679 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
mbed_official 354:e67efb2aab0e 5680
mbed_official 354:e67efb2aab0e 5681 /******************* Bit definition for SCB_BFAR register *******************/
mbed_official 354:e67efb2aab0e 5682 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
mbed_official 354:e67efb2aab0e 5683
mbed_official 354:e67efb2aab0e 5684 /******************* Bit definition for SCB_afsr register *******************/
mbed_official 354:e67efb2aab0e 5685 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
mbed_official 354:e67efb2aab0e 5686 /**
mbed_official 354:e67efb2aab0e 5687 * @}
mbed_official 354:e67efb2aab0e 5688 */
mbed_official 354:e67efb2aab0e 5689
mbed_official 354:e67efb2aab0e 5690 /**
mbed_official 354:e67efb2aab0e 5691 * @}
mbed_official 354:e67efb2aab0e 5692 */
mbed_official 354:e67efb2aab0e 5693 /** @addtogroup Exported_macro
mbed_official 354:e67efb2aab0e 5694 * @{
mbed_official 354:e67efb2aab0e 5695 */
mbed_official 354:e67efb2aab0e 5696
mbed_official 354:e67efb2aab0e 5697 /****************************** ADC Instances *********************************/
mbed_official 354:e67efb2aab0e 5698 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 354:e67efb2aab0e 5699
mbed_official 354:e67efb2aab0e 5700 /******************************** COMP Instances ******************************/
mbed_official 354:e67efb2aab0e 5701 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 354:e67efb2aab0e 5702 ((INSTANCE) == COMP2))
mbed_official 354:e67efb2aab0e 5703
mbed_official 354:e67efb2aab0e 5704 /****************************** CRC Instances *********************************/
mbed_official 354:e67efb2aab0e 5705 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 354:e67efb2aab0e 5706
mbed_official 354:e67efb2aab0e 5707 /****************************** DAC Instances *********************************/
mbed_official 354:e67efb2aab0e 5708 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 354:e67efb2aab0e 5709
mbed_official 354:e67efb2aab0e 5710 /****************************** DMA Instances *********************************/
mbed_official 354:e67efb2aab0e 5711 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 354:e67efb2aab0e 5712 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 354:e67efb2aab0e 5713 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 354:e67efb2aab0e 5714 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 354:e67efb2aab0e 5715 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 354:e67efb2aab0e 5716 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 354:e67efb2aab0e 5717 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 354:e67efb2aab0e 5718 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 354:e67efb2aab0e 5719 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 354:e67efb2aab0e 5720 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 354:e67efb2aab0e 5721 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 354:e67efb2aab0e 5722 ((INSTANCE) == DMA2_Channel5))
mbed_official 354:e67efb2aab0e 5723
mbed_official 354:e67efb2aab0e 5724 /******************************* GPIO Instances *******************************/
mbed_official 354:e67efb2aab0e 5725 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 354:e67efb2aab0e 5726 ((INSTANCE) == GPIOB) || \
mbed_official 354:e67efb2aab0e 5727 ((INSTANCE) == GPIOC) || \
mbed_official 354:e67efb2aab0e 5728 ((INSTANCE) == GPIOD) || \
mbed_official 354:e67efb2aab0e 5729 ((INSTANCE) == GPIOE) || \
mbed_official 354:e67efb2aab0e 5730 ((INSTANCE) == GPIOF) || \
mbed_official 354:e67efb2aab0e 5731 ((INSTANCE) == GPIOG) || \
mbed_official 354:e67efb2aab0e 5732 ((INSTANCE) == GPIOH))
mbed_official 354:e67efb2aab0e 5733
mbed_official 354:e67efb2aab0e 5734 /**************************** GPIO Lock Instances *****************************/
mbed_official 354:e67efb2aab0e 5735 /* On L1, all GPIO Bank support the Lock mechanism */
mbed_official 354:e67efb2aab0e 5736 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
mbed_official 354:e67efb2aab0e 5737
mbed_official 354:e67efb2aab0e 5738 /******************************** I2C Instances *******************************/
mbed_official 354:e67efb2aab0e 5739 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 354:e67efb2aab0e 5740 ((INSTANCE) == I2C2))
mbed_official 354:e67efb2aab0e 5741
mbed_official 354:e67efb2aab0e 5742 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 354:e67efb2aab0e 5743 ((INSTANCE) == SPI2) || \
mbed_official 354:e67efb2aab0e 5744 ((INSTANCE) == SPI3))
mbed_official 354:e67efb2aab0e 5745 /****************************** IWDG Instances ********************************/
mbed_official 354:e67efb2aab0e 5746 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 354:e67efb2aab0e 5747
mbed_official 354:e67efb2aab0e 5748 /****************************** OPAMP Instances *******************************/
mbed_official 354:e67efb2aab0e 5749 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
mbed_official 354:e67efb2aab0e 5750 ((INSTANCE) == OPAMP2))
mbed_official 354:e67efb2aab0e 5751
mbed_official 354:e67efb2aab0e 5752 /****************************** RTC Instances *********************************/
mbed_official 354:e67efb2aab0e 5753 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 354:e67efb2aab0e 5754
mbed_official 354:e67efb2aab0e 5755 /******************************** SPI Instances *******************************/
mbed_official 354:e67efb2aab0e 5756 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 354:e67efb2aab0e 5757 ((INSTANCE) == SPI2) || \
mbed_official 354:e67efb2aab0e 5758 ((INSTANCE) == SPI3))
mbed_official 354:e67efb2aab0e 5759
mbed_official 354:e67efb2aab0e 5760 /****************************** TIM Instances *********************************/
mbed_official 354:e67efb2aab0e 5761 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5762 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5763 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5764 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5765 ((INSTANCE) == TIM6) || \
mbed_official 354:e67efb2aab0e 5766 ((INSTANCE) == TIM7) || \
mbed_official 354:e67efb2aab0e 5767 ((INSTANCE) == TIM9) || \
mbed_official 354:e67efb2aab0e 5768 ((INSTANCE) == TIM10) || \
mbed_official 354:e67efb2aab0e 5769 ((INSTANCE) == TIM11))
mbed_official 354:e67efb2aab0e 5770
mbed_official 354:e67efb2aab0e 5771 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5772 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5773 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5774 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5775 ((INSTANCE) == TIM9) || \
mbed_official 354:e67efb2aab0e 5776 ((INSTANCE) == TIM10) || \
mbed_official 354:e67efb2aab0e 5777 ((INSTANCE) == TIM11))
mbed_official 354:e67efb2aab0e 5778
mbed_official 354:e67efb2aab0e 5779 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5780 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5781 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5782 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5783 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5784
mbed_official 354:e67efb2aab0e 5785 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5786 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5787 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5788 ((INSTANCE) == TIM5))
mbed_official 354:e67efb2aab0e 5789
mbed_official 354:e67efb2aab0e 5790 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5791 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5792 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5793 ((INSTANCE) == TIM5))
mbed_official 354:e67efb2aab0e 5794
mbed_official 354:e67efb2aab0e 5795 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5796 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5797 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5798 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5799 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5800
mbed_official 354:e67efb2aab0e 5801 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5802 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5803 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5804 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5805 ((INSTANCE) == TIM9) || \
mbed_official 354:e67efb2aab0e 5806 ((INSTANCE) == TIM10) || \
mbed_official 354:e67efb2aab0e 5807 ((INSTANCE) == TIM11))
mbed_official 354:e67efb2aab0e 5808
mbed_official 354:e67efb2aab0e 5809 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5810 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5811 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5812 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5813 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5814
mbed_official 354:e67efb2aab0e 5815 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5816 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5817 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5818 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5819 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5820
mbed_official 354:e67efb2aab0e 5821 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5822 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5823 ((INSTANCE) == TIM4))
mbed_official 354:e67efb2aab0e 5824
mbed_official 354:e67efb2aab0e 5825 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5826 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5827 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5828 ((INSTANCE) == TIM5))
mbed_official 354:e67efb2aab0e 5829
mbed_official 354:e67efb2aab0e 5830 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5831 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5832 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5833 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5834 ((INSTANCE) == TIM6) || \
mbed_official 354:e67efb2aab0e 5835 ((INSTANCE) == TIM7) || \
mbed_official 354:e67efb2aab0e 5836 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5837
mbed_official 354:e67efb2aab0e 5838 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5839 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5840 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5841 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5842 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5843
mbed_official 354:e67efb2aab0e 5844 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
mbed_official 354:e67efb2aab0e 5845
mbed_official 354:e67efb2aab0e 5846 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5847 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5848 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5849 ((INSTANCE) == TIM5))
mbed_official 354:e67efb2aab0e 5850
mbed_official 354:e67efb2aab0e 5851 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 354:e67efb2aab0e 5852 ((((INSTANCE) == TIM2) && \
mbed_official 354:e67efb2aab0e 5853 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 354:e67efb2aab0e 5854 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 354:e67efb2aab0e 5855 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 354:e67efb2aab0e 5856 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 354:e67efb2aab0e 5857 || \
mbed_official 354:e67efb2aab0e 5858 (((INSTANCE) == TIM3) && \
mbed_official 354:e67efb2aab0e 5859 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 354:e67efb2aab0e 5860 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 354:e67efb2aab0e 5861 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 354:e67efb2aab0e 5862 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 354:e67efb2aab0e 5863 || \
mbed_official 354:e67efb2aab0e 5864 (((INSTANCE) == TIM4) && \
mbed_official 354:e67efb2aab0e 5865 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 354:e67efb2aab0e 5866 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 354:e67efb2aab0e 5867 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 354:e67efb2aab0e 5868 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 354:e67efb2aab0e 5869 || \
mbed_official 354:e67efb2aab0e 5870 (((INSTANCE) == TIM5) && \
mbed_official 354:e67efb2aab0e 5871 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 354:e67efb2aab0e 5872 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 354:e67efb2aab0e 5873 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 354:e67efb2aab0e 5874 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 354:e67efb2aab0e 5875 || \
mbed_official 354:e67efb2aab0e 5876 (((INSTANCE) == TIM9) && \
mbed_official 354:e67efb2aab0e 5877 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 354:e67efb2aab0e 5878 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 354:e67efb2aab0e 5879 || \
mbed_official 354:e67efb2aab0e 5880 (((INSTANCE) == TIM10) && \
mbed_official 354:e67efb2aab0e 5881 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 354:e67efb2aab0e 5882 || \
mbed_official 354:e67efb2aab0e 5883 (((INSTANCE) == TIM11) && \
mbed_official 354:e67efb2aab0e 5884 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 354:e67efb2aab0e 5885
mbed_official 354:e67efb2aab0e 5886 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5887 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5888 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5889 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5890 ((INSTANCE) == TIM9) || \
mbed_official 354:e67efb2aab0e 5891 ((INSTANCE) == TIM10) || \
mbed_official 354:e67efb2aab0e 5892 ((INSTANCE) == TIM11))
mbed_official 354:e67efb2aab0e 5893
mbed_official 354:e67efb2aab0e 5894 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5895 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5896 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5897 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5898 ((INSTANCE) == TIM6) || \
mbed_official 354:e67efb2aab0e 5899 ((INSTANCE) == TIM7))
mbed_official 354:e67efb2aab0e 5900
mbed_official 354:e67efb2aab0e 5901 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5902 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5903 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5904 ((INSTANCE) == TIM5))
mbed_official 354:e67efb2aab0e 5905
mbed_official 354:e67efb2aab0e 5906 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5907 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5908 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5909 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5910 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5911
mbed_official 354:e67efb2aab0e 5912 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5913 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5914 ((INSTANCE) == TIM4) || \
mbed_official 354:e67efb2aab0e 5915 ((INSTANCE) == TIM5) || \
mbed_official 354:e67efb2aab0e 5916 ((INSTANCE) == TIM9))
mbed_official 354:e67efb2aab0e 5917
mbed_official 354:e67efb2aab0e 5918 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 354:e67efb2aab0e 5919 ((INSTANCE) == TIM3) || \
mbed_official 354:e67efb2aab0e 5920 ((INSTANCE) == TIM9) || \
mbed_official 354:e67efb2aab0e 5921 ((INSTANCE) == TIM10) || \
mbed_official 354:e67efb2aab0e 5922 ((INSTANCE) == TIM11))
mbed_official 354:e67efb2aab0e 5923
mbed_official 354:e67efb2aab0e 5924 /******************** USART Instances : Synchronous mode **********************/
mbed_official 354:e67efb2aab0e 5925 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5926 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5927 ((INSTANCE) == USART3))
mbed_official 354:e67efb2aab0e 5928
mbed_official 354:e67efb2aab0e 5929 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 354:e67efb2aab0e 5930 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5931 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5932 ((INSTANCE) == USART3) || \
mbed_official 354:e67efb2aab0e 5933 ((INSTANCE) == UART4) || \
mbed_official 354:e67efb2aab0e 5934 ((INSTANCE) == UART5))
mbed_official 354:e67efb2aab0e 5935
mbed_official 354:e67efb2aab0e 5936 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 354:e67efb2aab0e 5937 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5938 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5939 ((INSTANCE) == USART3) || \
mbed_official 354:e67efb2aab0e 5940 ((INSTANCE) == UART4) || \
mbed_official 354:e67efb2aab0e 5941 ((INSTANCE) == UART5))
mbed_official 354:e67efb2aab0e 5942
mbed_official 354:e67efb2aab0e 5943 /******************** UART Instances : LIN mode **********************/
mbed_official 354:e67efb2aab0e 5944 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5945 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5946 ((INSTANCE) == USART3) || \
mbed_official 354:e67efb2aab0e 5947 ((INSTANCE) == UART4) || \
mbed_official 354:e67efb2aab0e 5948 ((INSTANCE) == UART5))
mbed_official 354:e67efb2aab0e 5949
mbed_official 354:e67efb2aab0e 5950 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 354:e67efb2aab0e 5951 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5952 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5953 ((INSTANCE) == USART3))
mbed_official 354:e67efb2aab0e 5954
mbed_official 354:e67efb2aab0e 5955 /********************* UART Instances : Smard card mode ***********************/
mbed_official 354:e67efb2aab0e 5956 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5957 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5958 ((INSTANCE) == USART3))
mbed_official 354:e67efb2aab0e 5959
mbed_official 354:e67efb2aab0e 5960 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 354:e67efb2aab0e 5961 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5962 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5963 ((INSTANCE) == USART3) || \
mbed_official 354:e67efb2aab0e 5964 ((INSTANCE) == UART4) || \
mbed_official 354:e67efb2aab0e 5965 ((INSTANCE) == UART5))
mbed_official 354:e67efb2aab0e 5966
mbed_official 354:e67efb2aab0e 5967 /***************** UART Instances : Multi-Processor mode **********************/
mbed_official 354:e67efb2aab0e 5968 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 354:e67efb2aab0e 5969 ((INSTANCE) == USART2) || \
mbed_official 354:e67efb2aab0e 5970 ((INSTANCE) == USART3) || \
mbed_official 354:e67efb2aab0e 5971 ((INSTANCE) == UART4) || \
mbed_official 354:e67efb2aab0e 5972 ((INSTANCE) == UART5))
mbed_official 354:e67efb2aab0e 5973
mbed_official 354:e67efb2aab0e 5974 /****************************** WWDG Instances ********************************/
mbed_official 354:e67efb2aab0e 5975 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 354:e67efb2aab0e 5976
mbed_official 354:e67efb2aab0e 5977
mbed_official 354:e67efb2aab0e 5978 /****************************** LCD Instances ********************************/
mbed_official 354:e67efb2aab0e 5979 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
mbed_official 354:e67efb2aab0e 5980
mbed_official 354:e67efb2aab0e 5981 /****************************** USB Instances ********************************/
mbed_official 354:e67efb2aab0e 5982 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 354:e67efb2aab0e 5983
mbed_official 354:e67efb2aab0e 5984 /**
mbed_official 354:e67efb2aab0e 5985 * @}
mbed_official 354:e67efb2aab0e 5986 */
mbed_official 354:e67efb2aab0e 5987
mbed_official 354:e67efb2aab0e 5988 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5989 /* For a painless codes migration between the STM32L1xx device product */
mbed_official 354:e67efb2aab0e 5990 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 354:e67efb2aab0e 5991 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 354:e67efb2aab0e 5992 /* No need to update developed interrupt code when moving across */
mbed_official 354:e67efb2aab0e 5993 /* product lines within the same STM32L1 Family */
mbed_official 354:e67efb2aab0e 5994 /******************************************************************************/
mbed_official 354:e67efb2aab0e 5995
mbed_official 354:e67efb2aab0e 5996 /* Aliases for __IRQn */
mbed_official 354:e67efb2aab0e 5997
mbed_official 354:e67efb2aab0e 5998 /* Aliases for __IRQHandler */
mbed_official 354:e67efb2aab0e 5999
mbed_official 354:e67efb2aab0e 6000 /**
mbed_official 354:e67efb2aab0e 6001 * @}
mbed_official 354:e67efb2aab0e 6002 */
mbed_official 354:e67efb2aab0e 6003
mbed_official 354:e67efb2aab0e 6004 /**
mbed_official 354:e67efb2aab0e 6005 * @}
mbed_official 354:e67efb2aab0e 6006 */
mbed_official 354:e67efb2aab0e 6007
mbed_official 354:e67efb2aab0e 6008 #ifdef __cplusplus
mbed_official 354:e67efb2aab0e 6009 }
mbed_official 354:e67efb2aab0e 6010 #endif /* __cplusplus */
mbed_official 354:e67efb2aab0e 6011
mbed_official 354:e67efb2aab0e 6012 #endif /* __STM32L152xE_H */
mbed_official 354:e67efb2aab0e 6013
mbed_official 354:e67efb2aab0e 6014
mbed_official 354:e67efb2aab0e 6015
mbed_official 354:e67efb2aab0e 6016 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/