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targets/cmsis/TARGET_STM/TARGET_DISCO_F334C8/stm32f3xx_ll_fmc.h@381:5460fc57b6e4, 2014-11-03 (annotated)

Committer:
mbed_official
Date:
Mon Nov 03 10:30:07 2014 +0000
Revision:
381:5460fc57b6e4
Synchronized with git revision 02478cd1f27fc7b9643486472635eb515b2bca81



Full URL: https://github.com/mbedmicro/mbed/commit/02478cd1f27fc7b9643486472635eb515b2bca81/



Target: LPC1549 - Fix serial interrupt issues (issue report #616)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 381:5460fc57b6e4 1 /**
mbed_official 381:5460fc57b6e4 2 ******************************************************************************
mbed_official 381:5460fc57b6e4 3 * @file stm32f3xx_ll_fmc.h
mbed_official 381:5460fc57b6e4 4 * @author MCD Application Team
mbed_official 381:5460fc57b6e4 5 * @version V1.1.0
mbed_official 381:5460fc57b6e4 6 * @date 12-Sept-2014
mbed_official 381:5460fc57b6e4 7 * @brief Header file of FMC HAL module.
mbed_official 381:5460fc57b6e4 8 ******************************************************************************
mbed_official 381:5460fc57b6e4 9 * @attention
mbed_official 381:5460fc57b6e4 10 *
mbed_official 381:5460fc57b6e4 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 381:5460fc57b6e4 12 *
mbed_official 381:5460fc57b6e4 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 381:5460fc57b6e4 14 * are permitted provided that the following conditions are met:
mbed_official 381:5460fc57b6e4 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 381:5460fc57b6e4 16 * this list of conditions and the following disclaimer.
mbed_official 381:5460fc57b6e4 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 381:5460fc57b6e4 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 381:5460fc57b6e4 19 * and/or other materials provided with the distribution.
mbed_official 381:5460fc57b6e4 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 381:5460fc57b6e4 21 * may be used to endorse or promote products derived from this software
mbed_official 381:5460fc57b6e4 22 * without specific prior written permission.
mbed_official 381:5460fc57b6e4 23 *
mbed_official 381:5460fc57b6e4 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 381:5460fc57b6e4 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 381:5460fc57b6e4 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 381:5460fc57b6e4 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 381:5460fc57b6e4 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 381:5460fc57b6e4 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 381:5460fc57b6e4 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 381:5460fc57b6e4 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 381:5460fc57b6e4 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 381:5460fc57b6e4 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 381:5460fc57b6e4 34 *
mbed_official 381:5460fc57b6e4 35 ******************************************************************************
mbed_official 381:5460fc57b6e4 36 */
mbed_official 381:5460fc57b6e4 37
mbed_official 381:5460fc57b6e4 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 381:5460fc57b6e4 39 #ifndef __STM32F3xx_LL_FMC_H
mbed_official 381:5460fc57b6e4 40 #define __STM32F3xx_LL_FMC_H
mbed_official 381:5460fc57b6e4 41
mbed_official 381:5460fc57b6e4 42 #ifdef __cplusplus
mbed_official 381:5460fc57b6e4 43 extern "C" {
mbed_official 381:5460fc57b6e4 44 #endif
mbed_official 381:5460fc57b6e4 45
mbed_official 381:5460fc57b6e4 46 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
mbed_official 381:5460fc57b6e4 47
mbed_official 381:5460fc57b6e4 48 /* Includes ------------------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 49 #include "stm32f3xx_hal_def.h"
mbed_official 381:5460fc57b6e4 50
mbed_official 381:5460fc57b6e4 51 /** @addtogroup STM32F3xx_HAL_Driver
mbed_official 381:5460fc57b6e4 52 * @{
mbed_official 381:5460fc57b6e4 53 */
mbed_official 381:5460fc57b6e4 54
mbed_official 381:5460fc57b6e4 55 /** @addtogroup FMC
mbed_official 381:5460fc57b6e4 56 * @{
mbed_official 381:5460fc57b6e4 57 */
mbed_official 381:5460fc57b6e4 58
mbed_official 381:5460fc57b6e4 59 /* Exported typedef ----------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 60 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official 381:5460fc57b6e4 61 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official 381:5460fc57b6e4 62 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official 381:5460fc57b6e4 63 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official 381:5460fc57b6e4 64
mbed_official 381:5460fc57b6e4 65 #define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official 381:5460fc57b6e4 66 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official 381:5460fc57b6e4 67 #define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official 381:5460fc57b6e4 68 #define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official 381:5460fc57b6e4 69
mbed_official 381:5460fc57b6e4 70 /**
mbed_official 381:5460fc57b6e4 71 * @brief FMC_NORSRAM Configuration Structure definition
mbed_official 381:5460fc57b6e4 72 */
mbed_official 381:5460fc57b6e4 73 typedef struct
mbed_official 381:5460fc57b6e4 74 {
mbed_official 381:5460fc57b6e4 75 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official 381:5460fc57b6e4 76 This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official 381:5460fc57b6e4 77
mbed_official 381:5460fc57b6e4 78 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official 381:5460fc57b6e4 79 multiplexed on the data bus or not.
mbed_official 381:5460fc57b6e4 80 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official 381:5460fc57b6e4 81
mbed_official 381:5460fc57b6e4 82 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official 381:5460fc57b6e4 83 the corresponding memory device.
mbed_official 381:5460fc57b6e4 84 This parameter can be a value of @ref FMC_Memory_Type */
mbed_official 381:5460fc57b6e4 85
mbed_official 381:5460fc57b6e4 86 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 381:5460fc57b6e4 87 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official 381:5460fc57b6e4 88
mbed_official 381:5460fc57b6e4 89 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official 381:5460fc57b6e4 90 valid only with synchronous burst Flash memories.
mbed_official 381:5460fc57b6e4 91 This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official 381:5460fc57b6e4 92
mbed_official 381:5460fc57b6e4 93 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official 381:5460fc57b6e4 94 the Flash memory in burst mode.
mbed_official 381:5460fc57b6e4 95 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official 381:5460fc57b6e4 96
mbed_official 381:5460fc57b6e4 97 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official 381:5460fc57b6e4 98 memory, valid only when accessing Flash memories in burst mode.
mbed_official 381:5460fc57b6e4 99 This parameter can be a value of @ref FMC_Wrap_Mode */
mbed_official 381:5460fc57b6e4 100
mbed_official 381:5460fc57b6e4 101 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official 381:5460fc57b6e4 102 clock cycle before the wait state or during the wait state,
mbed_official 381:5460fc57b6e4 103 valid only when accessing memories in burst mode.
mbed_official 381:5460fc57b6e4 104 This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official 381:5460fc57b6e4 105
mbed_official 381:5460fc57b6e4 106 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official 381:5460fc57b6e4 107 This parameter can be a value of @ref FMC_Write_Operation */
mbed_official 381:5460fc57b6e4 108
mbed_official 381:5460fc57b6e4 109 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official 381:5460fc57b6e4 110 signal, valid for Flash memory access in burst mode.
mbed_official 381:5460fc57b6e4 111 This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official 381:5460fc57b6e4 112
mbed_official 381:5460fc57b6e4 113 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official 381:5460fc57b6e4 114 This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official 381:5460fc57b6e4 115
mbed_official 381:5460fc57b6e4 116 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official 381:5460fc57b6e4 117 valid only with asynchronous Flash memories.
mbed_official 381:5460fc57b6e4 118 This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official 381:5460fc57b6e4 119
mbed_official 381:5460fc57b6e4 120 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official 381:5460fc57b6e4 121 This parameter can be a value of @ref FMC_Write_Burst */
mbed_official 381:5460fc57b6e4 122
mbed_official 381:5460fc57b6e4 123 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official 381:5460fc57b6e4 124 This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official 381:5460fc57b6e4 125 through FMC_BCR2..4 registers.
mbed_official 381:5460fc57b6e4 126 This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official 381:5460fc57b6e4 127
mbed_official 381:5460fc57b6e4 128 }FMC_NORSRAM_InitTypeDef;
mbed_official 381:5460fc57b6e4 129
mbed_official 381:5460fc57b6e4 130 /**
mbed_official 381:5460fc57b6e4 131 * @brief FMC_NORSRAM Timing parameters structure definition
mbed_official 381:5460fc57b6e4 132 */
mbed_official 381:5460fc57b6e4 133 typedef struct
mbed_official 381:5460fc57b6e4 134 {
mbed_official 381:5460fc57b6e4 135 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 381:5460fc57b6e4 136 the duration of the address setup time.
mbed_official 381:5460fc57b6e4 137 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official 381:5460fc57b6e4 138 @note This parameter is not used with synchronous NOR Flash memories. */
mbed_official 381:5460fc57b6e4 139
mbed_official 381:5460fc57b6e4 140 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 381:5460fc57b6e4 141 the duration of the address hold time.
mbed_official 381:5460fc57b6e4 142 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official 381:5460fc57b6e4 143 @note This parameter is not used with synchronous NOR Flash memories. */
mbed_official 381:5460fc57b6e4 144
mbed_official 381:5460fc57b6e4 145 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 381:5460fc57b6e4 146 the duration of the data setup time.
mbed_official 381:5460fc57b6e4 147 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official 381:5460fc57b6e4 148 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official 381:5460fc57b6e4 149 NOR Flash memories. */
mbed_official 381:5460fc57b6e4 150
mbed_official 381:5460fc57b6e4 151 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official 381:5460fc57b6e4 152 the duration of the bus turnaround.
mbed_official 381:5460fc57b6e4 153 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official 381:5460fc57b6e4 154 @note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official 381:5460fc57b6e4 155
mbed_official 381:5460fc57b6e4 156 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official 381:5460fc57b6e4 157 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official 381:5460fc57b6e4 158 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official 381:5460fc57b6e4 159 accesses. */
mbed_official 381:5460fc57b6e4 160
mbed_official 381:5460fc57b6e4 161 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official 381:5460fc57b6e4 162 to the memory before getting the first data.
mbed_official 381:5460fc57b6e4 163 The parameter value depends on the memory type as shown below:
mbed_official 381:5460fc57b6e4 164 - It must be set to 0 in case of a CRAM
mbed_official 381:5460fc57b6e4 165 - It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official 381:5460fc57b6e4 166 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official 381:5460fc57b6e4 167 with synchronous burst mode enable */
mbed_official 381:5460fc57b6e4 168
mbed_official 381:5460fc57b6e4 169 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official 381:5460fc57b6e4 170 This parameter can be a value of @ref FMC_Access_Mode */
mbed_official 381:5460fc57b6e4 171
mbed_official 381:5460fc57b6e4 172 }FMC_NORSRAM_TimingTypeDef;
mbed_official 381:5460fc57b6e4 173
mbed_official 381:5460fc57b6e4 174 /**
mbed_official 381:5460fc57b6e4 175 * @brief FMC_NAND Configuration Structure definition
mbed_official 381:5460fc57b6e4 176 */
mbed_official 381:5460fc57b6e4 177 typedef struct
mbed_official 381:5460fc57b6e4 178 {
mbed_official 381:5460fc57b6e4 179 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official 381:5460fc57b6e4 180 This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official 381:5460fc57b6e4 181
mbed_official 381:5460fc57b6e4 182 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official 381:5460fc57b6e4 183 This parameter can be any value of @ref FMC_Wait_feature */
mbed_official 381:5460fc57b6e4 184
mbed_official 381:5460fc57b6e4 185 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 381:5460fc57b6e4 186 This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official 381:5460fc57b6e4 187
mbed_official 381:5460fc57b6e4 188 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official 381:5460fc57b6e4 189 This parameter can be any value of @ref FMC_ECC */
mbed_official 381:5460fc57b6e4 190
mbed_official 381:5460fc57b6e4 191 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official 381:5460fc57b6e4 192 This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official 381:5460fc57b6e4 193
mbed_official 381:5460fc57b6e4 194 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 381:5460fc57b6e4 195 delay between CLE low and RE low.
mbed_official 381:5460fc57b6e4 196 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 197
mbed_official 381:5460fc57b6e4 198 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 381:5460fc57b6e4 199 delay between ALE low and RE low.
mbed_official 381:5460fc57b6e4 200 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 201
mbed_official 381:5460fc57b6e4 202 }FMC_NAND_InitTypeDef;
mbed_official 381:5460fc57b6e4 203
mbed_official 381:5460fc57b6e4 204 /**
mbed_official 381:5460fc57b6e4 205 * @brief FMC_NAND_PCCARD Timing parameters structure definition
mbed_official 381:5460fc57b6e4 206 */
mbed_official 381:5460fc57b6e4 207 typedef struct
mbed_official 381:5460fc57b6e4 208 {
mbed_official 381:5460fc57b6e4 209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official 381:5460fc57b6e4 210 the command assertion for NAND-Flash read or write access
mbed_official 381:5460fc57b6e4 211 to common/Attribute or I/O memory space (depending on
mbed_official 381:5460fc57b6e4 212 the memory space timing to be configured).
mbed_official 381:5460fc57b6e4 213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 214
mbed_official 381:5460fc57b6e4 215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official 381:5460fc57b6e4 216 command for NAND-Flash read or write access to
mbed_official 381:5460fc57b6e4 217 common/Attribute or I/O memory space (depending on the
mbed_official 381:5460fc57b6e4 218 memory space timing to be configured).
mbed_official 381:5460fc57b6e4 219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 220
mbed_official 381:5460fc57b6e4 221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official 381:5460fc57b6e4 222 (and data for write access) after the command de-assertion
mbed_official 381:5460fc57b6e4 223 for NAND-Flash read or write access to common/Attribute
mbed_official 381:5460fc57b6e4 224 or I/O memory space (depending on the memory space timing
mbed_official 381:5460fc57b6e4 225 to be configured).
mbed_official 381:5460fc57b6e4 226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 227
mbed_official 381:5460fc57b6e4 228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official 381:5460fc57b6e4 229 data bus is kept in HiZ after the start of a NAND-Flash
mbed_official 381:5460fc57b6e4 230 write access to common/Attribute or I/O memory space (depending
mbed_official 381:5460fc57b6e4 231 on the memory space timing to be configured).
mbed_official 381:5460fc57b6e4 232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 233
mbed_official 381:5460fc57b6e4 234 }FMC_NAND_PCC_TimingTypeDef;
mbed_official 381:5460fc57b6e4 235
mbed_official 381:5460fc57b6e4 236 /**
mbed_official 381:5460fc57b6e4 237 * @brief FMC_NAND Configuration Structure definition
mbed_official 381:5460fc57b6e4 238 */
mbed_official 381:5460fc57b6e4 239 typedef struct
mbed_official 381:5460fc57b6e4 240 {
mbed_official 381:5460fc57b6e4 241 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official 381:5460fc57b6e4 242 This parameter can be any value of @ref FMC_Wait_feature */
mbed_official 381:5460fc57b6e4 243
mbed_official 381:5460fc57b6e4 244 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 381:5460fc57b6e4 245 delay between CLE low and RE low.
mbed_official 381:5460fc57b6e4 246 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 247
mbed_official 381:5460fc57b6e4 248 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 381:5460fc57b6e4 249 delay between ALE low and RE low.
mbed_official 381:5460fc57b6e4 250 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official 381:5460fc57b6e4 251
mbed_official 381:5460fc57b6e4 252 }FMC_PCCARD_InitTypeDef;
mbed_official 381:5460fc57b6e4 253
mbed_official 381:5460fc57b6e4 254 /* Exported constants --------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 255
mbed_official 381:5460fc57b6e4 256 /** @defgroup FMC_NOR_SRAM_Controller
mbed_official 381:5460fc57b6e4 257 * @{
mbed_official 381:5460fc57b6e4 258 */
mbed_official 381:5460fc57b6e4 259
mbed_official 381:5460fc57b6e4 260 /** @defgroup FMC_NORSRAM_Bank
mbed_official 381:5460fc57b6e4 261 * @{
mbed_official 381:5460fc57b6e4 262 */
mbed_official 381:5460fc57b6e4 263 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 264 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official 381:5460fc57b6e4 265 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official 381:5460fc57b6e4 266 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official 381:5460fc57b6e4 267
mbed_official 381:5460fc57b6e4 268 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
mbed_official 381:5460fc57b6e4 269 ((BANK) == FMC_NORSRAM_BANK2) || \
mbed_official 381:5460fc57b6e4 270 ((BANK) == FMC_NORSRAM_BANK3) || \
mbed_official 381:5460fc57b6e4 271 ((BANK) == FMC_NORSRAM_BANK4))
mbed_official 381:5460fc57b6e4 272 /**
mbed_official 381:5460fc57b6e4 273 * @}
mbed_official 381:5460fc57b6e4 274 */
mbed_official 381:5460fc57b6e4 275
mbed_official 381:5460fc57b6e4 276 /** @defgroup FMC_Data_Address_Bus_Multiplexing
mbed_official 381:5460fc57b6e4 277 * @{
mbed_official 381:5460fc57b6e4 278 */
mbed_official 381:5460fc57b6e4 279 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 280 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official 381:5460fc57b6e4 281
mbed_official 381:5460fc57b6e4 282 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
mbed_official 381:5460fc57b6e4 283 ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official 381:5460fc57b6e4 284 /**
mbed_official 381:5460fc57b6e4 285 * @}
mbed_official 381:5460fc57b6e4 286 */
mbed_official 381:5460fc57b6e4 287
mbed_official 381:5460fc57b6e4 288 /** @defgroup FMC_Memory_Type
mbed_official 381:5460fc57b6e4 289 * @{
mbed_official 381:5460fc57b6e4 290 */
mbed_official 381:5460fc57b6e4 291 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 292 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official 381:5460fc57b6e4 293 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official 381:5460fc57b6e4 294
mbed_official 381:5460fc57b6e4 295 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
mbed_official 381:5460fc57b6e4 296 ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
mbed_official 381:5460fc57b6e4 297 ((MEMORY) == FMC_MEMORY_TYPE_NOR))
mbed_official 381:5460fc57b6e4 298 /**
mbed_official 381:5460fc57b6e4 299 * @}
mbed_official 381:5460fc57b6e4 300 */
mbed_official 381:5460fc57b6e4 301
mbed_official 381:5460fc57b6e4 302 /** @defgroup FMC_NORSRAM_Data_Width
mbed_official 381:5460fc57b6e4 303 * @{
mbed_official 381:5460fc57b6e4 304 */
mbed_official 381:5460fc57b6e4 305 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 306 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official 381:5460fc57b6e4 307 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official 381:5460fc57b6e4 308
mbed_official 381:5460fc57b6e4 309 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
mbed_official 381:5460fc57b6e4 310 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
mbed_official 381:5460fc57b6e4 311 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official 381:5460fc57b6e4 312 /**
mbed_official 381:5460fc57b6e4 313 * @}
mbed_official 381:5460fc57b6e4 314 */
mbed_official 381:5460fc57b6e4 315
mbed_official 381:5460fc57b6e4 316 /** @defgroup FMC_NORSRAM_Flash_Access
mbed_official 381:5460fc57b6e4 317 * @{
mbed_official 381:5460fc57b6e4 318 */
mbed_official 381:5460fc57b6e4 319 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official 381:5460fc57b6e4 320 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 321 /**
mbed_official 381:5460fc57b6e4 322 * @}
mbed_official 381:5460fc57b6e4 323 */
mbed_official 381:5460fc57b6e4 324
mbed_official 381:5460fc57b6e4 325 /** @defgroup FMC_Burst_Access_Mode
mbed_official 381:5460fc57b6e4 326 * @{
mbed_official 381:5460fc57b6e4 327 */
mbed_official 381:5460fc57b6e4 328 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 329 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official 381:5460fc57b6e4 330
mbed_official 381:5460fc57b6e4 331 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
mbed_official 381:5460fc57b6e4 332 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official 381:5460fc57b6e4 333 /**
mbed_official 381:5460fc57b6e4 334 * @}
mbed_official 381:5460fc57b6e4 335 */
mbed_official 381:5460fc57b6e4 336
mbed_official 381:5460fc57b6e4 337
mbed_official 381:5460fc57b6e4 338 /** @defgroup FMC_Wait_Signal_Polarity
mbed_official 381:5460fc57b6e4 339 * @{
mbed_official 381:5460fc57b6e4 340 */
mbed_official 381:5460fc57b6e4 341 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 342 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official 381:5460fc57b6e4 343
mbed_official 381:5460fc57b6e4 344 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
mbed_official 381:5460fc57b6e4 345 ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official 381:5460fc57b6e4 346 /**
mbed_official 381:5460fc57b6e4 347 * @}
mbed_official 381:5460fc57b6e4 348 */
mbed_official 381:5460fc57b6e4 349
mbed_official 381:5460fc57b6e4 350 /** @defgroup FMC_Wrap_Mode
mbed_official 381:5460fc57b6e4 351 * @{
mbed_official 381:5460fc57b6e4 352 */
mbed_official 381:5460fc57b6e4 353 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 354 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official 381:5460fc57b6e4 355
mbed_official 381:5460fc57b6e4 356 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
mbed_official 381:5460fc57b6e4 357 ((MODE) == FMC_WRAP_MODE_ENABLE))
mbed_official 381:5460fc57b6e4 358 /**
mbed_official 381:5460fc57b6e4 359 * @}
mbed_official 381:5460fc57b6e4 360 */
mbed_official 381:5460fc57b6e4 361
mbed_official 381:5460fc57b6e4 362 /** @defgroup FMC_Wait_Timing
mbed_official 381:5460fc57b6e4 363 * @{
mbed_official 381:5460fc57b6e4 364 */
mbed_official 381:5460fc57b6e4 365 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 366 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official 381:5460fc57b6e4 367
mbed_official 381:5460fc57b6e4 368 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
mbed_official 381:5460fc57b6e4 369 ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
mbed_official 381:5460fc57b6e4 370 /**
mbed_official 381:5460fc57b6e4 371 * @}
mbed_official 381:5460fc57b6e4 372 */
mbed_official 381:5460fc57b6e4 373
mbed_official 381:5460fc57b6e4 374 /** @defgroup FMC_Write_Operation
mbed_official 381:5460fc57b6e4 375 * @{
mbed_official 381:5460fc57b6e4 376 */
mbed_official 381:5460fc57b6e4 377 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 378 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official 381:5460fc57b6e4 379
mbed_official 381:5460fc57b6e4 380 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
mbed_official 381:5460fc57b6e4 381 ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
mbed_official 381:5460fc57b6e4 382 /**
mbed_official 381:5460fc57b6e4 383 * @}
mbed_official 381:5460fc57b6e4 384 */
mbed_official 381:5460fc57b6e4 385
mbed_official 381:5460fc57b6e4 386 /** @defgroup FMC_Wait_Signal
mbed_official 381:5460fc57b6e4 387 * @{
mbed_official 381:5460fc57b6e4 388 */
mbed_official 381:5460fc57b6e4 389 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 390 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official 381:5460fc57b6e4 391
mbed_official 381:5460fc57b6e4 392 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
mbed_official 381:5460fc57b6e4 393 ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official 381:5460fc57b6e4 394 /**
mbed_official 381:5460fc57b6e4 395 * @}
mbed_official 381:5460fc57b6e4 396 */
mbed_official 381:5460fc57b6e4 397
mbed_official 381:5460fc57b6e4 398 /** @defgroup FMC_Extended_Mode
mbed_official 381:5460fc57b6e4 399 * @{
mbed_official 381:5460fc57b6e4 400 */
mbed_official 381:5460fc57b6e4 401 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 402 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official 381:5460fc57b6e4 403
mbed_official 381:5460fc57b6e4 404 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
mbed_official 381:5460fc57b6e4 405 ((MODE) == FMC_EXTENDED_MODE_ENABLE))
mbed_official 381:5460fc57b6e4 406 /**
mbed_official 381:5460fc57b6e4 407 * @}
mbed_official 381:5460fc57b6e4 408 */
mbed_official 381:5460fc57b6e4 409
mbed_official 381:5460fc57b6e4 410 /** @defgroup FMC_AsynchronousWait
mbed_official 381:5460fc57b6e4 411 * @{
mbed_official 381:5460fc57b6e4 412 */
mbed_official 381:5460fc57b6e4 413 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 414 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official 381:5460fc57b6e4 415
mbed_official 381:5460fc57b6e4 416 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
mbed_official 381:5460fc57b6e4 417 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official 381:5460fc57b6e4 418 /**
mbed_official 381:5460fc57b6e4 419 * @}
mbed_official 381:5460fc57b6e4 420 */
mbed_official 381:5460fc57b6e4 421
mbed_official 381:5460fc57b6e4 422 /** @defgroup FMC_Write_Burst
mbed_official 381:5460fc57b6e4 423 * @{
mbed_official 381:5460fc57b6e4 424 */
mbed_official 381:5460fc57b6e4 425 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 426 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official 381:5460fc57b6e4 427
mbed_official 381:5460fc57b6e4 428 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
mbed_official 381:5460fc57b6e4 429 ((BURST) == FMC_WRITE_BURST_ENABLE))
mbed_official 381:5460fc57b6e4 430 /**
mbed_official 381:5460fc57b6e4 431 * @}
mbed_official 381:5460fc57b6e4 432 */
mbed_official 381:5460fc57b6e4 433
mbed_official 381:5460fc57b6e4 434 /** @defgroup FMC_Continous_Clock
mbed_official 381:5460fc57b6e4 435 * @{
mbed_official 381:5460fc57b6e4 436 */
mbed_official 381:5460fc57b6e4 437 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 438 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official 381:5460fc57b6e4 439
mbed_official 381:5460fc57b6e4 440 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
mbed_official 381:5460fc57b6e4 441 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official 381:5460fc57b6e4 442 /**
mbed_official 381:5460fc57b6e4 443 * @}
mbed_official 381:5460fc57b6e4 444 */
mbed_official 381:5460fc57b6e4 445
mbed_official 381:5460fc57b6e4 446 /** @defgroup FMC_Address_Setup_Time
mbed_official 381:5460fc57b6e4 447 * @{
mbed_official 381:5460fc57b6e4 448 */
mbed_official 381:5460fc57b6e4 449 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official 381:5460fc57b6e4 450 /**
mbed_official 381:5460fc57b6e4 451 * @}
mbed_official 381:5460fc57b6e4 452 */
mbed_official 381:5460fc57b6e4 453
mbed_official 381:5460fc57b6e4 454 /** @defgroup FMC_Address_Hold_Time
mbed_official 381:5460fc57b6e4 455 * @{
mbed_official 381:5460fc57b6e4 456 */
mbed_official 381:5460fc57b6e4 457 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official 381:5460fc57b6e4 458 /**
mbed_official 381:5460fc57b6e4 459 * @}
mbed_official 381:5460fc57b6e4 460 */
mbed_official 381:5460fc57b6e4 461
mbed_official 381:5460fc57b6e4 462 /** @defgroup FMC_Data_Setup_Time
mbed_official 381:5460fc57b6e4 463 * @{
mbed_official 381:5460fc57b6e4 464 */
mbed_official 381:5460fc57b6e4 465 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official 381:5460fc57b6e4 466 /**
mbed_official 381:5460fc57b6e4 467 * @}
mbed_official 381:5460fc57b6e4 468 */
mbed_official 381:5460fc57b6e4 469
mbed_official 381:5460fc57b6e4 470 /** @defgroup FMC_Bus_Turn_around_Duration
mbed_official 381:5460fc57b6e4 471 * @{
mbed_official 381:5460fc57b6e4 472 */
mbed_official 381:5460fc57b6e4 473 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official 381:5460fc57b6e4 474 /**
mbed_official 381:5460fc57b6e4 475 * @}
mbed_official 381:5460fc57b6e4 476 */
mbed_official 381:5460fc57b6e4 477
mbed_official 381:5460fc57b6e4 478 /** @defgroup FMC_CLK_Division
mbed_official 381:5460fc57b6e4 479 * @{
mbed_official 381:5460fc57b6e4 480 */
mbed_official 381:5460fc57b6e4 481 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official 381:5460fc57b6e4 482 /**
mbed_official 381:5460fc57b6e4 483 * @}
mbed_official 381:5460fc57b6e4 484 */
mbed_official 381:5460fc57b6e4 485
mbed_official 381:5460fc57b6e4 486 /** @defgroup FMC_Data_Latency
mbed_official 381:5460fc57b6e4 487 * @{
mbed_official 381:5460fc57b6e4 488 */
mbed_official 381:5460fc57b6e4 489 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official 381:5460fc57b6e4 490 /**
mbed_official 381:5460fc57b6e4 491 * @}
mbed_official 381:5460fc57b6e4 492 */
mbed_official 381:5460fc57b6e4 493
mbed_official 381:5460fc57b6e4 494 /** @defgroup FMC_Access_Mode
mbed_official 381:5460fc57b6e4 495 * @{
mbed_official 381:5460fc57b6e4 496 */
mbed_official 381:5460fc57b6e4 497 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 498 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official 381:5460fc57b6e4 499 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official 381:5460fc57b6e4 500 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official 381:5460fc57b6e4 501
mbed_official 381:5460fc57b6e4 502 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
mbed_official 381:5460fc57b6e4 503 ((MODE) == FMC_ACCESS_MODE_B) || \
mbed_official 381:5460fc57b6e4 504 ((MODE) == FMC_ACCESS_MODE_C) || \
mbed_official 381:5460fc57b6e4 505 ((MODE) == FMC_ACCESS_MODE_D))
mbed_official 381:5460fc57b6e4 506 /**
mbed_official 381:5460fc57b6e4 507 * @}
mbed_official 381:5460fc57b6e4 508 */
mbed_official 381:5460fc57b6e4 509
mbed_official 381:5460fc57b6e4 510 /**
mbed_official 381:5460fc57b6e4 511 * @}
mbed_official 381:5460fc57b6e4 512 */
mbed_official 381:5460fc57b6e4 513
mbed_official 381:5460fc57b6e4 514 /** @defgroup FMC_NAND_Controller
mbed_official 381:5460fc57b6e4 515 * @{
mbed_official 381:5460fc57b6e4 516 */
mbed_official 381:5460fc57b6e4 517
mbed_official 381:5460fc57b6e4 518 /** @defgroup FMC_NAND_Bank
mbed_official 381:5460fc57b6e4 519 * @{
mbed_official 381:5460fc57b6e4 520 */
mbed_official 381:5460fc57b6e4 521 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official 381:5460fc57b6e4 522 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official 381:5460fc57b6e4 523
mbed_official 381:5460fc57b6e4 524 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
mbed_official 381:5460fc57b6e4 525 ((BANK) == FMC_NAND_BANK3))
mbed_official 381:5460fc57b6e4 526 /**
mbed_official 381:5460fc57b6e4 527 * @}
mbed_official 381:5460fc57b6e4 528 */
mbed_official 381:5460fc57b6e4 529
mbed_official 381:5460fc57b6e4 530 /** @defgroup FMC_Wait_feature
mbed_official 381:5460fc57b6e4 531 * @{
mbed_official 381:5460fc57b6e4 532 */
mbed_official 381:5460fc57b6e4 533 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 534 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official 381:5460fc57b6e4 535
mbed_official 381:5460fc57b6e4 536 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
mbed_official 381:5460fc57b6e4 537 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official 381:5460fc57b6e4 538 /**
mbed_official 381:5460fc57b6e4 539 * @}
mbed_official 381:5460fc57b6e4 540 */
mbed_official 381:5460fc57b6e4 541
mbed_official 381:5460fc57b6e4 542 /** @defgroup FMC_PCR_Memory_Type
mbed_official 381:5460fc57b6e4 543 * @{
mbed_official 381:5460fc57b6e4 544 */
mbed_official 381:5460fc57b6e4 545 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 546 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official 381:5460fc57b6e4 547 /**
mbed_official 381:5460fc57b6e4 548 * @}
mbed_official 381:5460fc57b6e4 549 */
mbed_official 381:5460fc57b6e4 550
mbed_official 381:5460fc57b6e4 551 /** @defgroup FMC_NAND_Data_Width
mbed_official 381:5460fc57b6e4 552 * @{
mbed_official 381:5460fc57b6e4 553 */
mbed_official 381:5460fc57b6e4 554 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 555 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official 381:5460fc57b6e4 556
mbed_official 381:5460fc57b6e4 557 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
mbed_official 381:5460fc57b6e4 558 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official 381:5460fc57b6e4 559 /**
mbed_official 381:5460fc57b6e4 560 * @}
mbed_official 381:5460fc57b6e4 561 */
mbed_official 381:5460fc57b6e4 562
mbed_official 381:5460fc57b6e4 563 /** @defgroup FMC_ECC
mbed_official 381:5460fc57b6e4 564 * @{
mbed_official 381:5460fc57b6e4 565 */
mbed_official 381:5460fc57b6e4 566 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 567 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official 381:5460fc57b6e4 568
mbed_official 381:5460fc57b6e4 569 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
mbed_official 381:5460fc57b6e4 570 ((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official 381:5460fc57b6e4 571 /**
mbed_official 381:5460fc57b6e4 572 * @}
mbed_official 381:5460fc57b6e4 573 */
mbed_official 381:5460fc57b6e4 574
mbed_official 381:5460fc57b6e4 575 /** @defgroup FMC_ECC_Page_Size
mbed_official 381:5460fc57b6e4 576 * @{
mbed_official 381:5460fc57b6e4 577 */
mbed_official 381:5460fc57b6e4 578 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official 381:5460fc57b6e4 579 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official 381:5460fc57b6e4 580 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official 381:5460fc57b6e4 581 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official 381:5460fc57b6e4 582 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official 381:5460fc57b6e4 583 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official 381:5460fc57b6e4 584
mbed_official 381:5460fc57b6e4 585 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
mbed_official 381:5460fc57b6e4 586 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
mbed_official 381:5460fc57b6e4 587 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
mbed_official 381:5460fc57b6e4 588 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
mbed_official 381:5460fc57b6e4 589 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
mbed_official 381:5460fc57b6e4 590 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official 381:5460fc57b6e4 591 /**
mbed_official 381:5460fc57b6e4 592 * @}
mbed_official 381:5460fc57b6e4 593 */
mbed_official 381:5460fc57b6e4 594
mbed_official 381:5460fc57b6e4 595 /** @defgroup FMC_TCLR_Setup_Time
mbed_official 381:5460fc57b6e4 596 * @{
mbed_official 381:5460fc57b6e4 597 */
mbed_official 381:5460fc57b6e4 598 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 599 /**
mbed_official 381:5460fc57b6e4 600 * @}
mbed_official 381:5460fc57b6e4 601 */
mbed_official 381:5460fc57b6e4 602
mbed_official 381:5460fc57b6e4 603 /** @defgroup FMC_TAR_Setup_Time
mbed_official 381:5460fc57b6e4 604 * @{
mbed_official 381:5460fc57b6e4 605 */
mbed_official 381:5460fc57b6e4 606 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 607 /**
mbed_official 381:5460fc57b6e4 608 * @}
mbed_official 381:5460fc57b6e4 609 */
mbed_official 381:5460fc57b6e4 610
mbed_official 381:5460fc57b6e4 611 /** @defgroup FMC_Setup_Time
mbed_official 381:5460fc57b6e4 612 * @{
mbed_official 381:5460fc57b6e4 613 */
mbed_official 381:5460fc57b6e4 614 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 615 /**
mbed_official 381:5460fc57b6e4 616 * @}
mbed_official 381:5460fc57b6e4 617 */
mbed_official 381:5460fc57b6e4 618
mbed_official 381:5460fc57b6e4 619 /** @defgroup FMC_Wait_Setup_Time
mbed_official 381:5460fc57b6e4 620 * @{
mbed_official 381:5460fc57b6e4 621 */
mbed_official 381:5460fc57b6e4 622 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 623 /**
mbed_official 381:5460fc57b6e4 624 * @}
mbed_official 381:5460fc57b6e4 625 */
mbed_official 381:5460fc57b6e4 626
mbed_official 381:5460fc57b6e4 627 /** @defgroup FMC_Hold_Setup_Time
mbed_official 381:5460fc57b6e4 628 * @{
mbed_official 381:5460fc57b6e4 629 */
mbed_official 381:5460fc57b6e4 630 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 631 /**
mbed_official 381:5460fc57b6e4 632 * @}
mbed_official 381:5460fc57b6e4 633 */
mbed_official 381:5460fc57b6e4 634
mbed_official 381:5460fc57b6e4 635 /** @defgroup FMC_HiZ_Setup_Time
mbed_official 381:5460fc57b6e4 636 * @{
mbed_official 381:5460fc57b6e4 637 */
mbed_official 381:5460fc57b6e4 638 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official 381:5460fc57b6e4 639 /**
mbed_official 381:5460fc57b6e4 640 * @}
mbed_official 381:5460fc57b6e4 641 */
mbed_official 381:5460fc57b6e4 642
mbed_official 381:5460fc57b6e4 643 /**
mbed_official 381:5460fc57b6e4 644 * @}
mbed_official 381:5460fc57b6e4 645 */
mbed_official 381:5460fc57b6e4 646
mbed_official 381:5460fc57b6e4 647 /** @defgroup FMC_NORSRAM_Device_Instance
mbed_official 381:5460fc57b6e4 648 * @{
mbed_official 381:5460fc57b6e4 649 */
mbed_official 381:5460fc57b6e4 650 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
mbed_official 381:5460fc57b6e4 651 /**
mbed_official 381:5460fc57b6e4 652 * @}
mbed_official 381:5460fc57b6e4 653 */
mbed_official 381:5460fc57b6e4 654
mbed_official 381:5460fc57b6e4 655 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
mbed_official 381:5460fc57b6e4 656 * @{
mbed_official 381:5460fc57b6e4 657 */
mbed_official 381:5460fc57b6e4 658 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official 381:5460fc57b6e4 659 /**
mbed_official 381:5460fc57b6e4 660 * @}
mbed_official 381:5460fc57b6e4 661 */
mbed_official 381:5460fc57b6e4 662
mbed_official 381:5460fc57b6e4 663 /** @defgroup FMC_NAND_Device_Instance
mbed_official 381:5460fc57b6e4 664 * @{
mbed_official 381:5460fc57b6e4 665 */
mbed_official 381:5460fc57b6e4 666 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
mbed_official 381:5460fc57b6e4 667 /**
mbed_official 381:5460fc57b6e4 668 * @}
mbed_official 381:5460fc57b6e4 669 */
mbed_official 381:5460fc57b6e4 670
mbed_official 381:5460fc57b6e4 671 /** @defgroup FMC_PCCARD_Device_Instance
mbed_official 381:5460fc57b6e4 672 * @{
mbed_official 381:5460fc57b6e4 673 */
mbed_official 381:5460fc57b6e4 674 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
mbed_official 381:5460fc57b6e4 675
mbed_official 381:5460fc57b6e4 676 /**
mbed_official 381:5460fc57b6e4 677 * @}
mbed_official 381:5460fc57b6e4 678 */
mbed_official 381:5460fc57b6e4 679
mbed_official 381:5460fc57b6e4 680 /** @defgroup FMC_Interrupt_definition
mbed_official 381:5460fc57b6e4 681 * @brief FMC Interrupt definition
mbed_official 381:5460fc57b6e4 682 * @{
mbed_official 381:5460fc57b6e4 683 */
mbed_official 381:5460fc57b6e4 684 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official 381:5460fc57b6e4 685 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official 381:5460fc57b6e4 686 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official 381:5460fc57b6e4 687 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official 381:5460fc57b6e4 688
mbed_official 381:5460fc57b6e4 689 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official 381:5460fc57b6e4 690
mbed_official 381:5460fc57b6e4 691 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
mbed_official 381:5460fc57b6e4 692 ((IT) == FMC_IT_LEVEL) || \
mbed_official 381:5460fc57b6e4 693 ((IT) == FMC_IT_FALLING_EDGE) || \
mbed_official 381:5460fc57b6e4 694 ((IT) == FMC_IT_REFRESH_ERROR))
mbed_official 381:5460fc57b6e4 695 /**
mbed_official 381:5460fc57b6e4 696 * @}
mbed_official 381:5460fc57b6e4 697 */
mbed_official 381:5460fc57b6e4 698
mbed_official 381:5460fc57b6e4 699 /** @defgroup FMC_Flag_definition
mbed_official 381:5460fc57b6e4 700 * @brief FMC Flag definition
mbed_official 381:5460fc57b6e4 701 * @{
mbed_official 381:5460fc57b6e4 702 */
mbed_official 381:5460fc57b6e4 703 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official 381:5460fc57b6e4 704 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official 381:5460fc57b6e4 705 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official 381:5460fc57b6e4 706 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official 381:5460fc57b6e4 707
mbed_official 381:5460fc57b6e4 708 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
mbed_official 381:5460fc57b6e4 709 ((FLAG) == FMC_FLAG_LEVEL) || \
mbed_official 381:5460fc57b6e4 710 ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
mbed_official 381:5460fc57b6e4 711 ((FLAG) == FMC_FLAG_FEMPT))
mbed_official 381:5460fc57b6e4 712
mbed_official 381:5460fc57b6e4 713 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official 381:5460fc57b6e4 714 /**
mbed_official 381:5460fc57b6e4 715 * @}
mbed_official 381:5460fc57b6e4 716 */
mbed_official 381:5460fc57b6e4 717
mbed_official 381:5460fc57b6e4 718 /* Exported macro ------------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 719
mbed_official 381:5460fc57b6e4 720 /** @defgroup FMC_NOR_Macros
mbed_official 381:5460fc57b6e4 721 * @brief macros to handle NOR device enable/disable and read/write operations
mbed_official 381:5460fc57b6e4 722 * @{
mbed_official 381:5460fc57b6e4 723 */
mbed_official 381:5460fc57b6e4 724
mbed_official 381:5460fc57b6e4 725 /**
mbed_official 381:5460fc57b6e4 726 * @brief Enable the NORSRAM device access.
mbed_official 381:5460fc57b6e4 727 * @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official 381:5460fc57b6e4 728 * @param __BANK__: FMC_NORSRAM Bank
mbed_official 381:5460fc57b6e4 729 * @retval None
mbed_official 381:5460fc57b6e4 730 */
mbed_official 381:5460fc57b6e4 731 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
mbed_official 381:5460fc57b6e4 732
mbed_official 381:5460fc57b6e4 733 /**
mbed_official 381:5460fc57b6e4 734 * @brief Disable the NORSRAM device access.
mbed_official 381:5460fc57b6e4 735 * @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official 381:5460fc57b6e4 736 * @param __BANK__: FMC_NORSRAM Bank
mbed_official 381:5460fc57b6e4 737 * @retval None
mbed_official 381:5460fc57b6e4 738 */
mbed_official 381:5460fc57b6e4 739 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official 381:5460fc57b6e4 740
mbed_official 381:5460fc57b6e4 741 /**
mbed_official 381:5460fc57b6e4 742 * @}
mbed_official 381:5460fc57b6e4 743 */
mbed_official 381:5460fc57b6e4 744
mbed_official 381:5460fc57b6e4 745 /** @defgroup FMC_NAND_Macros
mbed_official 381:5460fc57b6e4 746 * @brief macros to handle NAND device enable/disable
mbed_official 381:5460fc57b6e4 747 * @{
mbed_official 381:5460fc57b6e4 748 */
mbed_official 381:5460fc57b6e4 749
mbed_official 381:5460fc57b6e4 750 /**
mbed_official 381:5460fc57b6e4 751 * @brief Enable the NAND device access.
mbed_official 381:5460fc57b6e4 752 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 753 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 754 * @retval None
mbed_official 381:5460fc57b6e4 755 */
mbed_official 381:5460fc57b6e4 756 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
mbed_official 381:5460fc57b6e4 757 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
mbed_official 381:5460fc57b6e4 758
mbed_official 381:5460fc57b6e4 759 /**
mbed_official 381:5460fc57b6e4 760 * @brief Disable the NAND device access.
mbed_official 381:5460fc57b6e4 761 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 762 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 763 * @retval None
mbed_official 381:5460fc57b6e4 764 */
mbed_official 381:5460fc57b6e4 765 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official 381:5460fc57b6e4 766 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official 381:5460fc57b6e4 767 /**
mbed_official 381:5460fc57b6e4 768 * @}
mbed_official 381:5460fc57b6e4 769 */
mbed_official 381:5460fc57b6e4 770
mbed_official 381:5460fc57b6e4 771 /** @defgroup FMC_PCCARD_Macros
mbed_official 381:5460fc57b6e4 772 * @brief macros to handle SRAM read/write operations
mbed_official 381:5460fc57b6e4 773 * @{
mbed_official 381:5460fc57b6e4 774 */
mbed_official 381:5460fc57b6e4 775
mbed_official 381:5460fc57b6e4 776 /**
mbed_official 381:5460fc57b6e4 777 * @brief Enable the PCCARD device access.
mbed_official 381:5460fc57b6e4 778 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 779 * @retval None
mbed_official 381:5460fc57b6e4 780 */
mbed_official 381:5460fc57b6e4 781 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
mbed_official 381:5460fc57b6e4 782
mbed_official 381:5460fc57b6e4 783 /**
mbed_official 381:5460fc57b6e4 784 * @brief Disable the PCCARD device access.
mbed_official 381:5460fc57b6e4 785 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 786 * @retval None
mbed_official 381:5460fc57b6e4 787 */
mbed_official 381:5460fc57b6e4 788 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official 381:5460fc57b6e4 789 /**
mbed_official 381:5460fc57b6e4 790 * @}
mbed_official 381:5460fc57b6e4 791 */
mbed_official 381:5460fc57b6e4 792
mbed_official 381:5460fc57b6e4 793 /** @defgroup FMC_Interrupt
mbed_official 381:5460fc57b6e4 794 * @brief macros to handle FMC interrupts
mbed_official 381:5460fc57b6e4 795 * @{
mbed_official 381:5460fc57b6e4 796 */
mbed_official 381:5460fc57b6e4 797
mbed_official 381:5460fc57b6e4 798 /**
mbed_official 381:5460fc57b6e4 799 * @brief Enable the NAND device interrupt.
mbed_official 381:5460fc57b6e4 800 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 801 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 802 * @param __INTERRUPT__: FMC_NAND interrupt
mbed_official 381:5460fc57b6e4 803 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 804 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official 381:5460fc57b6e4 805 * @arg FMC_IT_LEVEL: Interrupt level.
mbed_official 381:5460fc57b6e4 806 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official 381:5460fc57b6e4 807 * @retval None
mbed_official 381:5460fc57b6e4 808 */
mbed_official 381:5460fc57b6e4 809 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
mbed_official 381:5460fc57b6e4 810 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
mbed_official 381:5460fc57b6e4 811
mbed_official 381:5460fc57b6e4 812 /**
mbed_official 381:5460fc57b6e4 813 * @brief Disable the NAND device interrupt.
mbed_official 381:5460fc57b6e4 814 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 815 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 816 * @param __INTERRUPT__: FMC_NAND interrupt
mbed_official 381:5460fc57b6e4 817 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 818 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official 381:5460fc57b6e4 819 * @arg FMC_IT_LEVEL: Interrupt level.
mbed_official 381:5460fc57b6e4 820 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official 381:5460fc57b6e4 821 * @retval None
mbed_official 381:5460fc57b6e4 822 */
mbed_official 381:5460fc57b6e4 823 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official 381:5460fc57b6e4 824 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official 381:5460fc57b6e4 825
mbed_official 381:5460fc57b6e4 826 /**
mbed_official 381:5460fc57b6e4 827 * @brief Get flag status of the NAND device.
mbed_official 381:5460fc57b6e4 828 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 829 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 830 * @param __FLAG__: FMC_NAND flag
mbed_official 381:5460fc57b6e4 831 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 832 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official 381:5460fc57b6e4 833 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official 381:5460fc57b6e4 834 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official 381:5460fc57b6e4 835 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official 381:5460fc57b6e4 836 * @retval The state of FLAG (SET or RESET).
mbed_official 381:5460fc57b6e4 837 */
mbed_official 381:5460fc57b6e4 838 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official 381:5460fc57b6e4 839 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official 381:5460fc57b6e4 840 /**
mbed_official 381:5460fc57b6e4 841 * @brief Clear flag status of the NAND device.
mbed_official 381:5460fc57b6e4 842 * @param __INSTANCE__: FMC_NAND Instance
mbed_official 381:5460fc57b6e4 843 * @param __BANK__: FMC_NAND Bank
mbed_official 381:5460fc57b6e4 844 * @param __FLAG__: FMC_NAND flag
mbed_official 381:5460fc57b6e4 845 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 846 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official 381:5460fc57b6e4 847 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official 381:5460fc57b6e4 848 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official 381:5460fc57b6e4 849 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official 381:5460fc57b6e4 850 * @retval None
mbed_official 381:5460fc57b6e4 851 */
mbed_official 381:5460fc57b6e4 852 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official 381:5460fc57b6e4 853 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official 381:5460fc57b6e4 854 /**
mbed_official 381:5460fc57b6e4 855 * @brief Enable the PCCARD device interrupt.
mbed_official 381:5460fc57b6e4 856 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 857 * @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official 381:5460fc57b6e4 858 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 859 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official 381:5460fc57b6e4 860 * @arg FMC_IT_LEVEL: Interrupt level.
mbed_official 381:5460fc57b6e4 861 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official 381:5460fc57b6e4 862 * @retval None
mbed_official 381:5460fc57b6e4 863 */
mbed_official 381:5460fc57b6e4 864 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
mbed_official 381:5460fc57b6e4 865
mbed_official 381:5460fc57b6e4 866 /**
mbed_official 381:5460fc57b6e4 867 * @brief Disable the PCCARD device interrupt.
mbed_official 381:5460fc57b6e4 868 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 869 * @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official 381:5460fc57b6e4 870 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 871 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official 381:5460fc57b6e4 872 * @arg FMC_IT_LEVEL: Interrupt level.
mbed_official 381:5460fc57b6e4 873 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official 381:5460fc57b6e4 874 * @retval None
mbed_official 381:5460fc57b6e4 875 */
mbed_official 381:5460fc57b6e4 876 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official 381:5460fc57b6e4 877
mbed_official 381:5460fc57b6e4 878 /**
mbed_official 381:5460fc57b6e4 879 * @brief Get flag status of the PCCARD device.
mbed_official 381:5460fc57b6e4 880 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 881 * @param __FLAG__: FMC_PCCARD flag
mbed_official 381:5460fc57b6e4 882 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 883 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official 381:5460fc57b6e4 884 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official 381:5460fc57b6e4 885 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official 381:5460fc57b6e4 886 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official 381:5460fc57b6e4 887 * @retval The state of FLAG (SET or RESET).
mbed_official 381:5460fc57b6e4 888 */
mbed_official 381:5460fc57b6e4 889 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official 381:5460fc57b6e4 890
mbed_official 381:5460fc57b6e4 891 /**
mbed_official 381:5460fc57b6e4 892 * @brief Clear flag status of the PCCARD device.
mbed_official 381:5460fc57b6e4 893 * @param __INSTANCE__: FMC_PCCARD Instance
mbed_official 381:5460fc57b6e4 894 * @param __FLAG__: FMC_PCCARD flag
mbed_official 381:5460fc57b6e4 895 * This parameter can be any combination of the following values:
mbed_official 381:5460fc57b6e4 896 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official 381:5460fc57b6e4 897 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official 381:5460fc57b6e4 898 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official 381:5460fc57b6e4 899 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official 381:5460fc57b6e4 900 * @retval None
mbed_official 381:5460fc57b6e4 901 */
mbed_official 381:5460fc57b6e4 902 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official 381:5460fc57b6e4 903
mbed_official 381:5460fc57b6e4 904 /**
mbed_official 381:5460fc57b6e4 905 * @}
mbed_official 381:5460fc57b6e4 906 */
mbed_official 381:5460fc57b6e4 907
mbed_official 381:5460fc57b6e4 908 /* Exported functions --------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 909
mbed_official 381:5460fc57b6e4 910 /* FMC_NORSRAM Controller functions *******************************************/
mbed_official 381:5460fc57b6e4 911 /* Initialization/de-initialization functions */
mbed_official 381:5460fc57b6e4 912 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
mbed_official 381:5460fc57b6e4 913 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
mbed_official 381:5460fc57b6e4 914 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official 381:5460fc57b6e4 915 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
mbed_official 381:5460fc57b6e4 916
mbed_official 381:5460fc57b6e4 917 /* FMC_NORSRAM Control functions */
mbed_official 381:5460fc57b6e4 918 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official 381:5460fc57b6e4 919 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official 381:5460fc57b6e4 920
mbed_official 381:5460fc57b6e4 921 /* FMC_NAND Controller functions **********************************************/
mbed_official 381:5460fc57b6e4 922 /* Initialization/de-initialization functions */
mbed_official 381:5460fc57b6e4 923 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
mbed_official 381:5460fc57b6e4 924 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
mbed_official 381:5460fc57b6e4 925 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
mbed_official 381:5460fc57b6e4 926 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official 381:5460fc57b6e4 927
mbed_official 381:5460fc57b6e4 928 /* FMC_NAND Control functions */
mbed_official 381:5460fc57b6e4 929 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official 381:5460fc57b6e4 930 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official 381:5460fc57b6e4 931 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official 381:5460fc57b6e4 932
mbed_official 381:5460fc57b6e4 933 /* FMC_PCCARD Controller functions ********************************************/
mbed_official 381:5460fc57b6e4 934 /* Initialization/de-initialization functions */
mbed_official 381:5460fc57b6e4 935 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
mbed_official 381:5460fc57b6e4 936 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
mbed_official 381:5460fc57b6e4 937 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
mbed_official 381:5460fc57b6e4 938 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
mbed_official 381:5460fc57b6e4 939 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official 381:5460fc57b6e4 940
mbed_official 381:5460fc57b6e4 941 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
mbed_official 381:5460fc57b6e4 942 /**
mbed_official 381:5460fc57b6e4 943 * @}
mbed_official 381:5460fc57b6e4 944 */
mbed_official 381:5460fc57b6e4 945
mbed_official 381:5460fc57b6e4 946 /**
mbed_official 381:5460fc57b6e4 947 * @}
mbed_official 381:5460fc57b6e4 948 */
mbed_official 381:5460fc57b6e4 949
mbed_official 381:5460fc57b6e4 950 #ifdef __cplusplus
mbed_official 381:5460fc57b6e4 951 }
mbed_official 381:5460fc57b6e4 952 #endif
mbed_official 381:5460fc57b6e4 953
mbed_official 381:5460fc57b6e4 954 #endif /* __STM32F3xx_LL_FMC_H */
mbed_official 381:5460fc57b6e4 955
mbed_official 381:5460fc57b6e4 956 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/