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targets/cmsis/TARGET_STM/TARGET_DISCO_F334C8/stm32f3xx_hal_tim.h@381:5460fc57b6e4, 2014-11-03 (annotated)

Committer:: mbed_official
Date:: Mon Nov 03 10:30:07 2014 +0000
Revision:: 381:5460fc57b6e4

Synchronized with git revision 02478cd1f27fc7b9643486472635eb515b2bca81

Full URL: https://github.com/mbedmicro/mbed/commit/02478cd1f27fc7b9643486472635eb515b2bca81/

Target: LPC1549 - Fix serial interrupt issues (issue report #616)

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	381:5460fc57b6e4	1	/**
mbed_official	381:5460fc57b6e4	2	******************************************************************************
mbed_official	381:5460fc57b6e4	3	* @file stm32f3xx_hal_tim.h
mbed_official	381:5460fc57b6e4	4	* @author MCD Application Team
mbed_official	381:5460fc57b6e4	5	* @version V1.1.0
mbed_official	381:5460fc57b6e4	6	* @date 12-Sept-2014
mbed_official	381:5460fc57b6e4	7	* @brief Header file of TIM HAL module.
mbed_official	381:5460fc57b6e4	8	******************************************************************************
mbed_official	381:5460fc57b6e4	9	* @attention
mbed_official	381:5460fc57b6e4	10	*
mbed_official	381:5460fc57b6e4	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	381:5460fc57b6e4	12	*
mbed_official	381:5460fc57b6e4	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	381:5460fc57b6e4	14	* are permitted provided that the following conditions are met:
mbed_official	381:5460fc57b6e4	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	381:5460fc57b6e4	16	* this list of conditions and the following disclaimer.
mbed_official	381:5460fc57b6e4	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	381:5460fc57b6e4	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	381:5460fc57b6e4	19	* and/or other materials provided with the distribution.
mbed_official	381:5460fc57b6e4	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	381:5460fc57b6e4	21	* may be used to endorse or promote products derived from this software
mbed_official	381:5460fc57b6e4	22	* without specific prior written permission.
mbed_official	381:5460fc57b6e4	23	*
mbed_official	381:5460fc57b6e4	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	381:5460fc57b6e4	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	381:5460fc57b6e4	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	381:5460fc57b6e4	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	381:5460fc57b6e4	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	381:5460fc57b6e4	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	381:5460fc57b6e4	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	381:5460fc57b6e4	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	381:5460fc57b6e4	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	381:5460fc57b6e4	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	381:5460fc57b6e4	34	*
mbed_official	381:5460fc57b6e4	35	******************************************************************************
mbed_official	381:5460fc57b6e4	36	*/
mbed_official	381:5460fc57b6e4	37
mbed_official	381:5460fc57b6e4	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	381:5460fc57b6e4	39	#ifndef __STM32F3xx_HAL_TIM_H
mbed_official	381:5460fc57b6e4	40	#define __STM32F3xx_HAL_TIM_H
mbed_official	381:5460fc57b6e4	41
mbed_official	381:5460fc57b6e4	42	#ifdef __cplusplus
mbed_official	381:5460fc57b6e4	43	extern "C" {
mbed_official	381:5460fc57b6e4	44	#endif
mbed_official	381:5460fc57b6e4	45
mbed_official	381:5460fc57b6e4	46	/* Includes ------------------------------------------------------------------*/
mbed_official	381:5460fc57b6e4	47	#include "stm32f3xx_hal_def.h"
mbed_official	381:5460fc57b6e4	48
mbed_official	381:5460fc57b6e4	49	/** @addtogroup STM32F3xx_HAL_Driver
mbed_official	381:5460fc57b6e4	50	* @{
mbed_official	381:5460fc57b6e4	51	*/
mbed_official	381:5460fc57b6e4	52
mbed_official	381:5460fc57b6e4	53	/** @addtogroup TIM
mbed_official	381:5460fc57b6e4	54	* @{
mbed_official	381:5460fc57b6e4	55	*/
mbed_official	381:5460fc57b6e4	56
mbed_official	381:5460fc57b6e4	57	/* Exported types ------------------------------------------------------------*/
mbed_official	381:5460fc57b6e4	58	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	381:5460fc57b6e4	59	* @{
mbed_official	381:5460fc57b6e4	60	*/
mbed_official	381:5460fc57b6e4	61
mbed_official	381:5460fc57b6e4	62	/**
mbed_official	381:5460fc57b6e4	63	* @brief TIM Time base Configuration Structure definition
mbed_official	381:5460fc57b6e4	64	*/
mbed_official	381:5460fc57b6e4	65	typedef struct
mbed_official	381:5460fc57b6e4	66	{
mbed_official	381:5460fc57b6e4	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	381:5460fc57b6e4	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	381:5460fc57b6e4	69
mbed_official	381:5460fc57b6e4	70	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	381:5460fc57b6e4	71	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	381:5460fc57b6e4	72
mbed_official	381:5460fc57b6e4	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	381:5460fc57b6e4	74	Auto-Reload Register at the next update event.
mbed_official	381:5460fc57b6e4	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	381:5460fc57b6e4	76
mbed_official	381:5460fc57b6e4	77	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	381:5460fc57b6e4	78	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	381:5460fc57b6e4	79
mbed_official	381:5460fc57b6e4	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	381:5460fc57b6e4	81	reaches zero, an update event is generated and counting restarts
mbed_official	381:5460fc57b6e4	82	from the RCR value (N).
mbed_official	381:5460fc57b6e4	83	This means in PWM mode that (N+1) corresponds to:
mbed_official	381:5460fc57b6e4	84	- the number of PWM periods in edge-aligned mode
mbed_official	381:5460fc57b6e4	85	- the number of half PWM period in center-aligned mode
mbed_official	381:5460fc57b6e4	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	381:5460fc57b6e4	87	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	88	} TIM_Base_InitTypeDef;
mbed_official	381:5460fc57b6e4	89
mbed_official	381:5460fc57b6e4	90	/**
mbed_official	381:5460fc57b6e4	91	* @brief TIM Output Compare Configuration Structure definition
mbed_official	381:5460fc57b6e4	92	*/
mbed_official	381:5460fc57b6e4	93	typedef struct
mbed_official	381:5460fc57b6e4	94	{
mbed_official	381:5460fc57b6e4	95	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	381:5460fc57b6e4	96	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
mbed_official	381:5460fc57b6e4	97
mbed_official	381:5460fc57b6e4	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	381:5460fc57b6e4	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	381:5460fc57b6e4	100
mbed_official	381:5460fc57b6e4	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	381:5460fc57b6e4	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	381:5460fc57b6e4	103
mbed_official	381:5460fc57b6e4	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	381:5460fc57b6e4	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	381:5460fc57b6e4	106	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	107
mbed_official	381:5460fc57b6e4	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	381:5460fc57b6e4	109	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	381:5460fc57b6e4	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	381:5460fc57b6e4	111
mbed_official	381:5460fc57b6e4	112
mbed_official	381:5460fc57b6e4	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	381:5460fc57b6e4	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	381:5460fc57b6e4	115	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	116
mbed_official	381:5460fc57b6e4	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	381:5460fc57b6e4	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	381:5460fc57b6e4	119	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	120	} TIM_OC_InitTypeDef;
mbed_official	381:5460fc57b6e4	121
mbed_official	381:5460fc57b6e4	122	/**
mbed_official	381:5460fc57b6e4	123	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	381:5460fc57b6e4	124	*/
mbed_official	381:5460fc57b6e4	125	typedef struct
mbed_official	381:5460fc57b6e4	126	{
mbed_official	381:5460fc57b6e4	127	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	381:5460fc57b6e4	128	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
mbed_official	381:5460fc57b6e4	129
mbed_official	381:5460fc57b6e4	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	381:5460fc57b6e4	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	381:5460fc57b6e4	132
mbed_official	381:5460fc57b6e4	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	381:5460fc57b6e4	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	381:5460fc57b6e4	135
mbed_official	381:5460fc57b6e4	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	381:5460fc57b6e4	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	381:5460fc57b6e4	138	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	139
mbed_official	381:5460fc57b6e4	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	381:5460fc57b6e4	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	381:5460fc57b6e4	142	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	143
mbed_official	381:5460fc57b6e4	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	381:5460fc57b6e4	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	381:5460fc57b6e4	146	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	381:5460fc57b6e4	147
mbed_official	381:5460fc57b6e4	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	381:5460fc57b6e4	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	381:5460fc57b6e4	150
mbed_official	381:5460fc57b6e4	151	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	381:5460fc57b6e4	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	381:5460fc57b6e4	153
mbed_official	381:5460fc57b6e4	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	381:5460fc57b6e4	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	381:5460fc57b6e4	156	} TIM_OnePulse_InitTypeDef;
mbed_official	381:5460fc57b6e4	157
mbed_official	381:5460fc57b6e4	158
mbed_official	381:5460fc57b6e4	159	/**
mbed_official	381:5460fc57b6e4	160	* @brief TIM Input Capture Configuration Structure definition
mbed_official	381:5460fc57b6e4	161	*/
mbed_official	381:5460fc57b6e4	162	typedef struct
mbed_official	381:5460fc57b6e4	163	{
mbed_official	381:5460fc57b6e4	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	381:5460fc57b6e4	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	381:5460fc57b6e4	166
mbed_official	381:5460fc57b6e4	167	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	381:5460fc57b6e4	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	381:5460fc57b6e4	169
mbed_official	381:5460fc57b6e4	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	381:5460fc57b6e4	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	381:5460fc57b6e4	172
mbed_official	381:5460fc57b6e4	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	381:5460fc57b6e4	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	381:5460fc57b6e4	175	} TIM_IC_InitTypeDef;
mbed_official	381:5460fc57b6e4	176
mbed_official	381:5460fc57b6e4	177	/**
mbed_official	381:5460fc57b6e4	178	* @brief TIM Encoder Configuration Structure definition
mbed_official	381:5460fc57b6e4	179	*/
mbed_official	381:5460fc57b6e4	180	typedef struct
mbed_official	381:5460fc57b6e4	181	{
mbed_official	381:5460fc57b6e4	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	381:5460fc57b6e4	183	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	381:5460fc57b6e4	184
mbed_official	381:5460fc57b6e4	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	381:5460fc57b6e4	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	381:5460fc57b6e4	187
mbed_official	381:5460fc57b6e4	188	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	381:5460fc57b6e4	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	381:5460fc57b6e4	190
mbed_official	381:5460fc57b6e4	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	381:5460fc57b6e4	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	381:5460fc57b6e4	193
mbed_official	381:5460fc57b6e4	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	381:5460fc57b6e4	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	381:5460fc57b6e4	196
mbed_official	381:5460fc57b6e4	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	381:5460fc57b6e4	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	381:5460fc57b6e4	199
mbed_official	381:5460fc57b6e4	200	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	381:5460fc57b6e4	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	381:5460fc57b6e4	202
mbed_official	381:5460fc57b6e4	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	381:5460fc57b6e4	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	381:5460fc57b6e4	205
mbed_official	381:5460fc57b6e4	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	381:5460fc57b6e4	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	381:5460fc57b6e4	208	} TIM_Encoder_InitTypeDef;
mbed_official	381:5460fc57b6e4	209
mbed_official	381:5460fc57b6e4	210
mbed_official	381:5460fc57b6e4	211	/**
mbed_official	381:5460fc57b6e4	212	* @brief Clock Configuration Handle Structure definition
mbed_official	381:5460fc57b6e4	213	*/
mbed_official	381:5460fc57b6e4	214	typedef struct
mbed_official	381:5460fc57b6e4	215	{
mbed_official	381:5460fc57b6e4	216	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	381:5460fc57b6e4	217	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	381:5460fc57b6e4	218	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	381:5460fc57b6e4	219	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	381:5460fc57b6e4	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	381:5460fc57b6e4	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	381:5460fc57b6e4	222	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	381:5460fc57b6e4	223	This parameter can be a value of @ref TIM_Clock_Filter */
mbed_official	381:5460fc57b6e4	224	}TIM_ClockConfigTypeDef;
mbed_official	381:5460fc57b6e4	225
mbed_official	381:5460fc57b6e4	226	/**
mbed_official	381:5460fc57b6e4	227	* @brief Clear Input Configuration Handle Structure definition
mbed_official	381:5460fc57b6e4	228	*/
mbed_official	381:5460fc57b6e4	229	typedef struct
mbed_official	381:5460fc57b6e4	230	{
mbed_official	381:5460fc57b6e4	231	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	381:5460fc57b6e4	232	This parameter can be ENABLE or DISABLE */
mbed_official	381:5460fc57b6e4	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	381:5460fc57b6e4	234	This parameter can be a value of @ref TIMEx_ClearInput_Source */
mbed_official	381:5460fc57b6e4	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	381:5460fc57b6e4	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	381:5460fc57b6e4	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	381:5460fc57b6e4	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	381:5460fc57b6e4	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	381:5460fc57b6e4	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
mbed_official	381:5460fc57b6e4	241	}TIM_ClearInputConfigTypeDef;
mbed_official	381:5460fc57b6e4	242
mbed_official	381:5460fc57b6e4	243	/**
mbed_official	381:5460fc57b6e4	244	* @brief TIM Slave configuration Structure definition
mbed_official	381:5460fc57b6e4	245	*/
mbed_official	381:5460fc57b6e4	246	typedef struct {
mbed_official	381:5460fc57b6e4	247	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	381:5460fc57b6e4	248	This parameter can be a value of @ref TIMEx_Slave_Mode */
mbed_official	381:5460fc57b6e4	249	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	381:5460fc57b6e4	250	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	381:5460fc57b6e4	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	381:5460fc57b6e4	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	381:5460fc57b6e4	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	381:5460fc57b6e4	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	381:5460fc57b6e4	255	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	381:5460fc57b6e4	256	This parameter can be a value of @ref TIM_Trigger_Filter */
mbed_official	381:5460fc57b6e4	257
mbed_official	381:5460fc57b6e4	258	}TIM_SlaveConfigTypeDef;
mbed_official	381:5460fc57b6e4	259
mbed_official	381:5460fc57b6e4	260	/**
mbed_official	381:5460fc57b6e4	261	* @brief HAL State structures definition
mbed_official	381:5460fc57b6e4	262	*/
mbed_official	381:5460fc57b6e4	263	typedef enum
mbed_official	381:5460fc57b6e4	264	{
mbed_official	381:5460fc57b6e4	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	381:5460fc57b6e4	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	381:5460fc57b6e4	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	381:5460fc57b6e4	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	381:5460fc57b6e4	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	381:5460fc57b6e4	270	}HAL_TIM_StateTypeDef;
mbed_official	381:5460fc57b6e4	271
mbed_official	381:5460fc57b6e4	272	/**
mbed_official	381:5460fc57b6e4	273	* @brief HAL Active channel structures definition
mbed_official	381:5460fc57b6e4	274	*/
mbed_official	381:5460fc57b6e4	275	typedef enum
mbed_official	381:5460fc57b6e4	276	{
mbed_official	381:5460fc57b6e4	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	381:5460fc57b6e4	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	381:5460fc57b6e4	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	381:5460fc57b6e4	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	381:5460fc57b6e4	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	381:5460fc57b6e4	282	}HAL_TIM_ActiveChannel;
mbed_official	381:5460fc57b6e4	283
mbed_official	381:5460fc57b6e4	284	/**
mbed_official	381:5460fc57b6e4	285	* @brief TIM Time Base Handle Structure definition
mbed_official	381:5460fc57b6e4	286	*/
mbed_official	381:5460fc57b6e4	287	typedef struct
mbed_official	381:5460fc57b6e4	288	{
mbed_official	381:5460fc57b6e4	289	TIM_TypeDef Instance; /!< Register base address */
mbed_official	381:5460fc57b6e4	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	381:5460fc57b6e4	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	381:5460fc57b6e4	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	381:5460fc57b6e4	293	This array is accessed by a @ref DMA_Handle_index */
mbed_official	381:5460fc57b6e4	294	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	381:5460fc57b6e4	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	381:5460fc57b6e4	296	}TIM_HandleTypeDef;
mbed_official	381:5460fc57b6e4	297
mbed_official	381:5460fc57b6e4	298	/**
mbed_official	381:5460fc57b6e4	299	* @}
mbed_official	381:5460fc57b6e4	300	*/
mbed_official	381:5460fc57b6e4	301
mbed_official	381:5460fc57b6e4	302	/* Exported constants --------------------------------------------------------*/
mbed_official	381:5460fc57b6e4	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	381:5460fc57b6e4	304	* @{
mbed_official	381:5460fc57b6e4	305	*/
mbed_official	381:5460fc57b6e4	306
mbed_official	381:5460fc57b6e4	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
mbed_official	381:5460fc57b6e4	308	* @{
mbed_official	381:5460fc57b6e4	309	*/
mbed_official	381:5460fc57b6e4	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	381:5460fc57b6e4	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	381:5460fc57b6e4	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	381:5460fc57b6e4	313	/**
mbed_official	381:5460fc57b6e4	314	* @}
mbed_official	381:5460fc57b6e4	315	*/
mbed_official	381:5460fc57b6e4	316
mbed_official	381:5460fc57b6e4	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
mbed_official	381:5460fc57b6e4	318	* @{
mbed_official	381:5460fc57b6e4	319	*/
mbed_official	381:5460fc57b6e4	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	381:5460fc57b6e4	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	381:5460fc57b6e4	322	/**
mbed_official	381:5460fc57b6e4	323	* @}
mbed_official	381:5460fc57b6e4	324	*/
mbed_official	381:5460fc57b6e4	325
mbed_official	381:5460fc57b6e4	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
mbed_official	381:5460fc57b6e4	327	* @{
mbed_official	381:5460fc57b6e4	328	*/
mbed_official	381:5460fc57b6e4	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	381:5460fc57b6e4	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	381:5460fc57b6e4	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	381:5460fc57b6e4	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	381:5460fc57b6e4	333	/**
mbed_official	381:5460fc57b6e4	334	* @}
mbed_official	381:5460fc57b6e4	335	*/
mbed_official	381:5460fc57b6e4	336
mbed_official	381:5460fc57b6e4	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
mbed_official	381:5460fc57b6e4	338	* @{
mbed_official	381:5460fc57b6e4	339	*/
mbed_official	381:5460fc57b6e4	340
mbed_official	381:5460fc57b6e4	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	381:5460fc57b6e4	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	381:5460fc57b6e4	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	381:5460fc57b6e4	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	381:5460fc57b6e4	346
mbed_official	381:5460fc57b6e4	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	381:5460fc57b6e4	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	381:5460fc57b6e4	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	381:5460fc57b6e4	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	381:5460fc57b6e4	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	381:5460fc57b6e4	352	/**
mbed_official	381:5460fc57b6e4	353	* @}
mbed_official	381:5460fc57b6e4	354	*/
mbed_official	381:5460fc57b6e4	355
mbed_official	381:5460fc57b6e4	356	/** @defgroup TIM_ClockDivision TIM Clock Division
mbed_official	381:5460fc57b6e4	357	* @{
mbed_official	381:5460fc57b6e4	358	*/
mbed_official	381:5460fc57b6e4	359
mbed_official	381:5460fc57b6e4	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	381:5460fc57b6e4	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	381:5460fc57b6e4	363
mbed_official	381:5460fc57b6e4	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	381:5460fc57b6e4	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	381:5460fc57b6e4	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	381:5460fc57b6e4	367	/**
mbed_official	381:5460fc57b6e4	368	* @}
mbed_official	381:5460fc57b6e4	369	*/
mbed_official	381:5460fc57b6e4	370
mbed_official	381:5460fc57b6e4	371	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
mbed_official	381:5460fc57b6e4	372	* @{
mbed_official	381:5460fc57b6e4	373	*/
mbed_official	381:5460fc57b6e4	374
mbed_official	381:5460fc57b6e4	375	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	376	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	381:5460fc57b6e4	377
mbed_official	381:5460fc57b6e4	378	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
mbed_official	381:5460fc57b6e4	379	((STATE) == TIM_OUTPUTSTATE_ENABLE))
mbed_official	381:5460fc57b6e4	380	/**
mbed_official	381:5460fc57b6e4	381	* @}
mbed_official	381:5460fc57b6e4	382	*/
mbed_official	381:5460fc57b6e4	383	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
mbed_official	381:5460fc57b6e4	384	* @{
mbed_official	381:5460fc57b6e4	385	*/
mbed_official	381:5460fc57b6e4	386	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	387	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	381:5460fc57b6e4	388
mbed_official	381:5460fc57b6e4	389	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	381:5460fc57b6e4	390	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	381:5460fc57b6e4	391	/**
mbed_official	381:5460fc57b6e4	392	* @}
mbed_official	381:5460fc57b6e4	393	*/
mbed_official	381:5460fc57b6e4	394	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
mbed_official	381:5460fc57b6e4	395	* @{
mbed_official	381:5460fc57b6e4	396	*/
mbed_official	381:5460fc57b6e4	397
mbed_official	381:5460fc57b6e4	398	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	399	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	381:5460fc57b6e4	400
mbed_official	381:5460fc57b6e4	401	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
mbed_official	381:5460fc57b6e4	402	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
mbed_official	381:5460fc57b6e4	403	/**
mbed_official	381:5460fc57b6e4	404	* @}
mbed_official	381:5460fc57b6e4	405	*/
mbed_official	381:5460fc57b6e4	406
mbed_official	381:5460fc57b6e4	407	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
mbed_official	381:5460fc57b6e4	408	* @{
mbed_official	381:5460fc57b6e4	409	*/
mbed_official	381:5460fc57b6e4	410
mbed_official	381:5460fc57b6e4	411	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	412	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	381:5460fc57b6e4	413
mbed_official	381:5460fc57b6e4	414	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	381:5460fc57b6e4	415	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	381:5460fc57b6e4	416	/**
mbed_official	381:5460fc57b6e4	417	* @}
mbed_official	381:5460fc57b6e4	418	*/
mbed_official	381:5460fc57b6e4	419
mbed_official	381:5460fc57b6e4	420	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
mbed_official	381:5460fc57b6e4	421	* @{
mbed_official	381:5460fc57b6e4	422	*/
mbed_official	381:5460fc57b6e4	423
mbed_official	381:5460fc57b6e4	424	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	425	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	381:5460fc57b6e4	426
mbed_official	381:5460fc57b6e4	427	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	381:5460fc57b6e4	428	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	381:5460fc57b6e4	429	/**
mbed_official	381:5460fc57b6e4	430	* @}
mbed_official	381:5460fc57b6e4	431	*/
mbed_official	381:5460fc57b6e4	432
mbed_official	381:5460fc57b6e4	433	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
mbed_official	381:5460fc57b6e4	434	* @{
mbed_official	381:5460fc57b6e4	435	*/
mbed_official	381:5460fc57b6e4	436
mbed_official	381:5460fc57b6e4	437	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	381:5460fc57b6e4	438	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	439	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	381:5460fc57b6e4	440	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	381:5460fc57b6e4	441	/**
mbed_official	381:5460fc57b6e4	442	* @}
mbed_official	381:5460fc57b6e4	443	*/
mbed_official	381:5460fc57b6e4	444
mbed_official	381:5460fc57b6e4	445	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
mbed_official	381:5460fc57b6e4	446	* @{
mbed_official	381:5460fc57b6e4	447	*/
mbed_official	381:5460fc57b6e4	448
mbed_official	381:5460fc57b6e4	449	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	381:5460fc57b6e4	450	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	451	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	381:5460fc57b6e4	452	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	381:5460fc57b6e4	453	/**
mbed_official	381:5460fc57b6e4	454	* @}
mbed_official	381:5460fc57b6e4	455	*/
mbed_official	381:5460fc57b6e4	456
mbed_official	381:5460fc57b6e4	457
mbed_official	381:5460fc57b6e4	458
mbed_official	381:5460fc57b6e4	459	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
mbed_official	381:5460fc57b6e4	460	* @{
mbed_official	381:5460fc57b6e4	461	*/
mbed_official	381:5460fc57b6e4	462
mbed_official	381:5460fc57b6e4	463	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	381:5460fc57b6e4	464	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	381:5460fc57b6e4	465	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	381:5460fc57b6e4	466
mbed_official	381:5460fc57b6e4	467	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	381:5460fc57b6e4	468	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	381:5460fc57b6e4	469	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	381:5460fc57b6e4	470	/**
mbed_official	381:5460fc57b6e4	471	* @}
mbed_official	381:5460fc57b6e4	472	*/
mbed_official	381:5460fc57b6e4	473
mbed_official	381:5460fc57b6e4	474	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
mbed_official	381:5460fc57b6e4	475	* @{
mbed_official	381:5460fc57b6e4	476	*/
mbed_official	381:5460fc57b6e4	477
mbed_official	381:5460fc57b6e4	478	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	381:5460fc57b6e4	479	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	381:5460fc57b6e4	480	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	381:5460fc57b6e4	481	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	381:5460fc57b6e4	482	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	381:5460fc57b6e4	483
mbed_official	381:5460fc57b6e4	484	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	381:5460fc57b6e4	485	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	381:5460fc57b6e4	486	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	381:5460fc57b6e4	487	/**
mbed_official	381:5460fc57b6e4	488	* @}
mbed_official	381:5460fc57b6e4	489	*/
mbed_official	381:5460fc57b6e4	490
mbed_official	381:5460fc57b6e4	491	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
mbed_official	381:5460fc57b6e4	492	* @{
mbed_official	381:5460fc57b6e4	493	*/
mbed_official	381:5460fc57b6e4	494
mbed_official	381:5460fc57b6e4	495	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	381:5460fc57b6e4	496	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	381:5460fc57b6e4	497	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	381:5460fc57b6e4	498	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	381:5460fc57b6e4	499
mbed_official	381:5460fc57b6e4	500	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	381:5460fc57b6e4	501	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	381:5460fc57b6e4	502	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	381:5460fc57b6e4	503	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	381:5460fc57b6e4	504	/**
mbed_official	381:5460fc57b6e4	505	* @}
mbed_official	381:5460fc57b6e4	506	*/
mbed_official	381:5460fc57b6e4	507
mbed_official	381:5460fc57b6e4	508	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
mbed_official	381:5460fc57b6e4	509	* @{
mbed_official	381:5460fc57b6e4	510	*/
mbed_official	381:5460fc57b6e4	511
mbed_official	381:5460fc57b6e4	512	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	381:5460fc57b6e4	513	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	514	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	381:5460fc57b6e4	515	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	381:5460fc57b6e4	516	/**
mbed_official	381:5460fc57b6e4	517	* @}
mbed_official	381:5460fc57b6e4	518	*/
mbed_official	381:5460fc57b6e4	519	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
mbed_official	381:5460fc57b6e4	520	* @{
mbed_official	381:5460fc57b6e4	521	*/
mbed_official	381:5460fc57b6e4	522	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	381:5460fc57b6e4	523	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	381:5460fc57b6e4	524	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	381:5460fc57b6e4	525	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	381:5460fc57b6e4	526	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	381:5460fc57b6e4	527	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	381:5460fc57b6e4	528	/**
mbed_official	381:5460fc57b6e4	529	* @}
mbed_official	381:5460fc57b6e4	530	*/
mbed_official	381:5460fc57b6e4	531	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
mbed_official	381:5460fc57b6e4	532	* @{
mbed_official	381:5460fc57b6e4	533	*/
mbed_official	381:5460fc57b6e4	534	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	381:5460fc57b6e4	535	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	381:5460fc57b6e4	536	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	381:5460fc57b6e4	537	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	381:5460fc57b6e4	538	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	381:5460fc57b6e4	539	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	381:5460fc57b6e4	540	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	381:5460fc57b6e4	541	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	381:5460fc57b6e4	542
mbed_official	381:5460fc57b6e4	543	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	381:5460fc57b6e4	544
mbed_official	381:5460fc57b6e4	545	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
mbed_official	381:5460fc57b6e4	546	((IT) == TIM_IT_CC1) \|\| \
mbed_official	381:5460fc57b6e4	547	((IT) == TIM_IT_CC2) \|\| \
mbed_official	381:5460fc57b6e4	548	((IT) == TIM_IT_CC3) \|\| \
mbed_official	381:5460fc57b6e4	549	((IT) == TIM_IT_CC4) \|\| \
mbed_official	381:5460fc57b6e4	550	((IT) == TIM_IT_COM) \|\| \
mbed_official	381:5460fc57b6e4	551	((IT) == TIM_IT_TRIGGER) \|\| \
mbed_official	381:5460fc57b6e4	552	((IT) == TIM_IT_BREAK))
mbed_official	381:5460fc57b6e4	553	/**
mbed_official	381:5460fc57b6e4	554	* @}
mbed_official	381:5460fc57b6e4	555	*/
mbed_official	381:5460fc57b6e4	556	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	381:5460fc57b6e4	557	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	558
mbed_official	381:5460fc57b6e4	559	/** @defgroup TIM_DMA_sources TIM DMA Sources
mbed_official	381:5460fc57b6e4	560	* @{
mbed_official	381:5460fc57b6e4	561	*/
mbed_official	381:5460fc57b6e4	562
mbed_official	381:5460fc57b6e4	563	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	381:5460fc57b6e4	564	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	381:5460fc57b6e4	565	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	381:5460fc57b6e4	566	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	381:5460fc57b6e4	567	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	381:5460fc57b6e4	568	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	381:5460fc57b6e4	569	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	381:5460fc57b6e4	570	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	381:5460fc57b6e4	571
mbed_official	381:5460fc57b6e4	572	/**
mbed_official	381:5460fc57b6e4	573	* @}
mbed_official	381:5460fc57b6e4	574	*/
mbed_official	381:5460fc57b6e4	575
mbed_official	381:5460fc57b6e4	576	/** @defgroup TIM_Flag_definition TIM Flag Definition
mbed_official	381:5460fc57b6e4	577	* @{
mbed_official	381:5460fc57b6e4	578	*/
mbed_official	381:5460fc57b6e4	579
mbed_official	381:5460fc57b6e4	580	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	381:5460fc57b6e4	581	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	381:5460fc57b6e4	582	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	381:5460fc57b6e4	583	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	381:5460fc57b6e4	584	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	381:5460fc57b6e4	585	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	381:5460fc57b6e4	586	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	381:5460fc57b6e4	587	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	381:5460fc57b6e4	588	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	381:5460fc57b6e4	589	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	381:5460fc57b6e4	590	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	381:5460fc57b6e4	591	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	381:5460fc57b6e4	592
mbed_official	381:5460fc57b6e4	593	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	381:5460fc57b6e4	594	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	381:5460fc57b6e4	595	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	381:5460fc57b6e4	596	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	381:5460fc57b6e4	597	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	381:5460fc57b6e4	598	((FLAG) == TIM_FLAG_COM) \|\| \
mbed_official	381:5460fc57b6e4	599	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	381:5460fc57b6e4	600	((FLAG) == TIM_FLAG_BREAK) \|\| \
mbed_official	381:5460fc57b6e4	601	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	381:5460fc57b6e4	602	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	381:5460fc57b6e4	603	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	381:5460fc57b6e4	604	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	381:5460fc57b6e4	605	/**
mbed_official	381:5460fc57b6e4	606	* @}
mbed_official	381:5460fc57b6e4	607	*/
mbed_official	381:5460fc57b6e4	608
mbed_official	381:5460fc57b6e4	609	/** @defgroup TIM_Clock_Source TIM Clock Source
mbed_official	381:5460fc57b6e4	610	* @{
mbed_official	381:5460fc57b6e4	611	*/
mbed_official	381:5460fc57b6e4	612	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	381:5460fc57b6e4	613	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	381:5460fc57b6e4	614	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	615	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	381:5460fc57b6e4	616	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	381:5460fc57b6e4	617	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	381:5460fc57b6e4	618	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	381:5460fc57b6e4	619	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	381:5460fc57b6e4	620	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	381:5460fc57b6e4	621	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	381:5460fc57b6e4	622
mbed_official	381:5460fc57b6e4	623	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	381:5460fc57b6e4	624	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	381:5460fc57b6e4	625	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	381:5460fc57b6e4	626	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	381:5460fc57b6e4	627	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	381:5460fc57b6e4	628	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	381:5460fc57b6e4	629	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	381:5460fc57b6e4	630	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	381:5460fc57b6e4	631	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	381:5460fc57b6e4	632	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	381:5460fc57b6e4	633	/**
mbed_official	381:5460fc57b6e4	634	* @}
mbed_official	381:5460fc57b6e4	635	*/
mbed_official	381:5460fc57b6e4	636
mbed_official	381:5460fc57b6e4	637	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
mbed_official	381:5460fc57b6e4	638	* @{
mbed_official	381:5460fc57b6e4	639	*/
mbed_official	381:5460fc57b6e4	640	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	381:5460fc57b6e4	641	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	381:5460fc57b6e4	642	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	381:5460fc57b6e4	643	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	381:5460fc57b6e4	644	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	381:5460fc57b6e4	645
mbed_official	381:5460fc57b6e4	646	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	381:5460fc57b6e4	647	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	381:5460fc57b6e4	648	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	381:5460fc57b6e4	649	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	381:5460fc57b6e4	650	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	381:5460fc57b6e4	651	/**
mbed_official	381:5460fc57b6e4	652	* @}
mbed_official	381:5460fc57b6e4	653	*/
mbed_official	381:5460fc57b6e4	654	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
mbed_official	381:5460fc57b6e4	655	* @{
mbed_official	381:5460fc57b6e4	656	*/
mbed_official	381:5460fc57b6e4	657	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	381:5460fc57b6e4	658	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	381:5460fc57b6e4	659	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	381:5460fc57b6e4	660	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	381:5460fc57b6e4	661
mbed_official	381:5460fc57b6e4	662	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	381:5460fc57b6e4	663	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	381:5460fc57b6e4	664	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	381:5460fc57b6e4	665	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	381:5460fc57b6e4	666	/**
mbed_official	381:5460fc57b6e4	667	* @}
mbed_official	381:5460fc57b6e4	668	*/
mbed_official	381:5460fc57b6e4	669	/** @defgroup TIM_Clock_Filter TIM Clock Filter
mbed_official	381:5460fc57b6e4	670	* @{
mbed_official	381:5460fc57b6e4	671	*/
mbed_official	381:5460fc57b6e4	672
mbed_official	381:5460fc57b6e4	673	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	381:5460fc57b6e4	674	/**
mbed_official	381:5460fc57b6e4	675	* @}
mbed_official	381:5460fc57b6e4	676	*/
mbed_official	381:5460fc57b6e4	677
mbed_official	381:5460fc57b6e4	678	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
mbed_official	381:5460fc57b6e4	679	* @{
mbed_official	381:5460fc57b6e4	680	*/
mbed_official	381:5460fc57b6e4	681	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	381:5460fc57b6e4	682	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	381:5460fc57b6e4	683
mbed_official	381:5460fc57b6e4	684
mbed_official	381:5460fc57b6e4	685	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	381:5460fc57b6e4	686	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	381:5460fc57b6e4	687	/**
mbed_official	381:5460fc57b6e4	688	* @}
mbed_official	381:5460fc57b6e4	689	*/
mbed_official	381:5460fc57b6e4	690
mbed_official	381:5460fc57b6e4	691	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
mbed_official	381:5460fc57b6e4	692	* @{
mbed_official	381:5460fc57b6e4	693	*/
mbed_official	381:5460fc57b6e4	694	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	381:5460fc57b6e4	695	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	381:5460fc57b6e4	696	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	381:5460fc57b6e4	697	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	381:5460fc57b6e4	698	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	381:5460fc57b6e4	699	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	381:5460fc57b6e4	700	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	381:5460fc57b6e4	701	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	381:5460fc57b6e4	702	/**
mbed_official	381:5460fc57b6e4	703	* @}
mbed_official	381:5460fc57b6e4	704	*/
mbed_official	381:5460fc57b6e4	705
mbed_official	381:5460fc57b6e4	706	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
mbed_official	381:5460fc57b6e4	707	* @{
mbed_official	381:5460fc57b6e4	708	*/
mbed_official	381:5460fc57b6e4	709
mbed_official	381:5460fc57b6e4	710	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	381:5460fc57b6e4	711	/**
mbed_official	381:5460fc57b6e4	712	* @}
mbed_official	381:5460fc57b6e4	713	*/
mbed_official	381:5460fc57b6e4	714
mbed_official	381:5460fc57b6e4	715	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
mbed_official	381:5460fc57b6e4	716	* @{
mbed_official	381:5460fc57b6e4	717	*/
mbed_official	381:5460fc57b6e4	718	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	381:5460fc57b6e4	719	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	720
mbed_official	381:5460fc57b6e4	721	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	722	((STATE) == TIM_OSSR_DISABLE))
mbed_official	381:5460fc57b6e4	723	/**
mbed_official	381:5460fc57b6e4	724	* @}
mbed_official	381:5460fc57b6e4	725	*/
mbed_official	381:5460fc57b6e4	726
mbed_official	381:5460fc57b6e4	727	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
mbed_official	381:5460fc57b6e4	728	* @{
mbed_official	381:5460fc57b6e4	729	*/
mbed_official	381:5460fc57b6e4	730	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	381:5460fc57b6e4	731	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	732
mbed_official	381:5460fc57b6e4	733	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	734	((STATE) == TIM_OSSI_DISABLE))
mbed_official	381:5460fc57b6e4	735	/**
mbed_official	381:5460fc57b6e4	736	* @}
mbed_official	381:5460fc57b6e4	737	*/
mbed_official	381:5460fc57b6e4	738	/** @defgroup TIM_Lock_level TIM Lock Configuration
mbed_official	381:5460fc57b6e4	739	* @{
mbed_official	381:5460fc57b6e4	740	*/
mbed_official	381:5460fc57b6e4	741	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	742	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	381:5460fc57b6e4	743	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	381:5460fc57b6e4	744	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	381:5460fc57b6e4	745
mbed_official	381:5460fc57b6e4	746	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	381:5460fc57b6e4	747	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	381:5460fc57b6e4	748	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	381:5460fc57b6e4	749	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	381:5460fc57b6e4	750	/**
mbed_official	381:5460fc57b6e4	751	* @}
mbed_official	381:5460fc57b6e4	752	*/
mbed_official	381:5460fc57b6e4	753	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
mbed_official	381:5460fc57b6e4	754	* @{
mbed_official	381:5460fc57b6e4	755	*/
mbed_official	381:5460fc57b6e4	756	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	381:5460fc57b6e4	757	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	758
mbed_official	381:5460fc57b6e4	759	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	760	((STATE) == TIM_BREAK_DISABLE))
mbed_official	381:5460fc57b6e4	761	/**
mbed_official	381:5460fc57b6e4	762	* @}
mbed_official	381:5460fc57b6e4	763	*/
mbed_official	381:5460fc57b6e4	764	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
mbed_official	381:5460fc57b6e4	765	* @{
mbed_official	381:5460fc57b6e4	766	*/
mbed_official	381:5460fc57b6e4	767	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	768	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	381:5460fc57b6e4	769
mbed_official	381:5460fc57b6e4	770	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	381:5460fc57b6e4	771	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	381:5460fc57b6e4	772	/**
mbed_official	381:5460fc57b6e4	773	* @}
mbed_official	381:5460fc57b6e4	774	*/
mbed_official	381:5460fc57b6e4	775	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
mbed_official	381:5460fc57b6e4	776	* @{
mbed_official	381:5460fc57b6e4	777	*/
mbed_official	381:5460fc57b6e4	778	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	381:5460fc57b6e4	779	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	780
mbed_official	381:5460fc57b6e4	781	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	782	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	381:5460fc57b6e4	783	/**
mbed_official	381:5460fc57b6e4	784	* @}
mbed_official	381:5460fc57b6e4	785	*/
mbed_official	381:5460fc57b6e4	786
mbed_official	381:5460fc57b6e4	787	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	381:5460fc57b6e4	788	* @{
mbed_official	381:5460fc57b6e4	789	*/
mbed_official	381:5460fc57b6e4	790	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	791	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	381:5460fc57b6e4	792	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	381:5460fc57b6e4	793	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	381:5460fc57b6e4	794	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	381:5460fc57b6e4	795	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	381:5460fc57b6e4	796	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	381:5460fc57b6e4	797	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	381:5460fc57b6e4	798
mbed_official	381:5460fc57b6e4	799	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	381:5460fc57b6e4	800	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	801	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	381:5460fc57b6e4	802	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	381:5460fc57b6e4	803	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	381:5460fc57b6e4	804	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	381:5460fc57b6e4	805	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	381:5460fc57b6e4	806	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	381:5460fc57b6e4	807
mbed_official	381:5460fc57b6e4	808
mbed_official	381:5460fc57b6e4	809	/**
mbed_official	381:5460fc57b6e4	810	* @}
mbed_official	381:5460fc57b6e4	811	*/
mbed_official	381:5460fc57b6e4	812	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
mbed_official	381:5460fc57b6e4	813	* @{
mbed_official	381:5460fc57b6e4	814	*/
mbed_official	381:5460fc57b6e4	815
mbed_official	381:5460fc57b6e4	816	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	381:5460fc57b6e4	817	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	818	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	381:5460fc57b6e4	819	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	381:5460fc57b6e4	820	/**
mbed_official	381:5460fc57b6e4	821	* @}
mbed_official	381:5460fc57b6e4	822	*/
mbed_official	381:5460fc57b6e4	823	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
mbed_official	381:5460fc57b6e4	824	* @{
mbed_official	381:5460fc57b6e4	825	*/
mbed_official	381:5460fc57b6e4	826
mbed_official	381:5460fc57b6e4	827	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	828	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	381:5460fc57b6e4	829	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	381:5460fc57b6e4	830	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	381:5460fc57b6e4	831	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	381:5460fc57b6e4	832	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	381:5460fc57b6e4	833	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	381:5460fc57b6e4	834	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	381:5460fc57b6e4	835	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	381:5460fc57b6e4	836	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	381:5460fc57b6e4	837	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	381:5460fc57b6e4	838	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	381:5460fc57b6e4	839	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	381:5460fc57b6e4	840	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	381:5460fc57b6e4	841	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	381:5460fc57b6e4	842	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	381:5460fc57b6e4	843	((SELECTION) == TIM_TS_ETRF))
mbed_official	381:5460fc57b6e4	844	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	381:5460fc57b6e4	845	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	381:5460fc57b6e4	846	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	381:5460fc57b6e4	847	((SELECTION) == TIM_TS_ITR3))
mbed_official	381:5460fc57b6e4	848	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	381:5460fc57b6e4	849	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	381:5460fc57b6e4	850	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	381:5460fc57b6e4	851	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	381:5460fc57b6e4	852	((SELECTION) == TIM_TS_NONE))
mbed_official	381:5460fc57b6e4	853	/**
mbed_official	381:5460fc57b6e4	854	* @}
mbed_official	381:5460fc57b6e4	855	*/
mbed_official	381:5460fc57b6e4	856
mbed_official	381:5460fc57b6e4	857	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
mbed_official	381:5460fc57b6e4	858	* @{
mbed_official	381:5460fc57b6e4	859	*/
mbed_official	381:5460fc57b6e4	860	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	381:5460fc57b6e4	861	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	381:5460fc57b6e4	862	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	381:5460fc57b6e4	863	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	381:5460fc57b6e4	864	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	381:5460fc57b6e4	865
mbed_official	381:5460fc57b6e4	866	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	381:5460fc57b6e4	867	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	381:5460fc57b6e4	868	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	381:5460fc57b6e4	869	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	381:5460fc57b6e4	870	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	381:5460fc57b6e4	871	/**
mbed_official	381:5460fc57b6e4	872	* @}
mbed_official	381:5460fc57b6e4	873	*/
mbed_official	381:5460fc57b6e4	874
mbed_official	381:5460fc57b6e4	875	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
mbed_official	381:5460fc57b6e4	876	* @{
mbed_official	381:5460fc57b6e4	877	*/
mbed_official	381:5460fc57b6e4	878	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	381:5460fc57b6e4	879	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	381:5460fc57b6e4	880	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	381:5460fc57b6e4	881	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	381:5460fc57b6e4	882
mbed_official	381:5460fc57b6e4	883	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	381:5460fc57b6e4	884	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	381:5460fc57b6e4	885	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	381:5460fc57b6e4	886	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	381:5460fc57b6e4	887	/**
mbed_official	381:5460fc57b6e4	888	* @}
mbed_official	381:5460fc57b6e4	889	*/
mbed_official	381:5460fc57b6e4	890
mbed_official	381:5460fc57b6e4	891	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
mbed_official	381:5460fc57b6e4	892	* @{
mbed_official	381:5460fc57b6e4	893	*/
mbed_official	381:5460fc57b6e4	894
mbed_official	381:5460fc57b6e4	895	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	381:5460fc57b6e4	896	/**
mbed_official	381:5460fc57b6e4	897	* @}
mbed_official	381:5460fc57b6e4	898	*/
mbed_official	381:5460fc57b6e4	899
mbed_official	381:5460fc57b6e4	900	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
mbed_official	381:5460fc57b6e4	901	* @{
mbed_official	381:5460fc57b6e4	902	*/
mbed_official	381:5460fc57b6e4	903
mbed_official	381:5460fc57b6e4	904	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	905	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	381:5460fc57b6e4	906
mbed_official	381:5460fc57b6e4	907	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	381:5460fc57b6e4	908	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	381:5460fc57b6e4	909
mbed_official	381:5460fc57b6e4	910	/**
mbed_official	381:5460fc57b6e4	911	* @}
mbed_official	381:5460fc57b6e4	912	*/
mbed_official	381:5460fc57b6e4	913
mbed_official	381:5460fc57b6e4	914	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
mbed_official	381:5460fc57b6e4	915	* @{
mbed_official	381:5460fc57b6e4	916	*/
mbed_official	381:5460fc57b6e4	917
mbed_official	381:5460fc57b6e4	918	#define TIM_DMABurstLength_1Transfer (0x00000000)
mbed_official	381:5460fc57b6e4	919	#define TIM_DMABurstLength_2Transfers (0x00000100)
mbed_official	381:5460fc57b6e4	920	#define TIM_DMABurstLength_3Transfers (0x00000200)
mbed_official	381:5460fc57b6e4	921	#define TIM_DMABurstLength_4Transfers (0x00000300)
mbed_official	381:5460fc57b6e4	922	#define TIM_DMABurstLength_5Transfers (0x00000400)
mbed_official	381:5460fc57b6e4	923	#define TIM_DMABurstLength_6Transfers (0x00000500)
mbed_official	381:5460fc57b6e4	924	#define TIM_DMABurstLength_7Transfers (0x00000600)
mbed_official	381:5460fc57b6e4	925	#define TIM_DMABurstLength_8Transfers (0x00000700)
mbed_official	381:5460fc57b6e4	926	#define TIM_DMABurstLength_9Transfers (0x00000800)
mbed_official	381:5460fc57b6e4	927	#define TIM_DMABurstLength_10Transfers (0x00000900)
mbed_official	381:5460fc57b6e4	928	#define TIM_DMABurstLength_11Transfers (0x00000A00)
mbed_official	381:5460fc57b6e4	929	#define TIM_DMABurstLength_12Transfers (0x00000B00)
mbed_official	381:5460fc57b6e4	930	#define TIM_DMABurstLength_13Transfers (0x00000C00)
mbed_official	381:5460fc57b6e4	931	#define TIM_DMABurstLength_14Transfers (0x00000D00)
mbed_official	381:5460fc57b6e4	932	#define TIM_DMABurstLength_15Transfers (0x00000E00)
mbed_official	381:5460fc57b6e4	933	#define TIM_DMABurstLength_16Transfers (0x00000F00)
mbed_official	381:5460fc57b6e4	934	#define TIM_DMABurstLength_17Transfers (0x00001000)
mbed_official	381:5460fc57b6e4	935	#define TIM_DMABurstLength_18Transfers (0x00001100)
mbed_official	381:5460fc57b6e4	936	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
mbed_official	381:5460fc57b6e4	937	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
mbed_official	381:5460fc57b6e4	938	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
mbed_official	381:5460fc57b6e4	939	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
mbed_official	381:5460fc57b6e4	940	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
mbed_official	381:5460fc57b6e4	941	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
mbed_official	381:5460fc57b6e4	942	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
mbed_official	381:5460fc57b6e4	943	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
mbed_official	381:5460fc57b6e4	944	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
mbed_official	381:5460fc57b6e4	945	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
mbed_official	381:5460fc57b6e4	946	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
mbed_official	381:5460fc57b6e4	947	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
mbed_official	381:5460fc57b6e4	948	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
mbed_official	381:5460fc57b6e4	949	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
mbed_official	381:5460fc57b6e4	950	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
mbed_official	381:5460fc57b6e4	951	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
mbed_official	381:5460fc57b6e4	952	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
mbed_official	381:5460fc57b6e4	953	((LENGTH) == TIM_DMABurstLength_18Transfers))
mbed_official	381:5460fc57b6e4	954	/**
mbed_official	381:5460fc57b6e4	955	* @}
mbed_official	381:5460fc57b6e4	956	*/
mbed_official	381:5460fc57b6e4	957
mbed_official	381:5460fc57b6e4	958	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
mbed_official	381:5460fc57b6e4	959	* @{
mbed_official	381:5460fc57b6e4	960	*/
mbed_official	381:5460fc57b6e4	961
mbed_official	381:5460fc57b6e4	962	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	381:5460fc57b6e4	963	/**
mbed_official	381:5460fc57b6e4	964	* @}
mbed_official	381:5460fc57b6e4	965	*/
mbed_official	381:5460fc57b6e4	966
mbed_official	381:5460fc57b6e4	967	/** @defgroup DMA_Handle_index TIM DMA Handle Index
mbed_official	381:5460fc57b6e4	968	* @{
mbed_official	381:5460fc57b6e4	969	*/
mbed_official	381:5460fc57b6e4	970	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	381:5460fc57b6e4	971	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	381:5460fc57b6e4	972	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	381:5460fc57b6e4	973	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	381:5460fc57b6e4	974	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	381:5460fc57b6e4	975	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	381:5460fc57b6e4	976	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	381:5460fc57b6e4	977	/**
mbed_official	381:5460fc57b6e4	978	* @}
mbed_official	381:5460fc57b6e4	979	*/
mbed_official	381:5460fc57b6e4	980
mbed_official	381:5460fc57b6e4	981	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
mbed_official	381:5460fc57b6e4	982	* @{
mbed_official	381:5460fc57b6e4	983	*/
mbed_official	381:5460fc57b6e4	984	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	381:5460fc57b6e4	985	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	986	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	381:5460fc57b6e4	987	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	381:5460fc57b6e4	988	/**
mbed_official	381:5460fc57b6e4	989	* @}
mbed_official	381:5460fc57b6e4	990	*/
mbed_official	381:5460fc57b6e4	991
mbed_official	381:5460fc57b6e4	992	/**
mbed_official	381:5460fc57b6e4	993	* @}
mbed_official	381:5460fc57b6e4	994	*/
mbed_official	381:5460fc57b6e4	995
mbed_official	381:5460fc57b6e4	996	/* Exported macros -----------------------------------------------------------*/
mbed_official	381:5460fc57b6e4	997	/** @defgroup TIM_Exported_Macros TIM Exported Macros
mbed_official	381:5460fc57b6e4	998	* @{
mbed_official	381:5460fc57b6e4	999	*/
mbed_official	381:5460fc57b6e4	1000
mbed_official	381:5460fc57b6e4	1001	/** @brief Reset TIM handle state
mbed_official	381:5460fc57b6e4	1002	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1003	* @retval None
mbed_official	381:5460fc57b6e4	1004	*/
mbed_official	381:5460fc57b6e4	1005	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	381:5460fc57b6e4	1006
mbed_official	381:5460fc57b6e4	1007	/**
mbed_official	381:5460fc57b6e4	1008	* @brief Enable the TIM peripheral.
mbed_official	381:5460fc57b6e4	1009	* @param __HANDLE__: TIM handle
mbed_official	381:5460fc57b6e4	1010	* @retval None
mbed_official	381:5460fc57b6e4	1011	*/
mbed_official	381:5460fc57b6e4	1012	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	381:5460fc57b6e4	1013
mbed_official	381:5460fc57b6e4	1014	/**
mbed_official	381:5460fc57b6e4	1015	* @brief Enable the TIM main Output.
mbed_official	381:5460fc57b6e4	1016	* @param __HANDLE__: TIM handle
mbed_official	381:5460fc57b6e4	1017	* @retval None
mbed_official	381:5460fc57b6e4	1018	*/
mbed_official	381:5460fc57b6e4	1019	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	381:5460fc57b6e4	1020
mbed_official	381:5460fc57b6e4	1021	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	381:5460fc57b6e4	1022	channels have been disabled */
mbed_official	381:5460fc57b6e4	1023	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	381:5460fc57b6e4	1024	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	381:5460fc57b6e4	1025
mbed_official	381:5460fc57b6e4	1026	/**
mbed_official	381:5460fc57b6e4	1027	* @brief Disable the TIM peripheral.
mbed_official	381:5460fc57b6e4	1028	* @param __HANDLE__: TIM handle
mbed_official	381:5460fc57b6e4	1029	* @retval None
mbed_official	381:5460fc57b6e4	1030	*/
mbed_official	381:5460fc57b6e4	1031	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1032	do { \
mbed_official	381:5460fc57b6e4	1033	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	381:5460fc57b6e4	1034	{ \
mbed_official	381:5460fc57b6e4	1035	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	381:5460fc57b6e4	1036	{ \
mbed_official	381:5460fc57b6e4	1037	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	381:5460fc57b6e4	1038	} \
mbed_official	381:5460fc57b6e4	1039	} \
mbed_official	381:5460fc57b6e4	1040	} while(0)
mbed_official	381:5460fc57b6e4	1041	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
mbed_official	381:5460fc57b6e4	1042	channels have been disabled */
mbed_official	381:5460fc57b6e4	1043	/**
mbed_official	381:5460fc57b6e4	1044	* @brief Disable the TIM main Output.
mbed_official	381:5460fc57b6e4	1045	* @param __HANDLE__: TIM handle
mbed_official	381:5460fc57b6e4	1046	* @retval None
mbed_official	381:5460fc57b6e4	1047	*/
mbed_official	381:5460fc57b6e4	1048	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1049	do { \
mbed_official	381:5460fc57b6e4	1050	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	381:5460fc57b6e4	1051	{ \
mbed_official	381:5460fc57b6e4	1052	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	381:5460fc57b6e4	1053	{ \
mbed_official	381:5460fc57b6e4	1054	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	381:5460fc57b6e4	1055	} \
mbed_official	381:5460fc57b6e4	1056	} \
mbed_official	381:5460fc57b6e4	1057	} while(0)
mbed_official	381:5460fc57b6e4	1058
mbed_official	381:5460fc57b6e4	1059	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	381:5460fc57b6e4	1060	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	381:5460fc57b6e4	1061	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	381:5460fc57b6e4	1062	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	381:5460fc57b6e4	1063	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	381:5460fc57b6e4	1064	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	381:5460fc57b6e4	1065
mbed_official	381:5460fc57b6e4	1066	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	381:5460fc57b6e4	1067	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	381:5460fc57b6e4	1068
mbed_official	381:5460fc57b6e4	1069	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	381:5460fc57b6e4	1070	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	381:5460fc57b6e4	1071
mbed_official	381:5460fc57b6e4	1072	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	381:5460fc57b6e4	1073	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	381:5460fc57b6e4	1074	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	381:5460fc57b6e4	1075	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	381:5460fc57b6e4	1076	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	381:5460fc57b6e4	1077
mbed_official	381:5460fc57b6e4	1078	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
mbed_official	381:5460fc57b6e4	1079	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	381:5460fc57b6e4	1080	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	381:5460fc57b6e4	1081	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	381:5460fc57b6e4	1082	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	381:5460fc57b6e4	1083
mbed_official	381:5460fc57b6e4	1084	/**
mbed_official	381:5460fc57b6e4	1085	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	381:5460fc57b6e4	1086	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1087	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	381:5460fc57b6e4	1088	* @retval None
mbed_official	381:5460fc57b6e4	1089	*/
mbed_official	381:5460fc57b6e4	1090	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	381:5460fc57b6e4	1091
mbed_official	381:5460fc57b6e4	1092	/**
mbed_official	381:5460fc57b6e4	1093	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	381:5460fc57b6e4	1094	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1095	* @retval None
mbed_official	381:5460fc57b6e4	1096	*/
mbed_official	381:5460fc57b6e4	1097	#define __HAL_TIM_GetCounter(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1098	((__HANDLE__)->Instance->CNT)
mbed_official	381:5460fc57b6e4	1099
mbed_official	381:5460fc57b6e4	1100	/**
mbed_official	381:5460fc57b6e4	1101	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	381:5460fc57b6e4	1102	* another time any Init function.
mbed_official	381:5460fc57b6e4	1103	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1104	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	381:5460fc57b6e4	1105	* @retval None
mbed_official	381:5460fc57b6e4	1106	*/
mbed_official	381:5460fc57b6e4	1107	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
mbed_official	381:5460fc57b6e4	1108	do{ \
mbed_official	381:5460fc57b6e4	1109	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	381:5460fc57b6e4	1110	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	381:5460fc57b6e4	1111	} while(0)
mbed_official	381:5460fc57b6e4	1112
mbed_official	381:5460fc57b6e4	1113	/**
mbed_official	381:5460fc57b6e4	1114	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	381:5460fc57b6e4	1115	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1116	* @retval None
mbed_official	381:5460fc57b6e4	1117	*/
mbed_official	381:5460fc57b6e4	1118	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1119	((__HANDLE__)->Instance->ARR)
mbed_official	381:5460fc57b6e4	1120
mbed_official	381:5460fc57b6e4	1121	/**
mbed_official	381:5460fc57b6e4	1122	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	381:5460fc57b6e4	1123	* another time any Init function.
mbed_official	381:5460fc57b6e4	1124	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1125	* @param __CKD__: specifies the clock division value.
mbed_official	381:5460fc57b6e4	1126	* This parameter can be one of the following value:
mbed_official	381:5460fc57b6e4	1127	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	381:5460fc57b6e4	1128	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	381:5460fc57b6e4	1129	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	381:5460fc57b6e4	1130	* @retval None
mbed_official	381:5460fc57b6e4	1131	*/
mbed_official	381:5460fc57b6e4	1132	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
mbed_official	381:5460fc57b6e4	1133	do{ \
mbed_official	381:5460fc57b6e4	1134	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	381:5460fc57b6e4	1135	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	381:5460fc57b6e4	1136	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	381:5460fc57b6e4	1137	} while(0)
mbed_official	381:5460fc57b6e4	1138
mbed_official	381:5460fc57b6e4	1139	/**
mbed_official	381:5460fc57b6e4	1140	* @brief Gets the TIM Clock Division value on runtime
mbed_official	381:5460fc57b6e4	1141	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1142	* @retval None
mbed_official	381:5460fc57b6e4	1143	*/
mbed_official	381:5460fc57b6e4	1144	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1145	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	381:5460fc57b6e4	1146
mbed_official	381:5460fc57b6e4	1147	/**
mbed_official	381:5460fc57b6e4	1148	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	381:5460fc57b6e4	1149	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	381:5460fc57b6e4	1150	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1151	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	381:5460fc57b6e4	1152	* This parameter can be one of the following values:
mbed_official	381:5460fc57b6e4	1153	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	381:5460fc57b6e4	1154	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	381:5460fc57b6e4	1155	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	381:5460fc57b6e4	1156	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	381:5460fc57b6e4	1157	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	381:5460fc57b6e4	1158	* This parameter can be one of the following values:
mbed_official	381:5460fc57b6e4	1159	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	381:5460fc57b6e4	1160	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	381:5460fc57b6e4	1161	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	381:5460fc57b6e4	1162	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	381:5460fc57b6e4	1163	* @retval None
mbed_official	381:5460fc57b6e4	1164	*/
mbed_official	381:5460fc57b6e4	1165	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	381:5460fc57b6e4	1166	do{ \
mbed_official	381:5460fc57b6e4	1167	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
mbed_official	381:5460fc57b6e4	1168	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	381:5460fc57b6e4	1169	} while(0)
mbed_official	381:5460fc57b6e4	1170
mbed_official	381:5460fc57b6e4	1171	/**
mbed_official	381:5460fc57b6e4	1172	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	381:5460fc57b6e4	1173	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1174	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	381:5460fc57b6e4	1175	* This parameter can be one of the following values:
mbed_official	381:5460fc57b6e4	1176	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	381:5460fc57b6e4	1177	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	381:5460fc57b6e4	1178	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	381:5460fc57b6e4	1179	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	381:5460fc57b6e4	1180	* @retval None
mbed_official	381:5460fc57b6e4	1181	*/
mbed_official	381:5460fc57b6e4	1182	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
mbed_official	381:5460fc57b6e4	1183	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	381:5460fc57b6e4	1184	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	381:5460fc57b6e4	1185	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	381:5460fc57b6e4	1186	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	381:5460fc57b6e4	1187
mbed_official	381:5460fc57b6e4	1188	/**
mbed_official	381:5460fc57b6e4	1189	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	381:5460fc57b6e4	1190	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1191	* @note When the USR bit of the TIMx_CR1 register is set, only counter
mbed_official	381:5460fc57b6e4	1192	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	381:5460fc57b6e4	1193	* enabled)
mbed_official	381:5460fc57b6e4	1194	* @retval None
mbed_official	381:5460fc57b6e4	1195	*/
mbed_official	381:5460fc57b6e4	1196	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1197	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	381:5460fc57b6e4	1198
mbed_official	381:5460fc57b6e4	1199	/**
mbed_official	381:5460fc57b6e4	1200	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	381:5460fc57b6e4	1201	* @param __HANDLE__: TIM handle.
mbed_official	381:5460fc57b6e4	1202	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
mbed_official	381:5460fc57b6e4	1203	* following events generate an update interrupt or DMA request (if
mbed_official	381:5460fc57b6e4	1204	* enabled):
mbed_official	381:5460fc57b6e4	1205	* Counter overflow/underflow
mbed_official	381:5460fc57b6e4	1206	* Setting the UG bit
mbed_official	381:5460fc57b6e4	1207	* Update generation through the slave mode controller
mbed_official	381:5460fc57b6e4	1208	* @retval None
mbed_official	381:5460fc57b6e4	1209	*/
mbed_official	381:5460fc57b6e4	1210	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	381:5460fc57b6e4	1211	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	381:5460fc57b6e4	1212
mbed_official	381:5460fc57b6e4	1213	/**
mbed_official	381:5460fc57b6e4	1214	* @}
mbed_official	381:5460fc57b6e4	1215	*/
mbed_official	381:5460fc57b6e4	1216
mbed_official	381:5460fc57b6e4	1217	/* Include TIM HAL Extended module */
mbed_official	381:5460fc57b6e4	1218	#include "stm32f3xx_hal_tim_ex.h"
mbed_official	381:5460fc57b6e4	1219
mbed_official	381:5460fc57b6e4	1220	/* Exported functions --------------------------------------------------------*/
mbed_official	381:5460fc57b6e4	1221	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
mbed_official	381:5460fc57b6e4	1222	* @{
mbed_official	381:5460fc57b6e4	1223	*/
mbed_official	381:5460fc57b6e4	1224
mbed_official	381:5460fc57b6e4	1225	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
mbed_official	381:5460fc57b6e4	1226	* @brief Time Base functions
mbed_official	381:5460fc57b6e4	1227	* @{
mbed_official	381:5460fc57b6e4	1228	*/
mbed_official	381:5460fc57b6e4	1229	/* Time Base functions ********************************************************/
mbed_official	381:5460fc57b6e4	1230	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1231	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1232	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1233	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1234	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1235	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1236	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1237	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1238	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1239	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1240	/* Non-Blocking mode: DMA */
mbed_official	381:5460fc57b6e4	1241	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	381:5460fc57b6e4	1242	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1243	/**
mbed_official	381:5460fc57b6e4	1244	* @}
mbed_official	381:5460fc57b6e4	1245	*/
mbed_official	381:5460fc57b6e4	1246
mbed_official	381:5460fc57b6e4	1247	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
mbed_official	381:5460fc57b6e4	1248	* @brief Time Output Compare functions
mbed_official	381:5460fc57b6e4	1249	* @{
mbed_official	381:5460fc57b6e4	1250	*/
mbed_official	381:5460fc57b6e4	1251	/* Timer Output Compare functions **********************************************/
mbed_official	381:5460fc57b6e4	1252	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1253	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1254	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1255	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1256	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1257	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1258	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1259	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1260	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1261	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1262	/* Non-Blocking mode: DMA */
mbed_official	381:5460fc57b6e4	1263	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	381:5460fc57b6e4	1264	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1265	/**
mbed_official	381:5460fc57b6e4	1266	* @}
mbed_official	381:5460fc57b6e4	1267	*/
mbed_official	381:5460fc57b6e4	1268
mbed_official	381:5460fc57b6e4	1269	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
mbed_official	381:5460fc57b6e4	1270	* @brief Time PWM functions
mbed_official	381:5460fc57b6e4	1271	* @{
mbed_official	381:5460fc57b6e4	1272	*/
mbed_official	381:5460fc57b6e4	1273	/* Timer PWM functions *********************************************************/
mbed_official	381:5460fc57b6e4	1274	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1275	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1276	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1277	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1278	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1279	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1280	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1281	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1282	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1283	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1284	/* Non-Blocking mode: DMA */
mbed_official	381:5460fc57b6e4	1285	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	381:5460fc57b6e4	1286	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1287	/**
mbed_official	381:5460fc57b6e4	1288	* @}
mbed_official	381:5460fc57b6e4	1289	*/
mbed_official	381:5460fc57b6e4	1290
mbed_official	381:5460fc57b6e4	1291	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
mbed_official	381:5460fc57b6e4	1292	* @brief Time Input Capture functions
mbed_official	381:5460fc57b6e4	1293	* @{
mbed_official	381:5460fc57b6e4	1294	*/
mbed_official	381:5460fc57b6e4	1295	/* Timer Input Capture functions ***********************************************/
mbed_official	381:5460fc57b6e4	1296	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1297	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1298	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1299	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1300	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1301	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1302	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1303	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1304	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1305	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1306	/* Non-Blocking mode: DMA */
mbed_official	381:5460fc57b6e4	1307	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	381:5460fc57b6e4	1308	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1309	/**
mbed_official	381:5460fc57b6e4	1310	* @}
mbed_official	381:5460fc57b6e4	1311	*/
mbed_official	381:5460fc57b6e4	1312
mbed_official	381:5460fc57b6e4	1313	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
mbed_official	381:5460fc57b6e4	1314	* @brief Time One Pulse functions
mbed_official	381:5460fc57b6e4	1315	* @{
mbed_official	381:5460fc57b6e4	1316	*/
mbed_official	381:5460fc57b6e4	1317	/* Timer One Pulse functions ***************************************************/
mbed_official	381:5460fc57b6e4	1318	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	381:5460fc57b6e4	1319	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1320	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1321	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1322	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1323	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	381:5460fc57b6e4	1324	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	381:5460fc57b6e4	1325	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1326	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	381:5460fc57b6e4	1327	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	381:5460fc57b6e4	1328	/**
mbed_official	381:5460fc57b6e4	1329	* @}
mbed_official	381:5460fc57b6e4	1330	*/
mbed_official	381:5460fc57b6e4	1331
mbed_official	381:5460fc57b6e4	1332	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
mbed_official	381:5460fc57b6e4	1333	* @brief Time Encoder functions
mbed_official	381:5460fc57b6e4	1334	* @{
mbed_official	381:5460fc57b6e4	1335	*/
mbed_official	381:5460fc57b6e4	1336	/* Timer Encoder functions *****************************************************/
mbed_official	381:5460fc57b6e4	1337	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	381:5460fc57b6e4	1338	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1339	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1340	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1341	/* Blocking mode: Polling */
mbed_official	381:5460fc57b6e4	1342	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1343	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1344	/* Non-Blocking mode: Interrupt */
mbed_official	381:5460fc57b6e4	1345	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1346	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1347	/* Non-Blocking mode: DMA */
mbed_official	381:5460fc57b6e4	1348	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	381:5460fc57b6e4	1349	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1350	/**
mbed_official	381:5460fc57b6e4	1351	* @}
mbed_official	381:5460fc57b6e4	1352	*/
mbed_official	381:5460fc57b6e4	1353
mbed_official	381:5460fc57b6e4	1354	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
mbed_official	381:5460fc57b6e4	1355	* @brief IRQ handler management
mbed_official	381:5460fc57b6e4	1356	* @{
mbed_official	381:5460fc57b6e4	1357	*/
mbed_official	381:5460fc57b6e4	1358	/* Interrupt Handler functions **********************************************/
mbed_official	381:5460fc57b6e4	1359	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1360	/**
mbed_official	381:5460fc57b6e4	1361	* @}
mbed_official	381:5460fc57b6e4	1362	*/
mbed_official	381:5460fc57b6e4	1363
mbed_official	381:5460fc57b6e4	1364	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official	381:5460fc57b6e4	1365	* @brief Peripheral Control functions
mbed_official	381:5460fc57b6e4	1366	* @{
mbed_official	381:5460fc57b6e4	1367	*/
mbed_official	381:5460fc57b6e4	1368	/* Control functions *********************************************************/
mbed_official	381:5460fc57b6e4	1369	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1370	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1371	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1372	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	381:5460fc57b6e4	1373	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1374	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	381:5460fc57b6e4	1375	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	381:5460fc57b6e4	1376	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	381:5460fc57b6e4	1377	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	381:5460fc57b6e4	1378	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	381:5460fc57b6e4	1379	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	381:5460fc57b6e4	1380	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	381:5460fc57b6e4	1381	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	381:5460fc57b6e4	1382	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	381:5460fc57b6e4	1383	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	381:5460fc57b6e4	1384	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	381:5460fc57b6e4	1385	/**
mbed_official	381:5460fc57b6e4	1386	* @}
mbed_official	381:5460fc57b6e4	1387	*/
mbed_official	381:5460fc57b6e4	1388
mbed_official	381:5460fc57b6e4	1389	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
mbed_official	381:5460fc57b6e4	1390	* @brief TIM Callbacks functions
mbed_official	381:5460fc57b6e4	1391	* @{
mbed_official	381:5460fc57b6e4	1392	*/
mbed_official	381:5460fc57b6e4	1393	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	381:5460fc57b6e4	1394	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1395	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1396	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1397	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1398	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1399	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1400	/**
mbed_official	381:5460fc57b6e4	1401	* @}
mbed_official	381:5460fc57b6e4	1402	*/
mbed_official	381:5460fc57b6e4	1403
mbed_official	381:5460fc57b6e4	1404	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
mbed_official	381:5460fc57b6e4	1405	* @brief Peripheral State functions
mbed_official	381:5460fc57b6e4	1406	* @{
mbed_official	381:5460fc57b6e4	1407	*/
mbed_official	381:5460fc57b6e4	1408	/* Peripheral State functions **************************************************/
mbed_official	381:5460fc57b6e4	1409	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1410	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1411	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1412	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1413	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1414	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	381:5460fc57b6e4	1415	/**
mbed_official	381:5460fc57b6e4	1416	* @}
mbed_official	381:5460fc57b6e4	1417	*/
mbed_official	381:5460fc57b6e4	1418
mbed_official	381:5460fc57b6e4	1419	/**
mbed_official	381:5460fc57b6e4	1420	* @}
mbed_official	381:5460fc57b6e4	1421	*/
mbed_official	381:5460fc57b6e4	1422
mbed_official	381:5460fc57b6e4	1423	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	381:5460fc57b6e4	1424	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	381:5460fc57b6e4	1425	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	381:5460fc57b6e4	1426	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	381:5460fc57b6e4	1427	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	381:5460fc57b6e4	1428	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	381:5460fc57b6e4	1429	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	381:5460fc57b6e4	1430	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official	381:5460fc57b6e4	1431
mbed_official	381:5460fc57b6e4	1432	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	381:5460fc57b6e4	1433	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	381:5460fc57b6e4	1434	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	381:5460fc57b6e4	1435	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	381:5460fc57b6e4	1436
mbed_official	381:5460fc57b6e4	1437	/**
mbed_official	381:5460fc57b6e4	1438	* @}
mbed_official	381:5460fc57b6e4	1439	*/
mbed_official	381:5460fc57b6e4	1440
mbed_official	381:5460fc57b6e4	1441	/**
mbed_official	381:5460fc57b6e4	1442	* @}
mbed_official	381:5460fc57b6e4	1443	*/
mbed_official	381:5460fc57b6e4	1444
mbed_official	381:5460fc57b6e4	1445	#ifdef __cplusplus
mbed_official	381:5460fc57b6e4	1446	}
mbed_official	381:5460fc57b6e4	1447	#endif
mbed_official	381:5460fc57b6e4	1448
mbed_official	381:5460fc57b6e4	1449	#endif /* __STM32F3xx_HAL_TIM_H */
mbed_official	381:5460fc57b6e4	1450
mbed_official	381:5460fc57b6e4	1451	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	15 Nov 2014
Imports:	9
Forks:	0
Commits:	401
Dependents:	0
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Followers:	3

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Stuart Northfield

Tony Engeham

targets/cmsis/TARGET_STM/TARGET_DISCO_F334C8/stm32f3xx_hal_tim.h@381:5460fc57b6e4, 2014-11-03 (annotated)

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