Stuart Northfield / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include <stddef.h>
mbed_official 390:35c2c1cf29cd 17 #include "us_ticker_api.h"
mbed_official 390:35c2c1cf29cd 18 #include "PeripheralNames.h"
mbed_official 390:35c2c1cf29cd 19 #include "mtu2_iodefine.h"
mbed_official 390:35c2c1cf29cd 20
mbed_official 390:35c2c1cf29cd 21 #define US_TICKER_TIMER (OSTM0.OSTMnCMP)
mbed_official 390:35c2c1cf29cd 22 #define US_TICKER_TIMER_IRQn TIMER3_IRQn
mbed_official 390:35c2c1cf29cd 23
mbed_official 390:35c2c1cf29cd 24 int us_ticker_inited = 0;
mbed_official 390:35c2c1cf29cd 25
mbed_official 390:35c2c1cf29cd 26 void us_ticker_interrupt(void) {
mbed_official 390:35c2c1cf29cd 27 us_ticker_irq_handler();
mbed_official 390:35c2c1cf29cd 28 GIC_EndInterrupt(TGI2A_IRQn);
mbed_official 390:35c2c1cf29cd 29 }
mbed_official 390:35c2c1cf29cd 30
mbed_official 390:35c2c1cf29cd 31 void us_ticker_init(void) {
mbed_official 390:35c2c1cf29cd 32 if (us_ticker_inited) return;
mbed_official 390:35c2c1cf29cd 33 us_ticker_inited = 1;
mbed_official 390:35c2c1cf29cd 34
mbed_official 390:35c2c1cf29cd 35 /* Power Control for Peripherals */
mbed_official 390:35c2c1cf29cd 36 CPGSTBCR3 &= ~ 0x8; // turn on MTU2
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38 // timer settings
mbed_official 390:35c2c1cf29cd 39 MTU2.TSYR = 0x6; // cascading T_1-T_2
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41 MTU2.TCR_2 = 0x03; // divider 1/64
mbed_official 390:35c2c1cf29cd 42 MTU2.TCR_1 = 0x07; // count-up from T_2 pulse(cascade)
mbed_official 390:35c2c1cf29cd 43
mbed_official 390:35c2c1cf29cd 44 MTU2.TCNT_1 = 0x00; // counter value set to 0
mbed_official 390:35c2c1cf29cd 45 MTU2.TCNT_2 = 0x00; //
mbed_official 390:35c2c1cf29cd 46
mbed_official 390:35c2c1cf29cd 47 MTU2.TSTR |= 0x06; //
mbed_official 390:35c2c1cf29cd 48 MTU2.TSR_2 = 0xc0; // timer start
mbed_official 390:35c2c1cf29cd 49
mbed_official 390:35c2c1cf29cd 50 // INTC settings
mbed_official 390:35c2c1cf29cd 51 InterruptHandlerRegister(TGI2A_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
mbed_official 390:35c2c1cf29cd 52 GIC_SetPriority(TGI2A_IRQn, 5);
mbed_official 390:35c2c1cf29cd 53 GIC_EnableIRQ(TGI2A_IRQn);
mbed_official 390:35c2c1cf29cd 54 __enable_irq();
mbed_official 390:35c2c1cf29cd 55 }
mbed_official 390:35c2c1cf29cd 56
mbed_official 390:35c2c1cf29cd 57 //static const float PCLK =33.33, // dummy
mbed_official 390:35c2c1cf29cd 58 //PRESCALE =64.0; // dummy
mbed_official 390:35c2c1cf29cd 59 static const float FACTOR_C2U = 1.9201920192019204, //(PRESCALE/PCLK)
mbed_official 390:35c2c1cf29cd 60 FACTOR_U2C = 0.52078125; //(PCLK/PRESCALE)
mbed_official 390:35c2c1cf29cd 61
mbed_official 390:35c2c1cf29cd 62 #define F_CLK2us(val) ((uint32_t)((val)*FACTOR_C2U))
mbed_official 390:35c2c1cf29cd 63 #define F_us2CLK(val) ((uint32_t)((val)*FACTOR_U2C))
mbed_official 390:35c2c1cf29cd 64
mbed_official 390:35c2c1cf29cd 65
mbed_official 390:35c2c1cf29cd 66 uint32_t us_ticker_read() {
mbed_official 390:35c2c1cf29cd 67 static uint32_t max_val = 0x8551eb85; //*F_us2CLK(0xffffffff)+1;
mbed_official 390:35c2c1cf29cd 68 uint32_t val;
mbed_official 390:35c2c1cf29cd 69 if (!us_ticker_inited)
mbed_official 390:35c2c1cf29cd 70 us_ticker_init();
mbed_official 390:35c2c1cf29cd 71
mbed_official 390:35c2c1cf29cd 72 val = MTU2.TCNT_1<<16 | MTU2.TCNT_2; // concat cascaded Counters
mbed_official 390:35c2c1cf29cd 73 if (val > max_val) { // if overflow (in us-timer)
mbed_official 390:35c2c1cf29cd 74 val -= max_val; // correct value
mbed_official 390:35c2c1cf29cd 75 MTU2.TCNT_1 = 0; // reset counter
mbed_official 390:35c2c1cf29cd 76 MTU2.TCNT_2 = val;
mbed_official 390:35c2c1cf29cd 77 }
mbed_official 390:35c2c1cf29cd 78 val = F_CLK2us(val);
mbed_official 390:35c2c1cf29cd 79 return val;
mbed_official 390:35c2c1cf29cd 80 }
mbed_official 390:35c2c1cf29cd 81
mbed_official 390:35c2c1cf29cd 82 void us_ticker_set_interrupt(timestamp_t timestamp) {
mbed_official 390:35c2c1cf29cd 83 // set match value
mbed_official 390:35c2c1cf29cd 84 timestamp = F_us2CLK(timestamp);
mbed_official 390:35c2c1cf29cd 85 MTU2.TGRA_2 = timestamp & 0xffff;
mbed_official 390:35c2c1cf29cd 86 // enable match interrupt
mbed_official 390:35c2c1cf29cd 87 MTU2.TIER_2 = 0x01;
mbed_official 390:35c2c1cf29cd 88 }
mbed_official 390:35c2c1cf29cd 89
mbed_official 390:35c2c1cf29cd 90 void us_ticker_disable_interrupt(void) {
mbed_official 390:35c2c1cf29cd 91 MTU2.TIER_2 &= ~(0xc0);
mbed_official 390:35c2c1cf29cd 92 }
mbed_official 390:35c2c1cf29cd 93
mbed_official 390:35c2c1cf29cd 94 void us_ticker_clear_interrupt(void) {
mbed_official 390:35c2c1cf29cd 95 MTU2.TSR_2 &= 0xc0;
mbed_official 390:35c2c1cf29cd 96 }