Stuart Northfield / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include <string.h>
mbed_official 390:35c2c1cf29cd 17 #include "ethernet_api.h"
mbed_official 390:35c2c1cf29cd 18 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 19 #include "mbed_interface.h"
mbed_official 390:35c2c1cf29cd 20 #include "toolchain.h"
mbed_official 390:35c2c1cf29cd 21 #include "mbed_error.h"
mbed_official 390:35c2c1cf29cd 22 #include "ether_iodefine.h"
mbed_official 390:35c2c1cf29cd 23 #include "ethernetext_api.h"
mbed_official 390:35c2c1cf29cd 24
mbed_official 390:35c2c1cf29cd 25 /* Descriptor info */
mbed_official 390:35c2c1cf29cd 26 #define NUM_OF_TX_DESCRIPTOR (16)
mbed_official 390:35c2c1cf29cd 27 #define NUM_OF_RX_DESCRIPTOR (16)
mbed_official 390:35c2c1cf29cd 28 #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
mbed_official 390:35c2c1cf29cd 29 #define MAX_SEND_SIZE (1514)
mbed_official 390:35c2c1cf29cd 30 #define BUFF_BOUNDARY_MSK (0x0000000F)
mbed_official 390:35c2c1cf29cd 31 /* Ethernet Descriptor Value Define */
mbed_official 390:35c2c1cf29cd 32 #define TD0_TFP_TOP_BOTTOM (0x30000000)
mbed_official 390:35c2c1cf29cd 33 #define TD0_TACT (0x80000000)
mbed_official 390:35c2c1cf29cd 34 #define TD0_TDLE (0x40000000)
mbed_official 390:35c2c1cf29cd 35 #define RD0_RACT (0x80000000)
mbed_official 390:35c2c1cf29cd 36 #define RD0_RDLE (0x40000000)
mbed_official 390:35c2c1cf29cd 37 #define RD0_RFE (0x08000000)
mbed_official 390:35c2c1cf29cd 38 #define RD0_RCSE (0x04000000)
mbed_official 390:35c2c1cf29cd 39 #define RD0_RFS (0x03FF0000)
mbed_official 390:35c2c1cf29cd 40 #define RD0_RCS (0x0000FFFF)
mbed_official 390:35c2c1cf29cd 41 #define RD0_RFS_RFOF (0x02000000)
mbed_official 390:35c2c1cf29cd 42 #define RD0_RFS_RUAF (0x00400000)
mbed_official 390:35c2c1cf29cd 43 #define RD0_RFS_RRF (0x00100000)
mbed_official 390:35c2c1cf29cd 44 #define RD0_RFS_RTLF (0x00080000)
mbed_official 390:35c2c1cf29cd 45 #define RD0_RFS_RTSF (0x00040000)
mbed_official 390:35c2c1cf29cd 46 #define RD0_RFS_PRE (0x00020000)
mbed_official 390:35c2c1cf29cd 47 #define RD0_RFS_CERF (0x00010000)
mbed_official 390:35c2c1cf29cd 48 #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
mbed_official 390:35c2c1cf29cd 49 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
mbed_official 390:35c2c1cf29cd 50 #define RD1_RDL_MSK (0x0000FFFF)
mbed_official 390:35c2c1cf29cd 51 /* PHY Register */
mbed_official 390:35c2c1cf29cd 52 #define BASIC_MODE_CONTROL_REG (0)
mbed_official 390:35c2c1cf29cd 53 #define BASIC_MODE_STATUS_REG (1)
mbed_official 390:35c2c1cf29cd 54 #define PHY_IDENTIFIER1_REG (2)
mbed_official 390:35c2c1cf29cd 55 #define PHY_IDENTIFIER2_REG (3)
mbed_official 390:35c2c1cf29cd 56 #define PHY_SP_CTL_STS_REG (31)
mbed_official 390:35c2c1cf29cd 57 /* MII management interface access */
mbed_official 390:35c2c1cf29cd 58 #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
mbed_official 390:35c2c1cf29cd 59 #define PHY_ST (1)
mbed_official 390:35c2c1cf29cd 60 #define PHY_WRITE (1)
mbed_official 390:35c2c1cf29cd 61 #define PHY_READ (2)
mbed_official 390:35c2c1cf29cd 62 #define MDC_WAIT (6) /* 400ns/4 */
mbed_official 390:35c2c1cf29cd 63 #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
mbed_official 390:35c2c1cf29cd 64 #define BASIC_STS_MSK_AUTO_CMP (0x0010) /* Auto-Negotiate Complete */
mbed_official 390:35c2c1cf29cd 65 #define M_PHY_ID (0xFFFFFFF0)
mbed_official 390:35c2c1cf29cd 66 #define PHY_ID_LAN8710A (0x0007C0F0)
mbed_official 390:35c2c1cf29cd 67 /* ETHERPIR0 */
mbed_official 390:35c2c1cf29cd 68 #define PIR0_MDI (0x00000008)
mbed_official 390:35c2c1cf29cd 69 #define PIR0_MDO (0x00000004)
mbed_official 390:35c2c1cf29cd 70 #define PIR0_MMD (0x00000002)
mbed_official 390:35c2c1cf29cd 71 #define PIR0_MDC (0x00000001)
mbed_official 390:35c2c1cf29cd 72 #define PIR0_MDC_HIGH (0x00000001)
mbed_official 390:35c2c1cf29cd 73 #define PIR0_MDC_LOW (0x00000000)
mbed_official 390:35c2c1cf29cd 74 /* ETHEREDRRR0 */
mbed_official 390:35c2c1cf29cd 75 #define EDRRR0_RR (0x00000001)
mbed_official 390:35c2c1cf29cd 76 /* ETHEREDTRR0 */
mbed_official 390:35c2c1cf29cd 77 #define EDTRR0_TR (0x00000003)
mbed_official 390:35c2c1cf29cd 78 /* software wait */
mbed_official 390:35c2c1cf29cd 79 #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
mbed_official 390:35c2c1cf29cd 80
mbed_official 390:35c2c1cf29cd 81 #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
mbed_official 390:35c2c1cf29cd 82 /* 0x00040000 : Detect frame reception */
mbed_official 390:35c2c1cf29cd 83 /* 0x00010000 : Receive FIFO overflow */
mbed_official 390:35c2c1cf29cd 84 /* 0x00000010 : Residual bit frame reception */
mbed_official 390:35c2c1cf29cd 85 /* 0x00000008 : Long frame reception */
mbed_official 390:35c2c1cf29cd 86 /* 0x00000004 : Short frame reception */
mbed_official 390:35c2c1cf29cd 87 /* 0x00000002 : PHY-LSI reception error */
mbed_official 390:35c2c1cf29cd 88 /* 0x00000001 : Receive frame CRC error */
mbed_official 390:35c2c1cf29cd 89 #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
mbed_official 390:35c2c1cf29cd 90
mbed_official 390:35c2c1cf29cd 91 /* Send descriptor */
mbed_official 390:35c2c1cf29cd 92 typedef struct tag_edmac_send_desc {
mbed_official 390:35c2c1cf29cd 93 uint32_t td0;
mbed_official 390:35c2c1cf29cd 94 uint32_t td1;
mbed_official 390:35c2c1cf29cd 95 uint8_t *td2;
mbed_official 390:35c2c1cf29cd 96 uint32_t padding4;
mbed_official 390:35c2c1cf29cd 97 } edmac_send_desc_t;
mbed_official 390:35c2c1cf29cd 98
mbed_official 390:35c2c1cf29cd 99 /* Receive descriptor */
mbed_official 390:35c2c1cf29cd 100 typedef struct tag_edmac_recv_desc {
mbed_official 390:35c2c1cf29cd 101 uint32_t rd0;
mbed_official 390:35c2c1cf29cd 102 uint32_t rd1;
mbed_official 390:35c2c1cf29cd 103 uint8_t *rd2;
mbed_official 390:35c2c1cf29cd 104 uint32_t padding4;
mbed_official 390:35c2c1cf29cd 105 } edmac_recv_desc_t;
mbed_official 390:35c2c1cf29cd 106
mbed_official 390:35c2c1cf29cd 107 /* memory */
mbed_official 390:35c2c1cf29cd 108 #pragma arm section zidata="NC_BSS"
mbed_official 390:35c2c1cf29cd 109 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
mbed_official 390:35c2c1cf29cd 110 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
mbed_official 390:35c2c1cf29cd 111 static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
mbed_official 390:35c2c1cf29cd 112 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
mbed_official 390:35c2c1cf29cd 113 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
mbed_official 390:35c2c1cf29cd 114 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER) + BUFF_BOUNDARY_MSK];
mbed_official 390:35c2c1cf29cd 115 #pragma arm section zidata
mbed_official 390:35c2c1cf29cd 116 static int32_t rx_read_offset; /* read offset */
mbed_official 390:35c2c1cf29cd 117 static int32_t tx_wite_offset; /* write offset */
mbed_official 390:35c2c1cf29cd 118 static uint32_t send_top_index;
mbed_official 390:35c2c1cf29cd 119 static uint32_t recv_top_index;
mbed_official 390:35c2c1cf29cd 120 static int32_t Interrupt_priority;
mbed_official 390:35c2c1cf29cd 121 static edmac_send_desc_t *p_eth_desc_dsend = NULL;
mbed_official 390:35c2c1cf29cd 122 static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
mbed_official 390:35c2c1cf29cd 123 static edmac_recv_desc_t *p_recv_end_desc = NULL;
mbed_official 390:35c2c1cf29cd 124 static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
mbed_official 390:35c2c1cf29cd 125 static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
mbed_official 390:35c2c1cf29cd 126 static uint32_t phy_id = 0;
mbed_official 390:35c2c1cf29cd 127 static uint32_t start_stop = 1; /* 0:stop 1:start */
mbed_official 390:35c2c1cf29cd 128
mbed_official 390:35c2c1cf29cd 129 /* function */
mbed_official 390:35c2c1cf29cd 130 static void lan_reg_reset(void);
mbed_official 390:35c2c1cf29cd 131 static void lan_desc_create(void);
mbed_official 390:35c2c1cf29cd 132 static void lan_reg_set(int32_t link);
mbed_official 390:35c2c1cf29cd 133 static uint16_t phy_reg_read(uint16_t reg_addr);
mbed_official 390:35c2c1cf29cd 134 static void phy_reg_write(uint16_t reg_addr, uint16_t data);
mbed_official 390:35c2c1cf29cd 135 static void mii_preamble(void);
mbed_official 390:35c2c1cf29cd 136 static void mii_cmd(uint16_t reg_addr, uint32_t option);
mbed_official 390:35c2c1cf29cd 137 static void mii_reg_read(uint16_t *data);
mbed_official 390:35c2c1cf29cd 138 static void mii_reg_write(uint16_t data);
mbed_official 390:35c2c1cf29cd 139 static void mii_z(void);
mbed_official 390:35c2c1cf29cd 140 static void mii_write_1(void);
mbed_official 390:35c2c1cf29cd 141 static void mii_write_0(void);
mbed_official 390:35c2c1cf29cd 142 static void set_ether_pir(uint32_t set_data);
mbed_official 390:35c2c1cf29cd 143 static void wait_100us(int32_t wait_cnt);
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145
mbed_official 390:35c2c1cf29cd 146 int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
mbed_official 390:35c2c1cf29cd 147 int32_t i;
mbed_official 390:35c2c1cf29cd 148 uint16_t val;
mbed_official 390:35c2c1cf29cd 149
mbed_official 390:35c2c1cf29cd 150 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
mbed_official 390:35c2c1cf29cd 151
mbed_official 390:35c2c1cf29cd 152 /* P4_2(PHY Reset) */
mbed_official 390:35c2c1cf29cd 153 GPIOP4 &= ~0x0004; /* Outputs low level */
mbed_official 390:35c2c1cf29cd 154 GPIOPMC4 &= ~0x0004; /* Port mode */
mbed_official 390:35c2c1cf29cd 155 GPIOPM4 &= ~0x0004; /* Output mode */
mbed_official 390:35c2c1cf29cd 156
mbed_official 390:35c2c1cf29cd 157 /* GPIO P1 P1_14(ET_COL) */
mbed_official 390:35c2c1cf29cd 158 GPIOPMC1 |= 0x4000;
mbed_official 390:35c2c1cf29cd 159 GPIOPFCAE1 &= ~0x4000;
mbed_official 390:35c2c1cf29cd 160 GPIOPFCE1 |= 0x4000;
mbed_official 390:35c2c1cf29cd 161 GPIOPFC1 |= 0x4000;
mbed_official 390:35c2c1cf29cd 162
mbed_official 390:35c2c1cf29cd 163 /* P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
mbed_official 390:35c2c1cf29cd 164 GPIOPMC3 |= 0x0078;
mbed_official 390:35c2c1cf29cd 165 GPIOPFCAE3 &= ~0x0078;
mbed_official 390:35c2c1cf29cd 166 GPIOPFCE3 &= ~0x0078;
mbed_official 390:35c2c1cf29cd 167 GPIOPFC3 |= 0x0078;
mbed_official 390:35c2c1cf29cd 168 GPIOPIPC3 |= 0x0078;
mbed_official 390:35c2c1cf29cd 169
mbed_official 390:35c2c1cf29cd 170 /* P5_9(ET_MDC) */
mbed_official 390:35c2c1cf29cd 171 GPIOPMC5 |= 0x0200;
mbed_official 390:35c2c1cf29cd 172 GPIOPFCAE5 &= ~0x0200;
mbed_official 390:35c2c1cf29cd 173 GPIOPFCE5 &= ~0x0200;
mbed_official 390:35c2c1cf29cd 174 GPIOPFC5 |= 0x0200;
mbed_official 390:35c2c1cf29cd 175 GPIOPIPC5 |= 0x0200;
mbed_official 390:35c2c1cf29cd 176
mbed_official 390:35c2c1cf29cd 177 /* P10_0(ET_TXCLK), P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
mbed_official 390:35c2c1cf29cd 178 /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
mbed_official 390:35c2c1cf29cd 179 GPIOPMC10 |= 0x0FFF;
mbed_official 390:35c2c1cf29cd 180 GPIOPFCAE10 &= ~0x0FFF;
mbed_official 390:35c2c1cf29cd 181 GPIOPFCE10 |= 0x0FFF;
mbed_official 390:35c2c1cf29cd 182 GPIOPFC10 |= 0x0FFF;
mbed_official 390:35c2c1cf29cd 183 GPIOPIPC10 |= 0x0FFF;
mbed_official 390:35c2c1cf29cd 184
mbed_official 390:35c2c1cf29cd 185 /* Resets the E-MAC,E-DMAC */
mbed_official 390:35c2c1cf29cd 186 lan_reg_reset();
mbed_official 390:35c2c1cf29cd 187
mbed_official 390:35c2c1cf29cd 188 /* PHY Reset */
mbed_official 390:35c2c1cf29cd 189 GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
mbed_official 390:35c2c1cf29cd 190 wait_100us(250); /* 25msec */
mbed_official 390:35c2c1cf29cd 191 GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
mbed_official 390:35c2c1cf29cd 192 wait_100us(100); /* 10msec */
mbed_official 390:35c2c1cf29cd 193
mbed_official 390:35c2c1cf29cd 194 /* Resets the PHY-LSI */
mbed_official 390:35c2c1cf29cd 195 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
mbed_official 390:35c2c1cf29cd 196 for (i = 10000; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 197 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
mbed_official 390:35c2c1cf29cd 198 if (((uint32_t)val & 0x8000uL) == 0) {
mbed_official 390:35c2c1cf29cd 199 break; /* Reset complete */
mbed_official 390:35c2c1cf29cd 200 }
mbed_official 390:35c2c1cf29cd 201 }
mbed_official 390:35c2c1cf29cd 202
mbed_official 390:35c2c1cf29cd 203 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
mbed_official 390:35c2c1cf29cd 204 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
mbed_official 390:35c2c1cf29cd 205
mbed_official 390:35c2c1cf29cd 206 Interrupt_priority = p_ethcfg->int_priority;
mbed_official 390:35c2c1cf29cd 207 p_recv_cb_fnc = p_ethcfg->recv_cb;
mbed_official 390:35c2c1cf29cd 208 start_stop = 1;
mbed_official 390:35c2c1cf29cd 209
mbed_official 390:35c2c1cf29cd 210 if (p_ethcfg->ether_mac != NULL) {
mbed_official 390:35c2c1cf29cd 211 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
mbed_official 390:35c2c1cf29cd 212 } else {
mbed_official 390:35c2c1cf29cd 213 ethernet_address(mac_addr); /* Get MAC Address */
mbed_official 390:35c2c1cf29cd 214 }
mbed_official 390:35c2c1cf29cd 215
mbed_official 390:35c2c1cf29cd 216 return 0;
mbed_official 390:35c2c1cf29cd 217 }
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 void ethernetext_start_stop(int32_t mode) {
mbed_official 390:35c2c1cf29cd 220 if (mode == 1) {
mbed_official 390:35c2c1cf29cd 221 /* start */
mbed_official 390:35c2c1cf29cd 222 ETHEREDTRR0 |= EDTRR0_TR;
mbed_official 390:35c2c1cf29cd 223 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 390:35c2c1cf29cd 224 start_stop = 1;
mbed_official 390:35c2c1cf29cd 225 } else {
mbed_official 390:35c2c1cf29cd 226 /* stop */
mbed_official 390:35c2c1cf29cd 227 ETHEREDTRR0 &= ~EDTRR0_TR;
mbed_official 390:35c2c1cf29cd 228 ETHEREDRRR0 &= ~EDRRR0_RR;
mbed_official 390:35c2c1cf29cd 229 start_stop = 0;
mbed_official 390:35c2c1cf29cd 230 }
mbed_official 390:35c2c1cf29cd 231 }
mbed_official 390:35c2c1cf29cd 232
mbed_official 390:35c2c1cf29cd 233 int ethernetext_chk_link_mode(void) {
mbed_official 390:35c2c1cf29cd 234 int32_t link;
mbed_official 390:35c2c1cf29cd 235 uint16_t data;
mbed_official 390:35c2c1cf29cd 236
mbed_official 390:35c2c1cf29cd 237 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
mbed_official 390:35c2c1cf29cd 238 data = phy_reg_read(PHY_SP_CTL_STS_REG);
mbed_official 390:35c2c1cf29cd 239 switch (((uint32_t)data >> 2) & 0x00000007) {
mbed_official 390:35c2c1cf29cd 240 case 0x0001:
mbed_official 390:35c2c1cf29cd 241 link = HALF_10M;
mbed_official 390:35c2c1cf29cd 242 break;
mbed_official 390:35c2c1cf29cd 243 case 0x0005:
mbed_official 390:35c2c1cf29cd 244 link = FULL_10M;
mbed_official 390:35c2c1cf29cd 245 break;
mbed_official 390:35c2c1cf29cd 246 case 0x0002:
mbed_official 390:35c2c1cf29cd 247 link = HALF_TX;
mbed_official 390:35c2c1cf29cd 248 break;
mbed_official 390:35c2c1cf29cd 249 case 0x0006:
mbed_official 390:35c2c1cf29cd 250 link = FULL_TX;
mbed_official 390:35c2c1cf29cd 251 break;
mbed_official 390:35c2c1cf29cd 252 default:
mbed_official 390:35c2c1cf29cd 253 link = NEGO_FAIL;
mbed_official 390:35c2c1cf29cd 254 break;
mbed_official 390:35c2c1cf29cd 255 }
mbed_official 390:35c2c1cf29cd 256 } else {
mbed_official 390:35c2c1cf29cd 257 link = NEGO_FAIL;
mbed_official 390:35c2c1cf29cd 258 }
mbed_official 390:35c2c1cf29cd 259
mbed_official 390:35c2c1cf29cd 260 return link;
mbed_official 390:35c2c1cf29cd 261 }
mbed_official 390:35c2c1cf29cd 262
mbed_official 390:35c2c1cf29cd 263 void ethernetext_set_link_mode(int32_t link) {
mbed_official 390:35c2c1cf29cd 264 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
mbed_official 390:35c2c1cf29cd 265 lan_desc_create(); /* Initialize of buffer memory */
mbed_official 390:35c2c1cf29cd 266 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
mbed_official 390:35c2c1cf29cd 267 }
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 int ethernet_init() {
mbed_official 390:35c2c1cf29cd 270 ethernet_cfg_t ethcfg;
mbed_official 390:35c2c1cf29cd 271
mbed_official 390:35c2c1cf29cd 272 ethcfg.int_priority = 0;
mbed_official 390:35c2c1cf29cd 273 ethcfg.recv_cb = NULL;
mbed_official 390:35c2c1cf29cd 274 ethcfg.ether_mac = NULL;
mbed_official 390:35c2c1cf29cd 275 ethernetext_init(&ethcfg);
mbed_official 390:35c2c1cf29cd 276 ethernet_set_link(-1, 0); /* Auto-Negotiation */
mbed_official 390:35c2c1cf29cd 277
mbed_official 390:35c2c1cf29cd 278 return 0;
mbed_official 390:35c2c1cf29cd 279 }
mbed_official 390:35c2c1cf29cd 280
mbed_official 390:35c2c1cf29cd 281 void ethernet_free() {
mbed_official 390:35c2c1cf29cd 282 ETHERARSTR |= 0x00000001; /* ETHER software reset */
mbed_official 390:35c2c1cf29cd 283 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
mbed_official 390:35c2c1cf29cd 284 }
mbed_official 390:35c2c1cf29cd 285
mbed_official 390:35c2c1cf29cd 286 int ethernet_write(const char *data, int slen) {
mbed_official 390:35c2c1cf29cd 287 edmac_send_desc_t *p_send_desc;
mbed_official 390:35c2c1cf29cd 288 int32_t copy_size;
mbed_official 390:35c2c1cf29cd 289
mbed_official 390:35c2c1cf29cd 290 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
mbed_official 390:35c2c1cf29cd 291 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
mbed_official 390:35c2c1cf29cd 292 copy_size = 0;
mbed_official 390:35c2c1cf29cd 293 } else {
mbed_official 390:35c2c1cf29cd 294 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
mbed_official 390:35c2c1cf29cd 295 if ((p_send_desc->td0 & TD0_TACT) != 0) {
mbed_official 390:35c2c1cf29cd 296 copy_size = 0;
mbed_official 390:35c2c1cf29cd 297 } else {
mbed_official 390:35c2c1cf29cd 298 copy_size = MAX_SEND_SIZE - tx_wite_offset;
mbed_official 390:35c2c1cf29cd 299 if (copy_size > slen) {
mbed_official 390:35c2c1cf29cd 300 copy_size = slen;
mbed_official 390:35c2c1cf29cd 301 }
mbed_official 390:35c2c1cf29cd 302 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
mbed_official 390:35c2c1cf29cd 303 tx_wite_offset += copy_size;
mbed_official 390:35c2c1cf29cd 304 }
mbed_official 390:35c2c1cf29cd 305 }
mbed_official 390:35c2c1cf29cd 306
mbed_official 390:35c2c1cf29cd 307 return copy_size;
mbed_official 390:35c2c1cf29cd 308 }
mbed_official 390:35c2c1cf29cd 309
mbed_official 390:35c2c1cf29cd 310 int ethernet_send() {
mbed_official 390:35c2c1cf29cd 311 edmac_send_desc_t *p_send_desc;
mbed_official 390:35c2c1cf29cd 312 int32_t ret;
mbed_official 390:35c2c1cf29cd 313
mbed_official 390:35c2c1cf29cd 314 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
mbed_official 390:35c2c1cf29cd 315 ret = 0;
mbed_official 390:35c2c1cf29cd 316 } else {
mbed_official 390:35c2c1cf29cd 317 /* Transfer 1 frame */
mbed_official 390:35c2c1cf29cd 318 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
mbed_official 390:35c2c1cf29cd 319
mbed_official 390:35c2c1cf29cd 320 /* Sets the frame length */
mbed_official 390:35c2c1cf29cd 321 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
mbed_official 390:35c2c1cf29cd 322 tx_wite_offset = 0;
mbed_official 390:35c2c1cf29cd 323
mbed_official 390:35c2c1cf29cd 324 /* Sets the transmit descriptor to transmit again */
mbed_official 390:35c2c1cf29cd 325 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
mbed_official 390:35c2c1cf29cd 326 p_send_desc->td0 |= TD0_TACT;
mbed_official 390:35c2c1cf29cd 327 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
mbed_official 390:35c2c1cf29cd 328 ETHEREDTRR0 |= EDTRR0_TR;
mbed_official 390:35c2c1cf29cd 329 }
mbed_official 390:35c2c1cf29cd 330
mbed_official 390:35c2c1cf29cd 331 /* Update the current descriptor */
mbed_official 390:35c2c1cf29cd 332 send_top_index++;
mbed_official 390:35c2c1cf29cd 333 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
mbed_official 390:35c2c1cf29cd 334 send_top_index = 0;
mbed_official 390:35c2c1cf29cd 335 }
mbed_official 390:35c2c1cf29cd 336 ret = 1;
mbed_official 390:35c2c1cf29cd 337 }
mbed_official 390:35c2c1cf29cd 338
mbed_official 390:35c2c1cf29cd 339 return ret;
mbed_official 390:35c2c1cf29cd 340 }
mbed_official 390:35c2c1cf29cd 341
mbed_official 390:35c2c1cf29cd 342 int ethernet_receive() {
mbed_official 390:35c2c1cf29cd 343 edmac_recv_desc_t *p_recv_desc;
mbed_official 390:35c2c1cf29cd 344 int32_t receive_size = 0;
mbed_official 390:35c2c1cf29cd 345
mbed_official 390:35c2c1cf29cd 346 if (p_eth_desc_drecv != NULL) {
mbed_official 390:35c2c1cf29cd 347 if (p_recv_end_desc != NULL) {
mbed_official 390:35c2c1cf29cd 348 /* Sets the receive descriptor to receive again */
mbed_official 390:35c2c1cf29cd 349 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
mbed_official 390:35c2c1cf29cd 350 p_recv_end_desc->rd0 |= RD0_RACT;
mbed_official 390:35c2c1cf29cd 351 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
mbed_official 390:35c2c1cf29cd 352 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 390:35c2c1cf29cd 353 }
mbed_official 390:35c2c1cf29cd 354 p_recv_end_desc = NULL;
mbed_official 390:35c2c1cf29cd 355 }
mbed_official 390:35c2c1cf29cd 356
mbed_official 390:35c2c1cf29cd 357 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
mbed_official 390:35c2c1cf29cd 358 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
mbed_official 390:35c2c1cf29cd 359 /* Receives 1 frame */
mbed_official 390:35c2c1cf29cd 360 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
mbed_official 390:35c2c1cf29cd 361 /* Receive frame error */
mbed_official 390:35c2c1cf29cd 362 /* Sets the receive descriptor to receive again */
mbed_official 390:35c2c1cf29cd 363 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
mbed_official 390:35c2c1cf29cd 364 p_recv_desc->rd0 |= RD0_RACT;
mbed_official 390:35c2c1cf29cd 365 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
mbed_official 390:35c2c1cf29cd 366 ETHEREDRRR0 |= EDRRR0_RR;
mbed_official 390:35c2c1cf29cd 367 }
mbed_official 390:35c2c1cf29cd 368 } else {
mbed_official 390:35c2c1cf29cd 369 /* Copies the received frame */
mbed_official 390:35c2c1cf29cd 370 rx_read_offset = 0;
mbed_official 390:35c2c1cf29cd 371 p_recv_end_desc = p_recv_desc;
mbed_official 390:35c2c1cf29cd 372 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
mbed_official 390:35c2c1cf29cd 373 }
mbed_official 390:35c2c1cf29cd 374
mbed_official 390:35c2c1cf29cd 375 /* Update the current descriptor */
mbed_official 390:35c2c1cf29cd 376 recv_top_index++;
mbed_official 390:35c2c1cf29cd 377 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
mbed_official 390:35c2c1cf29cd 378 recv_top_index = 0;
mbed_official 390:35c2c1cf29cd 379 }
mbed_official 390:35c2c1cf29cd 380 }
mbed_official 390:35c2c1cf29cd 381 }
mbed_official 390:35c2c1cf29cd 382
mbed_official 390:35c2c1cf29cd 383 return receive_size;
mbed_official 390:35c2c1cf29cd 384 }
mbed_official 390:35c2c1cf29cd 385
mbed_official 390:35c2c1cf29cd 386 int ethernet_read(char *data, int dlen) {
mbed_official 390:35c2c1cf29cd 387 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
mbed_official 390:35c2c1cf29cd 388 int32_t copy_size;
mbed_official 390:35c2c1cf29cd 389
mbed_official 390:35c2c1cf29cd 390 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
mbed_official 390:35c2c1cf29cd 391 copy_size = 0;
mbed_official 390:35c2c1cf29cd 392 } else {
mbed_official 390:35c2c1cf29cd 393 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
mbed_official 390:35c2c1cf29cd 394 if (copy_size > dlen) {
mbed_official 390:35c2c1cf29cd 395 copy_size = dlen;
mbed_official 390:35c2c1cf29cd 396 }
mbed_official 390:35c2c1cf29cd 397 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
mbed_official 390:35c2c1cf29cd 398 rx_read_offset += copy_size;
mbed_official 390:35c2c1cf29cd 399 }
mbed_official 390:35c2c1cf29cd 400
mbed_official 390:35c2c1cf29cd 401 return copy_size;
mbed_official 390:35c2c1cf29cd 402 }
mbed_official 390:35c2c1cf29cd 403
mbed_official 390:35c2c1cf29cd 404 void ethernet_address(char *mac) {
mbed_official 390:35c2c1cf29cd 405 if (mac != NULL) {
mbed_official 390:35c2c1cf29cd 406 mbed_mac_address(mac); /* Get MAC Address */
mbed_official 390:35c2c1cf29cd 407 }
mbed_official 390:35c2c1cf29cd 408 }
mbed_official 390:35c2c1cf29cd 409
mbed_official 390:35c2c1cf29cd 410 int ethernet_link(void) {
mbed_official 390:35c2c1cf29cd 411 int32_t ret;
mbed_official 390:35c2c1cf29cd 412 uint16_t data;
mbed_official 390:35c2c1cf29cd 413
mbed_official 390:35c2c1cf29cd 414 data = phy_reg_read(BASIC_MODE_STATUS_REG);
mbed_official 390:35c2c1cf29cd 415 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
mbed_official 390:35c2c1cf29cd 416 ret = 1;
mbed_official 390:35c2c1cf29cd 417 } else {
mbed_official 390:35c2c1cf29cd 418 ret = 0;
mbed_official 390:35c2c1cf29cd 419 }
mbed_official 390:35c2c1cf29cd 420
mbed_official 390:35c2c1cf29cd 421 return ret;
mbed_official 390:35c2c1cf29cd 422 }
mbed_official 390:35c2c1cf29cd 423
mbed_official 390:35c2c1cf29cd 424 void ethernet_set_link(int speed, int duplex) {
mbed_official 390:35c2c1cf29cd 425 uint16_t data;
mbed_official 390:35c2c1cf29cd 426 int32_t i;
mbed_official 390:35c2c1cf29cd 427 int32_t link;
mbed_official 390:35c2c1cf29cd 428
mbed_official 390:35c2c1cf29cd 429 if ((speed < 0) || (speed > 1)) {
mbed_official 390:35c2c1cf29cd 430 data = 0x1000; /* Auto-Negotiation Enable */
mbed_official 390:35c2c1cf29cd 431 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
mbed_official 390:35c2c1cf29cd 432 data = phy_reg_read(BASIC_MODE_STATUS_REG);
mbed_official 390:35c2c1cf29cd 433 for (i = 0; i < 1000; i++) {
mbed_official 390:35c2c1cf29cd 434 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
mbed_official 390:35c2c1cf29cd 435 break;
mbed_official 390:35c2c1cf29cd 436 }
mbed_official 390:35c2c1cf29cd 437 wait_100us(10);
mbed_official 390:35c2c1cf29cd 438 }
mbed_official 390:35c2c1cf29cd 439 } else {
mbed_official 390:35c2c1cf29cd 440 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
mbed_official 390:35c2c1cf29cd 441 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
mbed_official 390:35c2c1cf29cd 442 wait_100us(1);
mbed_official 390:35c2c1cf29cd 443 }
mbed_official 390:35c2c1cf29cd 444
mbed_official 390:35c2c1cf29cd 445 link = ethernetext_chk_link_mode();
mbed_official 390:35c2c1cf29cd 446 ethernetext_set_link_mode(link);
mbed_official 390:35c2c1cf29cd 447 }
mbed_official 390:35c2c1cf29cd 448
mbed_official 390:35c2c1cf29cd 449 void INT_Ether(void)
mbed_official 390:35c2c1cf29cd 450 {
mbed_official 390:35c2c1cf29cd 451 uint32_t stat_edmac;
mbed_official 390:35c2c1cf29cd 452 uint32_t stat_etherc;
mbed_official 390:35c2c1cf29cd 453
mbed_official 390:35c2c1cf29cd 454 /* Clear the interrupt request flag */
mbed_official 390:35c2c1cf29cd 455 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
mbed_official 390:35c2c1cf29cd 456 ETHEREESR0 = stat_edmac;
mbed_official 390:35c2c1cf29cd 457 /* Reception-related */
mbed_official 390:35c2c1cf29cd 458 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
mbed_official 390:35c2c1cf29cd 459 if (p_recv_cb_fnc != NULL) {
mbed_official 390:35c2c1cf29cd 460 p_recv_cb_fnc();
mbed_official 390:35c2c1cf29cd 461 }
mbed_official 390:35c2c1cf29cd 462 }
mbed_official 390:35c2c1cf29cd 463 /* E-MAC-related */
mbed_official 390:35c2c1cf29cd 464 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
mbed_official 390:35c2c1cf29cd 465 /* Clear the interrupt request flag */
mbed_official 390:35c2c1cf29cd 466 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
mbed_official 390:35c2c1cf29cd 467 ETHERECSR0 = stat_etherc;
mbed_official 390:35c2c1cf29cd 468 }
mbed_official 390:35c2c1cf29cd 469 }
mbed_official 390:35c2c1cf29cd 470
mbed_official 390:35c2c1cf29cd 471 static void lan_reg_reset(void) {
mbed_official 390:35c2c1cf29cd 472 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
mbed_official 390:35c2c1cf29cd 473
mbed_official 390:35c2c1cf29cd 474 ETHERARSTR |= 0x00000001; /* ETHER software reset */
mbed_official 390:35c2c1cf29cd 475 while (j--) {
mbed_official 390:35c2c1cf29cd 476 /* Do Nothing */
mbed_official 390:35c2c1cf29cd 477 }
mbed_official 390:35c2c1cf29cd 478
mbed_official 390:35c2c1cf29cd 479 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
mbed_official 390:35c2c1cf29cd 480 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
mbed_official 390:35c2c1cf29cd 481
mbed_official 390:35c2c1cf29cd 482 /* Check clear software reset */
mbed_official 390:35c2c1cf29cd 483 while ((ETHEREDMR0 & 0x00000003) != 0) {
mbed_official 390:35c2c1cf29cd 484 /* Do Nothing */
mbed_official 390:35c2c1cf29cd 485 }
mbed_official 390:35c2c1cf29cd 486 }
mbed_official 390:35c2c1cf29cd 487
mbed_official 390:35c2c1cf29cd 488 static void lan_desc_create(void) {
mbed_official 390:35c2c1cf29cd 489 int32_t i;
mbed_official 390:35c2c1cf29cd 490 uint8_t *p_memory_top;
mbed_official 390:35c2c1cf29cd 491
mbed_official 390:35c2c1cf29cd 492 (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory));
mbed_official 390:35c2c1cf29cd 493 p_memory_top = (uint8_t *)(((uint32_t)ehernet_nc_memory + BUFF_BOUNDARY_MSK) & ~BUFF_BOUNDARY_MSK);
mbed_official 390:35c2c1cf29cd 494
mbed_official 390:35c2c1cf29cd 495 /* Descriptor area configuration */
mbed_official 390:35c2c1cf29cd 496 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
mbed_official 390:35c2c1cf29cd 497 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
mbed_official 390:35c2c1cf29cd 498 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
mbed_official 390:35c2c1cf29cd 499 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
mbed_official 390:35c2c1cf29cd 500
mbed_official 390:35c2c1cf29cd 501 /* Transmit descriptor */
mbed_official 390:35c2c1cf29cd 502 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
mbed_official 390:35c2c1cf29cd 503 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
mbed_official 390:35c2c1cf29cd 504 p_memory_top += SIZE_OF_BUFFER;
mbed_official 390:35c2c1cf29cd 505 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
mbed_official 390:35c2c1cf29cd 506 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
mbed_official 390:35c2c1cf29cd 507 }
mbed_official 390:35c2c1cf29cd 508 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
mbed_official 390:35c2c1cf29cd 509
mbed_official 390:35c2c1cf29cd 510 /* Receive descriptor */
mbed_official 390:35c2c1cf29cd 511 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
mbed_official 390:35c2c1cf29cd 512 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
mbed_official 390:35c2c1cf29cd 513 p_memory_top += SIZE_OF_BUFFER;
mbed_official 390:35c2c1cf29cd 514 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
mbed_official 390:35c2c1cf29cd 515 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
mbed_official 390:35c2c1cf29cd 516 }
mbed_official 390:35c2c1cf29cd 517 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
mbed_official 390:35c2c1cf29cd 518
mbed_official 390:35c2c1cf29cd 519 /* Initialize descriptor management information */
mbed_official 390:35c2c1cf29cd 520 send_top_index = 0;
mbed_official 390:35c2c1cf29cd 521 recv_top_index = 0;
mbed_official 390:35c2c1cf29cd 522 rx_read_offset = 0;
mbed_official 390:35c2c1cf29cd 523 tx_wite_offset = 0;
mbed_official 390:35c2c1cf29cd 524 p_recv_end_desc = NULL;
mbed_official 390:35c2c1cf29cd 525 }
mbed_official 390:35c2c1cf29cd 526
mbed_official 390:35c2c1cf29cd 527 static void lan_reg_set(int32_t link) {
mbed_official 390:35c2c1cf29cd 528 /* MAC address setting */
mbed_official 390:35c2c1cf29cd 529 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
mbed_official 390:35c2c1cf29cd 530 | ((uint32_t)mac_addr[1] << 16)
mbed_official 390:35c2c1cf29cd 531 | ((uint32_t)mac_addr[2] << 8)
mbed_official 390:35c2c1cf29cd 532 | (uint32_t)mac_addr[3];
mbed_official 390:35c2c1cf29cd 533 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
mbed_official 390:35c2c1cf29cd 534 | (uint32_t)mac_addr[5];
mbed_official 390:35c2c1cf29cd 535
mbed_official 390:35c2c1cf29cd 536 /* E-DMAC */
mbed_official 390:35c2c1cf29cd 537 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
mbed_official 390:35c2c1cf29cd 538 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
mbed_official 390:35c2c1cf29cd 539 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
mbed_official 390:35c2c1cf29cd 540 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
mbed_official 390:35c2c1cf29cd 541 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
mbed_official 390:35c2c1cf29cd 542 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
mbed_official 390:35c2c1cf29cd 543 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
mbed_official 390:35c2c1cf29cd 544 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
mbed_official 390:35c2c1cf29cd 545 ETHEREDMR0 |= 0x00000040; /* Little endian */
mbed_official 390:35c2c1cf29cd 546 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
mbed_official 390:35c2c1cf29cd 547 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
mbed_official 390:35c2c1cf29cd 548 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
mbed_official 390:35c2c1cf29cd 549 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
mbed_official 390:35c2c1cf29cd 550 ETHERFCFTR0 &= ~0x001F00FF;
mbed_official 390:35c2c1cf29cd 551 ETHERFCFTR0 |= 0x00070007;
mbed_official 390:35c2c1cf29cd 552 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
mbed_official 390:35c2c1cf29cd 553
mbed_official 390:35c2c1cf29cd 554 /* E-MAC */
mbed_official 390:35c2c1cf29cd 555 ETHERECMR0 &= ~0x04BF2063; /* All clear */
mbed_official 390:35c2c1cf29cd 556 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
mbed_official 390:35c2c1cf29cd 557 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
mbed_official 390:35c2c1cf29cd 558 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
mbed_official 390:35c2c1cf29cd 559 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
mbed_official 390:35c2c1cf29cd 560 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
mbed_official 390:35c2c1cf29cd 561 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
mbed_official 390:35c2c1cf29cd 562 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
mbed_official 390:35c2c1cf29cd 563 } else {
mbed_official 390:35c2c1cf29cd 564 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
mbed_official 390:35c2c1cf29cd 565 }
mbed_official 390:35c2c1cf29cd 566
mbed_official 390:35c2c1cf29cd 567 /* Interrupt-related */
mbed_official 390:35c2c1cf29cd 568 if (p_recv_cb_fnc != NULL) {
mbed_official 390:35c2c1cf29cd 569 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
mbed_official 390:35c2c1cf29cd 570 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
mbed_official 390:35c2c1cf29cd 571 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
mbed_official 390:35c2c1cf29cd 572 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
mbed_official 390:35c2c1cf29cd 573 InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
mbed_official 390:35c2c1cf29cd 574 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
mbed_official 390:35c2c1cf29cd 575 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
mbed_official 390:35c2c1cf29cd 576 }
mbed_official 390:35c2c1cf29cd 577
mbed_official 390:35c2c1cf29cd 578 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
mbed_official 390:35c2c1cf29cd 579
mbed_official 390:35c2c1cf29cd 580 /* Enable transmission/reception */
mbed_official 390:35c2c1cf29cd 581 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
mbed_official 390:35c2c1cf29cd 582 ETHEREDRRR0 |= 0x00000001; /* RR */
mbed_official 390:35c2c1cf29cd 583 }
mbed_official 390:35c2c1cf29cd 584 }
mbed_official 390:35c2c1cf29cd 585
mbed_official 390:35c2c1cf29cd 586 static uint16_t phy_reg_read(uint16_t reg_addr) {
mbed_official 390:35c2c1cf29cd 587 uint16_t data;
mbed_official 390:35c2c1cf29cd 588
mbed_official 390:35c2c1cf29cd 589 mii_preamble();
mbed_official 390:35c2c1cf29cd 590 mii_cmd(reg_addr, PHY_READ);
mbed_official 390:35c2c1cf29cd 591 mii_z();
mbed_official 390:35c2c1cf29cd 592 mii_reg_read(&data);
mbed_official 390:35c2c1cf29cd 593 mii_z();
mbed_official 390:35c2c1cf29cd 594
mbed_official 390:35c2c1cf29cd 595 return data;
mbed_official 390:35c2c1cf29cd 596 }
mbed_official 390:35c2c1cf29cd 597
mbed_official 390:35c2c1cf29cd 598 static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
mbed_official 390:35c2c1cf29cd 599 mii_preamble();
mbed_official 390:35c2c1cf29cd 600 mii_cmd(reg_addr, PHY_WRITE);
mbed_official 390:35c2c1cf29cd 601 mii_write_1();
mbed_official 390:35c2c1cf29cd 602 mii_write_0();
mbed_official 390:35c2c1cf29cd 603 mii_reg_write(data);
mbed_official 390:35c2c1cf29cd 604 mii_z();
mbed_official 390:35c2c1cf29cd 605 }
mbed_official 390:35c2c1cf29cd 606
mbed_official 390:35c2c1cf29cd 607 static void mii_preamble(void) {
mbed_official 390:35c2c1cf29cd 608 int32_t i = 32;
mbed_official 390:35c2c1cf29cd 609
mbed_official 390:35c2c1cf29cd 610 for (i = 32; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 611 /* 1 is output via the MII (Media Independent Interface) block. */
mbed_official 390:35c2c1cf29cd 612 mii_write_1();
mbed_official 390:35c2c1cf29cd 613 }
mbed_official 390:35c2c1cf29cd 614 }
mbed_official 390:35c2c1cf29cd 615
mbed_official 390:35c2c1cf29cd 616 static void mii_cmd(uint16_t reg_addr, uint32_t option) {
mbed_official 390:35c2c1cf29cd 617 int32_t i;
mbed_official 390:35c2c1cf29cd 618 uint16_t data = 0;
mbed_official 390:35c2c1cf29cd 619
mbed_official 390:35c2c1cf29cd 620 data |= (PHY_ST << 14); /* ST code */
mbed_official 390:35c2c1cf29cd 621 data |= (option << 12); /* OP code */
mbed_official 390:35c2c1cf29cd 622 data |= (PHY_ADDR << 7); /* PHY Address */
mbed_official 390:35c2c1cf29cd 623 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
mbed_official 390:35c2c1cf29cd 624 for (i = 14; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 625 if ((data & 0x8000) == 0) {
mbed_official 390:35c2c1cf29cd 626 mii_write_0();
mbed_official 390:35c2c1cf29cd 627 } else {
mbed_official 390:35c2c1cf29cd 628 mii_write_1();
mbed_official 390:35c2c1cf29cd 629 }
mbed_official 390:35c2c1cf29cd 630 data <<= 1;
mbed_official 390:35c2c1cf29cd 631 }
mbed_official 390:35c2c1cf29cd 632 }
mbed_official 390:35c2c1cf29cd 633
mbed_official 390:35c2c1cf29cd 634 static void mii_reg_read(uint16_t *data) {
mbed_official 390:35c2c1cf29cd 635 int32_t i;
mbed_official 390:35c2c1cf29cd 636 uint16_t reg_data = 0;
mbed_official 390:35c2c1cf29cd 637
mbed_official 390:35c2c1cf29cd 638 /* Data are read in one bit at a time */
mbed_official 390:35c2c1cf29cd 639 for (i = 16; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 640 set_ether_pir(PIR0_MDC_LOW);
mbed_official 390:35c2c1cf29cd 641 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 390:35c2c1cf29cd 642 reg_data <<= 1;
mbed_official 390:35c2c1cf29cd 643 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
mbed_official 390:35c2c1cf29cd 644 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 390:35c2c1cf29cd 645 set_ether_pir(PIR0_MDC_LOW);
mbed_official 390:35c2c1cf29cd 646 }
mbed_official 390:35c2c1cf29cd 647 *data = reg_data;
mbed_official 390:35c2c1cf29cd 648 }
mbed_official 390:35c2c1cf29cd 649
mbed_official 390:35c2c1cf29cd 650 static void mii_reg_write(uint16_t data) {
mbed_official 390:35c2c1cf29cd 651 int32_t i;
mbed_official 390:35c2c1cf29cd 652
mbed_official 390:35c2c1cf29cd 653 /* Data are written one bit at a time */
mbed_official 390:35c2c1cf29cd 654 for (i = 16; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 655 if ((data & 0x8000) == 0) {
mbed_official 390:35c2c1cf29cd 656 mii_write_0();
mbed_official 390:35c2c1cf29cd 657 } else {
mbed_official 390:35c2c1cf29cd 658 mii_write_1();
mbed_official 390:35c2c1cf29cd 659 }
mbed_official 390:35c2c1cf29cd 660 data <<= 1;
mbed_official 390:35c2c1cf29cd 661 }
mbed_official 390:35c2c1cf29cd 662 }
mbed_official 390:35c2c1cf29cd 663
mbed_official 390:35c2c1cf29cd 664 static void mii_z(void) {
mbed_official 390:35c2c1cf29cd 665 set_ether_pir(PIR0_MDC_LOW);
mbed_official 390:35c2c1cf29cd 666 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 390:35c2c1cf29cd 667 set_ether_pir(PIR0_MDC_HIGH);
mbed_official 390:35c2c1cf29cd 668 set_ether_pir(PIR0_MDC_LOW);
mbed_official 390:35c2c1cf29cd 669 }
mbed_official 390:35c2c1cf29cd 670
mbed_official 390:35c2c1cf29cd 671 static void mii_write_1(void) {
mbed_official 390:35c2c1cf29cd 672 set_ether_pir(PIR0_MDO | PIR0_MMD);
mbed_official 390:35c2c1cf29cd 673 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
mbed_official 390:35c2c1cf29cd 674 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
mbed_official 390:35c2c1cf29cd 675 set_ether_pir(PIR0_MDO | PIR0_MMD);
mbed_official 390:35c2c1cf29cd 676 }
mbed_official 390:35c2c1cf29cd 677
mbed_official 390:35c2c1cf29cd 678 static void mii_write_0(void) {
mbed_official 390:35c2c1cf29cd 679 set_ether_pir(PIR0_MMD);
mbed_official 390:35c2c1cf29cd 680 set_ether_pir(PIR0_MMD | PIR0_MDC);
mbed_official 390:35c2c1cf29cd 681 set_ether_pir(PIR0_MMD | PIR0_MDC);
mbed_official 390:35c2c1cf29cd 682 set_ether_pir(PIR0_MMD);
mbed_official 390:35c2c1cf29cd 683 }
mbed_official 390:35c2c1cf29cd 684
mbed_official 390:35c2c1cf29cd 685 static void set_ether_pir(uint32_t set_data) {
mbed_official 390:35c2c1cf29cd 686 int32_t i;
mbed_official 390:35c2c1cf29cd 687
mbed_official 390:35c2c1cf29cd 688 for (i = MDC_WAIT; i > 0; i--) {
mbed_official 390:35c2c1cf29cd 689 ETHERPIR0 = set_data;
mbed_official 390:35c2c1cf29cd 690 }
mbed_official 390:35c2c1cf29cd 691 }
mbed_official 390:35c2c1cf29cd 692
mbed_official 390:35c2c1cf29cd 693 static void wait_100us(int32_t wait_cnt) {
mbed_official 390:35c2c1cf29cd 694 volatile int32_t j = LOOP_100us * wait_cnt;
mbed_official 390:35c2c1cf29cd 695
mbed_official 390:35c2c1cf29cd 696 while (--j) {
mbed_official 390:35c2c1cf29cd 697 /* Do Nothing */
mbed_official 390:35c2c1cf29cd 698 }
mbed_official 390:35c2c1cf29cd 699 }