Stuart Northfield / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer*
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 24 * File Name : scif_iodefine.h
mbed_official 390:35c2c1cf29cd 25 * $Rev: $
mbed_official 390:35c2c1cf29cd 26 * $Date:: $
mbed_official 390:35c2c1cf29cd 27 * Description : Definition of I/O Register (V1.00a)
mbed_official 390:35c2c1cf29cd 28 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 29 #ifndef SCIF_IODEFINE_H
mbed_official 390:35c2c1cf29cd 30 #define SCIF_IODEFINE_H
mbed_official 390:35c2c1cf29cd 31 /* ->QAC 0857 : Over 1024 #define (C90) */
mbed_official 390:35c2c1cf29cd 32 /* ->SEC M1.10.1 : Not magic number */
mbed_official 390:35c2c1cf29cd 33
mbed_official 390:35c2c1cf29cd 34 struct st_scif
mbed_official 390:35c2c1cf29cd 35 { /* SCIF */
mbed_official 390:35c2c1cf29cd 36 volatile uint16_t SCSMR; /* SCSMR */
mbed_official 390:35c2c1cf29cd 37 volatile uint8_t dummy1[2]; /* */
mbed_official 390:35c2c1cf29cd 38 volatile uint8_t SCBRR; /* SCBRR */
mbed_official 390:35c2c1cf29cd 39 volatile uint8_t dummy2[3]; /* */
mbed_official 390:35c2c1cf29cd 40 volatile uint16_t SCSCR; /* SCSCR */
mbed_official 390:35c2c1cf29cd 41 volatile uint8_t dummy3[2]; /* */
mbed_official 390:35c2c1cf29cd 42 volatile uint8_t SCFTDR; /* SCFTDR */
mbed_official 390:35c2c1cf29cd 43 volatile uint8_t dummy4[3]; /* */
mbed_official 390:35c2c1cf29cd 44 volatile uint16_t SCFSR; /* SCFSR */
mbed_official 390:35c2c1cf29cd 45 volatile uint8_t dummy5[2]; /* */
mbed_official 390:35c2c1cf29cd 46 volatile uint8_t SCFRDR; /* SCFRDR */
mbed_official 390:35c2c1cf29cd 47 volatile uint8_t dummy6[3]; /* */
mbed_official 390:35c2c1cf29cd 48 volatile uint16_t SCFCR; /* SCFCR */
mbed_official 390:35c2c1cf29cd 49 volatile uint8_t dummy7[2]; /* */
mbed_official 390:35c2c1cf29cd 50 volatile uint16_t SCFDR; /* SCFDR */
mbed_official 390:35c2c1cf29cd 51 volatile uint8_t dummy8[2]; /* */
mbed_official 390:35c2c1cf29cd 52 volatile uint16_t SCSPTR; /* SCSPTR */
mbed_official 390:35c2c1cf29cd 53 volatile uint8_t dummy9[2]; /* */
mbed_official 390:35c2c1cf29cd 54 volatile uint16_t SCLSR; /* SCLSR */
mbed_official 390:35c2c1cf29cd 55 volatile uint8_t dummy10[2]; /* */
mbed_official 390:35c2c1cf29cd 56 volatile uint16_t SCEMR; /* SCEMR */
mbed_official 390:35c2c1cf29cd 57 };
mbed_official 390:35c2c1cf29cd 58
mbed_official 390:35c2c1cf29cd 59
mbed_official 390:35c2c1cf29cd 60 #define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
mbed_official 390:35c2c1cf29cd 61 #define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
mbed_official 390:35c2c1cf29cd 62 #define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
mbed_official 390:35c2c1cf29cd 63 #define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
mbed_official 390:35c2c1cf29cd 64 #define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
mbed_official 390:35c2c1cf29cd 65 #define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
mbed_official 390:35c2c1cf29cd 66 #define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
mbed_official 390:35c2c1cf29cd 67 #define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 #define P_SCIF0 (0xE8007000uL) /* SCIF0 */
mbed_official 390:35c2c1cf29cd 70 #define P_SCIF1 (0xE8007800uL) /* SCIF1 */
mbed_official 390:35c2c1cf29cd 71 #define P_SCIF2 (0xE8008000uL) /* SCIF2 */
mbed_official 390:35c2c1cf29cd 72 #define P_SCIF3 (0xE8008800uL) /* SCIF3 */
mbed_official 390:35c2c1cf29cd 73 #define P_SCIF4 (0xE8009000uL) /* SCIF4 */
mbed_official 390:35c2c1cf29cd 74 #define P_SCIF5 (0xE8009800uL) /* SCIF5 */
mbed_official 390:35c2c1cf29cd 75 #define P_SCIF6 (0xE800A000uL) /* SCIF6 */
mbed_official 390:35c2c1cf29cd 76 #define P_SCIF7 (0xE800A800uL) /* SCIF7 */
mbed_official 390:35c2c1cf29cd 77
mbed_official 390:35c2c1cf29cd 78
mbed_official 390:35c2c1cf29cd 79 /* Start of channnel array defines of SCIF */
mbed_official 390:35c2c1cf29cd 80
mbed_official 390:35c2c1cf29cd 81 /* Channnel array defines of SCIF */
mbed_official 390:35c2c1cf29cd 82 /*(Sample) value = SCIF[ channel ]->SCSMR; */
mbed_official 390:35c2c1cf29cd 83 #define SCIF_COUNT 8
mbed_official 390:35c2c1cf29cd 84 #define SCIF_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 85 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 86 &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
mbed_official 390:35c2c1cf29cd 87 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 88
mbed_official 390:35c2c1cf29cd 89 /* End of channnel array defines of SCIF */
mbed_official 390:35c2c1cf29cd 90
mbed_official 390:35c2c1cf29cd 91
mbed_official 390:35c2c1cf29cd 92 #define SCSMR_0 SCIF0.SCSMR
mbed_official 390:35c2c1cf29cd 93 #define SCBRR_0 SCIF0.SCBRR
mbed_official 390:35c2c1cf29cd 94 #define SCSCR_0 SCIF0.SCSCR
mbed_official 390:35c2c1cf29cd 95 #define SCFTDR_0 SCIF0.SCFTDR
mbed_official 390:35c2c1cf29cd 96 #define SCFSR_0 SCIF0.SCFSR
mbed_official 390:35c2c1cf29cd 97 #define SCFRDR_0 SCIF0.SCFRDR
mbed_official 390:35c2c1cf29cd 98 #define SCFCR_0 SCIF0.SCFCR
mbed_official 390:35c2c1cf29cd 99 #define SCFDR_0 SCIF0.SCFDR
mbed_official 390:35c2c1cf29cd 100 #define SCSPTR_0 SCIF0.SCSPTR
mbed_official 390:35c2c1cf29cd 101 #define SCLSR_0 SCIF0.SCLSR
mbed_official 390:35c2c1cf29cd 102 #define SCEMR_0 SCIF0.SCEMR
mbed_official 390:35c2c1cf29cd 103 #define SCSMR_1 SCIF1.SCSMR
mbed_official 390:35c2c1cf29cd 104 #define SCBRR_1 SCIF1.SCBRR
mbed_official 390:35c2c1cf29cd 105 #define SCSCR_1 SCIF1.SCSCR
mbed_official 390:35c2c1cf29cd 106 #define SCFTDR_1 SCIF1.SCFTDR
mbed_official 390:35c2c1cf29cd 107 #define SCFSR_1 SCIF1.SCFSR
mbed_official 390:35c2c1cf29cd 108 #define SCFRDR_1 SCIF1.SCFRDR
mbed_official 390:35c2c1cf29cd 109 #define SCFCR_1 SCIF1.SCFCR
mbed_official 390:35c2c1cf29cd 110 #define SCFDR_1 SCIF1.SCFDR
mbed_official 390:35c2c1cf29cd 111 #define SCSPTR_1 SCIF1.SCSPTR
mbed_official 390:35c2c1cf29cd 112 #define SCLSR_1 SCIF1.SCLSR
mbed_official 390:35c2c1cf29cd 113 #define SCEMR_1 SCIF1.SCEMR
mbed_official 390:35c2c1cf29cd 114 #define SCSMR_2 SCIF2.SCSMR
mbed_official 390:35c2c1cf29cd 115 #define SCBRR_2 SCIF2.SCBRR
mbed_official 390:35c2c1cf29cd 116 #define SCSCR_2 SCIF2.SCSCR
mbed_official 390:35c2c1cf29cd 117 #define SCFTDR_2 SCIF2.SCFTDR
mbed_official 390:35c2c1cf29cd 118 #define SCFSR_2 SCIF2.SCFSR
mbed_official 390:35c2c1cf29cd 119 #define SCFRDR_2 SCIF2.SCFRDR
mbed_official 390:35c2c1cf29cd 120 #define SCFCR_2 SCIF2.SCFCR
mbed_official 390:35c2c1cf29cd 121 #define SCFDR_2 SCIF2.SCFDR
mbed_official 390:35c2c1cf29cd 122 #define SCSPTR_2 SCIF2.SCSPTR
mbed_official 390:35c2c1cf29cd 123 #define SCLSR_2 SCIF2.SCLSR
mbed_official 390:35c2c1cf29cd 124 #define SCEMR_2 SCIF2.SCEMR
mbed_official 390:35c2c1cf29cd 125 #define SCSMR_3 SCIF3.SCSMR
mbed_official 390:35c2c1cf29cd 126 #define SCBRR_3 SCIF3.SCBRR
mbed_official 390:35c2c1cf29cd 127 #define SCSCR_3 SCIF3.SCSCR
mbed_official 390:35c2c1cf29cd 128 #define SCFTDR_3 SCIF3.SCFTDR
mbed_official 390:35c2c1cf29cd 129 #define SCFSR_3 SCIF3.SCFSR
mbed_official 390:35c2c1cf29cd 130 #define SCFRDR_3 SCIF3.SCFRDR
mbed_official 390:35c2c1cf29cd 131 #define SCFCR_3 SCIF3.SCFCR
mbed_official 390:35c2c1cf29cd 132 #define SCFDR_3 SCIF3.SCFDR
mbed_official 390:35c2c1cf29cd 133 #define SCSPTR_3 SCIF3.SCSPTR
mbed_official 390:35c2c1cf29cd 134 #define SCLSR_3 SCIF3.SCLSR
mbed_official 390:35c2c1cf29cd 135 #define SCEMR_3 SCIF3.SCEMR
mbed_official 390:35c2c1cf29cd 136 #define SCSMR_4 SCIF4.SCSMR
mbed_official 390:35c2c1cf29cd 137 #define SCBRR_4 SCIF4.SCBRR
mbed_official 390:35c2c1cf29cd 138 #define SCSCR_4 SCIF4.SCSCR
mbed_official 390:35c2c1cf29cd 139 #define SCFTDR_4 SCIF4.SCFTDR
mbed_official 390:35c2c1cf29cd 140 #define SCFSR_4 SCIF4.SCFSR
mbed_official 390:35c2c1cf29cd 141 #define SCFRDR_4 SCIF4.SCFRDR
mbed_official 390:35c2c1cf29cd 142 #define SCFCR_4 SCIF4.SCFCR
mbed_official 390:35c2c1cf29cd 143 #define SCFDR_4 SCIF4.SCFDR
mbed_official 390:35c2c1cf29cd 144 #define SCSPTR_4 SCIF4.SCSPTR
mbed_official 390:35c2c1cf29cd 145 #define SCLSR_4 SCIF4.SCLSR
mbed_official 390:35c2c1cf29cd 146 #define SCEMR_4 SCIF4.SCEMR
mbed_official 390:35c2c1cf29cd 147 #define SCSMR_5 SCIF5.SCSMR
mbed_official 390:35c2c1cf29cd 148 #define SCBRR_5 SCIF5.SCBRR
mbed_official 390:35c2c1cf29cd 149 #define SCSCR_5 SCIF5.SCSCR
mbed_official 390:35c2c1cf29cd 150 #define SCFTDR_5 SCIF5.SCFTDR
mbed_official 390:35c2c1cf29cd 151 #define SCFSR_5 SCIF5.SCFSR
mbed_official 390:35c2c1cf29cd 152 #define SCFRDR_5 SCIF5.SCFRDR
mbed_official 390:35c2c1cf29cd 153 #define SCFCR_5 SCIF5.SCFCR
mbed_official 390:35c2c1cf29cd 154 #define SCFDR_5 SCIF5.SCFDR
mbed_official 390:35c2c1cf29cd 155 #define SCSPTR_5 SCIF5.SCSPTR
mbed_official 390:35c2c1cf29cd 156 #define SCLSR_5 SCIF5.SCLSR
mbed_official 390:35c2c1cf29cd 157 #define SCEMR_5 SCIF5.SCEMR
mbed_official 390:35c2c1cf29cd 158 #define SCSMR_6 SCIF6.SCSMR
mbed_official 390:35c2c1cf29cd 159 #define SCBRR_6 SCIF6.SCBRR
mbed_official 390:35c2c1cf29cd 160 #define SCSCR_6 SCIF6.SCSCR
mbed_official 390:35c2c1cf29cd 161 #define SCFTDR_6 SCIF6.SCFTDR
mbed_official 390:35c2c1cf29cd 162 #define SCFSR_6 SCIF6.SCFSR
mbed_official 390:35c2c1cf29cd 163 #define SCFRDR_6 SCIF6.SCFRDR
mbed_official 390:35c2c1cf29cd 164 #define SCFCR_6 SCIF6.SCFCR
mbed_official 390:35c2c1cf29cd 165 #define SCFDR_6 SCIF6.SCFDR
mbed_official 390:35c2c1cf29cd 166 #define SCSPTR_6 SCIF6.SCSPTR
mbed_official 390:35c2c1cf29cd 167 #define SCLSR_6 SCIF6.SCLSR
mbed_official 390:35c2c1cf29cd 168 #define SCEMR_6 SCIF6.SCEMR
mbed_official 390:35c2c1cf29cd 169 #define SCSMR_7 SCIF7.SCSMR
mbed_official 390:35c2c1cf29cd 170 #define SCBRR_7 SCIF7.SCBRR
mbed_official 390:35c2c1cf29cd 171 #define SCSCR_7 SCIF7.SCSCR
mbed_official 390:35c2c1cf29cd 172 #define SCFTDR_7 SCIF7.SCFTDR
mbed_official 390:35c2c1cf29cd 173 #define SCFSR_7 SCIF7.SCFSR
mbed_official 390:35c2c1cf29cd 174 #define SCFRDR_7 SCIF7.SCFRDR
mbed_official 390:35c2c1cf29cd 175 #define SCFCR_7 SCIF7.SCFCR
mbed_official 390:35c2c1cf29cd 176 #define SCFDR_7 SCIF7.SCFDR
mbed_official 390:35c2c1cf29cd 177 #define SCSPTR_7 SCIF7.SCSPTR
mbed_official 390:35c2c1cf29cd 178 #define SCLSR_7 SCIF7.SCLSR
mbed_official 390:35c2c1cf29cd 179 #define SCEMR_7 SCIF7.SCEMR
mbed_official 390:35c2c1cf29cd 180 /* <-SEC M1.10.1 */
mbed_official 390:35c2c1cf29cd 181 /* <-QAC 0857 */
mbed_official 390:35c2c1cf29cd 182 #endif