Stuart Northfield / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer*
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 24 * File Name : pfv_iodefine.h
mbed_official 390:35c2c1cf29cd 25 * $Rev: $
mbed_official 390:35c2c1cf29cd 26 * $Date:: $
mbed_official 390:35c2c1cf29cd 27 * Description : Definition of I/O Register (V1.00a)
mbed_official 390:35c2c1cf29cd 28 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 29 #ifndef PFV_IODEFINE_H
mbed_official 390:35c2c1cf29cd 30 #define PFV_IODEFINE_H
mbed_official 390:35c2c1cf29cd 31 /* ->SEC M1.10.1 : Not magic number */
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 struct st_pfv
mbed_official 390:35c2c1cf29cd 34 { /* PFV */
mbed_official 390:35c2c1cf29cd 35 volatile uint32_t PFVCR; /* PFVCR */
mbed_official 390:35c2c1cf29cd 36 volatile uint32_t PFVICR; /* PFVICR */
mbed_official 390:35c2c1cf29cd 37 volatile uint32_t PFVISR; /* PFVISR */
mbed_official 390:35c2c1cf29cd 38 volatile uint8_t dummy1[20]; /* */
mbed_official 390:35c2c1cf29cd 39 #define PFVID_COUNT 8
mbed_official 390:35c2c1cf29cd 40 volatile uint32_t PFVID0; /* PFVID0 */
mbed_official 390:35c2c1cf29cd 41 volatile uint32_t PFVID1; /* PFVID1 */
mbed_official 390:35c2c1cf29cd 42 volatile uint32_t PFVID2; /* PFVID2 */
mbed_official 390:35c2c1cf29cd 43 volatile uint32_t PFVID3; /* PFVID3 */
mbed_official 390:35c2c1cf29cd 44 volatile uint32_t PFVID4; /* PFVID4 */
mbed_official 390:35c2c1cf29cd 45 volatile uint32_t PFVID5; /* PFVID5 */
mbed_official 390:35c2c1cf29cd 46 volatile uint32_t PFVID6; /* PFVID6 */
mbed_official 390:35c2c1cf29cd 47 volatile uint32_t PFVID7; /* PFVID7 */
mbed_official 390:35c2c1cf29cd 48 #define PFVOD_COUNT 8
mbed_official 390:35c2c1cf29cd 49 volatile uint32_t PFVOD0; /* PFVOD0 */
mbed_official 390:35c2c1cf29cd 50 volatile uint32_t PFVOD1; /* PFVOD1 */
mbed_official 390:35c2c1cf29cd 51 volatile uint32_t PFVOD2; /* PFVOD2 */
mbed_official 390:35c2c1cf29cd 52 volatile uint32_t PFVOD3; /* PFVOD3 */
mbed_official 390:35c2c1cf29cd 53 volatile uint32_t PFVOD4; /* PFVOD4 */
mbed_official 390:35c2c1cf29cd 54 volatile uint32_t PFVOD5; /* PFVOD5 */
mbed_official 390:35c2c1cf29cd 55 volatile uint32_t PFVOD6; /* PFVOD6 */
mbed_official 390:35c2c1cf29cd 56 volatile uint32_t PFVOD7; /* PFVOD7 */
mbed_official 390:35c2c1cf29cd 57 volatile uint8_t dummy2[4]; /* */
mbed_official 390:35c2c1cf29cd 58 volatile uint32_t PFVIFSR; /* PFVIFSR */
mbed_official 390:35c2c1cf29cd 59 volatile uint32_t PFVOFSR; /* PFVOFSR */
mbed_official 390:35c2c1cf29cd 60 volatile uint32_t PFVACR; /* PFVACR */
mbed_official 390:35c2c1cf29cd 61 volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
mbed_official 390:35c2c1cf29cd 62 volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
mbed_official 390:35c2c1cf29cd 63 volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
mbed_official 390:35c2c1cf29cd 64 volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
mbed_official 390:35c2c1cf29cd 65 volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
mbed_official 390:35c2c1cf29cd 66 volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
mbed_official 390:35c2c1cf29cd 67 volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
mbed_official 390:35c2c1cf29cd 68 volatile uint32_t PFVSZR; /* PFVSZR */
mbed_official 390:35c2c1cf29cd 69 };
mbed_official 390:35c2c1cf29cd 70
mbed_official 390:35c2c1cf29cd 71
mbed_official 390:35c2c1cf29cd 72 #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
mbed_official 390:35c2c1cf29cd 73 #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
mbed_official 390:35c2c1cf29cd 74
mbed_official 390:35c2c1cf29cd 75
mbed_official 390:35c2c1cf29cd 76 /* Start of channnel array defines of PFV */
mbed_official 390:35c2c1cf29cd 77
mbed_official 390:35c2c1cf29cd 78 /* Channnel array defines of PFV */
mbed_official 390:35c2c1cf29cd 79 /*(Sample) value = PFV[ channel ]->PFVCR; */
mbed_official 390:35c2c1cf29cd 80 #define PFV_COUNT 2
mbed_official 390:35c2c1cf29cd 81 #define PFV_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 82 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 83 &PFV0, &PFV1 \
mbed_official 390:35c2c1cf29cd 84 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 85
mbed_official 390:35c2c1cf29cd 86 /* End of channnel array defines of PFV */
mbed_official 390:35c2c1cf29cd 87
mbed_official 390:35c2c1cf29cd 88
mbed_official 390:35c2c1cf29cd 89 #define PFV0PFVCR PFV0.PFVCR
mbed_official 390:35c2c1cf29cd 90 #define PFV0PFVICR PFV0.PFVICR
mbed_official 390:35c2c1cf29cd 91 #define PFV0PFVISR PFV0.PFVISR
mbed_official 390:35c2c1cf29cd 92 #define PFV0PFVID0 PFV0.PFVID0
mbed_official 390:35c2c1cf29cd 93 #define PFV0PFVID1 PFV0.PFVID1
mbed_official 390:35c2c1cf29cd 94 #define PFV0PFVID2 PFV0.PFVID2
mbed_official 390:35c2c1cf29cd 95 #define PFV0PFVID3 PFV0.PFVID3
mbed_official 390:35c2c1cf29cd 96 #define PFV0PFVID4 PFV0.PFVID4
mbed_official 390:35c2c1cf29cd 97 #define PFV0PFVID5 PFV0.PFVID5
mbed_official 390:35c2c1cf29cd 98 #define PFV0PFVID6 PFV0.PFVID6
mbed_official 390:35c2c1cf29cd 99 #define PFV0PFVID7 PFV0.PFVID7
mbed_official 390:35c2c1cf29cd 100 #define PFV0PFVOD0 PFV0.PFVOD0
mbed_official 390:35c2c1cf29cd 101 #define PFV0PFVOD1 PFV0.PFVOD1
mbed_official 390:35c2c1cf29cd 102 #define PFV0PFVOD2 PFV0.PFVOD2
mbed_official 390:35c2c1cf29cd 103 #define PFV0PFVOD3 PFV0.PFVOD3
mbed_official 390:35c2c1cf29cd 104 #define PFV0PFVOD4 PFV0.PFVOD4
mbed_official 390:35c2c1cf29cd 105 #define PFV0PFVOD5 PFV0.PFVOD5
mbed_official 390:35c2c1cf29cd 106 #define PFV0PFVOD6 PFV0.PFVOD6
mbed_official 390:35c2c1cf29cd 107 #define PFV0PFVOD7 PFV0.PFVOD7
mbed_official 390:35c2c1cf29cd 108 #define PFV0PFVIFSR PFV0.PFVIFSR
mbed_official 390:35c2c1cf29cd 109 #define PFV0PFVOFSR PFV0.PFVOFSR
mbed_official 390:35c2c1cf29cd 110 #define PFV0PFVACR PFV0.PFVACR
mbed_official 390:35c2c1cf29cd 111 #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
mbed_official 390:35c2c1cf29cd 112 #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 113 #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 114 #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 115 #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 116 #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 117 #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 118 #define PFV0PFVSZR PFV0.PFVSZR
mbed_official 390:35c2c1cf29cd 119 #define PFV1PFVCR PFV1.PFVCR
mbed_official 390:35c2c1cf29cd 120 #define PFV1PFVICR PFV1.PFVICR
mbed_official 390:35c2c1cf29cd 121 #define PFV1PFVISR PFV1.PFVISR
mbed_official 390:35c2c1cf29cd 122 #define PFV1PFVID0 PFV1.PFVID0
mbed_official 390:35c2c1cf29cd 123 #define PFV1PFVID1 PFV1.PFVID1
mbed_official 390:35c2c1cf29cd 124 #define PFV1PFVID2 PFV1.PFVID2
mbed_official 390:35c2c1cf29cd 125 #define PFV1PFVID3 PFV1.PFVID3
mbed_official 390:35c2c1cf29cd 126 #define PFV1PFVID4 PFV1.PFVID4
mbed_official 390:35c2c1cf29cd 127 #define PFV1PFVID5 PFV1.PFVID5
mbed_official 390:35c2c1cf29cd 128 #define PFV1PFVID6 PFV1.PFVID6
mbed_official 390:35c2c1cf29cd 129 #define PFV1PFVID7 PFV1.PFVID7
mbed_official 390:35c2c1cf29cd 130 #define PFV1PFVOD0 PFV1.PFVOD0
mbed_official 390:35c2c1cf29cd 131 #define PFV1PFVOD1 PFV1.PFVOD1
mbed_official 390:35c2c1cf29cd 132 #define PFV1PFVOD2 PFV1.PFVOD2
mbed_official 390:35c2c1cf29cd 133 #define PFV1PFVOD3 PFV1.PFVOD3
mbed_official 390:35c2c1cf29cd 134 #define PFV1PFVOD4 PFV1.PFVOD4
mbed_official 390:35c2c1cf29cd 135 #define PFV1PFVOD5 PFV1.PFVOD5
mbed_official 390:35c2c1cf29cd 136 #define PFV1PFVOD6 PFV1.PFVOD6
mbed_official 390:35c2c1cf29cd 137 #define PFV1PFVOD7 PFV1.PFVOD7
mbed_official 390:35c2c1cf29cd 138 #define PFV1PFVIFSR PFV1.PFVIFSR
mbed_official 390:35c2c1cf29cd 139 #define PFV1PFVOFSR PFV1.PFVOFSR
mbed_official 390:35c2c1cf29cd 140 #define PFV1PFVACR PFV1.PFVACR
mbed_official 390:35c2c1cf29cd 141 #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
mbed_official 390:35c2c1cf29cd 142 #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 143 #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 144 #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 145 #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 146 #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 147 #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 148 #define PFV1PFVSZR PFV1.PFVSZR
mbed_official 390:35c2c1cf29cd 149 /* <-SEC M1.10.1 */
mbed_official 390:35c2c1cf29cd 150 #endif