Stuart Northfield
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/scif_iobitmask.h@390:35c2c1cf29cd, 2014-11-06 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Nov 06 11:00:10 2014 +0000
- Revision:
- 390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7
Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/
[RZ/A1H] mbed-RZ first release
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : scif_iobitmask.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: 1115 $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: 2014-07-09 15:35:02 +0900#$ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : SCIF register define header |
| mbed_official | 390:35c2c1cf29cd | 28 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef SCIF_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define SCIF_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 31 | |
| mbed_official | 390:35c2c1cf29cd | 32 | |
| mbed_official | 390:35c2c1cf29cd | 33 | /* ==== Mask values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 34 | /* ---- SCIF0 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 35 | #define SCIF0_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 36 | #define SCIF0_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 37 | #define SCIF0_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 38 | #define SCIF0_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 39 | #define SCIF0_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 40 | #define SCIF0_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 41 | |
| mbed_official | 390:35c2c1cf29cd | 42 | #define SCIF0_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 43 | |
| mbed_official | 390:35c2c1cf29cd | 44 | #define SCIF0_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 45 | #define SCIF0_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 46 | #define SCIF0_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 47 | #define SCIF0_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 48 | #define SCIF0_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 49 | #define SCIF0_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 50 | |
| mbed_official | 390:35c2c1cf29cd | 51 | #define SCIF0_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 52 | |
| mbed_official | 390:35c2c1cf29cd | 53 | #define SCIF0_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 54 | #define SCIF0_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 55 | #define SCIF0_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 56 | #define SCIF0_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 57 | #define SCIF0_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 58 | #define SCIF0_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 59 | #define SCIF0_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 60 | #define SCIF0_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 61 | #define SCIF0_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 62 | #define SCIF0_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 63 | |
| mbed_official | 390:35c2c1cf29cd | 64 | #define SCIF0_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 65 | |
| mbed_official | 390:35c2c1cf29cd | 66 | #define SCIF0_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 67 | #define SCIF0_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 68 | #define SCIF0_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 69 | #define SCIF0_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 70 | #define SCIF0_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 71 | #define SCIF0_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 72 | #define SCIF0_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 73 | |
| mbed_official | 390:35c2c1cf29cd | 74 | #define SCIF0_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 75 | #define SCIF0_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 76 | |
| mbed_official | 390:35c2c1cf29cd | 77 | #define SCIF0_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 78 | #define SCIF0_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 79 | #define SCIF0_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 80 | #define SCIF0_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 81 | #define SCIF0_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 82 | #define SCIF0_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 83 | #define SCIF0_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 84 | #define SCIF0_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 85 | |
| mbed_official | 390:35c2c1cf29cd | 86 | #define SCIF0_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 87 | |
| mbed_official | 390:35c2c1cf29cd | 88 | #define SCIF0_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 89 | #define SCIF0_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 90 | |
| mbed_official | 390:35c2c1cf29cd | 91 | /* ---- SCIF1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 92 | #define SCIF1_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 93 | #define SCIF1_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 94 | #define SCIF1_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 95 | #define SCIF1_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 96 | #define SCIF1_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 97 | #define SCIF1_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 98 | |
| mbed_official | 390:35c2c1cf29cd | 99 | #define SCIF1_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 100 | |
| mbed_official | 390:35c2c1cf29cd | 101 | #define SCIF1_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 102 | #define SCIF1_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 103 | #define SCIF1_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 104 | #define SCIF1_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 105 | #define SCIF1_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 106 | #define SCIF1_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 107 | |
| mbed_official | 390:35c2c1cf29cd | 108 | #define SCIF1_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 109 | |
| mbed_official | 390:35c2c1cf29cd | 110 | #define SCIF1_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 111 | #define SCIF1_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 112 | #define SCIF1_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 113 | #define SCIF1_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 114 | #define SCIF1_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 115 | #define SCIF1_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 116 | #define SCIF1_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 117 | #define SCIF1_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 118 | #define SCIF1_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 119 | #define SCIF1_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 120 | |
| mbed_official | 390:35c2c1cf29cd | 121 | #define SCIF1_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 122 | |
| mbed_official | 390:35c2c1cf29cd | 123 | #define SCIF1_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 124 | #define SCIF1_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 125 | #define SCIF1_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 126 | #define SCIF1_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 127 | #define SCIF1_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 128 | #define SCIF1_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 129 | #define SCIF1_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 130 | |
| mbed_official | 390:35c2c1cf29cd | 131 | #define SCIF1_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 132 | #define SCIF1_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 133 | |
| mbed_official | 390:35c2c1cf29cd | 134 | #define SCIF1_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 135 | #define SCIF1_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 136 | #define SCIF1_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 137 | #define SCIF1_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 138 | #define SCIF1_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 139 | #define SCIF1_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 140 | #define SCIF1_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 141 | #define SCIF1_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 142 | |
| mbed_official | 390:35c2c1cf29cd | 143 | #define SCIF1_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 144 | |
| mbed_official | 390:35c2c1cf29cd | 145 | #define SCIF1_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 146 | #define SCIF1_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 147 | |
| mbed_official | 390:35c2c1cf29cd | 148 | /* ---- SCIF2 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 149 | #define SCIF2_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 150 | #define SCIF2_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 151 | #define SCIF2_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 152 | #define SCIF2_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 153 | #define SCIF2_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 154 | #define SCIF2_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 155 | |
| mbed_official | 390:35c2c1cf29cd | 156 | #define SCIF2_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 157 | |
| mbed_official | 390:35c2c1cf29cd | 158 | #define SCIF2_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 159 | #define SCIF2_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 160 | #define SCIF2_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 161 | #define SCIF2_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 162 | #define SCIF2_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 163 | #define SCIF2_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 164 | |
| mbed_official | 390:35c2c1cf29cd | 165 | #define SCIF2_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 166 | |
| mbed_official | 390:35c2c1cf29cd | 167 | #define SCIF2_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 168 | #define SCIF2_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 169 | #define SCIF2_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 170 | #define SCIF2_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 171 | #define SCIF2_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 172 | #define SCIF2_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 173 | #define SCIF2_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 174 | #define SCIF2_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 175 | #define SCIF2_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 176 | #define SCIF2_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 177 | |
| mbed_official | 390:35c2c1cf29cd | 178 | #define SCIF2_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 179 | |
| mbed_official | 390:35c2c1cf29cd | 180 | #define SCIF2_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 181 | #define SCIF2_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 182 | #define SCIF2_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 183 | #define SCIF2_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 184 | #define SCIF2_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 185 | #define SCIF2_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 186 | #define SCIF2_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 187 | |
| mbed_official | 390:35c2c1cf29cd | 188 | #define SCIF2_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 189 | #define SCIF2_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 190 | |
| mbed_official | 390:35c2c1cf29cd | 191 | #define SCIF2_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 192 | #define SCIF2_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 193 | #define SCIF2_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 194 | #define SCIF2_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 195 | #define SCIF2_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 196 | #define SCIF2_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 197 | #define SCIF2_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 198 | #define SCIF2_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 199 | |
| mbed_official | 390:35c2c1cf29cd | 200 | #define SCIF2_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 201 | |
| mbed_official | 390:35c2c1cf29cd | 202 | #define SCIF2_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 203 | #define SCIF2_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 204 | |
| mbed_official | 390:35c2c1cf29cd | 205 | /* ---- SCIF3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 206 | #define SCIF3_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 207 | #define SCIF3_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 208 | #define SCIF3_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 209 | #define SCIF3_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 210 | #define SCIF3_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 211 | #define SCIF3_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 212 | |
| mbed_official | 390:35c2c1cf29cd | 213 | #define SCIF3_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 214 | |
| mbed_official | 390:35c2c1cf29cd | 215 | #define SCIF3_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 216 | #define SCIF3_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 217 | #define SCIF3_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 218 | #define SCIF3_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 219 | #define SCIF3_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 220 | #define SCIF3_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 221 | |
| mbed_official | 390:35c2c1cf29cd | 222 | #define SCIF3_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 223 | |
| mbed_official | 390:35c2c1cf29cd | 224 | #define SCIF3_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 225 | #define SCIF3_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 226 | #define SCIF3_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 227 | #define SCIF3_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 228 | #define SCIF3_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 229 | #define SCIF3_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 230 | #define SCIF3_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 231 | #define SCIF3_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 232 | #define SCIF3_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 233 | #define SCIF3_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 234 | |
| mbed_official | 390:35c2c1cf29cd | 235 | #define SCIF3_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 236 | |
| mbed_official | 390:35c2c1cf29cd | 237 | #define SCIF3_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 238 | #define SCIF3_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 239 | #define SCIF3_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 240 | #define SCIF3_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 241 | #define SCIF3_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 242 | #define SCIF3_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 243 | #define SCIF3_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 244 | |
| mbed_official | 390:35c2c1cf29cd | 245 | #define SCIF3_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 246 | #define SCIF3_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 247 | |
| mbed_official | 390:35c2c1cf29cd | 248 | #define SCIF3_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 249 | #define SCIF3_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 250 | #define SCIF3_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 251 | #define SCIF3_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 252 | #define SCIF3_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 253 | #define SCIF3_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 254 | #define SCIF3_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 255 | #define SCIF3_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 256 | |
| mbed_official | 390:35c2c1cf29cd | 257 | #define SCIF3_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 258 | |
| mbed_official | 390:35c2c1cf29cd | 259 | #define SCIF3_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 260 | #define SCIF3_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 261 | |
| mbed_official | 390:35c2c1cf29cd | 262 | /* ---- SCIF4 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 263 | #define SCIF4_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 264 | #define SCIF4_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 265 | #define SCIF4_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 266 | #define SCIF4_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 267 | #define SCIF4_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 268 | #define SCIF4_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 269 | |
| mbed_official | 390:35c2c1cf29cd | 270 | #define SCIF4_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 271 | |
| mbed_official | 390:35c2c1cf29cd | 272 | #define SCIF4_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 273 | #define SCIF4_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 274 | #define SCIF4_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 275 | #define SCIF4_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 276 | #define SCIF4_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 277 | #define SCIF4_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 278 | |
| mbed_official | 390:35c2c1cf29cd | 279 | #define SCIF4_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 280 | |
| mbed_official | 390:35c2c1cf29cd | 281 | #define SCIF4_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 282 | #define SCIF4_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 283 | #define SCIF4_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 284 | #define SCIF4_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 285 | #define SCIF4_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 286 | #define SCIF4_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 287 | #define SCIF4_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 288 | #define SCIF4_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 289 | #define SCIF4_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 290 | #define SCIF4_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 291 | |
| mbed_official | 390:35c2c1cf29cd | 292 | #define SCIF4_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 293 | |
| mbed_official | 390:35c2c1cf29cd | 294 | #define SCIF4_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 295 | #define SCIF4_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 296 | #define SCIF4_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 297 | #define SCIF4_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 298 | #define SCIF4_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 299 | #define SCIF4_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 300 | #define SCIF4_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 301 | |
| mbed_official | 390:35c2c1cf29cd | 302 | #define SCIF4_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 303 | #define SCIF4_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 304 | |
| mbed_official | 390:35c2c1cf29cd | 305 | #define SCIF4_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 306 | #define SCIF4_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 307 | #define SCIF4_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 308 | #define SCIF4_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 309 | #define SCIF4_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 310 | #define SCIF4_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 311 | #define SCIF4_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 312 | #define SCIF4_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 313 | |
| mbed_official | 390:35c2c1cf29cd | 314 | #define SCIF4_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 315 | |
| mbed_official | 390:35c2c1cf29cd | 316 | #define SCIF4_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 317 | #define SCIF4_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 318 | |
| mbed_official | 390:35c2c1cf29cd | 319 | /* ---- SCIF5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 320 | #define SCIF5_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 321 | #define SCIF5_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 322 | #define SCIF5_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 323 | #define SCIF5_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 324 | #define SCIF5_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 325 | #define SCIF5_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 326 | |
| mbed_official | 390:35c2c1cf29cd | 327 | #define SCIF5_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 328 | |
| mbed_official | 390:35c2c1cf29cd | 329 | #define SCIF5_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 330 | #define SCIF5_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 331 | #define SCIF5_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 332 | #define SCIF5_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 333 | #define SCIF5_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 334 | #define SCIF5_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 335 | |
| mbed_official | 390:35c2c1cf29cd | 336 | #define SCIF5_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 337 | |
| mbed_official | 390:35c2c1cf29cd | 338 | #define SCIF5_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 339 | #define SCIF5_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 340 | #define SCIF5_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 341 | #define SCIF5_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 342 | #define SCIF5_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 343 | #define SCIF5_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 344 | #define SCIF5_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 345 | #define SCIF5_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 346 | #define SCIF5_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 347 | #define SCIF5_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 348 | |
| mbed_official | 390:35c2c1cf29cd | 349 | #define SCIF5_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 350 | |
| mbed_official | 390:35c2c1cf29cd | 351 | #define SCIF5_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 352 | #define SCIF5_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 353 | #define SCIF5_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 354 | #define SCIF5_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 355 | #define SCIF5_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 356 | #define SCIF5_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 357 | #define SCIF5_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 358 | |
| mbed_official | 390:35c2c1cf29cd | 359 | #define SCIF5_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 360 | #define SCIF5_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 361 | |
| mbed_official | 390:35c2c1cf29cd | 362 | #define SCIF5_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 363 | #define SCIF5_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 364 | #define SCIF5_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 365 | #define SCIF5_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 366 | #define SCIF5_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 367 | #define SCIF5_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 368 | #define SCIF5_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 369 | #define SCIF5_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 370 | |
| mbed_official | 390:35c2c1cf29cd | 371 | #define SCIF5_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 372 | |
| mbed_official | 390:35c2c1cf29cd | 373 | #define SCIF5_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 374 | #define SCIF5_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 375 | |
| mbed_official | 390:35c2c1cf29cd | 376 | /* ---- SCIF6 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 377 | #define SCIF6_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 378 | #define SCIF6_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 379 | #define SCIF6_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 380 | #define SCIF6_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 381 | #define SCIF6_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 382 | #define SCIF6_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 383 | |
| mbed_official | 390:35c2c1cf29cd | 384 | #define SCIF6_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 385 | |
| mbed_official | 390:35c2c1cf29cd | 386 | #define SCIF6_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 387 | #define SCIF6_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 388 | #define SCIF6_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 389 | #define SCIF6_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 390 | #define SCIF6_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 391 | #define SCIF6_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 392 | |
| mbed_official | 390:35c2c1cf29cd | 393 | #define SCIF6_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 394 | |
| mbed_official | 390:35c2c1cf29cd | 395 | #define SCIF6_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 396 | #define SCIF6_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 397 | #define SCIF6_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 398 | #define SCIF6_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 399 | #define SCIF6_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 400 | #define SCIF6_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 401 | #define SCIF6_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 402 | #define SCIF6_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 403 | #define SCIF6_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 404 | #define SCIF6_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 405 | |
| mbed_official | 390:35c2c1cf29cd | 406 | #define SCIF6_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 407 | |
| mbed_official | 390:35c2c1cf29cd | 408 | #define SCIF6_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 409 | #define SCIF6_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 410 | #define SCIF6_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 411 | #define SCIF6_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 412 | #define SCIF6_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 413 | #define SCIF6_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 414 | #define SCIF6_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 415 | |
| mbed_official | 390:35c2c1cf29cd | 416 | #define SCIF6_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 417 | #define SCIF6_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 418 | |
| mbed_official | 390:35c2c1cf29cd | 419 | #define SCIF6_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 420 | #define SCIF6_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 421 | #define SCIF6_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 422 | #define SCIF6_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 423 | #define SCIF6_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 424 | #define SCIF6_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 425 | #define SCIF6_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 426 | #define SCIF6_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 427 | |
| mbed_official | 390:35c2c1cf29cd | 428 | #define SCIF6_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 429 | |
| mbed_official | 390:35c2c1cf29cd | 430 | #define SCIF6_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 431 | #define SCIF6_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 432 | |
| mbed_official | 390:35c2c1cf29cd | 433 | /* ---- SCIF7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 434 | #define SCIF7_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 435 | #define SCIF7_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 436 | #define SCIF7_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 437 | #define SCIF7_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 438 | #define SCIF7_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 439 | #define SCIF7_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 440 | |
| mbed_official | 390:35c2c1cf29cd | 441 | #define SCIF7_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 442 | |
| mbed_official | 390:35c2c1cf29cd | 443 | #define SCIF7_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 444 | #define SCIF7_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 445 | #define SCIF7_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 446 | #define SCIF7_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 447 | #define SCIF7_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 448 | #define SCIF7_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 449 | |
| mbed_official | 390:35c2c1cf29cd | 450 | #define SCIF7_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 451 | |
| mbed_official | 390:35c2c1cf29cd | 452 | #define SCIF7_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 453 | #define SCIF7_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 454 | #define SCIF7_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 455 | #define SCIF7_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 456 | #define SCIF7_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 457 | #define SCIF7_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 458 | #define SCIF7_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 459 | #define SCIF7_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 460 | #define SCIF7_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 461 | #define SCIF7_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 462 | |
| mbed_official | 390:35c2c1cf29cd | 463 | #define SCIF7_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 464 | |
| mbed_official | 390:35c2c1cf29cd | 465 | #define SCIF7_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 466 | #define SCIF7_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 467 | #define SCIF7_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 468 | #define SCIF7_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 469 | #define SCIF7_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 470 | #define SCIF7_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 471 | #define SCIF7_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 472 | |
| mbed_official | 390:35c2c1cf29cd | 473 | #define SCIF7_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 474 | #define SCIF7_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 475 | |
| mbed_official | 390:35c2c1cf29cd | 476 | #define SCIF7_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 477 | #define SCIF7_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 478 | #define SCIF7_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 479 | #define SCIF7_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 480 | #define SCIF7_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 481 | #define SCIF7_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 482 | #define SCIF7_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 483 | #define SCIF7_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 484 | |
| mbed_official | 390:35c2c1cf29cd | 485 | #define SCIF7_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 486 | |
| mbed_official | 390:35c2c1cf29cd | 487 | #define SCIF7_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 488 | #define SCIF7_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 489 | |
| mbed_official | 390:35c2c1cf29cd | 490 | /* ---- SCIFn ---- */ |
| mbed_official | 390:35c2c1cf29cd | 491 | #define SCIFn_SCSMR_CKS (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 492 | #define SCIFn_SCSMR_STOP (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 493 | #define SCIFn_SCSMR_OE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 494 | #define SCIFn_SCSMR_PE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 495 | #define SCIFn_SCSMR_CHR (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 496 | #define SCIFn_SCSMR_CA (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 497 | |
| mbed_official | 390:35c2c1cf29cd | 498 | #define SCIFn_SCBRR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 499 | |
| mbed_official | 390:35c2c1cf29cd | 500 | #define SCIFn_SCSCR_CKE (0x0003u) |
| mbed_official | 390:35c2c1cf29cd | 501 | #define SCIFn_SCSCR_REIE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 502 | #define SCIFn_SCSCR_RE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 503 | #define SCIFn_SCSCR_TE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 504 | #define SCIFn_SCSCR_RIE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 505 | #define SCIFn_SCSCR_TIE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 506 | |
| mbed_official | 390:35c2c1cf29cd | 507 | #define SCIFn_SCFTDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 508 | |
| mbed_official | 390:35c2c1cf29cd | 509 | #define SCIFn_SCFSR_DR (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 510 | #define SCIFn_SCFSR_RDF (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 511 | #define SCIFn_SCFSR_PER (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 512 | #define SCIFn_SCFSR_FER (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 513 | #define SCIFn_SCFSR_BRK (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 514 | #define SCIFn_SCFSR_TDFE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 515 | #define SCIFn_SCFSR_TEND (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 516 | #define SCIFn_SCFSR_ER (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 517 | #define SCIFn_SCFSR_FERN (0x0F00u) |
| mbed_official | 390:35c2c1cf29cd | 518 | #define SCIFn_SCFSR_PERN (0xF000u) |
| mbed_official | 390:35c2c1cf29cd | 519 | |
| mbed_official | 390:35c2c1cf29cd | 520 | #define SCIFn_SCFRDR_D (0xFFu) |
| mbed_official | 390:35c2c1cf29cd | 521 | |
| mbed_official | 390:35c2c1cf29cd | 522 | #define SCIFn_SCFCR_LOOP (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 523 | #define SCIFn_SCFCR_RFRST (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 524 | #define SCIFn_SCFCR_TFRST (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 525 | #define SCIFn_SCFCR_MCE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 526 | #define SCIFn_SCFCR_TTRG (0x0030u) |
| mbed_official | 390:35c2c1cf29cd | 527 | #define SCIFn_SCFCR_RTRG (0x00C0u) |
| mbed_official | 390:35c2c1cf29cd | 528 | #define SCIFn_SCFCR_RSTRG (0x0700u) |
| mbed_official | 390:35c2c1cf29cd | 529 | |
| mbed_official | 390:35c2c1cf29cd | 530 | #define SCIFn_SCFDR_R (0x001Fu) |
| mbed_official | 390:35c2c1cf29cd | 531 | #define SCIFn_SCFDR_T (0x1F00u) |
| mbed_official | 390:35c2c1cf29cd | 532 | |
| mbed_official | 390:35c2c1cf29cd | 533 | #define SCIFn_SCSPTR_SPB2DT (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 534 | #define SCIFn_SCSPTR_SPB2IO (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 535 | #define SCIFn_SCSPTR_SCKDT (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 536 | #define SCIFn_SCSPTR_SCKIO (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 537 | #define SCIFn_SCSPTR_CTSDT (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 538 | #define SCIFn_SCSPTR_CTSIO (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 539 | #define SCIFn_SCSPTR_RTSDT (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 540 | #define SCIFn_SCSPTR_RTSIO (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 541 | |
| mbed_official | 390:35c2c1cf29cd | 542 | #define SCIFn_SCLSR_ORER (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 543 | |
| mbed_official | 390:35c2c1cf29cd | 544 | #define SCIFn_SCEMR_ABCS (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 545 | #define SCIFn_SCEMR_BGDM (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 546 | |
| mbed_official | 390:35c2c1cf29cd | 547 | |
| mbed_official | 390:35c2c1cf29cd | 548 | /* ==== Shift values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 549 | /* ---- SCIF0 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 550 | #define SCIF0_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 551 | #define SCIF0_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 552 | #define SCIF0_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 553 | #define SCIF0_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 554 | #define SCIF0_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 555 | #define SCIF0_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 556 | |
| mbed_official | 390:35c2c1cf29cd | 557 | #define SCIF0_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 558 | |
| mbed_official | 390:35c2c1cf29cd | 559 | #define SCIF0_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 560 | #define SCIF0_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 561 | #define SCIF0_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 562 | #define SCIF0_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 563 | #define SCIF0_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 564 | #define SCIF0_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 565 | |
| mbed_official | 390:35c2c1cf29cd | 566 | #define SCIF0_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 567 | |
| mbed_official | 390:35c2c1cf29cd | 568 | #define SCIF0_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 569 | #define SCIF0_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 570 | #define SCIF0_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 571 | #define SCIF0_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 572 | #define SCIF0_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 573 | #define SCIF0_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 574 | #define SCIF0_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 575 | #define SCIF0_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 576 | #define SCIF0_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 577 | #define SCIF0_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 578 | |
| mbed_official | 390:35c2c1cf29cd | 579 | #define SCIF0_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 580 | |
| mbed_official | 390:35c2c1cf29cd | 581 | #define SCIF0_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 582 | #define SCIF0_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 583 | #define SCIF0_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 584 | #define SCIF0_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 585 | #define SCIF0_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 586 | #define SCIF0_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 587 | #define SCIF0_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 588 | |
| mbed_official | 390:35c2c1cf29cd | 589 | #define SCIF0_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 590 | #define SCIF0_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 591 | |
| mbed_official | 390:35c2c1cf29cd | 592 | #define SCIF0_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 593 | #define SCIF0_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 594 | #define SCIF0_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 595 | #define SCIF0_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 596 | #define SCIF0_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 597 | #define SCIF0_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 598 | #define SCIF0_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 599 | #define SCIF0_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 600 | |
| mbed_official | 390:35c2c1cf29cd | 601 | #define SCIF0_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 602 | |
| mbed_official | 390:35c2c1cf29cd | 603 | #define SCIF0_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 604 | #define SCIF0_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 605 | |
| mbed_official | 390:35c2c1cf29cd | 606 | /* ---- SCIF1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 607 | #define SCIF1_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 608 | #define SCIF1_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 609 | #define SCIF1_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 610 | #define SCIF1_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 611 | #define SCIF1_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 612 | #define SCIF1_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 613 | |
| mbed_official | 390:35c2c1cf29cd | 614 | #define SCIF1_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 615 | |
| mbed_official | 390:35c2c1cf29cd | 616 | #define SCIF1_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 617 | #define SCIF1_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 618 | #define SCIF1_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 619 | #define SCIF1_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 620 | #define SCIF1_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 621 | #define SCIF1_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 622 | |
| mbed_official | 390:35c2c1cf29cd | 623 | #define SCIF1_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 624 | |
| mbed_official | 390:35c2c1cf29cd | 625 | #define SCIF1_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 626 | #define SCIF1_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 627 | #define SCIF1_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 628 | #define SCIF1_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 629 | #define SCIF1_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 630 | #define SCIF1_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 631 | #define SCIF1_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 632 | #define SCIF1_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 633 | #define SCIF1_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 634 | #define SCIF1_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 635 | |
| mbed_official | 390:35c2c1cf29cd | 636 | #define SCIF1_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 637 | |
| mbed_official | 390:35c2c1cf29cd | 638 | #define SCIF1_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 639 | #define SCIF1_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 640 | #define SCIF1_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 641 | #define SCIF1_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 642 | #define SCIF1_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 643 | #define SCIF1_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 644 | #define SCIF1_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 645 | |
| mbed_official | 390:35c2c1cf29cd | 646 | #define SCIF1_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 647 | #define SCIF1_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 648 | |
| mbed_official | 390:35c2c1cf29cd | 649 | #define SCIF1_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 650 | #define SCIF1_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 651 | #define SCIF1_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 652 | #define SCIF1_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 653 | #define SCIF1_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 654 | #define SCIF1_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 655 | #define SCIF1_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 656 | #define SCIF1_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 657 | |
| mbed_official | 390:35c2c1cf29cd | 658 | #define SCIF1_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 659 | |
| mbed_official | 390:35c2c1cf29cd | 660 | #define SCIF1_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 661 | #define SCIF1_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 662 | |
| mbed_official | 390:35c2c1cf29cd | 663 | /* ---- SCIF2 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 664 | #define SCIF2_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 665 | #define SCIF2_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 666 | #define SCIF2_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 667 | #define SCIF2_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 668 | #define SCIF2_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 669 | #define SCIF2_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 670 | |
| mbed_official | 390:35c2c1cf29cd | 671 | #define SCIF2_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 672 | |
| mbed_official | 390:35c2c1cf29cd | 673 | #define SCIF2_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 674 | #define SCIF2_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 675 | #define SCIF2_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 676 | #define SCIF2_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 677 | #define SCIF2_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 678 | #define SCIF2_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 679 | |
| mbed_official | 390:35c2c1cf29cd | 680 | #define SCIF2_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 681 | |
| mbed_official | 390:35c2c1cf29cd | 682 | #define SCIF2_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 683 | #define SCIF2_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 684 | #define SCIF2_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 685 | #define SCIF2_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 686 | #define SCIF2_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 687 | #define SCIF2_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 688 | #define SCIF2_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 689 | #define SCIF2_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 690 | #define SCIF2_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 691 | #define SCIF2_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 692 | |
| mbed_official | 390:35c2c1cf29cd | 693 | #define SCIF2_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 694 | |
| mbed_official | 390:35c2c1cf29cd | 695 | #define SCIF2_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 696 | #define SCIF2_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 697 | #define SCIF2_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 698 | #define SCIF2_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 699 | #define SCIF2_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 700 | #define SCIF2_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 701 | #define SCIF2_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 702 | |
| mbed_official | 390:35c2c1cf29cd | 703 | #define SCIF2_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 704 | #define SCIF2_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 705 | |
| mbed_official | 390:35c2c1cf29cd | 706 | #define SCIF2_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 707 | #define SCIF2_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 708 | #define SCIF2_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 709 | #define SCIF2_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 710 | #define SCIF2_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 711 | #define SCIF2_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 712 | #define SCIF2_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 713 | #define SCIF2_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 714 | |
| mbed_official | 390:35c2c1cf29cd | 715 | #define SCIF2_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 716 | |
| mbed_official | 390:35c2c1cf29cd | 717 | #define SCIF2_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 718 | #define SCIF2_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 719 | |
| mbed_official | 390:35c2c1cf29cd | 720 | /* ---- SCIF3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 721 | #define SCIF3_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 722 | #define SCIF3_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 723 | #define SCIF3_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 724 | #define SCIF3_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 725 | #define SCIF3_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 726 | #define SCIF3_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 727 | |
| mbed_official | 390:35c2c1cf29cd | 728 | #define SCIF3_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 729 | |
| mbed_official | 390:35c2c1cf29cd | 730 | #define SCIF3_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 731 | #define SCIF3_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 732 | #define SCIF3_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 733 | #define SCIF3_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 734 | #define SCIF3_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 735 | #define SCIF3_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 736 | |
| mbed_official | 390:35c2c1cf29cd | 737 | #define SCIF3_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 738 | |
| mbed_official | 390:35c2c1cf29cd | 739 | #define SCIF3_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 740 | #define SCIF3_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 741 | #define SCIF3_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 742 | #define SCIF3_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 743 | #define SCIF3_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 744 | #define SCIF3_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 745 | #define SCIF3_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 746 | #define SCIF3_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 747 | #define SCIF3_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 748 | #define SCIF3_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 749 | |
| mbed_official | 390:35c2c1cf29cd | 750 | #define SCIF3_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 751 | |
| mbed_official | 390:35c2c1cf29cd | 752 | #define SCIF3_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 753 | #define SCIF3_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 754 | #define SCIF3_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 755 | #define SCIF3_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 756 | #define SCIF3_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 757 | #define SCIF3_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 758 | #define SCIF3_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 759 | |
| mbed_official | 390:35c2c1cf29cd | 760 | #define SCIF3_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 761 | #define SCIF3_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 762 | |
| mbed_official | 390:35c2c1cf29cd | 763 | #define SCIF3_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 764 | #define SCIF3_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 765 | #define SCIF3_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 766 | #define SCIF3_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 767 | #define SCIF3_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 768 | #define SCIF3_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 769 | #define SCIF3_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 770 | #define SCIF3_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 771 | |
| mbed_official | 390:35c2c1cf29cd | 772 | #define SCIF3_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 773 | |
| mbed_official | 390:35c2c1cf29cd | 774 | #define SCIF3_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 775 | #define SCIF3_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 776 | |
| mbed_official | 390:35c2c1cf29cd | 777 | /* ---- SCIF4 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 778 | #define SCIF4_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 779 | #define SCIF4_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 780 | #define SCIF4_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 781 | #define SCIF4_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 782 | #define SCIF4_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 783 | #define SCIF4_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 784 | |
| mbed_official | 390:35c2c1cf29cd | 785 | #define SCIF4_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 786 | |
| mbed_official | 390:35c2c1cf29cd | 787 | #define SCIF4_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 788 | #define SCIF4_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 789 | #define SCIF4_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 790 | #define SCIF4_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 791 | #define SCIF4_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 792 | #define SCIF4_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 793 | |
| mbed_official | 390:35c2c1cf29cd | 794 | #define SCIF4_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 795 | |
| mbed_official | 390:35c2c1cf29cd | 796 | #define SCIF4_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 797 | #define SCIF4_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 798 | #define SCIF4_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 799 | #define SCIF4_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 800 | #define SCIF4_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 801 | #define SCIF4_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 802 | #define SCIF4_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 803 | #define SCIF4_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 804 | #define SCIF4_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 805 | #define SCIF4_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 806 | |
| mbed_official | 390:35c2c1cf29cd | 807 | #define SCIF4_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 808 | |
| mbed_official | 390:35c2c1cf29cd | 809 | #define SCIF4_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 810 | #define SCIF4_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 811 | #define SCIF4_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 812 | #define SCIF4_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 813 | #define SCIF4_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 814 | #define SCIF4_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 815 | #define SCIF4_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 816 | |
| mbed_official | 390:35c2c1cf29cd | 817 | #define SCIF4_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 818 | #define SCIF4_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 819 | |
| mbed_official | 390:35c2c1cf29cd | 820 | #define SCIF4_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 821 | #define SCIF4_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 822 | #define SCIF4_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 823 | #define SCIF4_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 824 | #define SCIF4_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 825 | #define SCIF4_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 826 | #define SCIF4_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 827 | #define SCIF4_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 828 | |
| mbed_official | 390:35c2c1cf29cd | 829 | #define SCIF4_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 830 | |
| mbed_official | 390:35c2c1cf29cd | 831 | #define SCIF4_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 832 | #define SCIF4_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 833 | |
| mbed_official | 390:35c2c1cf29cd | 834 | /* ---- SCIF5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 835 | #define SCIF5_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 836 | #define SCIF5_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 837 | #define SCIF5_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 838 | #define SCIF5_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 839 | #define SCIF5_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 840 | #define SCIF5_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 841 | |
| mbed_official | 390:35c2c1cf29cd | 842 | #define SCIF5_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 843 | |
| mbed_official | 390:35c2c1cf29cd | 844 | #define SCIF5_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 845 | #define SCIF5_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 846 | #define SCIF5_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 847 | #define SCIF5_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 848 | #define SCIF5_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 849 | #define SCIF5_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 850 | |
| mbed_official | 390:35c2c1cf29cd | 851 | #define SCIF5_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 852 | |
| mbed_official | 390:35c2c1cf29cd | 853 | #define SCIF5_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 854 | #define SCIF5_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 855 | #define SCIF5_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 856 | #define SCIF5_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 857 | #define SCIF5_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 858 | #define SCIF5_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 859 | #define SCIF5_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 860 | #define SCIF5_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 861 | #define SCIF5_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 862 | #define SCIF5_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 863 | |
| mbed_official | 390:35c2c1cf29cd | 864 | #define SCIF5_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 865 | |
| mbed_official | 390:35c2c1cf29cd | 866 | #define SCIF5_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 867 | #define SCIF5_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 868 | #define SCIF5_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 869 | #define SCIF5_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 870 | #define SCIF5_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 871 | #define SCIF5_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 872 | #define SCIF5_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 873 | |
| mbed_official | 390:35c2c1cf29cd | 874 | #define SCIF5_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 875 | #define SCIF5_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 876 | |
| mbed_official | 390:35c2c1cf29cd | 877 | #define SCIF5_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 878 | #define SCIF5_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 879 | #define SCIF5_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 880 | #define SCIF5_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 881 | #define SCIF5_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 882 | #define SCIF5_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 883 | #define SCIF5_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 884 | #define SCIF5_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 885 | |
| mbed_official | 390:35c2c1cf29cd | 886 | #define SCIF5_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 887 | |
| mbed_official | 390:35c2c1cf29cd | 888 | #define SCIF5_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 889 | #define SCIF5_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 890 | |
| mbed_official | 390:35c2c1cf29cd | 891 | /* ---- SCIF6 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 892 | #define SCIF6_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 893 | #define SCIF6_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 894 | #define SCIF6_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 895 | #define SCIF6_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 896 | #define SCIF6_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 897 | #define SCIF6_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 898 | |
| mbed_official | 390:35c2c1cf29cd | 899 | #define SCIF6_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 900 | |
| mbed_official | 390:35c2c1cf29cd | 901 | #define SCIF6_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 902 | #define SCIF6_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 903 | #define SCIF6_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 904 | #define SCIF6_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 905 | #define SCIF6_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 906 | #define SCIF6_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 907 | |
| mbed_official | 390:35c2c1cf29cd | 908 | #define SCIF6_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 909 | |
| mbed_official | 390:35c2c1cf29cd | 910 | #define SCIF6_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 911 | #define SCIF6_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 912 | #define SCIF6_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 913 | #define SCIF6_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 914 | #define SCIF6_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 915 | #define SCIF6_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 916 | #define SCIF6_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 917 | #define SCIF6_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 918 | #define SCIF6_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 919 | #define SCIF6_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 920 | |
| mbed_official | 390:35c2c1cf29cd | 921 | #define SCIF6_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 922 | |
| mbed_official | 390:35c2c1cf29cd | 923 | #define SCIF6_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 924 | #define SCIF6_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 925 | #define SCIF6_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 926 | #define SCIF6_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 927 | #define SCIF6_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 928 | #define SCIF6_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 929 | #define SCIF6_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 930 | |
| mbed_official | 390:35c2c1cf29cd | 931 | #define SCIF6_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 932 | #define SCIF6_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 933 | |
| mbed_official | 390:35c2c1cf29cd | 934 | #define SCIF6_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 935 | #define SCIF6_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 936 | #define SCIF6_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 937 | #define SCIF6_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 938 | #define SCIF6_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 939 | #define SCIF6_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 940 | #define SCIF6_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 941 | #define SCIF6_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 942 | |
| mbed_official | 390:35c2c1cf29cd | 943 | #define SCIF6_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 944 | |
| mbed_official | 390:35c2c1cf29cd | 945 | #define SCIF6_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 946 | #define SCIF6_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 947 | |
| mbed_official | 390:35c2c1cf29cd | 948 | /* ---- SCIF7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 949 | #define SCIF7_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 950 | #define SCIF7_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 951 | #define SCIF7_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 952 | #define SCIF7_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 953 | #define SCIF7_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 954 | #define SCIF7_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 955 | |
| mbed_official | 390:35c2c1cf29cd | 956 | #define SCIF7_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 957 | |
| mbed_official | 390:35c2c1cf29cd | 958 | #define SCIF7_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 959 | #define SCIF7_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 960 | #define SCIF7_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 961 | #define SCIF7_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 962 | #define SCIF7_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 963 | #define SCIF7_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 964 | |
| mbed_official | 390:35c2c1cf29cd | 965 | #define SCIF7_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 966 | |
| mbed_official | 390:35c2c1cf29cd | 967 | #define SCIF7_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 968 | #define SCIF7_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 969 | #define SCIF7_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 970 | #define SCIF7_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 971 | #define SCIF7_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 972 | #define SCIF7_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 973 | #define SCIF7_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 974 | #define SCIF7_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 975 | #define SCIF7_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 976 | #define SCIF7_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 977 | |
| mbed_official | 390:35c2c1cf29cd | 978 | #define SCIF7_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 979 | |
| mbed_official | 390:35c2c1cf29cd | 980 | #define SCIF7_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 981 | #define SCIF7_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 982 | #define SCIF7_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 983 | #define SCIF7_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 984 | #define SCIF7_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 985 | #define SCIF7_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 986 | #define SCIF7_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 987 | |
| mbed_official | 390:35c2c1cf29cd | 988 | #define SCIF7_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 989 | #define SCIF7_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 990 | |
| mbed_official | 390:35c2c1cf29cd | 991 | #define SCIF7_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 992 | #define SCIF7_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 993 | #define SCIF7_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 994 | #define SCIF7_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 995 | #define SCIF7_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 996 | #define SCIF7_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 997 | #define SCIF7_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 998 | #define SCIF7_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 999 | |
| mbed_official | 390:35c2c1cf29cd | 1000 | #define SCIF7_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1001 | |
| mbed_official | 390:35c2c1cf29cd | 1002 | #define SCIF7_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1003 | #define SCIF7_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1004 | |
| mbed_official | 390:35c2c1cf29cd | 1005 | /* ---- SCIFn ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1006 | #define SCIFn_SCSMR_CKS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1007 | #define SCIFn_SCSMR_STOP_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1008 | #define SCIFn_SCSMR_OE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1009 | #define SCIFn_SCSMR_PE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1010 | #define SCIFn_SCSMR_CHR_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1011 | #define SCIFn_SCSMR_CA_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1012 | |
| mbed_official | 390:35c2c1cf29cd | 1013 | #define SCIFn_SCBRR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1014 | |
| mbed_official | 390:35c2c1cf29cd | 1015 | #define SCIFn_SCSCR_CKE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1016 | #define SCIFn_SCSCR_REIE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1017 | #define SCIFn_SCSCR_RE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1018 | #define SCIFn_SCSCR_TE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1019 | #define SCIFn_SCSCR_RIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1020 | #define SCIFn_SCSCR_TIE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1021 | |
| mbed_official | 390:35c2c1cf29cd | 1022 | #define SCIFn_SCFTDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1023 | |
| mbed_official | 390:35c2c1cf29cd | 1024 | #define SCIFn_SCFSR_DR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1025 | #define SCIFn_SCFSR_RDF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1026 | #define SCIFn_SCFSR_PER_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1027 | #define SCIFn_SCFSR_FER_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1028 | #define SCIFn_SCFSR_BRK_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1029 | #define SCIFn_SCFSR_TDFE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1030 | #define SCIFn_SCFSR_TEND_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1031 | #define SCIFn_SCFSR_ER_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1032 | #define SCIFn_SCFSR_FERN_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1033 | #define SCIFn_SCFSR_PERN_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1034 | |
| mbed_official | 390:35c2c1cf29cd | 1035 | #define SCIFn_SCFRDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1036 | |
| mbed_official | 390:35c2c1cf29cd | 1037 | #define SCIFn_SCFCR_LOOP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1038 | #define SCIFn_SCFCR_RFRST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1039 | #define SCIFn_SCFCR_TFRST_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1040 | #define SCIFn_SCFCR_MCE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1041 | #define SCIFn_SCFCR_TTRG_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1042 | #define SCIFn_SCFCR_RTRG_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1043 | #define SCIFn_SCFCR_RSTRG_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1044 | |
| mbed_official | 390:35c2c1cf29cd | 1045 | #define SCIFn_SCFDR_R_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1046 | #define SCIFn_SCFDR_T_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1047 | |
| mbed_official | 390:35c2c1cf29cd | 1048 | #define SCIFn_SCSPTR_SPB2DT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1049 | #define SCIFn_SCSPTR_SPB2IO_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1050 | #define SCIFn_SCSPTR_SCKDT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1051 | #define SCIFn_SCSPTR_SCKIO_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1052 | #define SCIFn_SCSPTR_CTSDT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1053 | #define SCIFn_SCSPTR_CTSIO_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1054 | #define SCIFn_SCSPTR_RTSDT_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1055 | #define SCIFn_SCSPTR_RTSIO_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1056 | |
| mbed_official | 390:35c2c1cf29cd | 1057 | #define SCIFn_SCLSR_ORER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1058 | |
| mbed_official | 390:35c2c1cf29cd | 1059 | #define SCIFn_SCEMR_ABCS_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1060 | #define SCIFn_SCEMR_BGDM_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1061 | |
| mbed_official | 390:35c2c1cf29cd | 1062 | |
| mbed_official | 390:35c2c1cf29cd | 1063 | #endif /* SCIF_IOBITMASK_H */ |
| mbed_official | 390:35c2c1cf29cd | 1064 | |
| mbed_official | 390:35c2c1cf29cd | 1065 | /* End of File */ |
