Stuart Northfield
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h@390:35c2c1cf29cd, 2014-11-06 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Nov 06 11:00:10 2014 +0000
- Revision:
- 390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7
Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/
[RZ/A1H] mbed-RZ first release
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : mtu2_iobitmask.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: 1138 $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: 2014-08-08 11:03:56 +0900#$ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : MTU2 register define header |
| mbed_official | 390:35c2c1cf29cd | 28 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef MTU2_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define MTU2_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 31 | |
| mbed_official | 390:35c2c1cf29cd | 32 | |
| mbed_official | 390:35c2c1cf29cd | 33 | /* ==== Mask values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 34 | #define MTU2_TCR_n_TPSC (0x07u) |
| mbed_official | 390:35c2c1cf29cd | 35 | #define MTU2_TCR_n_CKEG (0x18u) |
| mbed_official | 390:35c2c1cf29cd | 36 | #define MTU2_TCR_n_CCLR (0xE0u) |
| mbed_official | 390:35c2c1cf29cd | 37 | |
| mbed_official | 390:35c2c1cf29cd | 38 | #define MTU2_TMDR_n_MD (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 39 | |
| mbed_official | 390:35c2c1cf29cd | 40 | #define MTU2_TIOR_2_IOA (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 41 | #define MTU2_TIOR_2_IOB (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 42 | |
| mbed_official | 390:35c2c1cf29cd | 43 | #define MTU2_TIER_n_TGIEA (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 44 | #define MTU2_TIER_n_TGIEB (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 45 | #define MTU2_TIER_n_TCIEV (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 46 | #define MTU2_TIER_2_TCIEU (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 47 | #define MTU2_TIER_n_TTGE (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 48 | |
| mbed_official | 390:35c2c1cf29cd | 49 | #define MTU2_TSR_n_TGFA (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 50 | #define MTU2_TSR_n_TGFB (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 51 | #define MTU2_TSR_n_TCFV (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 52 | #define MTU2_TSR_2_TCFU (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 53 | #define MTU2_TSR_2_TCFD (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 54 | |
| mbed_official | 390:35c2c1cf29cd | 55 | #define MTU2_TCNT_n_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 56 | |
| mbed_official | 390:35c2c1cf29cd | 57 | #define MTU2_TGRA_n_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 58 | |
| mbed_official | 390:35c2c1cf29cd | 59 | #define MTU2_TGRB_n_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 60 | |
| mbed_official | 390:35c2c1cf29cd | 61 | #define MTU2_TMDR_3_BFA (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 62 | #define MTU2_TMDR_3_BFB (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 63 | |
| mbed_official | 390:35c2c1cf29cd | 64 | #define MTU2_TMDR_4_BFA (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 65 | #define MTU2_TMDR_4_BFB (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 66 | |
| mbed_official | 390:35c2c1cf29cd | 67 | #define MTU2_TIORH_3_IOA (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 68 | #define MTU2_TIORH_3_IOB (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 69 | |
| mbed_official | 390:35c2c1cf29cd | 70 | #define MTU2_TIORL_3_IOC (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 71 | #define MTU2_TIORL_3_IOD (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 72 | |
| mbed_official | 390:35c2c1cf29cd | 73 | #define MTU2_TIORH_4_IOA (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 74 | #define MTU2_TIORH_4_IOB (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 75 | |
| mbed_official | 390:35c2c1cf29cd | 76 | #define MTU2_TIORL_4_IOC (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 77 | #define MTU2_TIORL_4_IOD (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 78 | |
| mbed_official | 390:35c2c1cf29cd | 79 | #define MTU2_TIER_3_TGIEC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 80 | #define MTU2_TIER_3_TGIED (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 81 | |
| mbed_official | 390:35c2c1cf29cd | 82 | #define MTU2_TIER_4_TGIEC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 83 | #define MTU2_TIER_4_TGIED (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 84 | #define MTU2_TIER_4_TTGE2 (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 85 | |
| mbed_official | 390:35c2c1cf29cd | 86 | #define MTU2_TOER_OE3B (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 87 | #define MTU2_TOER_OE4A (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 88 | #define MTU2_TOER_OE4B (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 89 | #define MTU2_TOER_OE3D (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 90 | #define MTU2_TOER_OE4C (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 91 | #define MTU2_TOER_OE4D (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 92 | |
| mbed_official | 390:35c2c1cf29cd | 93 | #define MTU2_TGCR_UF (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 94 | #define MTU2_TGCR_VF (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 95 | #define MTU2_TGCR_WF (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 96 | #define MTU2_TGCR_FB (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 97 | #define MTU2_TGCR_P (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 98 | #define MTU2_TGCR_N (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 99 | #define MTU2_TGCR_BDC (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 100 | |
| mbed_official | 390:35c2c1cf29cd | 101 | #define MTU2_TOCR1_OLSP (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 102 | #define MTU2_TOCR1_OLSN (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 103 | #define MTU2_TOCR1_TOCS (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 104 | #define MTU2_TOCR1_TOCL (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 105 | #define MTU2_TOCR1_PSYE (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 106 | |
| mbed_official | 390:35c2c1cf29cd | 107 | #define MTU2_TOCR2_OLS1P (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 108 | #define MTU2_TOCR2_OLS1N (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 109 | #define MTU2_TOCR2_OLS2P (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 110 | #define MTU2_TOCR2_OLS2N (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 111 | #define MTU2_TOCR2_OLS3P (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 112 | #define MTU2_TOCR2_OLS3N (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 113 | #define MTU2_TOCR2_BF (0xC0u) |
| mbed_official | 390:35c2c1cf29cd | 114 | |
| mbed_official | 390:35c2c1cf29cd | 115 | #define MTU2_TCDR_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 116 | |
| mbed_official | 390:35c2c1cf29cd | 117 | #define MTU2_TDDR_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 118 | |
| mbed_official | 390:35c2c1cf29cd | 119 | #define MTU2_TCNTS_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 120 | |
| mbed_official | 390:35c2c1cf29cd | 121 | #define MTU2_TCBR_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 122 | |
| mbed_official | 390:35c2c1cf29cd | 123 | #define MTU2_TGRC_3_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 124 | |
| mbed_official | 390:35c2c1cf29cd | 125 | #define MTU2_TGRD_3_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 126 | |
| mbed_official | 390:35c2c1cf29cd | 127 | #define MTU2_TGRC_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 128 | |
| mbed_official | 390:35c2c1cf29cd | 129 | #define MTU2_TGRD_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 130 | |
| mbed_official | 390:35c2c1cf29cd | 131 | #define MTU2_TSR_3_TGFC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 132 | #define MTU2_TSR_3_TGFD (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 133 | #define MTU2_TSR_3_TCFD (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 134 | |
| mbed_official | 390:35c2c1cf29cd | 135 | #define MTU2_TSR_4_TGFC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 136 | #define MTU2_TSR_4_TGFD (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 137 | #define MTU2_TSR_4_TCFD (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 138 | |
| mbed_official | 390:35c2c1cf29cd | 139 | #define MTU2_TITCR_4VCOR (0x07u) |
| mbed_official | 390:35c2c1cf29cd | 140 | #define MTU2_TITCR_T4VEN (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 141 | #define MTU2_TITCR_3ACOR (0x70u) |
| mbed_official | 390:35c2c1cf29cd | 142 | #define MTU2_TITCR_T3AEN (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 143 | |
| mbed_official | 390:35c2c1cf29cd | 144 | #define MTU2_TITCNT_4VCNT (0x07u) |
| mbed_official | 390:35c2c1cf29cd | 145 | #define MTU2_TITCNT_3ACNT (0x70u) |
| mbed_official | 390:35c2c1cf29cd | 146 | |
| mbed_official | 390:35c2c1cf29cd | 147 | #define MTU2_TBTER_BTE (0x03u) |
| mbed_official | 390:35c2c1cf29cd | 148 | |
| mbed_official | 390:35c2c1cf29cd | 149 | #define MTU2_TDER_TDER (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 150 | |
| mbed_official | 390:35c2c1cf29cd | 151 | #define MTU2_TOLBR_OLS1P (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 152 | #define MTU2_TOLBR_OLS1N (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 153 | #define MTU2_TOLBR_OLS2P (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 154 | #define MTU2_TOLBR_OLS2N (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 155 | #define MTU2_TOLBR_OLS3P (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 156 | #define MTU2_TOLBR_OLS3N (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 157 | |
| mbed_official | 390:35c2c1cf29cd | 158 | #define MTU2_TBTM_3_TTSA (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 159 | #define MTU2_TBTM_3_TTSB (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 160 | |
| mbed_official | 390:35c2c1cf29cd | 161 | #define MTU2_TBTM_4_TTSA (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 162 | #define MTU2_TBTM_4_TTSB (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 163 | |
| mbed_official | 390:35c2c1cf29cd | 164 | #define MTU2_TADCR_ITB4VE (0x0001u) |
| mbed_official | 390:35c2c1cf29cd | 165 | #define MTU2_TADCR_ITB3AE (0x0002u) |
| mbed_official | 390:35c2c1cf29cd | 166 | #define MTU2_TADCR_ITA4VE (0x0004u) |
| mbed_official | 390:35c2c1cf29cd | 167 | #define MTU2_TADCR_ITA3AE (0x0008u) |
| mbed_official | 390:35c2c1cf29cd | 168 | #define MTU2_TADCR_DT4BE (0x0010u) |
| mbed_official | 390:35c2c1cf29cd | 169 | #define MTU2_TADCR_UT4BE (0x0020u) |
| mbed_official | 390:35c2c1cf29cd | 170 | #define MTU2_TADCR_DT4AE (0x0040u) |
| mbed_official | 390:35c2c1cf29cd | 171 | #define MTU2_TADCR_UT4AE (0x0080u) |
| mbed_official | 390:35c2c1cf29cd | 172 | #define MTU2_TADCR_BF (0xC000u) |
| mbed_official | 390:35c2c1cf29cd | 173 | |
| mbed_official | 390:35c2c1cf29cd | 174 | #define MTU2_TADCORA_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 175 | |
| mbed_official | 390:35c2c1cf29cd | 176 | #define MTU2_TADCORB_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 177 | |
| mbed_official | 390:35c2c1cf29cd | 178 | #define MTU2_TADCOBRA_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 179 | |
| mbed_official | 390:35c2c1cf29cd | 180 | #define MTU2_TADCOBRB_4_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 181 | |
| mbed_official | 390:35c2c1cf29cd | 182 | #define MTU2_TWCR_WRE (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 183 | #define MTU2_TWCR_CCE (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 184 | |
| mbed_official | 390:35c2c1cf29cd | 185 | #define MTU2_TSTR_CST0 (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 186 | #define MTU2_TSTR_CST1 (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 187 | #define MTU2_TSTR_CST2 (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 188 | #define MTU2_TSTR_CST3 (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 189 | #define MTU2_TSTR_CST4 (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 190 | |
| mbed_official | 390:35c2c1cf29cd | 191 | #define MTU2_TSYR_SYNC0 (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 192 | #define MTU2_TSYR_SYNC1 (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 193 | #define MTU2_TSYR_SYNC2 (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 194 | #define MTU2_TSYR_SYNC3 (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 195 | #define MTU2_TSYR_SYNC4 (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 196 | |
| mbed_official | 390:35c2c1cf29cd | 197 | #define MTU2_TRWER_RWE (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 198 | |
| mbed_official | 390:35c2c1cf29cd | 199 | #define MTU2_TMDR_0_BFA (0x10u) |
| mbed_official | 390:35c2c1cf29cd | 200 | #define MTU2_TMDR_0_BFB (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 201 | #define MTU2_TMDR_0_BFE (0x40u) |
| mbed_official | 390:35c2c1cf29cd | 202 | |
| mbed_official | 390:35c2c1cf29cd | 203 | #define MTU2_TIORH_0_IOA (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 204 | #define MTU2_TIORH_0_IOB (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 205 | |
| mbed_official | 390:35c2c1cf29cd | 206 | #define MTU2_TIORL_0_IOC (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 207 | #define MTU2_TIORL_0_IOD (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 208 | |
| mbed_official | 390:35c2c1cf29cd | 209 | #define MTU2_TIER_0_TGIEC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 210 | #define MTU2_TIER_0_TGIED (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 211 | |
| mbed_official | 390:35c2c1cf29cd | 212 | #define MTU2_TSR_0_TGFC (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 213 | #define MTU2_TSR_0_TGFD (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 214 | |
| mbed_official | 390:35c2c1cf29cd | 215 | #define MTU2_TGRC_0_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 216 | |
| mbed_official | 390:35c2c1cf29cd | 217 | #define MTU2_TGRD_0_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 218 | |
| mbed_official | 390:35c2c1cf29cd | 219 | #define MTU2_TGRE_0_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 220 | |
| mbed_official | 390:35c2c1cf29cd | 221 | #define MTU2_TGRF_0_D (0xFFFFu) |
| mbed_official | 390:35c2c1cf29cd | 222 | |
| mbed_official | 390:35c2c1cf29cd | 223 | #define MTU2_TIER2_0_TGIEE (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 224 | #define MTU2_TIER2_0_TGIEF (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 225 | |
| mbed_official | 390:35c2c1cf29cd | 226 | #define MTU2_TSR2_0_TGFE (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 227 | #define MTU2_TSR2_0_TGFF (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 228 | |
| mbed_official | 390:35c2c1cf29cd | 229 | #define MTU2_TBTM_0_TTSA (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 230 | #define MTU2_TBTM_0_TTSB (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 231 | #define MTU2_TBTM_0_TTSE (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 232 | |
| mbed_official | 390:35c2c1cf29cd | 233 | #define MTU2_TIOR_1_IOA (0x0Fu) |
| mbed_official | 390:35c2c1cf29cd | 234 | #define MTU2_TIOR_1_IOB (0xF0u) |
| mbed_official | 390:35c2c1cf29cd | 235 | |
| mbed_official | 390:35c2c1cf29cd | 236 | #define MTU2_TIER_1_TCIEU (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 237 | |
| mbed_official | 390:35c2c1cf29cd | 238 | #define MTU2_TSR_1_TCFU (0x20u) |
| mbed_official | 390:35c2c1cf29cd | 239 | #define MTU2_TSR_1_TCFD (0x80u) |
| mbed_official | 390:35c2c1cf29cd | 240 | |
| mbed_official | 390:35c2c1cf29cd | 241 | #define MTU2_TICCR_I1AE (0x01u) |
| mbed_official | 390:35c2c1cf29cd | 242 | #define MTU2_TICCR_I1BE (0x02u) |
| mbed_official | 390:35c2c1cf29cd | 243 | #define MTU2_TICCR_I2AE (0x04u) |
| mbed_official | 390:35c2c1cf29cd | 244 | #define MTU2_TICCR_I2BE (0x08u) |
| mbed_official | 390:35c2c1cf29cd | 245 | |
| mbed_official | 390:35c2c1cf29cd | 246 | |
| mbed_official | 390:35c2c1cf29cd | 247 | /* ==== Shift values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 248 | #define MTU2_TCR_n_TPSC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 249 | #define MTU2_TCR_n_CKEG_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 250 | #define MTU2_TCR_n_CCLR_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 251 | |
| mbed_official | 390:35c2c1cf29cd | 252 | #define MTU2_TMDR_n_MD_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 253 | |
| mbed_official | 390:35c2c1cf29cd | 254 | #define MTU2_TIOR_2_IOA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 255 | #define MTU2_TIOR_2_IOB_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 256 | |
| mbed_official | 390:35c2c1cf29cd | 257 | #define MTU2_TIER_n_TGIEA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 258 | #define MTU2_TIER_n_TGIEB_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 259 | #define MTU2_TIER_n_TCIEV_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 260 | #define MTU2_TIER_2_TCIEU_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 261 | #define MTU2_TIER_n_TTGE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 262 | |
| mbed_official | 390:35c2c1cf29cd | 263 | #define MTU2_TSR_n_TGFA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 264 | #define MTU2_TSR_n_TGFB_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 265 | #define MTU2_TSR_n_TCFV_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 266 | #define MTU2_TSR_2_TCFU_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 267 | #define MTU2_TSR_2_TCFD_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 268 | |
| mbed_official | 390:35c2c1cf29cd | 269 | #define MTU2_TCNT_n_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 270 | |
| mbed_official | 390:35c2c1cf29cd | 271 | #define MTU2_TGRA_n_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 272 | |
| mbed_official | 390:35c2c1cf29cd | 273 | #define MTU2_TGRB_n_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 274 | |
| mbed_official | 390:35c2c1cf29cd | 275 | #define MTU2_TMDR_3_BFA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 276 | #define MTU2_TMDR_3_BFB_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 277 | |
| mbed_official | 390:35c2c1cf29cd | 278 | #define MTU2_TMDR_4_BFA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 279 | #define MTU2_TMDR_4_BFB_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 280 | |
| mbed_official | 390:35c2c1cf29cd | 281 | #define MTU2_TIORH_3_IOA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 282 | #define MTU2_TIORH_3_IOB_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 283 | |
| mbed_official | 390:35c2c1cf29cd | 284 | #define MTU2_TIORL_3_IOC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 285 | #define MTU2_TIORL_3_IOD_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 286 | |
| mbed_official | 390:35c2c1cf29cd | 287 | #define MTU2_TIORH_4_IOA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 288 | #define MTU2_TIORH_4_IOB_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 289 | |
| mbed_official | 390:35c2c1cf29cd | 290 | #define MTU2_TIORL_4_IOC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 291 | #define MTU2_TIORL_4_IOD_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 292 | |
| mbed_official | 390:35c2c1cf29cd | 293 | #define MTU2_TIER_3_TGIEC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 294 | #define MTU2_TIER_3_TGIED_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 295 | |
| mbed_official | 390:35c2c1cf29cd | 296 | #define MTU2_TIER_4_TGIEC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 297 | #define MTU2_TIER_4_TGIED_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 298 | #define MTU2_TIER_4_TTGE2_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 299 | |
| mbed_official | 390:35c2c1cf29cd | 300 | #define MTU2_TOER_OE3B_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 301 | #define MTU2_TOER_OE4A_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 302 | #define MTU2_TOER_OE4B_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 303 | #define MTU2_TOER_OE3D_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 304 | #define MTU2_TOER_OE4C_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 305 | #define MTU2_TOER_OE4D_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 306 | |
| mbed_official | 390:35c2c1cf29cd | 307 | #define MTU2_TGCR_UF_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 308 | #define MTU2_TGCR_VF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 309 | #define MTU2_TGCR_WF_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 310 | #define MTU2_TGCR_FB_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 311 | #define MTU2_TGCR_P_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 312 | #define MTU2_TGCR_N_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 313 | #define MTU2_TGCR_BDC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 314 | |
| mbed_official | 390:35c2c1cf29cd | 315 | #define MTU2_TOCR1_OLSP_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 316 | #define MTU2_TOCR1_OLSN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 317 | #define MTU2_TOCR1_TOCS_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 318 | #define MTU2_TOCR1_TOCL_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 319 | #define MTU2_TOCR1_PSYE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 320 | |
| mbed_official | 390:35c2c1cf29cd | 321 | #define MTU2_TOCR2_OLS1P_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 322 | #define MTU2_TOCR2_OLS1N_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 323 | #define MTU2_TOCR2_OLS2P_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 324 | #define MTU2_TOCR2_OLS2N_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 325 | #define MTU2_TOCR2_OLS3P_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 326 | #define MTU2_TOCR2_OLS3N_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 327 | #define MTU2_TOCR2_BF_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 328 | |
| mbed_official | 390:35c2c1cf29cd | 329 | #define MTU2_TCDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 330 | |
| mbed_official | 390:35c2c1cf29cd | 331 | #define MTU2_TDDR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 332 | |
| mbed_official | 390:35c2c1cf29cd | 333 | #define MTU2_TCNTS_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 334 | |
| mbed_official | 390:35c2c1cf29cd | 335 | #define MTU2_TCBR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 336 | |
| mbed_official | 390:35c2c1cf29cd | 337 | #define MTU2_TGRC_3_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 338 | |
| mbed_official | 390:35c2c1cf29cd | 339 | #define MTU2_TGRD_3_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 340 | |
| mbed_official | 390:35c2c1cf29cd | 341 | #define MTU2_TGRC_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 342 | |
| mbed_official | 390:35c2c1cf29cd | 343 | #define MTU2_TGRD_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 344 | |
| mbed_official | 390:35c2c1cf29cd | 345 | #define MTU2_TSR_3_TGFC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 346 | #define MTU2_TSR_3_TGFD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 347 | #define MTU2_TSR_3_TCFD_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 348 | |
| mbed_official | 390:35c2c1cf29cd | 349 | #define MTU2_TSR_4_TGFC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 350 | #define MTU2_TSR_4_TGFD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 351 | #define MTU2_TSR_4_TCFD_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 352 | |
| mbed_official | 390:35c2c1cf29cd | 353 | #define MTU2_TITCR_4VCOR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 354 | #define MTU2_TITCR_T4VEN_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 355 | #define MTU2_TITCR_3ACOR_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 356 | #define MTU2_TITCR_T3AEN_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 357 | |
| mbed_official | 390:35c2c1cf29cd | 358 | #define MTU2_TITCNT_4VCNT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 359 | #define MTU2_TITCNT_3ACNT_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 360 | |
| mbed_official | 390:35c2c1cf29cd | 361 | #define MTU2_TBTER_BTE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 362 | |
| mbed_official | 390:35c2c1cf29cd | 363 | #define MTU2_TDER_TDER_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 364 | |
| mbed_official | 390:35c2c1cf29cd | 365 | #define MTU2_TOLBR_OLS1P_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 366 | #define MTU2_TOLBR_OLS1N_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 367 | #define MTU2_TOLBR_OLS2P_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 368 | #define MTU2_TOLBR_OLS2N_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 369 | #define MTU2_TOLBR_OLS3P_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 370 | #define MTU2_TOLBR_OLS3N_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 371 | |
| mbed_official | 390:35c2c1cf29cd | 372 | #define MTU2_TBTM_3_TTSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 373 | #define MTU2_TBTM_3_TTSB_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 374 | |
| mbed_official | 390:35c2c1cf29cd | 375 | #define MTU2_TBTM_4_TTSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 376 | #define MTU2_TBTM_4_TTSB_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 377 | |
| mbed_official | 390:35c2c1cf29cd | 378 | #define MTU2_TADCR_ITB4VE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 379 | #define MTU2_TADCR_ITB3AE_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 380 | #define MTU2_TADCR_ITA4VE_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 381 | #define MTU2_TADCR_ITA3AE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 382 | #define MTU2_TADCR_DT4BE_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 383 | #define MTU2_TADCR_UT4BE_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 384 | #define MTU2_TADCR_DT4AE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 385 | #define MTU2_TADCR_UT4AE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 386 | #define MTU2_TADCR_BF_SHIFT (14u) |
| mbed_official | 390:35c2c1cf29cd | 387 | |
| mbed_official | 390:35c2c1cf29cd | 388 | #define MTU2_TADCORA_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 389 | |
| mbed_official | 390:35c2c1cf29cd | 390 | #define MTU2_TADCORB_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 391 | |
| mbed_official | 390:35c2c1cf29cd | 392 | #define MTU2_TADCOBRA_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 393 | |
| mbed_official | 390:35c2c1cf29cd | 394 | #define MTU2_TADCOBRB_4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 395 | |
| mbed_official | 390:35c2c1cf29cd | 396 | #define MTU2_TWCR_WRE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 397 | #define MTU2_TWCR_CCE_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 398 | |
| mbed_official | 390:35c2c1cf29cd | 399 | #define MTU2_TSTR_CST0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 400 | #define MTU2_TSTR_CST1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 401 | #define MTU2_TSTR_CST2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 402 | #define MTU2_TSTR_CST3_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 403 | #define MTU2_TSTR_CST4_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 404 | |
| mbed_official | 390:35c2c1cf29cd | 405 | #define MTU2_TSYR_SYNC0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 406 | #define MTU2_TSYR_SYNC1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 407 | #define MTU2_TSYR_SYNC2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 408 | #define MTU2_TSYR_SYNC3_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 409 | #define MTU2_TSYR_SYNC4_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 410 | |
| mbed_official | 390:35c2c1cf29cd | 411 | #define MTU2_TRWER_RWE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 412 | |
| mbed_official | 390:35c2c1cf29cd | 413 | #define MTU2_TMDR_0_BFA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 414 | #define MTU2_TMDR_0_BFB_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 415 | #define MTU2_TMDR_0_BFE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 416 | |
| mbed_official | 390:35c2c1cf29cd | 417 | #define MTU2_TIORH_0_IOA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 418 | #define MTU2_TIORH_0_IOB_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 419 | |
| mbed_official | 390:35c2c1cf29cd | 420 | #define MTU2_TIORL_0_IOC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 421 | #define MTU2_TIORL_0_IOD_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 422 | |
| mbed_official | 390:35c2c1cf29cd | 423 | #define MTU2_TIER_0_TGIEC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 424 | #define MTU2_TIER_0_TGIED_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 425 | |
| mbed_official | 390:35c2c1cf29cd | 426 | #define MTU2_TSR_0_TGFC_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 427 | #define MTU2_TSR_0_TGFD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 428 | |
| mbed_official | 390:35c2c1cf29cd | 429 | #define MTU2_TGRC_0_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 430 | |
| mbed_official | 390:35c2c1cf29cd | 431 | #define MTU2_TGRD_0_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 432 | |
| mbed_official | 390:35c2c1cf29cd | 433 | #define MTU2_TGRE_0_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 434 | |
| mbed_official | 390:35c2c1cf29cd | 435 | #define MTU2_TGRF_0_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 436 | |
| mbed_official | 390:35c2c1cf29cd | 437 | #define MTU2_TIER2_0_TGIEE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 438 | #define MTU2_TIER2_0_TGIEF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 439 | |
| mbed_official | 390:35c2c1cf29cd | 440 | #define MTU2_TSR2_0_TGFE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 441 | #define MTU2_TSR2_0_TGFF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 442 | |
| mbed_official | 390:35c2c1cf29cd | 443 | #define MTU2_TBTM_0_TTSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 444 | #define MTU2_TBTM_0_TTSB_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 445 | #define MTU2_TBTM_0_TTSE_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 446 | |
| mbed_official | 390:35c2c1cf29cd | 447 | #define MTU2_TIOR_1_IOA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 448 | #define MTU2_TIOR_1_IOB_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 449 | |
| mbed_official | 390:35c2c1cf29cd | 450 | #define MTU2_TIER_1_TCIEU_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 451 | |
| mbed_official | 390:35c2c1cf29cd | 452 | #define MTU2_TSR_1_TCFU_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 453 | #define MTU2_TSR_1_TCFD_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 454 | |
| mbed_official | 390:35c2c1cf29cd | 455 | #define MTU2_TICCR_I1AE_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 456 | #define MTU2_TICCR_I1BE_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 457 | #define MTU2_TICCR_I2AE_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 458 | #define MTU2_TICCR_I2BE_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 459 | |
| mbed_official | 390:35c2c1cf29cd | 460 | |
| mbed_official | 390:35c2c1cf29cd | 461 | #endif /* MTU2_IOBITMASK_H */ |
| mbed_official | 390:35c2c1cf29cd | 462 | /* End of File */ |
