Stuart Northfield
mbed library sources
Fork of
mbed-src
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mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h@390:35c2c1cf29cd, 2014-11-06 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Nov 06 11:00:10 2014 +0000
- Revision:
- 390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7
Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/
[RZ/A1H] mbed-RZ first release
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : dmac_iobitmask.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: 1114 $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: 2014-07-09 14:56:39 +0900#$ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : DMAC register define header |
| mbed_official | 390:35c2c1cf29cd | 28 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef DMAC_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define DMAC_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 31 | |
| mbed_official | 390:35c2c1cf29cd | 32 | |
| mbed_official | 390:35c2c1cf29cd | 33 | /* ==== Mask values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 34 | /* ---- DMAC0 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 35 | #define DMAC0_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 36 | |
| mbed_official | 390:35c2c1cf29cd | 37 | #define DMAC0_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 38 | |
| mbed_official | 390:35c2c1cf29cd | 39 | #define DMAC0_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 40 | |
| mbed_official | 390:35c2c1cf29cd | 41 | #define DMAC0_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 42 | |
| mbed_official | 390:35c2c1cf29cd | 43 | #define DMAC0_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 44 | |
| mbed_official | 390:35c2c1cf29cd | 45 | #define DMAC0_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 46 | |
| mbed_official | 390:35c2c1cf29cd | 47 | #define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 48 | |
| mbed_official | 390:35c2c1cf29cd | 49 | #define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 50 | |
| mbed_official | 390:35c2c1cf29cd | 51 | #define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 52 | |
| mbed_official | 390:35c2c1cf29cd | 53 | #define DMAC0_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 54 | #define DMAC0_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 55 | #define DMAC0_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 56 | #define DMAC0_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 57 | #define DMAC0_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 58 | #define DMAC0_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 59 | #define DMAC0_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 60 | #define DMAC0_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 61 | #define DMAC0_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 62 | #define DMAC0_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 63 | #define DMAC0_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 64 | #define DMAC0_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 65 | #define DMAC0_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 66 | |
| mbed_official | 390:35c2c1cf29cd | 67 | #define DMAC0_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 68 | #define DMAC0_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 69 | #define DMAC0_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 70 | #define DMAC0_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 71 | #define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 72 | #define DMAC0_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 73 | #define DMAC0_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 74 | #define DMAC0_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 75 | #define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 76 | #define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 77 | #define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 78 | |
| mbed_official | 390:35c2c1cf29cd | 79 | #define DMAC0_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 80 | #define DMAC0_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 81 | #define DMAC0_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 82 | #define DMAC0_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 83 | #define DMAC0_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 84 | #define DMAC0_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 85 | #define DMAC0_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 86 | #define DMAC0_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 87 | #define DMAC0_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 88 | #define DMAC0_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 89 | #define DMAC0_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 90 | #define DMAC0_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 91 | #define DMAC0_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 92 | #define DMAC0_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 93 | #define DMAC0_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 94 | #define DMAC0_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 95 | #define DMAC0_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 96 | #define DMAC0_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 97 | |
| mbed_official | 390:35c2c1cf29cd | 98 | #define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 99 | |
| mbed_official | 390:35c2c1cf29cd | 100 | #define DMAC0_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 101 | #define DMAC0_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 102 | |
| mbed_official | 390:35c2c1cf29cd | 103 | #define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 104 | |
| mbed_official | 390:35c2c1cf29cd | 105 | #define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 106 | |
| mbed_official | 390:35c2c1cf29cd | 107 | /* ---- DMAC1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 108 | #define DMAC1_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 109 | |
| mbed_official | 390:35c2c1cf29cd | 110 | #define DMAC1_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 111 | |
| mbed_official | 390:35c2c1cf29cd | 112 | #define DMAC1_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 113 | |
| mbed_official | 390:35c2c1cf29cd | 114 | #define DMAC1_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 115 | |
| mbed_official | 390:35c2c1cf29cd | 116 | #define DMAC1_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 117 | |
| mbed_official | 390:35c2c1cf29cd | 118 | #define DMAC1_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 119 | |
| mbed_official | 390:35c2c1cf29cd | 120 | #define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 121 | |
| mbed_official | 390:35c2c1cf29cd | 122 | #define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 123 | |
| mbed_official | 390:35c2c1cf29cd | 124 | #define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 125 | |
| mbed_official | 390:35c2c1cf29cd | 126 | #define DMAC1_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 127 | #define DMAC1_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 128 | #define DMAC1_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 129 | #define DMAC1_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 130 | #define DMAC1_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 131 | #define DMAC1_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 132 | #define DMAC1_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 133 | #define DMAC1_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 134 | #define DMAC1_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 135 | #define DMAC1_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 136 | #define DMAC1_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 137 | #define DMAC1_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 138 | #define DMAC1_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 139 | |
| mbed_official | 390:35c2c1cf29cd | 140 | #define DMAC1_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 141 | #define DMAC1_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 142 | #define DMAC1_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 143 | #define DMAC1_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 144 | #define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 145 | #define DMAC1_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 146 | #define DMAC1_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 147 | #define DMAC1_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 148 | #define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 149 | #define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 150 | #define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 151 | |
| mbed_official | 390:35c2c1cf29cd | 152 | #define DMAC1_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 153 | #define DMAC1_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 154 | #define DMAC1_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 155 | #define DMAC1_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 156 | #define DMAC1_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 157 | #define DMAC1_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 158 | #define DMAC1_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 159 | #define DMAC1_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 160 | #define DMAC1_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 161 | #define DMAC1_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 162 | #define DMAC1_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 163 | #define DMAC1_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 164 | #define DMAC1_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 165 | #define DMAC1_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 166 | #define DMAC1_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 167 | #define DMAC1_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 168 | #define DMAC1_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 169 | #define DMAC1_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 170 | |
| mbed_official | 390:35c2c1cf29cd | 171 | #define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 172 | |
| mbed_official | 390:35c2c1cf29cd | 173 | #define DMAC1_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 174 | #define DMAC1_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 175 | |
| mbed_official | 390:35c2c1cf29cd | 176 | #define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 177 | |
| mbed_official | 390:35c2c1cf29cd | 178 | #define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 179 | |
| mbed_official | 390:35c2c1cf29cd | 180 | /* ---- DMAC2 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 181 | #define DMAC2_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 182 | |
| mbed_official | 390:35c2c1cf29cd | 183 | #define DMAC2_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 184 | |
| mbed_official | 390:35c2c1cf29cd | 185 | #define DMAC2_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 186 | |
| mbed_official | 390:35c2c1cf29cd | 187 | #define DMAC2_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 188 | |
| mbed_official | 390:35c2c1cf29cd | 189 | #define DMAC2_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 190 | |
| mbed_official | 390:35c2c1cf29cd | 191 | #define DMAC2_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 192 | |
| mbed_official | 390:35c2c1cf29cd | 193 | #define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 194 | |
| mbed_official | 390:35c2c1cf29cd | 195 | #define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 196 | |
| mbed_official | 390:35c2c1cf29cd | 197 | #define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 198 | |
| mbed_official | 390:35c2c1cf29cd | 199 | #define DMAC2_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 200 | #define DMAC2_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 201 | #define DMAC2_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 202 | #define DMAC2_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 203 | #define DMAC2_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 204 | #define DMAC2_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 205 | #define DMAC2_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 206 | #define DMAC2_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 207 | #define DMAC2_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 208 | #define DMAC2_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 209 | #define DMAC2_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 210 | #define DMAC2_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 211 | #define DMAC2_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 212 | |
| mbed_official | 390:35c2c1cf29cd | 213 | #define DMAC2_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 214 | #define DMAC2_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 215 | #define DMAC2_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 216 | #define DMAC2_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 217 | #define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 218 | #define DMAC2_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 219 | #define DMAC2_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 220 | #define DMAC2_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 221 | #define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 222 | #define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 223 | #define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 224 | |
| mbed_official | 390:35c2c1cf29cd | 225 | #define DMAC2_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 226 | #define DMAC2_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 227 | #define DMAC2_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 228 | #define DMAC2_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 229 | #define DMAC2_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 230 | #define DMAC2_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 231 | #define DMAC2_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 232 | #define DMAC2_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 233 | #define DMAC2_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 234 | #define DMAC2_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 235 | #define DMAC2_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 236 | #define DMAC2_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 237 | #define DMAC2_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 238 | #define DMAC2_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 239 | #define DMAC2_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 240 | #define DMAC2_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 241 | #define DMAC2_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 242 | #define DMAC2_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 243 | |
| mbed_official | 390:35c2c1cf29cd | 244 | #define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 245 | |
| mbed_official | 390:35c2c1cf29cd | 246 | #define DMAC2_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 247 | #define DMAC2_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 248 | |
| mbed_official | 390:35c2c1cf29cd | 249 | #define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 250 | |
| mbed_official | 390:35c2c1cf29cd | 251 | #define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 252 | |
| mbed_official | 390:35c2c1cf29cd | 253 | /* ---- DMAC3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 254 | #define DMAC3_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 255 | |
| mbed_official | 390:35c2c1cf29cd | 256 | #define DMAC3_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 257 | |
| mbed_official | 390:35c2c1cf29cd | 258 | #define DMAC3_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 259 | |
| mbed_official | 390:35c2c1cf29cd | 260 | #define DMAC3_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 261 | |
| mbed_official | 390:35c2c1cf29cd | 262 | #define DMAC3_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 263 | |
| mbed_official | 390:35c2c1cf29cd | 264 | #define DMAC3_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 265 | |
| mbed_official | 390:35c2c1cf29cd | 266 | #define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 267 | |
| mbed_official | 390:35c2c1cf29cd | 268 | #define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 269 | |
| mbed_official | 390:35c2c1cf29cd | 270 | #define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 271 | |
| mbed_official | 390:35c2c1cf29cd | 272 | #define DMAC3_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 273 | #define DMAC3_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 274 | #define DMAC3_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 275 | #define DMAC3_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 276 | #define DMAC3_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 277 | #define DMAC3_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 278 | #define DMAC3_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 279 | #define DMAC3_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 280 | #define DMAC3_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 281 | #define DMAC3_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 282 | #define DMAC3_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 283 | #define DMAC3_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 284 | #define DMAC3_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 285 | |
| mbed_official | 390:35c2c1cf29cd | 286 | #define DMAC3_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 287 | #define DMAC3_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 288 | #define DMAC3_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 289 | #define DMAC3_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 290 | #define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 291 | #define DMAC3_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 292 | #define DMAC3_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 293 | #define DMAC3_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 294 | #define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 295 | #define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 296 | #define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 297 | |
| mbed_official | 390:35c2c1cf29cd | 298 | #define DMAC3_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 299 | #define DMAC3_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 300 | #define DMAC3_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 301 | #define DMAC3_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 302 | #define DMAC3_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 303 | #define DMAC3_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 304 | #define DMAC3_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 305 | #define DMAC3_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 306 | #define DMAC3_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 307 | #define DMAC3_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 308 | #define DMAC3_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 309 | #define DMAC3_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 310 | #define DMAC3_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 311 | #define DMAC3_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 312 | #define DMAC3_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 313 | #define DMAC3_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 314 | #define DMAC3_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 315 | #define DMAC3_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 316 | |
| mbed_official | 390:35c2c1cf29cd | 317 | #define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 318 | |
| mbed_official | 390:35c2c1cf29cd | 319 | #define DMAC3_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 320 | #define DMAC3_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 321 | |
| mbed_official | 390:35c2c1cf29cd | 322 | #define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 323 | |
| mbed_official | 390:35c2c1cf29cd | 324 | #define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 325 | |
| mbed_official | 390:35c2c1cf29cd | 326 | /* ---- DMAC4 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 327 | #define DMAC4_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 328 | |
| mbed_official | 390:35c2c1cf29cd | 329 | #define DMAC4_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 330 | |
| mbed_official | 390:35c2c1cf29cd | 331 | #define DMAC4_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 332 | |
| mbed_official | 390:35c2c1cf29cd | 333 | #define DMAC4_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 334 | |
| mbed_official | 390:35c2c1cf29cd | 335 | #define DMAC4_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 336 | |
| mbed_official | 390:35c2c1cf29cd | 337 | #define DMAC4_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 338 | |
| mbed_official | 390:35c2c1cf29cd | 339 | #define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 340 | |
| mbed_official | 390:35c2c1cf29cd | 341 | #define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 342 | |
| mbed_official | 390:35c2c1cf29cd | 343 | #define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 344 | |
| mbed_official | 390:35c2c1cf29cd | 345 | #define DMAC4_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 346 | #define DMAC4_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 347 | #define DMAC4_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 348 | #define DMAC4_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 349 | #define DMAC4_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 350 | #define DMAC4_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 351 | #define DMAC4_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 352 | #define DMAC4_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 353 | #define DMAC4_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 354 | #define DMAC4_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 355 | #define DMAC4_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 356 | #define DMAC4_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 357 | #define DMAC4_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 358 | |
| mbed_official | 390:35c2c1cf29cd | 359 | #define DMAC4_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 360 | #define DMAC4_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 361 | #define DMAC4_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 362 | #define DMAC4_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 363 | #define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 364 | #define DMAC4_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 365 | #define DMAC4_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 366 | #define DMAC4_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 367 | #define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 368 | #define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 369 | #define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 370 | |
| mbed_official | 390:35c2c1cf29cd | 371 | #define DMAC4_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 372 | #define DMAC4_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 373 | #define DMAC4_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 374 | #define DMAC4_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 375 | #define DMAC4_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 376 | #define DMAC4_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 377 | #define DMAC4_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 378 | #define DMAC4_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 379 | #define DMAC4_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 380 | #define DMAC4_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 381 | #define DMAC4_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 382 | #define DMAC4_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 383 | #define DMAC4_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 384 | #define DMAC4_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 385 | #define DMAC4_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 386 | #define DMAC4_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 387 | #define DMAC4_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 388 | #define DMAC4_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 389 | |
| mbed_official | 390:35c2c1cf29cd | 390 | #define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 391 | |
| mbed_official | 390:35c2c1cf29cd | 392 | #define DMAC4_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 393 | #define DMAC4_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 394 | |
| mbed_official | 390:35c2c1cf29cd | 395 | #define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 396 | |
| mbed_official | 390:35c2c1cf29cd | 397 | #define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 398 | |
| mbed_official | 390:35c2c1cf29cd | 399 | /* ---- DMAC5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 400 | #define DMAC5_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 401 | |
| mbed_official | 390:35c2c1cf29cd | 402 | #define DMAC5_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 403 | |
| mbed_official | 390:35c2c1cf29cd | 404 | #define DMAC5_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 405 | |
| mbed_official | 390:35c2c1cf29cd | 406 | #define DMAC5_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 407 | |
| mbed_official | 390:35c2c1cf29cd | 408 | #define DMAC5_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 409 | |
| mbed_official | 390:35c2c1cf29cd | 410 | #define DMAC5_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 411 | |
| mbed_official | 390:35c2c1cf29cd | 412 | #define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 413 | |
| mbed_official | 390:35c2c1cf29cd | 414 | #define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 415 | |
| mbed_official | 390:35c2c1cf29cd | 416 | #define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 417 | |
| mbed_official | 390:35c2c1cf29cd | 418 | #define DMAC5_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 419 | #define DMAC5_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 420 | #define DMAC5_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 421 | #define DMAC5_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 422 | #define DMAC5_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 423 | #define DMAC5_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 424 | #define DMAC5_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 425 | #define DMAC5_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 426 | #define DMAC5_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 427 | #define DMAC5_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 428 | #define DMAC5_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 429 | #define DMAC5_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 430 | #define DMAC5_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 431 | |
| mbed_official | 390:35c2c1cf29cd | 432 | #define DMAC5_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 433 | #define DMAC5_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 434 | #define DMAC5_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 435 | #define DMAC5_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 436 | #define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 437 | #define DMAC5_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 438 | #define DMAC5_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 439 | #define DMAC5_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 440 | #define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 441 | #define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 442 | #define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 443 | |
| mbed_official | 390:35c2c1cf29cd | 444 | #define DMAC5_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 445 | #define DMAC5_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 446 | #define DMAC5_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 447 | #define DMAC5_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 448 | #define DMAC5_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 449 | #define DMAC5_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 450 | #define DMAC5_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 451 | #define DMAC5_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 452 | #define DMAC5_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 453 | #define DMAC5_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 454 | #define DMAC5_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 455 | #define DMAC5_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 456 | #define DMAC5_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 457 | #define DMAC5_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 458 | #define DMAC5_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 459 | #define DMAC5_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 460 | #define DMAC5_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 461 | #define DMAC5_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 462 | |
| mbed_official | 390:35c2c1cf29cd | 463 | #define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 464 | |
| mbed_official | 390:35c2c1cf29cd | 465 | #define DMAC5_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 466 | #define DMAC5_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 467 | |
| mbed_official | 390:35c2c1cf29cd | 468 | #define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 469 | |
| mbed_official | 390:35c2c1cf29cd | 470 | #define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 471 | |
| mbed_official | 390:35c2c1cf29cd | 472 | /* ---- DMAC6 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 473 | #define DMAC6_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 474 | |
| mbed_official | 390:35c2c1cf29cd | 475 | #define DMAC6_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 476 | |
| mbed_official | 390:35c2c1cf29cd | 477 | #define DMAC6_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 478 | |
| mbed_official | 390:35c2c1cf29cd | 479 | #define DMAC6_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 480 | |
| mbed_official | 390:35c2c1cf29cd | 481 | #define DMAC6_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 482 | |
| mbed_official | 390:35c2c1cf29cd | 483 | #define DMAC6_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 484 | |
| mbed_official | 390:35c2c1cf29cd | 485 | #define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 486 | |
| mbed_official | 390:35c2c1cf29cd | 487 | #define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 488 | |
| mbed_official | 390:35c2c1cf29cd | 489 | #define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 490 | |
| mbed_official | 390:35c2c1cf29cd | 491 | #define DMAC6_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 492 | #define DMAC6_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 493 | #define DMAC6_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 494 | #define DMAC6_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 495 | #define DMAC6_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 496 | #define DMAC6_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 497 | #define DMAC6_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 498 | #define DMAC6_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 499 | #define DMAC6_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 500 | #define DMAC6_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 501 | #define DMAC6_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 502 | #define DMAC6_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 503 | #define DMAC6_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 504 | |
| mbed_official | 390:35c2c1cf29cd | 505 | #define DMAC6_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 506 | #define DMAC6_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 507 | #define DMAC6_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 508 | #define DMAC6_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 509 | #define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 510 | #define DMAC6_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 511 | #define DMAC6_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 512 | #define DMAC6_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 513 | #define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 514 | #define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 515 | #define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 516 | |
| mbed_official | 390:35c2c1cf29cd | 517 | #define DMAC6_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 518 | #define DMAC6_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 519 | #define DMAC6_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 520 | #define DMAC6_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 521 | #define DMAC6_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 522 | #define DMAC6_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 523 | #define DMAC6_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 524 | #define DMAC6_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 525 | #define DMAC6_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 526 | #define DMAC6_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 527 | #define DMAC6_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 528 | #define DMAC6_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 529 | #define DMAC6_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 530 | #define DMAC6_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 531 | #define DMAC6_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 532 | #define DMAC6_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 533 | #define DMAC6_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 534 | #define DMAC6_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 535 | |
| mbed_official | 390:35c2c1cf29cd | 536 | #define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 537 | |
| mbed_official | 390:35c2c1cf29cd | 538 | #define DMAC6_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 539 | #define DMAC6_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 540 | |
| mbed_official | 390:35c2c1cf29cd | 541 | #define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 542 | |
| mbed_official | 390:35c2c1cf29cd | 543 | #define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 544 | |
| mbed_official | 390:35c2c1cf29cd | 545 | /* ---- DMAC7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 546 | #define DMAC7_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 547 | |
| mbed_official | 390:35c2c1cf29cd | 548 | #define DMAC7_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 549 | |
| mbed_official | 390:35c2c1cf29cd | 550 | #define DMAC7_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 551 | |
| mbed_official | 390:35c2c1cf29cd | 552 | #define DMAC7_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 553 | |
| mbed_official | 390:35c2c1cf29cd | 554 | #define DMAC7_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 555 | |
| mbed_official | 390:35c2c1cf29cd | 556 | #define DMAC7_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 557 | |
| mbed_official | 390:35c2c1cf29cd | 558 | #define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 559 | |
| mbed_official | 390:35c2c1cf29cd | 560 | #define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 561 | |
| mbed_official | 390:35c2c1cf29cd | 562 | #define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 563 | |
| mbed_official | 390:35c2c1cf29cd | 564 | #define DMAC7_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 565 | #define DMAC7_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 566 | #define DMAC7_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 567 | #define DMAC7_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 568 | #define DMAC7_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 569 | #define DMAC7_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 570 | #define DMAC7_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 571 | #define DMAC7_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 572 | #define DMAC7_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 573 | #define DMAC7_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 574 | #define DMAC7_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 575 | #define DMAC7_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 576 | #define DMAC7_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 577 | |
| mbed_official | 390:35c2c1cf29cd | 578 | #define DMAC7_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 579 | #define DMAC7_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 580 | #define DMAC7_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 581 | #define DMAC7_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 582 | #define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 583 | #define DMAC7_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 584 | #define DMAC7_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 585 | #define DMAC7_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 586 | #define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 587 | #define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 588 | #define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 589 | |
| mbed_official | 390:35c2c1cf29cd | 590 | #define DMAC7_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 591 | #define DMAC7_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 592 | #define DMAC7_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 593 | #define DMAC7_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 594 | #define DMAC7_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 595 | #define DMAC7_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 596 | #define DMAC7_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 597 | #define DMAC7_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 598 | #define DMAC7_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 599 | #define DMAC7_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 600 | #define DMAC7_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 601 | #define DMAC7_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 602 | #define DMAC7_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 603 | #define DMAC7_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 604 | #define DMAC7_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 605 | #define DMAC7_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 606 | #define DMAC7_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 607 | #define DMAC7_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 608 | |
| mbed_official | 390:35c2c1cf29cd | 609 | #define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 610 | |
| mbed_official | 390:35c2c1cf29cd | 611 | #define DMAC7_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 612 | #define DMAC7_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 613 | |
| mbed_official | 390:35c2c1cf29cd | 614 | #define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 615 | |
| mbed_official | 390:35c2c1cf29cd | 616 | #define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 617 | |
| mbed_official | 390:35c2c1cf29cd | 618 | /* ---- DMAC0-7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 619 | #define DMAC07_DCTRL_0_7_PR (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 620 | #define DMAC07_DCTRL_0_7_LVINT (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 621 | #define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL) |
| mbed_official | 390:35c2c1cf29cd | 622 | #define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL) |
| mbed_official | 390:35c2c1cf29cd | 623 | |
| mbed_official | 390:35c2c1cf29cd | 624 | #define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 625 | #define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 626 | #define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 627 | #define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 628 | #define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 629 | #define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 630 | #define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 631 | #define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 632 | |
| mbed_official | 390:35c2c1cf29cd | 633 | #define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 634 | #define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 635 | #define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 636 | #define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 637 | #define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 638 | #define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 639 | #define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 640 | #define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 641 | |
| mbed_official | 390:35c2c1cf29cd | 642 | #define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 643 | #define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 644 | #define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 645 | #define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 646 | #define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 647 | #define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 648 | #define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 649 | #define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 650 | |
| mbed_official | 390:35c2c1cf29cd | 651 | #define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 652 | #define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 653 | #define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 654 | #define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 655 | #define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 656 | #define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 657 | #define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 658 | #define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 659 | |
| mbed_official | 390:35c2c1cf29cd | 660 | #define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 661 | #define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 662 | #define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 663 | #define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 664 | #define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 665 | #define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 666 | #define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 667 | #define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 668 | |
| mbed_official | 390:35c2c1cf29cd | 669 | /* ---- DMAC8 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 670 | #define DMAC8_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 671 | |
| mbed_official | 390:35c2c1cf29cd | 672 | #define DMAC8_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 673 | |
| mbed_official | 390:35c2c1cf29cd | 674 | #define DMAC8_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 675 | |
| mbed_official | 390:35c2c1cf29cd | 676 | #define DMAC8_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 677 | |
| mbed_official | 390:35c2c1cf29cd | 678 | #define DMAC8_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 679 | |
| mbed_official | 390:35c2c1cf29cd | 680 | #define DMAC8_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 681 | |
| mbed_official | 390:35c2c1cf29cd | 682 | #define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 683 | |
| mbed_official | 390:35c2c1cf29cd | 684 | #define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 685 | |
| mbed_official | 390:35c2c1cf29cd | 686 | #define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 687 | |
| mbed_official | 390:35c2c1cf29cd | 688 | #define DMAC8_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 689 | #define DMAC8_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 690 | #define DMAC8_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 691 | #define DMAC8_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 692 | #define DMAC8_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 693 | #define DMAC8_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 694 | #define DMAC8_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 695 | #define DMAC8_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 696 | #define DMAC8_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 697 | #define DMAC8_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 698 | #define DMAC8_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 699 | #define DMAC8_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 700 | #define DMAC8_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 701 | |
| mbed_official | 390:35c2c1cf29cd | 702 | #define DMAC8_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 703 | #define DMAC8_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 704 | #define DMAC8_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 705 | #define DMAC8_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 706 | #define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 707 | #define DMAC8_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 708 | #define DMAC8_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 709 | #define DMAC8_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 710 | #define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 711 | #define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 712 | #define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 713 | |
| mbed_official | 390:35c2c1cf29cd | 714 | #define DMAC8_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 715 | #define DMAC8_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 716 | #define DMAC8_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 717 | #define DMAC8_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 718 | #define DMAC8_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 719 | #define DMAC8_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 720 | #define DMAC8_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 721 | #define DMAC8_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 722 | #define DMAC8_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 723 | #define DMAC8_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 724 | #define DMAC8_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 725 | #define DMAC8_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 726 | #define DMAC8_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 727 | #define DMAC8_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 728 | #define DMAC8_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 729 | #define DMAC8_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 730 | #define DMAC8_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 731 | #define DMAC8_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 732 | |
| mbed_official | 390:35c2c1cf29cd | 733 | #define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 734 | |
| mbed_official | 390:35c2c1cf29cd | 735 | #define DMAC8_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 736 | #define DMAC8_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 737 | |
| mbed_official | 390:35c2c1cf29cd | 738 | #define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 739 | |
| mbed_official | 390:35c2c1cf29cd | 740 | #define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 741 | |
| mbed_official | 390:35c2c1cf29cd | 742 | /* ---- DMAC9 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 743 | #define DMAC9_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 744 | |
| mbed_official | 390:35c2c1cf29cd | 745 | #define DMAC9_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 746 | |
| mbed_official | 390:35c2c1cf29cd | 747 | #define DMAC9_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 748 | |
| mbed_official | 390:35c2c1cf29cd | 749 | #define DMAC9_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 750 | |
| mbed_official | 390:35c2c1cf29cd | 751 | #define DMAC9_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 752 | |
| mbed_official | 390:35c2c1cf29cd | 753 | #define DMAC9_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 754 | |
| mbed_official | 390:35c2c1cf29cd | 755 | #define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 756 | |
| mbed_official | 390:35c2c1cf29cd | 757 | #define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 758 | |
| mbed_official | 390:35c2c1cf29cd | 759 | #define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 760 | |
| mbed_official | 390:35c2c1cf29cd | 761 | #define DMAC9_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 762 | #define DMAC9_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 763 | #define DMAC9_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 764 | #define DMAC9_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 765 | #define DMAC9_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 766 | #define DMAC9_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 767 | #define DMAC9_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 768 | #define DMAC9_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 769 | #define DMAC9_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 770 | #define DMAC9_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 771 | #define DMAC9_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 772 | #define DMAC9_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 773 | #define DMAC9_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 774 | |
| mbed_official | 390:35c2c1cf29cd | 775 | #define DMAC9_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 776 | #define DMAC9_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 777 | #define DMAC9_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 778 | #define DMAC9_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 779 | #define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 780 | #define DMAC9_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 781 | #define DMAC9_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 782 | #define DMAC9_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 783 | #define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 784 | #define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 785 | #define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 786 | |
| mbed_official | 390:35c2c1cf29cd | 787 | #define DMAC9_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 788 | #define DMAC9_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 789 | #define DMAC9_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 790 | #define DMAC9_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 791 | #define DMAC9_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 792 | #define DMAC9_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 793 | #define DMAC9_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 794 | #define DMAC9_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 795 | #define DMAC9_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 796 | #define DMAC9_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 797 | #define DMAC9_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 798 | #define DMAC9_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 799 | #define DMAC9_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 800 | #define DMAC9_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 801 | #define DMAC9_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 802 | #define DMAC9_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 803 | #define DMAC9_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 804 | #define DMAC9_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 805 | |
| mbed_official | 390:35c2c1cf29cd | 806 | #define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 807 | |
| mbed_official | 390:35c2c1cf29cd | 808 | #define DMAC9_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 809 | #define DMAC9_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 810 | |
| mbed_official | 390:35c2c1cf29cd | 811 | #define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 812 | |
| mbed_official | 390:35c2c1cf29cd | 813 | #define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 814 | |
| mbed_official | 390:35c2c1cf29cd | 815 | /* ---- DMAC10 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 816 | #define DMAC10_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 817 | |
| mbed_official | 390:35c2c1cf29cd | 818 | #define DMAC10_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 819 | |
| mbed_official | 390:35c2c1cf29cd | 820 | #define DMAC10_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 821 | |
| mbed_official | 390:35c2c1cf29cd | 822 | #define DMAC10_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 823 | |
| mbed_official | 390:35c2c1cf29cd | 824 | #define DMAC10_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 825 | |
| mbed_official | 390:35c2c1cf29cd | 826 | #define DMAC10_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 827 | |
| mbed_official | 390:35c2c1cf29cd | 828 | #define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 829 | |
| mbed_official | 390:35c2c1cf29cd | 830 | #define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 831 | |
| mbed_official | 390:35c2c1cf29cd | 832 | #define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 833 | |
| mbed_official | 390:35c2c1cf29cd | 834 | #define DMAC10_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 835 | #define DMAC10_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 836 | #define DMAC10_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 837 | #define DMAC10_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 838 | #define DMAC10_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 839 | #define DMAC10_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 840 | #define DMAC10_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 841 | #define DMAC10_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 842 | #define DMAC10_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 843 | #define DMAC10_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 844 | #define DMAC10_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 845 | #define DMAC10_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 846 | #define DMAC10_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 847 | |
| mbed_official | 390:35c2c1cf29cd | 848 | #define DMAC10_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 849 | #define DMAC10_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 850 | #define DMAC10_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 851 | #define DMAC10_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 852 | #define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 853 | #define DMAC10_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 854 | #define DMAC10_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 855 | #define DMAC10_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 856 | #define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 857 | #define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 858 | #define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 859 | |
| mbed_official | 390:35c2c1cf29cd | 860 | #define DMAC10_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 861 | #define DMAC10_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 862 | #define DMAC10_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 863 | #define DMAC10_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 864 | #define DMAC10_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 865 | #define DMAC10_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 866 | #define DMAC10_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 867 | #define DMAC10_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 868 | #define DMAC10_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 869 | #define DMAC10_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 870 | #define DMAC10_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 871 | #define DMAC10_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 872 | #define DMAC10_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 873 | #define DMAC10_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 874 | #define DMAC10_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 875 | #define DMAC10_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 876 | #define DMAC10_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 877 | #define DMAC10_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 878 | |
| mbed_official | 390:35c2c1cf29cd | 879 | #define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 880 | |
| mbed_official | 390:35c2c1cf29cd | 881 | #define DMAC10_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 882 | #define DMAC10_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 883 | |
| mbed_official | 390:35c2c1cf29cd | 884 | #define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 885 | |
| mbed_official | 390:35c2c1cf29cd | 886 | #define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 887 | |
| mbed_official | 390:35c2c1cf29cd | 888 | /* ---- DMAC11 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 889 | #define DMAC11_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 890 | |
| mbed_official | 390:35c2c1cf29cd | 891 | #define DMAC11_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 892 | |
| mbed_official | 390:35c2c1cf29cd | 893 | #define DMAC11_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 894 | |
| mbed_official | 390:35c2c1cf29cd | 895 | #define DMAC11_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 896 | |
| mbed_official | 390:35c2c1cf29cd | 897 | #define DMAC11_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 898 | |
| mbed_official | 390:35c2c1cf29cd | 899 | #define DMAC11_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 900 | |
| mbed_official | 390:35c2c1cf29cd | 901 | #define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 902 | |
| mbed_official | 390:35c2c1cf29cd | 903 | #define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 904 | |
| mbed_official | 390:35c2c1cf29cd | 905 | #define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 906 | |
| mbed_official | 390:35c2c1cf29cd | 907 | #define DMAC11_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 908 | #define DMAC11_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 909 | #define DMAC11_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 910 | #define DMAC11_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 911 | #define DMAC11_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 912 | #define DMAC11_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 913 | #define DMAC11_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 914 | #define DMAC11_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 915 | #define DMAC11_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 916 | #define DMAC11_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 917 | #define DMAC11_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 918 | #define DMAC11_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 919 | #define DMAC11_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 920 | |
| mbed_official | 390:35c2c1cf29cd | 921 | #define DMAC11_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 922 | #define DMAC11_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 923 | #define DMAC11_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 924 | #define DMAC11_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 925 | #define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 926 | #define DMAC11_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 927 | #define DMAC11_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 928 | #define DMAC11_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 929 | #define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 930 | #define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 931 | #define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 932 | |
| mbed_official | 390:35c2c1cf29cd | 933 | #define DMAC11_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 934 | #define DMAC11_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 935 | #define DMAC11_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 936 | #define DMAC11_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 937 | #define DMAC11_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 938 | #define DMAC11_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 939 | #define DMAC11_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 940 | #define DMAC11_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 941 | #define DMAC11_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 942 | #define DMAC11_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 943 | #define DMAC11_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 944 | #define DMAC11_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 945 | #define DMAC11_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 946 | #define DMAC11_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 947 | #define DMAC11_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 948 | #define DMAC11_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 949 | #define DMAC11_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 950 | #define DMAC11_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 951 | |
| mbed_official | 390:35c2c1cf29cd | 952 | #define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 953 | |
| mbed_official | 390:35c2c1cf29cd | 954 | #define DMAC11_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 955 | #define DMAC11_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 956 | |
| mbed_official | 390:35c2c1cf29cd | 957 | #define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 958 | |
| mbed_official | 390:35c2c1cf29cd | 959 | #define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 960 | |
| mbed_official | 390:35c2c1cf29cd | 961 | /* ---- DMAC12 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 962 | #define DMAC12_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 963 | |
| mbed_official | 390:35c2c1cf29cd | 964 | #define DMAC12_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 965 | |
| mbed_official | 390:35c2c1cf29cd | 966 | #define DMAC12_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 967 | |
| mbed_official | 390:35c2c1cf29cd | 968 | #define DMAC12_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 969 | |
| mbed_official | 390:35c2c1cf29cd | 970 | #define DMAC12_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 971 | |
| mbed_official | 390:35c2c1cf29cd | 972 | #define DMAC12_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 973 | |
| mbed_official | 390:35c2c1cf29cd | 974 | #define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 975 | |
| mbed_official | 390:35c2c1cf29cd | 976 | #define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 977 | |
| mbed_official | 390:35c2c1cf29cd | 978 | #define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 979 | |
| mbed_official | 390:35c2c1cf29cd | 980 | #define DMAC12_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 981 | #define DMAC12_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 982 | #define DMAC12_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 983 | #define DMAC12_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 984 | #define DMAC12_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 985 | #define DMAC12_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 986 | #define DMAC12_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 987 | #define DMAC12_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 988 | #define DMAC12_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 989 | #define DMAC12_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 990 | #define DMAC12_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 991 | #define DMAC12_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 992 | #define DMAC12_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 993 | |
| mbed_official | 390:35c2c1cf29cd | 994 | #define DMAC12_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 995 | #define DMAC12_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 996 | #define DMAC12_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 997 | #define DMAC12_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 998 | #define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 999 | #define DMAC12_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1000 | #define DMAC12_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1001 | #define DMAC12_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1002 | #define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1003 | #define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1004 | #define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 1005 | |
| mbed_official | 390:35c2c1cf29cd | 1006 | #define DMAC12_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 1007 | #define DMAC12_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1008 | #define DMAC12_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1009 | #define DMAC12_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1010 | #define DMAC12_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1011 | #define DMAC12_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 1012 | #define DMAC12_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1013 | #define DMAC12_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1014 | #define DMAC12_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 1015 | #define DMAC12_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 1016 | #define DMAC12_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 1017 | #define DMAC12_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1018 | #define DMAC12_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1019 | #define DMAC12_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1020 | #define DMAC12_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1021 | #define DMAC12_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1022 | #define DMAC12_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1023 | #define DMAC12_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1024 | |
| mbed_official | 390:35c2c1cf29cd | 1025 | #define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1026 | |
| mbed_official | 390:35c2c1cf29cd | 1027 | #define DMAC12_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 1028 | #define DMAC12_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1029 | |
| mbed_official | 390:35c2c1cf29cd | 1030 | #define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1031 | |
| mbed_official | 390:35c2c1cf29cd | 1032 | #define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1033 | |
| mbed_official | 390:35c2c1cf29cd | 1034 | /* ---- DMAC13 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1035 | #define DMAC13_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1036 | |
| mbed_official | 390:35c2c1cf29cd | 1037 | #define DMAC13_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1038 | |
| mbed_official | 390:35c2c1cf29cd | 1039 | #define DMAC13_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1040 | |
| mbed_official | 390:35c2c1cf29cd | 1041 | #define DMAC13_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1042 | |
| mbed_official | 390:35c2c1cf29cd | 1043 | #define DMAC13_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1044 | |
| mbed_official | 390:35c2c1cf29cd | 1045 | #define DMAC13_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1046 | |
| mbed_official | 390:35c2c1cf29cd | 1047 | #define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1048 | |
| mbed_official | 390:35c2c1cf29cd | 1049 | #define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1050 | |
| mbed_official | 390:35c2c1cf29cd | 1051 | #define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1052 | |
| mbed_official | 390:35c2c1cf29cd | 1053 | #define DMAC13_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1054 | #define DMAC13_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1055 | #define DMAC13_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1056 | #define DMAC13_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1057 | #define DMAC13_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1058 | #define DMAC13_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1059 | #define DMAC13_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1060 | #define DMAC13_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1061 | #define DMAC13_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1062 | #define DMAC13_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1063 | #define DMAC13_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 1064 | #define DMAC13_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 1065 | #define DMAC13_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1066 | |
| mbed_official | 390:35c2c1cf29cd | 1067 | #define DMAC13_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1068 | #define DMAC13_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1069 | #define DMAC13_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1070 | #define DMAC13_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1071 | #define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1072 | #define DMAC13_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1073 | #define DMAC13_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1074 | #define DMAC13_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1075 | #define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1076 | #define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1077 | #define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 1078 | |
| mbed_official | 390:35c2c1cf29cd | 1079 | #define DMAC13_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 1080 | #define DMAC13_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1081 | #define DMAC13_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1082 | #define DMAC13_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1083 | #define DMAC13_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1084 | #define DMAC13_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 1085 | #define DMAC13_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1086 | #define DMAC13_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1087 | #define DMAC13_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 1088 | #define DMAC13_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 1089 | #define DMAC13_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 1090 | #define DMAC13_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1091 | #define DMAC13_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1092 | #define DMAC13_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1093 | #define DMAC13_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1094 | #define DMAC13_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1095 | #define DMAC13_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1096 | #define DMAC13_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1097 | |
| mbed_official | 390:35c2c1cf29cd | 1098 | #define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1099 | |
| mbed_official | 390:35c2c1cf29cd | 1100 | #define DMAC13_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 1101 | #define DMAC13_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1102 | |
| mbed_official | 390:35c2c1cf29cd | 1103 | #define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1104 | |
| mbed_official | 390:35c2c1cf29cd | 1105 | #define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1106 | |
| mbed_official | 390:35c2c1cf29cd | 1107 | /* ---- DMAC14 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1108 | #define DMAC14_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1109 | |
| mbed_official | 390:35c2c1cf29cd | 1110 | #define DMAC14_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1111 | |
| mbed_official | 390:35c2c1cf29cd | 1112 | #define DMAC14_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1113 | |
| mbed_official | 390:35c2c1cf29cd | 1114 | #define DMAC14_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1115 | |
| mbed_official | 390:35c2c1cf29cd | 1116 | #define DMAC14_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1117 | |
| mbed_official | 390:35c2c1cf29cd | 1118 | #define DMAC14_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1119 | |
| mbed_official | 390:35c2c1cf29cd | 1120 | #define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1121 | |
| mbed_official | 390:35c2c1cf29cd | 1122 | #define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1123 | |
| mbed_official | 390:35c2c1cf29cd | 1124 | #define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1125 | |
| mbed_official | 390:35c2c1cf29cd | 1126 | #define DMAC14_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1127 | #define DMAC14_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1128 | #define DMAC14_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1129 | #define DMAC14_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1130 | #define DMAC14_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1131 | #define DMAC14_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1132 | #define DMAC14_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1133 | #define DMAC14_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1134 | #define DMAC14_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1135 | #define DMAC14_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1136 | #define DMAC14_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 1137 | #define DMAC14_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 1138 | #define DMAC14_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1139 | |
| mbed_official | 390:35c2c1cf29cd | 1140 | #define DMAC14_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1141 | #define DMAC14_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1142 | #define DMAC14_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1143 | #define DMAC14_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1144 | #define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1145 | #define DMAC14_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1146 | #define DMAC14_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1147 | #define DMAC14_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1148 | #define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1149 | #define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1150 | #define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 1151 | |
| mbed_official | 390:35c2c1cf29cd | 1152 | #define DMAC14_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 1153 | #define DMAC14_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1154 | #define DMAC14_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1155 | #define DMAC14_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1156 | #define DMAC14_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1157 | #define DMAC14_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 1158 | #define DMAC14_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1159 | #define DMAC14_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1160 | #define DMAC14_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 1161 | #define DMAC14_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 1162 | #define DMAC14_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 1163 | #define DMAC14_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1164 | #define DMAC14_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1165 | #define DMAC14_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1166 | #define DMAC14_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1167 | #define DMAC14_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1168 | #define DMAC14_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1169 | #define DMAC14_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1170 | |
| mbed_official | 390:35c2c1cf29cd | 1171 | #define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1172 | |
| mbed_official | 390:35c2c1cf29cd | 1173 | #define DMAC14_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 1174 | #define DMAC14_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1175 | |
| mbed_official | 390:35c2c1cf29cd | 1176 | #define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1177 | |
| mbed_official | 390:35c2c1cf29cd | 1178 | #define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1179 | |
| mbed_official | 390:35c2c1cf29cd | 1180 | /* ---- DMAC15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1181 | #define DMAC15_N0SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1182 | |
| mbed_official | 390:35c2c1cf29cd | 1183 | #define DMAC15_N0DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1184 | |
| mbed_official | 390:35c2c1cf29cd | 1185 | #define DMAC15_N0TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1186 | |
| mbed_official | 390:35c2c1cf29cd | 1187 | #define DMAC15_N1SA_n_SA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1188 | |
| mbed_official | 390:35c2c1cf29cd | 1189 | #define DMAC15_N1DA_n_DA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1190 | |
| mbed_official | 390:35c2c1cf29cd | 1191 | #define DMAC15_N1TB_n_TB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1192 | |
| mbed_official | 390:35c2c1cf29cd | 1193 | #define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1194 | |
| mbed_official | 390:35c2c1cf29cd | 1195 | #define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1196 | |
| mbed_official | 390:35c2c1cf29cd | 1197 | #define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1198 | |
| mbed_official | 390:35c2c1cf29cd | 1199 | #define DMAC15_CHSTAT_n_EN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1200 | #define DMAC15_CHSTAT_n_RQST (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1201 | #define DMAC15_CHSTAT_n_TACT (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1202 | #define DMAC15_CHSTAT_n_SUS (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1203 | #define DMAC15_CHSTAT_n_ER (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1204 | #define DMAC15_CHSTAT_n_END (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1205 | #define DMAC15_CHSTAT_n_TC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1206 | #define DMAC15_CHSTAT_n_SR (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1207 | #define DMAC15_CHSTAT_n_DL (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1208 | #define DMAC15_CHSTAT_n_DW (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1209 | #define DMAC15_CHSTAT_n_DER (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 1210 | #define DMAC15_CHSTAT_n_MODE (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 1211 | #define DMAC15_CHSTAT_n_INTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1212 | |
| mbed_official | 390:35c2c1cf29cd | 1213 | #define DMAC15_CHCTRL_n_SETEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1214 | #define DMAC15_CHCTRL_n_CLREN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1215 | #define DMAC15_CHCTRL_n_STG (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1216 | #define DMAC15_CHCTRL_n_SWRST (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1217 | #define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1218 | #define DMAC15_CHCTRL_n_CLREND (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1219 | #define DMAC15_CHCTRL_n_CLRTC (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1220 | #define DMAC15_CHCTRL_n_SETSUS (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 1221 | #define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 1222 | #define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL) |
| mbed_official | 390:35c2c1cf29cd | 1223 | #define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL) |
| mbed_official | 390:35c2c1cf29cd | 1224 | |
| mbed_official | 390:35c2c1cf29cd | 1225 | #define DMAC15_CHCFG_n_SEL (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 1226 | #define DMAC15_CHCFG_n_REQD (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1227 | #define DMAC15_CHCFG_n_LOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1228 | #define DMAC15_CHCFG_n_HIEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1229 | #define DMAC15_CHCFG_n_LVL (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1230 | #define DMAC15_CHCFG_n_AM (0x00000700uL) |
| mbed_official | 390:35c2c1cf29cd | 1231 | #define DMAC15_CHCFG_n_SDS (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1232 | #define DMAC15_CHCFG_n_DDS (0x000F0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1233 | #define DMAC15_CHCFG_n_SAD (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 1234 | #define DMAC15_CHCFG_n_DAD (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 1235 | #define DMAC15_CHCFG_n_TM (0x00400000uL) |
| mbed_official | 390:35c2c1cf29cd | 1236 | #define DMAC15_CHCFG_n_DEM (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1237 | #define DMAC15_CHCFG_n_TCM (0x02000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1238 | #define DMAC15_CHCFG_n_SBE (0x08000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1239 | #define DMAC15_CHCFG_n_RSEL (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1240 | #define DMAC15_CHCFG_n_RSW (0x20000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1241 | #define DMAC15_CHCFG_n_REN (0x40000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1242 | #define DMAC15_CHCFG_n_DMS (0x80000000uL) |
| mbed_official | 390:35c2c1cf29cd | 1243 | |
| mbed_official | 390:35c2c1cf29cd | 1244 | #define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1245 | |
| mbed_official | 390:35c2c1cf29cd | 1246 | #define DMAC15_CHEXT_n_SCA (0x000000F0uL) |
| mbed_official | 390:35c2c1cf29cd | 1247 | #define DMAC15_CHEXT_n_DCA (0x0000F000uL) |
| mbed_official | 390:35c2c1cf29cd | 1248 | |
| mbed_official | 390:35c2c1cf29cd | 1249 | #define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1250 | |
| mbed_official | 390:35c2c1cf29cd | 1251 | #define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 1252 | |
| mbed_official | 390:35c2c1cf29cd | 1253 | /* ---- DMAC8-15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1254 | #define DMAC815_DCTRL_8_15_PR (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1255 | #define DMAC815_DCTRL_8_15_LVINT (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1256 | #define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL) |
| mbed_official | 390:35c2c1cf29cd | 1257 | #define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL) |
| mbed_official | 390:35c2c1cf29cd | 1258 | |
| mbed_official | 390:35c2c1cf29cd | 1259 | #define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1260 | #define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1261 | #define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1262 | #define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1263 | #define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1264 | #define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1265 | #define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1266 | #define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1267 | |
| mbed_official | 390:35c2c1cf29cd | 1268 | #define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1269 | #define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1270 | #define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1271 | #define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1272 | #define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1273 | #define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1274 | #define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1275 | #define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1276 | |
| mbed_official | 390:35c2c1cf29cd | 1277 | #define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1278 | #define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1279 | #define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1280 | #define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1281 | #define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1282 | #define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1283 | #define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1284 | #define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1285 | |
| mbed_official | 390:35c2c1cf29cd | 1286 | #define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1287 | #define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1288 | #define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1289 | #define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1290 | #define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1291 | #define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1292 | #define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1293 | #define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1294 | |
| mbed_official | 390:35c2c1cf29cd | 1295 | #define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 1296 | #define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 1297 | #define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 1298 | #define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 1299 | #define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 1300 | #define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 1301 | #define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 1302 | #define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 1303 | |
| mbed_official | 390:35c2c1cf29cd | 1304 | /* ---- DMAC0-1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1305 | #define DMAC01_DMARS_CH0_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1306 | #define DMAC01_DMARS_CH0_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1307 | #define DMAC01_DMARS_CH1_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1308 | #define DMAC01_DMARS_CH1_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1309 | |
| mbed_official | 390:35c2c1cf29cd | 1310 | /* ---- DMAC2-3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1311 | #define DMAC23_DMARS_CH2_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1312 | #define DMAC23_DMARS_CH2_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1313 | #define DMAC23_DMARS_CH3_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1314 | #define DMAC23_DMARS_CH3_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1315 | |
| mbed_official | 390:35c2c1cf29cd | 1316 | /* ---- DMAC4-5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1317 | #define DMAC45_DMARS_CH4_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1318 | #define DMAC45_DMARS_CH4_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1319 | #define DMAC45_DMARS_CH5_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1320 | #define DMAC45_DMARS_CH5_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1321 | |
| mbed_official | 390:35c2c1cf29cd | 1322 | /* ---- DMAC6-7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1323 | #define DMAC67_DMARS_CH6_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1324 | #define DMAC67_DMARS_CH6_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1325 | #define DMAC67_DMARS_CH7_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1326 | #define DMAC67_DMARS_CH7_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1327 | |
| mbed_official | 390:35c2c1cf29cd | 1328 | /* ---- DMAC8-9 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1329 | #define DMAC89_DMARS_CH8_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1330 | #define DMAC89_DMARS_CH8_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1331 | #define DMAC89_DMARS_CH9_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1332 | #define DMAC89_DMARS_CH9_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1333 | |
| mbed_official | 390:35c2c1cf29cd | 1334 | /* ---- DMAC10-11 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1335 | #define DMAC1011_DMARS_CH10_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1336 | #define DMAC1011_DMARS_CH10_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1337 | #define DMAC1011_DMARS_CH11_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1338 | #define DMAC1011_DMARS_CH11_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1339 | |
| mbed_official | 390:35c2c1cf29cd | 1340 | /* ---- DMAC12-13 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1341 | #define DMAC1213_DMARS_CH12_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1342 | #define DMAC1213_DMARS_CH12_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1343 | #define DMAC1213_DMARS_CH13_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1344 | #define DMAC1213_DMARS_CH13_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1345 | |
| mbed_official | 390:35c2c1cf29cd | 1346 | /* ---- DMAC14-15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1347 | #define DMAC1415_DMARS_CH14_RID (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 1348 | #define DMAC1415_DMARS_CH14_MID (0x000001FCuL) |
| mbed_official | 390:35c2c1cf29cd | 1349 | #define DMAC1415_DMARS_CH15_RID (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 1350 | #define DMAC1415_DMARS_CH15_MID (0x01FC0000uL) |
| mbed_official | 390:35c2c1cf29cd | 1351 | |
| mbed_official | 390:35c2c1cf29cd | 1352 | |
| mbed_official | 390:35c2c1cf29cd | 1353 | /* ==== Shift values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 1354 | /* ---- DMAC0 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1355 | #define DMAC0_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1356 | |
| mbed_official | 390:35c2c1cf29cd | 1357 | #define DMAC0_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1358 | |
| mbed_official | 390:35c2c1cf29cd | 1359 | #define DMAC0_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1360 | |
| mbed_official | 390:35c2c1cf29cd | 1361 | #define DMAC0_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1362 | |
| mbed_official | 390:35c2c1cf29cd | 1363 | #define DMAC0_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1364 | |
| mbed_official | 390:35c2c1cf29cd | 1365 | #define DMAC0_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1366 | |
| mbed_official | 390:35c2c1cf29cd | 1367 | #define DMAC0_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1368 | |
| mbed_official | 390:35c2c1cf29cd | 1369 | #define DMAC0_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1370 | |
| mbed_official | 390:35c2c1cf29cd | 1371 | #define DMAC0_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1372 | |
| mbed_official | 390:35c2c1cf29cd | 1373 | #define DMAC0_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1374 | #define DMAC0_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1375 | #define DMAC0_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1376 | #define DMAC0_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1377 | #define DMAC0_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1378 | #define DMAC0_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1379 | #define DMAC0_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1380 | #define DMAC0_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1381 | #define DMAC0_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1382 | #define DMAC0_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1383 | #define DMAC0_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1384 | #define DMAC0_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1385 | #define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1386 | |
| mbed_official | 390:35c2c1cf29cd | 1387 | #define DMAC0_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1388 | #define DMAC0_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1389 | #define DMAC0_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1390 | #define DMAC0_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1391 | #define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1392 | #define DMAC0_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1393 | #define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1394 | #define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1395 | #define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1396 | #define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1397 | #define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1398 | |
| mbed_official | 390:35c2c1cf29cd | 1399 | #define DMAC0_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1400 | #define DMAC0_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1401 | #define DMAC0_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1402 | #define DMAC0_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1403 | #define DMAC0_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1404 | #define DMAC0_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1405 | #define DMAC0_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1406 | #define DMAC0_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1407 | #define DMAC0_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1408 | #define DMAC0_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1409 | #define DMAC0_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1410 | #define DMAC0_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1411 | #define DMAC0_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1412 | #define DMAC0_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1413 | #define DMAC0_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1414 | #define DMAC0_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1415 | #define DMAC0_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1416 | #define DMAC0_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1417 | |
| mbed_official | 390:35c2c1cf29cd | 1418 | #define DMAC0_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1419 | |
| mbed_official | 390:35c2c1cf29cd | 1420 | #define DMAC0_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1421 | #define DMAC0_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1422 | |
| mbed_official | 390:35c2c1cf29cd | 1423 | #define DMAC0_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1424 | |
| mbed_official | 390:35c2c1cf29cd | 1425 | #define DMAC0_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1426 | |
| mbed_official | 390:35c2c1cf29cd | 1427 | /* ---- DMAC1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1428 | #define DMAC1_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1429 | |
| mbed_official | 390:35c2c1cf29cd | 1430 | #define DMAC1_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1431 | |
| mbed_official | 390:35c2c1cf29cd | 1432 | #define DMAC1_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1433 | |
| mbed_official | 390:35c2c1cf29cd | 1434 | #define DMAC1_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1435 | |
| mbed_official | 390:35c2c1cf29cd | 1436 | #define DMAC1_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1437 | |
| mbed_official | 390:35c2c1cf29cd | 1438 | #define DMAC1_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1439 | |
| mbed_official | 390:35c2c1cf29cd | 1440 | #define DMAC1_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1441 | |
| mbed_official | 390:35c2c1cf29cd | 1442 | #define DMAC1_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1443 | |
| mbed_official | 390:35c2c1cf29cd | 1444 | #define DMAC1_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1445 | |
| mbed_official | 390:35c2c1cf29cd | 1446 | #define DMAC1_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1447 | #define DMAC1_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1448 | #define DMAC1_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1449 | #define DMAC1_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1450 | #define DMAC1_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1451 | #define DMAC1_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1452 | #define DMAC1_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1453 | #define DMAC1_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1454 | #define DMAC1_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1455 | #define DMAC1_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1456 | #define DMAC1_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1457 | #define DMAC1_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1458 | #define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1459 | |
| mbed_official | 390:35c2c1cf29cd | 1460 | #define DMAC1_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1461 | #define DMAC1_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1462 | #define DMAC1_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1463 | #define DMAC1_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1464 | #define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1465 | #define DMAC1_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1466 | #define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1467 | #define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1468 | #define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1469 | #define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1470 | #define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1471 | |
| mbed_official | 390:35c2c1cf29cd | 1472 | #define DMAC1_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1473 | #define DMAC1_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1474 | #define DMAC1_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1475 | #define DMAC1_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1476 | #define DMAC1_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1477 | #define DMAC1_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1478 | #define DMAC1_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1479 | #define DMAC1_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1480 | #define DMAC1_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1481 | #define DMAC1_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1482 | #define DMAC1_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1483 | #define DMAC1_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1484 | #define DMAC1_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1485 | #define DMAC1_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1486 | #define DMAC1_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1487 | #define DMAC1_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1488 | #define DMAC1_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1489 | #define DMAC1_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1490 | |
| mbed_official | 390:35c2c1cf29cd | 1491 | #define DMAC1_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1492 | |
| mbed_official | 390:35c2c1cf29cd | 1493 | #define DMAC1_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1494 | #define DMAC1_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1495 | |
| mbed_official | 390:35c2c1cf29cd | 1496 | #define DMAC1_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1497 | |
| mbed_official | 390:35c2c1cf29cd | 1498 | #define DMAC1_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1499 | |
| mbed_official | 390:35c2c1cf29cd | 1500 | /* ---- DMAC2 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1501 | #define DMAC2_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1502 | |
| mbed_official | 390:35c2c1cf29cd | 1503 | #define DMAC2_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1504 | |
| mbed_official | 390:35c2c1cf29cd | 1505 | #define DMAC2_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1506 | |
| mbed_official | 390:35c2c1cf29cd | 1507 | #define DMAC2_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1508 | |
| mbed_official | 390:35c2c1cf29cd | 1509 | #define DMAC2_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1510 | |
| mbed_official | 390:35c2c1cf29cd | 1511 | #define DMAC2_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1512 | |
| mbed_official | 390:35c2c1cf29cd | 1513 | #define DMAC2_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1514 | |
| mbed_official | 390:35c2c1cf29cd | 1515 | #define DMAC2_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1516 | |
| mbed_official | 390:35c2c1cf29cd | 1517 | #define DMAC2_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1518 | |
| mbed_official | 390:35c2c1cf29cd | 1519 | #define DMAC2_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1520 | #define DMAC2_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1521 | #define DMAC2_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1522 | #define DMAC2_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1523 | #define DMAC2_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1524 | #define DMAC2_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1525 | #define DMAC2_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1526 | #define DMAC2_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1527 | #define DMAC2_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1528 | #define DMAC2_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1529 | #define DMAC2_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1530 | #define DMAC2_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1531 | #define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1532 | |
| mbed_official | 390:35c2c1cf29cd | 1533 | #define DMAC2_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1534 | #define DMAC2_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1535 | #define DMAC2_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1536 | #define DMAC2_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1537 | #define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1538 | #define DMAC2_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1539 | #define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1540 | #define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1541 | #define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1542 | #define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1543 | #define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1544 | |
| mbed_official | 390:35c2c1cf29cd | 1545 | #define DMAC2_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1546 | #define DMAC2_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1547 | #define DMAC2_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1548 | #define DMAC2_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1549 | #define DMAC2_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1550 | #define DMAC2_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1551 | #define DMAC2_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1552 | #define DMAC2_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1553 | #define DMAC2_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1554 | #define DMAC2_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1555 | #define DMAC2_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1556 | #define DMAC2_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1557 | #define DMAC2_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1558 | #define DMAC2_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1559 | #define DMAC2_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1560 | #define DMAC2_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1561 | #define DMAC2_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1562 | #define DMAC2_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1563 | |
| mbed_official | 390:35c2c1cf29cd | 1564 | #define DMAC2_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1565 | |
| mbed_official | 390:35c2c1cf29cd | 1566 | #define DMAC2_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1567 | #define DMAC2_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1568 | |
| mbed_official | 390:35c2c1cf29cd | 1569 | #define DMAC2_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1570 | |
| mbed_official | 390:35c2c1cf29cd | 1571 | #define DMAC2_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1572 | |
| mbed_official | 390:35c2c1cf29cd | 1573 | /* ---- DMAC3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1574 | #define DMAC3_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1575 | |
| mbed_official | 390:35c2c1cf29cd | 1576 | #define DMAC3_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1577 | |
| mbed_official | 390:35c2c1cf29cd | 1578 | #define DMAC3_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1579 | |
| mbed_official | 390:35c2c1cf29cd | 1580 | #define DMAC3_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1581 | |
| mbed_official | 390:35c2c1cf29cd | 1582 | #define DMAC3_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1583 | |
| mbed_official | 390:35c2c1cf29cd | 1584 | #define DMAC3_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1585 | |
| mbed_official | 390:35c2c1cf29cd | 1586 | #define DMAC3_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1587 | |
| mbed_official | 390:35c2c1cf29cd | 1588 | #define DMAC3_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1589 | |
| mbed_official | 390:35c2c1cf29cd | 1590 | #define DMAC3_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1591 | |
| mbed_official | 390:35c2c1cf29cd | 1592 | #define DMAC3_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1593 | #define DMAC3_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1594 | #define DMAC3_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1595 | #define DMAC3_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1596 | #define DMAC3_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1597 | #define DMAC3_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1598 | #define DMAC3_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1599 | #define DMAC3_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1600 | #define DMAC3_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1601 | #define DMAC3_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1602 | #define DMAC3_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1603 | #define DMAC3_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1604 | #define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1605 | |
| mbed_official | 390:35c2c1cf29cd | 1606 | #define DMAC3_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1607 | #define DMAC3_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1608 | #define DMAC3_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1609 | #define DMAC3_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1610 | #define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1611 | #define DMAC3_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1612 | #define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1613 | #define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1614 | #define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1615 | #define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1616 | #define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1617 | |
| mbed_official | 390:35c2c1cf29cd | 1618 | #define DMAC3_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1619 | #define DMAC3_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1620 | #define DMAC3_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1621 | #define DMAC3_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1622 | #define DMAC3_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1623 | #define DMAC3_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1624 | #define DMAC3_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1625 | #define DMAC3_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1626 | #define DMAC3_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1627 | #define DMAC3_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1628 | #define DMAC3_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1629 | #define DMAC3_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1630 | #define DMAC3_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1631 | #define DMAC3_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1632 | #define DMAC3_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1633 | #define DMAC3_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1634 | #define DMAC3_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1635 | #define DMAC3_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1636 | |
| mbed_official | 390:35c2c1cf29cd | 1637 | #define DMAC3_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1638 | |
| mbed_official | 390:35c2c1cf29cd | 1639 | #define DMAC3_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1640 | #define DMAC3_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1641 | |
| mbed_official | 390:35c2c1cf29cd | 1642 | #define DMAC3_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1643 | |
| mbed_official | 390:35c2c1cf29cd | 1644 | #define DMAC3_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1645 | |
| mbed_official | 390:35c2c1cf29cd | 1646 | /* ---- DMAC4 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1647 | #define DMAC4_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1648 | |
| mbed_official | 390:35c2c1cf29cd | 1649 | #define DMAC4_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1650 | |
| mbed_official | 390:35c2c1cf29cd | 1651 | #define DMAC4_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1652 | |
| mbed_official | 390:35c2c1cf29cd | 1653 | #define DMAC4_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1654 | |
| mbed_official | 390:35c2c1cf29cd | 1655 | #define DMAC4_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1656 | |
| mbed_official | 390:35c2c1cf29cd | 1657 | #define DMAC4_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1658 | |
| mbed_official | 390:35c2c1cf29cd | 1659 | #define DMAC4_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1660 | |
| mbed_official | 390:35c2c1cf29cd | 1661 | #define DMAC4_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1662 | |
| mbed_official | 390:35c2c1cf29cd | 1663 | #define DMAC4_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1664 | |
| mbed_official | 390:35c2c1cf29cd | 1665 | #define DMAC4_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1666 | #define DMAC4_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1667 | #define DMAC4_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1668 | #define DMAC4_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1669 | #define DMAC4_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1670 | #define DMAC4_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1671 | #define DMAC4_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1672 | #define DMAC4_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1673 | #define DMAC4_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1674 | #define DMAC4_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1675 | #define DMAC4_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1676 | #define DMAC4_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1677 | #define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1678 | |
| mbed_official | 390:35c2c1cf29cd | 1679 | #define DMAC4_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1680 | #define DMAC4_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1681 | #define DMAC4_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1682 | #define DMAC4_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1683 | #define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1684 | #define DMAC4_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1685 | #define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1686 | #define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1687 | #define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1688 | #define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1689 | #define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1690 | |
| mbed_official | 390:35c2c1cf29cd | 1691 | #define DMAC4_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1692 | #define DMAC4_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1693 | #define DMAC4_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1694 | #define DMAC4_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1695 | #define DMAC4_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1696 | #define DMAC4_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1697 | #define DMAC4_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1698 | #define DMAC4_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1699 | #define DMAC4_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1700 | #define DMAC4_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1701 | #define DMAC4_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1702 | #define DMAC4_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1703 | #define DMAC4_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1704 | #define DMAC4_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1705 | #define DMAC4_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1706 | #define DMAC4_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1707 | #define DMAC4_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1708 | #define DMAC4_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1709 | |
| mbed_official | 390:35c2c1cf29cd | 1710 | #define DMAC4_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1711 | |
| mbed_official | 390:35c2c1cf29cd | 1712 | #define DMAC4_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1713 | #define DMAC4_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1714 | |
| mbed_official | 390:35c2c1cf29cd | 1715 | #define DMAC4_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1716 | |
| mbed_official | 390:35c2c1cf29cd | 1717 | #define DMAC4_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1718 | |
| mbed_official | 390:35c2c1cf29cd | 1719 | /* ---- DMAC5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1720 | #define DMAC5_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1721 | |
| mbed_official | 390:35c2c1cf29cd | 1722 | #define DMAC5_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1723 | |
| mbed_official | 390:35c2c1cf29cd | 1724 | #define DMAC5_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1725 | |
| mbed_official | 390:35c2c1cf29cd | 1726 | #define DMAC5_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1727 | |
| mbed_official | 390:35c2c1cf29cd | 1728 | #define DMAC5_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1729 | |
| mbed_official | 390:35c2c1cf29cd | 1730 | #define DMAC5_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1731 | |
| mbed_official | 390:35c2c1cf29cd | 1732 | #define DMAC5_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1733 | |
| mbed_official | 390:35c2c1cf29cd | 1734 | #define DMAC5_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1735 | |
| mbed_official | 390:35c2c1cf29cd | 1736 | #define DMAC5_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1737 | |
| mbed_official | 390:35c2c1cf29cd | 1738 | #define DMAC5_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1739 | #define DMAC5_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1740 | #define DMAC5_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1741 | #define DMAC5_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1742 | #define DMAC5_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1743 | #define DMAC5_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1744 | #define DMAC5_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1745 | #define DMAC5_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1746 | #define DMAC5_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1747 | #define DMAC5_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1748 | #define DMAC5_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1749 | #define DMAC5_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1750 | #define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1751 | |
| mbed_official | 390:35c2c1cf29cd | 1752 | #define DMAC5_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1753 | #define DMAC5_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1754 | #define DMAC5_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1755 | #define DMAC5_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1756 | #define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1757 | #define DMAC5_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1758 | #define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1759 | #define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1760 | #define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1761 | #define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1762 | #define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1763 | |
| mbed_official | 390:35c2c1cf29cd | 1764 | #define DMAC5_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1765 | #define DMAC5_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1766 | #define DMAC5_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1767 | #define DMAC5_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1768 | #define DMAC5_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1769 | #define DMAC5_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1770 | #define DMAC5_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1771 | #define DMAC5_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1772 | #define DMAC5_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1773 | #define DMAC5_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1774 | #define DMAC5_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1775 | #define DMAC5_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1776 | #define DMAC5_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1777 | #define DMAC5_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1778 | #define DMAC5_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1779 | #define DMAC5_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1780 | #define DMAC5_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1781 | #define DMAC5_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1782 | |
| mbed_official | 390:35c2c1cf29cd | 1783 | #define DMAC5_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1784 | |
| mbed_official | 390:35c2c1cf29cd | 1785 | #define DMAC5_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1786 | #define DMAC5_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1787 | |
| mbed_official | 390:35c2c1cf29cd | 1788 | #define DMAC5_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1789 | |
| mbed_official | 390:35c2c1cf29cd | 1790 | #define DMAC5_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1791 | |
| mbed_official | 390:35c2c1cf29cd | 1792 | /* ---- DMAC6 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1793 | #define DMAC6_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1794 | |
| mbed_official | 390:35c2c1cf29cd | 1795 | #define DMAC6_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1796 | |
| mbed_official | 390:35c2c1cf29cd | 1797 | #define DMAC6_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1798 | |
| mbed_official | 390:35c2c1cf29cd | 1799 | #define DMAC6_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1800 | |
| mbed_official | 390:35c2c1cf29cd | 1801 | #define DMAC6_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1802 | |
| mbed_official | 390:35c2c1cf29cd | 1803 | #define DMAC6_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1804 | |
| mbed_official | 390:35c2c1cf29cd | 1805 | #define DMAC6_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1806 | |
| mbed_official | 390:35c2c1cf29cd | 1807 | #define DMAC6_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1808 | |
| mbed_official | 390:35c2c1cf29cd | 1809 | #define DMAC6_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1810 | |
| mbed_official | 390:35c2c1cf29cd | 1811 | #define DMAC6_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1812 | #define DMAC6_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1813 | #define DMAC6_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1814 | #define DMAC6_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1815 | #define DMAC6_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1816 | #define DMAC6_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1817 | #define DMAC6_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1818 | #define DMAC6_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1819 | #define DMAC6_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1820 | #define DMAC6_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1821 | #define DMAC6_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1822 | #define DMAC6_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1823 | #define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1824 | |
| mbed_official | 390:35c2c1cf29cd | 1825 | #define DMAC6_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1826 | #define DMAC6_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1827 | #define DMAC6_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1828 | #define DMAC6_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1829 | #define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1830 | #define DMAC6_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1831 | #define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1832 | #define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1833 | #define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1834 | #define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1835 | #define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1836 | |
| mbed_official | 390:35c2c1cf29cd | 1837 | #define DMAC6_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1838 | #define DMAC6_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1839 | #define DMAC6_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1840 | #define DMAC6_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1841 | #define DMAC6_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1842 | #define DMAC6_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1843 | #define DMAC6_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1844 | #define DMAC6_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1845 | #define DMAC6_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1846 | #define DMAC6_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1847 | #define DMAC6_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1848 | #define DMAC6_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1849 | #define DMAC6_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1850 | #define DMAC6_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1851 | #define DMAC6_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1852 | #define DMAC6_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1853 | #define DMAC6_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1854 | #define DMAC6_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1855 | |
| mbed_official | 390:35c2c1cf29cd | 1856 | #define DMAC6_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1857 | |
| mbed_official | 390:35c2c1cf29cd | 1858 | #define DMAC6_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1859 | #define DMAC6_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1860 | |
| mbed_official | 390:35c2c1cf29cd | 1861 | #define DMAC6_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1862 | |
| mbed_official | 390:35c2c1cf29cd | 1863 | #define DMAC6_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1864 | |
| mbed_official | 390:35c2c1cf29cd | 1865 | /* ---- DMAC7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1866 | #define DMAC7_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1867 | |
| mbed_official | 390:35c2c1cf29cd | 1868 | #define DMAC7_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1869 | |
| mbed_official | 390:35c2c1cf29cd | 1870 | #define DMAC7_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1871 | |
| mbed_official | 390:35c2c1cf29cd | 1872 | #define DMAC7_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1873 | |
| mbed_official | 390:35c2c1cf29cd | 1874 | #define DMAC7_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1875 | |
| mbed_official | 390:35c2c1cf29cd | 1876 | #define DMAC7_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1877 | |
| mbed_official | 390:35c2c1cf29cd | 1878 | #define DMAC7_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1879 | |
| mbed_official | 390:35c2c1cf29cd | 1880 | #define DMAC7_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1881 | |
| mbed_official | 390:35c2c1cf29cd | 1882 | #define DMAC7_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1883 | |
| mbed_official | 390:35c2c1cf29cd | 1884 | #define DMAC7_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1885 | #define DMAC7_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1886 | #define DMAC7_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1887 | #define DMAC7_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1888 | #define DMAC7_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1889 | #define DMAC7_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1890 | #define DMAC7_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1891 | #define DMAC7_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1892 | #define DMAC7_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1893 | #define DMAC7_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1894 | #define DMAC7_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 1895 | #define DMAC7_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 1896 | #define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1897 | |
| mbed_official | 390:35c2c1cf29cd | 1898 | #define DMAC7_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1899 | #define DMAC7_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1900 | #define DMAC7_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1901 | #define DMAC7_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1902 | #define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1903 | #define DMAC7_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1904 | #define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1905 | #define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1906 | #define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 1907 | #define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1908 | #define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 1909 | |
| mbed_official | 390:35c2c1cf29cd | 1910 | #define DMAC7_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1911 | #define DMAC7_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1912 | #define DMAC7_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1913 | #define DMAC7_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1914 | #define DMAC7_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1915 | #define DMAC7_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 1916 | #define DMAC7_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1917 | #define DMAC7_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 1918 | #define DMAC7_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 1919 | #define DMAC7_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 1920 | #define DMAC7_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 1921 | #define DMAC7_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 1922 | #define DMAC7_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 1923 | #define DMAC7_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 1924 | #define DMAC7_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 1925 | #define DMAC7_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 1926 | #define DMAC7_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 1927 | #define DMAC7_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 1928 | |
| mbed_official | 390:35c2c1cf29cd | 1929 | #define DMAC7_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1930 | |
| mbed_official | 390:35c2c1cf29cd | 1931 | #define DMAC7_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1932 | #define DMAC7_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 1933 | |
| mbed_official | 390:35c2c1cf29cd | 1934 | #define DMAC7_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1935 | |
| mbed_official | 390:35c2c1cf29cd | 1936 | #define DMAC7_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1937 | |
| mbed_official | 390:35c2c1cf29cd | 1938 | /* ---- DMAC0-7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1939 | #define DMAC07_DCTRL_0_7_PR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1940 | #define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1941 | #define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1942 | #define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1943 | |
| mbed_official | 390:35c2c1cf29cd | 1944 | #define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1945 | #define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1946 | #define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1947 | #define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1948 | #define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1949 | #define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1950 | #define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1951 | #define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1952 | |
| mbed_official | 390:35c2c1cf29cd | 1953 | #define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1954 | #define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1955 | #define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1956 | #define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1957 | #define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1958 | #define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1959 | #define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1960 | #define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1961 | |
| mbed_official | 390:35c2c1cf29cd | 1962 | #define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1963 | #define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1964 | #define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1965 | #define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1966 | #define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1967 | #define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1968 | #define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1969 | #define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1970 | |
| mbed_official | 390:35c2c1cf29cd | 1971 | #define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1972 | #define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1973 | #define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1974 | #define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1975 | #define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1976 | #define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1977 | #define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1978 | #define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1979 | |
| mbed_official | 390:35c2c1cf29cd | 1980 | #define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1981 | #define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 1982 | #define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 1983 | #define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 1984 | #define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 1985 | #define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 1986 | #define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 1987 | #define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 1988 | |
| mbed_official | 390:35c2c1cf29cd | 1989 | /* ---- DMAC8 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 1990 | #define DMAC8_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1991 | |
| mbed_official | 390:35c2c1cf29cd | 1992 | #define DMAC8_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1993 | |
| mbed_official | 390:35c2c1cf29cd | 1994 | #define DMAC8_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1995 | |
| mbed_official | 390:35c2c1cf29cd | 1996 | #define DMAC8_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1997 | |
| mbed_official | 390:35c2c1cf29cd | 1998 | #define DMAC8_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 1999 | |
| mbed_official | 390:35c2c1cf29cd | 2000 | #define DMAC8_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2001 | |
| mbed_official | 390:35c2c1cf29cd | 2002 | #define DMAC8_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2003 | |
| mbed_official | 390:35c2c1cf29cd | 2004 | #define DMAC8_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2005 | |
| mbed_official | 390:35c2c1cf29cd | 2006 | #define DMAC8_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2007 | |
| mbed_official | 390:35c2c1cf29cd | 2008 | #define DMAC8_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2009 | #define DMAC8_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2010 | #define DMAC8_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2011 | #define DMAC8_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2012 | #define DMAC8_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2013 | #define DMAC8_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2014 | #define DMAC8_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2015 | #define DMAC8_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2016 | #define DMAC8_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2017 | #define DMAC8_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2018 | #define DMAC8_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2019 | #define DMAC8_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2020 | #define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2021 | |
| mbed_official | 390:35c2c1cf29cd | 2022 | #define DMAC8_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2023 | #define DMAC8_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2024 | #define DMAC8_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2025 | #define DMAC8_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2026 | #define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2027 | #define DMAC8_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2028 | #define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2029 | #define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2030 | #define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2031 | #define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2032 | #define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2033 | |
| mbed_official | 390:35c2c1cf29cd | 2034 | #define DMAC8_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2035 | #define DMAC8_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2036 | #define DMAC8_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2037 | #define DMAC8_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2038 | #define DMAC8_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2039 | #define DMAC8_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2040 | #define DMAC8_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2041 | #define DMAC8_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2042 | #define DMAC8_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2043 | #define DMAC8_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2044 | #define DMAC8_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2045 | #define DMAC8_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2046 | #define DMAC8_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2047 | #define DMAC8_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2048 | #define DMAC8_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2049 | #define DMAC8_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2050 | #define DMAC8_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2051 | #define DMAC8_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2052 | |
| mbed_official | 390:35c2c1cf29cd | 2053 | #define DMAC8_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2054 | |
| mbed_official | 390:35c2c1cf29cd | 2055 | #define DMAC8_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2056 | #define DMAC8_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2057 | |
| mbed_official | 390:35c2c1cf29cd | 2058 | #define DMAC8_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2059 | |
| mbed_official | 390:35c2c1cf29cd | 2060 | #define DMAC8_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2061 | |
| mbed_official | 390:35c2c1cf29cd | 2062 | /* ---- DMAC9 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2063 | #define DMAC9_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2064 | |
| mbed_official | 390:35c2c1cf29cd | 2065 | #define DMAC9_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2066 | |
| mbed_official | 390:35c2c1cf29cd | 2067 | #define DMAC9_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2068 | |
| mbed_official | 390:35c2c1cf29cd | 2069 | #define DMAC9_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2070 | |
| mbed_official | 390:35c2c1cf29cd | 2071 | #define DMAC9_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2072 | |
| mbed_official | 390:35c2c1cf29cd | 2073 | #define DMAC9_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2074 | |
| mbed_official | 390:35c2c1cf29cd | 2075 | #define DMAC9_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2076 | |
| mbed_official | 390:35c2c1cf29cd | 2077 | #define DMAC9_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2078 | |
| mbed_official | 390:35c2c1cf29cd | 2079 | #define DMAC9_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2080 | |
| mbed_official | 390:35c2c1cf29cd | 2081 | #define DMAC9_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2082 | #define DMAC9_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2083 | #define DMAC9_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2084 | #define DMAC9_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2085 | #define DMAC9_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2086 | #define DMAC9_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2087 | #define DMAC9_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2088 | #define DMAC9_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2089 | #define DMAC9_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2090 | #define DMAC9_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2091 | #define DMAC9_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2092 | #define DMAC9_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2093 | #define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2094 | |
| mbed_official | 390:35c2c1cf29cd | 2095 | #define DMAC9_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2096 | #define DMAC9_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2097 | #define DMAC9_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2098 | #define DMAC9_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2099 | #define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2100 | #define DMAC9_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2101 | #define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2102 | #define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2103 | #define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2104 | #define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2105 | #define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2106 | |
| mbed_official | 390:35c2c1cf29cd | 2107 | #define DMAC9_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2108 | #define DMAC9_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2109 | #define DMAC9_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2110 | #define DMAC9_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2111 | #define DMAC9_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2112 | #define DMAC9_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2113 | #define DMAC9_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2114 | #define DMAC9_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2115 | #define DMAC9_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2116 | #define DMAC9_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2117 | #define DMAC9_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2118 | #define DMAC9_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2119 | #define DMAC9_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2120 | #define DMAC9_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2121 | #define DMAC9_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2122 | #define DMAC9_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2123 | #define DMAC9_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2124 | #define DMAC9_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2125 | |
| mbed_official | 390:35c2c1cf29cd | 2126 | #define DMAC9_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2127 | |
| mbed_official | 390:35c2c1cf29cd | 2128 | #define DMAC9_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2129 | #define DMAC9_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2130 | |
| mbed_official | 390:35c2c1cf29cd | 2131 | #define DMAC9_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2132 | |
| mbed_official | 390:35c2c1cf29cd | 2133 | #define DMAC9_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2134 | |
| mbed_official | 390:35c2c1cf29cd | 2135 | /* ---- DMAC10 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2136 | #define DMAC10_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2137 | |
| mbed_official | 390:35c2c1cf29cd | 2138 | #define DMAC10_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2139 | |
| mbed_official | 390:35c2c1cf29cd | 2140 | #define DMAC10_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2141 | |
| mbed_official | 390:35c2c1cf29cd | 2142 | #define DMAC10_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2143 | |
| mbed_official | 390:35c2c1cf29cd | 2144 | #define DMAC10_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2145 | |
| mbed_official | 390:35c2c1cf29cd | 2146 | #define DMAC10_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2147 | |
| mbed_official | 390:35c2c1cf29cd | 2148 | #define DMAC10_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2149 | |
| mbed_official | 390:35c2c1cf29cd | 2150 | #define DMAC10_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2151 | |
| mbed_official | 390:35c2c1cf29cd | 2152 | #define DMAC10_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2153 | |
| mbed_official | 390:35c2c1cf29cd | 2154 | #define DMAC10_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2155 | #define DMAC10_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2156 | #define DMAC10_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2157 | #define DMAC10_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2158 | #define DMAC10_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2159 | #define DMAC10_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2160 | #define DMAC10_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2161 | #define DMAC10_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2162 | #define DMAC10_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2163 | #define DMAC10_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2164 | #define DMAC10_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2165 | #define DMAC10_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2166 | #define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2167 | |
| mbed_official | 390:35c2c1cf29cd | 2168 | #define DMAC10_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2169 | #define DMAC10_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2170 | #define DMAC10_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2171 | #define DMAC10_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2172 | #define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2173 | #define DMAC10_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2174 | #define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2175 | #define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2176 | #define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2177 | #define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2178 | #define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2179 | |
| mbed_official | 390:35c2c1cf29cd | 2180 | #define DMAC10_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2181 | #define DMAC10_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2182 | #define DMAC10_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2183 | #define DMAC10_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2184 | #define DMAC10_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2185 | #define DMAC10_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2186 | #define DMAC10_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2187 | #define DMAC10_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2188 | #define DMAC10_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2189 | #define DMAC10_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2190 | #define DMAC10_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2191 | #define DMAC10_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2192 | #define DMAC10_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2193 | #define DMAC10_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2194 | #define DMAC10_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2195 | #define DMAC10_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2196 | #define DMAC10_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2197 | #define DMAC10_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2198 | |
| mbed_official | 390:35c2c1cf29cd | 2199 | #define DMAC10_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2200 | |
| mbed_official | 390:35c2c1cf29cd | 2201 | #define DMAC10_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2202 | #define DMAC10_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2203 | |
| mbed_official | 390:35c2c1cf29cd | 2204 | #define DMAC10_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2205 | |
| mbed_official | 390:35c2c1cf29cd | 2206 | #define DMAC10_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2207 | |
| mbed_official | 390:35c2c1cf29cd | 2208 | /* ---- DMAC11 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2209 | #define DMAC11_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2210 | |
| mbed_official | 390:35c2c1cf29cd | 2211 | #define DMAC11_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2212 | |
| mbed_official | 390:35c2c1cf29cd | 2213 | #define DMAC11_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2214 | |
| mbed_official | 390:35c2c1cf29cd | 2215 | #define DMAC11_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2216 | |
| mbed_official | 390:35c2c1cf29cd | 2217 | #define DMAC11_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2218 | |
| mbed_official | 390:35c2c1cf29cd | 2219 | #define DMAC11_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2220 | |
| mbed_official | 390:35c2c1cf29cd | 2221 | #define DMAC11_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2222 | |
| mbed_official | 390:35c2c1cf29cd | 2223 | #define DMAC11_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2224 | |
| mbed_official | 390:35c2c1cf29cd | 2225 | #define DMAC11_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2226 | |
| mbed_official | 390:35c2c1cf29cd | 2227 | #define DMAC11_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2228 | #define DMAC11_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2229 | #define DMAC11_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2230 | #define DMAC11_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2231 | #define DMAC11_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2232 | #define DMAC11_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2233 | #define DMAC11_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2234 | #define DMAC11_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2235 | #define DMAC11_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2236 | #define DMAC11_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2237 | #define DMAC11_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2238 | #define DMAC11_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2239 | #define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2240 | |
| mbed_official | 390:35c2c1cf29cd | 2241 | #define DMAC11_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2242 | #define DMAC11_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2243 | #define DMAC11_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2244 | #define DMAC11_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2245 | #define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2246 | #define DMAC11_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2247 | #define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2248 | #define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2249 | #define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2250 | #define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2251 | #define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2252 | |
| mbed_official | 390:35c2c1cf29cd | 2253 | #define DMAC11_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2254 | #define DMAC11_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2255 | #define DMAC11_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2256 | #define DMAC11_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2257 | #define DMAC11_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2258 | #define DMAC11_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2259 | #define DMAC11_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2260 | #define DMAC11_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2261 | #define DMAC11_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2262 | #define DMAC11_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2263 | #define DMAC11_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2264 | #define DMAC11_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2265 | #define DMAC11_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2266 | #define DMAC11_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2267 | #define DMAC11_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2268 | #define DMAC11_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2269 | #define DMAC11_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2270 | #define DMAC11_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2271 | |
| mbed_official | 390:35c2c1cf29cd | 2272 | #define DMAC11_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2273 | |
| mbed_official | 390:35c2c1cf29cd | 2274 | #define DMAC11_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2275 | #define DMAC11_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2276 | |
| mbed_official | 390:35c2c1cf29cd | 2277 | #define DMAC11_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2278 | |
| mbed_official | 390:35c2c1cf29cd | 2279 | #define DMAC11_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2280 | |
| mbed_official | 390:35c2c1cf29cd | 2281 | /* ---- DMAC12 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2282 | #define DMAC12_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2283 | |
| mbed_official | 390:35c2c1cf29cd | 2284 | #define DMAC12_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2285 | |
| mbed_official | 390:35c2c1cf29cd | 2286 | #define DMAC12_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2287 | |
| mbed_official | 390:35c2c1cf29cd | 2288 | #define DMAC12_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2289 | |
| mbed_official | 390:35c2c1cf29cd | 2290 | #define DMAC12_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2291 | |
| mbed_official | 390:35c2c1cf29cd | 2292 | #define DMAC12_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2293 | |
| mbed_official | 390:35c2c1cf29cd | 2294 | #define DMAC12_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2295 | |
| mbed_official | 390:35c2c1cf29cd | 2296 | #define DMAC12_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2297 | |
| mbed_official | 390:35c2c1cf29cd | 2298 | #define DMAC12_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2299 | |
| mbed_official | 390:35c2c1cf29cd | 2300 | #define DMAC12_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2301 | #define DMAC12_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2302 | #define DMAC12_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2303 | #define DMAC12_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2304 | #define DMAC12_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2305 | #define DMAC12_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2306 | #define DMAC12_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2307 | #define DMAC12_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2308 | #define DMAC12_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2309 | #define DMAC12_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2310 | #define DMAC12_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2311 | #define DMAC12_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2312 | #define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2313 | |
| mbed_official | 390:35c2c1cf29cd | 2314 | #define DMAC12_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2315 | #define DMAC12_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2316 | #define DMAC12_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2317 | #define DMAC12_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2318 | #define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2319 | #define DMAC12_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2320 | #define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2321 | #define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2322 | #define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2323 | #define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2324 | #define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2325 | |
| mbed_official | 390:35c2c1cf29cd | 2326 | #define DMAC12_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2327 | #define DMAC12_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2328 | #define DMAC12_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2329 | #define DMAC12_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2330 | #define DMAC12_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2331 | #define DMAC12_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2332 | #define DMAC12_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2333 | #define DMAC12_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2334 | #define DMAC12_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2335 | #define DMAC12_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2336 | #define DMAC12_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2337 | #define DMAC12_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2338 | #define DMAC12_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2339 | #define DMAC12_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2340 | #define DMAC12_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2341 | #define DMAC12_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2342 | #define DMAC12_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2343 | #define DMAC12_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2344 | |
| mbed_official | 390:35c2c1cf29cd | 2345 | #define DMAC12_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2346 | |
| mbed_official | 390:35c2c1cf29cd | 2347 | #define DMAC12_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2348 | #define DMAC12_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2349 | |
| mbed_official | 390:35c2c1cf29cd | 2350 | #define DMAC12_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2351 | |
| mbed_official | 390:35c2c1cf29cd | 2352 | #define DMAC12_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2353 | |
| mbed_official | 390:35c2c1cf29cd | 2354 | /* ---- DMAC13 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2355 | #define DMAC13_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2356 | |
| mbed_official | 390:35c2c1cf29cd | 2357 | #define DMAC13_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2358 | |
| mbed_official | 390:35c2c1cf29cd | 2359 | #define DMAC13_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2360 | |
| mbed_official | 390:35c2c1cf29cd | 2361 | #define DMAC13_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2362 | |
| mbed_official | 390:35c2c1cf29cd | 2363 | #define DMAC13_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2364 | |
| mbed_official | 390:35c2c1cf29cd | 2365 | #define DMAC13_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2366 | |
| mbed_official | 390:35c2c1cf29cd | 2367 | #define DMAC13_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2368 | |
| mbed_official | 390:35c2c1cf29cd | 2369 | #define DMAC13_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2370 | |
| mbed_official | 390:35c2c1cf29cd | 2371 | #define DMAC13_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2372 | |
| mbed_official | 390:35c2c1cf29cd | 2373 | #define DMAC13_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2374 | #define DMAC13_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2375 | #define DMAC13_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2376 | #define DMAC13_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2377 | #define DMAC13_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2378 | #define DMAC13_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2379 | #define DMAC13_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2380 | #define DMAC13_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2381 | #define DMAC13_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2382 | #define DMAC13_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2383 | #define DMAC13_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2384 | #define DMAC13_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2385 | #define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2386 | |
| mbed_official | 390:35c2c1cf29cd | 2387 | #define DMAC13_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2388 | #define DMAC13_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2389 | #define DMAC13_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2390 | #define DMAC13_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2391 | #define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2392 | #define DMAC13_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2393 | #define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2394 | #define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2395 | #define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2396 | #define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2397 | #define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2398 | |
| mbed_official | 390:35c2c1cf29cd | 2399 | #define DMAC13_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2400 | #define DMAC13_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2401 | #define DMAC13_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2402 | #define DMAC13_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2403 | #define DMAC13_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2404 | #define DMAC13_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2405 | #define DMAC13_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2406 | #define DMAC13_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2407 | #define DMAC13_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2408 | #define DMAC13_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2409 | #define DMAC13_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2410 | #define DMAC13_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2411 | #define DMAC13_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2412 | #define DMAC13_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2413 | #define DMAC13_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2414 | #define DMAC13_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2415 | #define DMAC13_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2416 | #define DMAC13_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2417 | |
| mbed_official | 390:35c2c1cf29cd | 2418 | #define DMAC13_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2419 | |
| mbed_official | 390:35c2c1cf29cd | 2420 | #define DMAC13_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2421 | #define DMAC13_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2422 | |
| mbed_official | 390:35c2c1cf29cd | 2423 | #define DMAC13_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2424 | |
| mbed_official | 390:35c2c1cf29cd | 2425 | #define DMAC13_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2426 | |
| mbed_official | 390:35c2c1cf29cd | 2427 | /* ---- DMAC14 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2428 | #define DMAC14_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2429 | |
| mbed_official | 390:35c2c1cf29cd | 2430 | #define DMAC14_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2431 | |
| mbed_official | 390:35c2c1cf29cd | 2432 | #define DMAC14_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2433 | |
| mbed_official | 390:35c2c1cf29cd | 2434 | #define DMAC14_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2435 | |
| mbed_official | 390:35c2c1cf29cd | 2436 | #define DMAC14_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2437 | |
| mbed_official | 390:35c2c1cf29cd | 2438 | #define DMAC14_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2439 | |
| mbed_official | 390:35c2c1cf29cd | 2440 | #define DMAC14_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2441 | |
| mbed_official | 390:35c2c1cf29cd | 2442 | #define DMAC14_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2443 | |
| mbed_official | 390:35c2c1cf29cd | 2444 | #define DMAC14_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2445 | |
| mbed_official | 390:35c2c1cf29cd | 2446 | #define DMAC14_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2447 | #define DMAC14_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2448 | #define DMAC14_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2449 | #define DMAC14_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2450 | #define DMAC14_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2451 | #define DMAC14_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2452 | #define DMAC14_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2453 | #define DMAC14_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2454 | #define DMAC14_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2455 | #define DMAC14_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2456 | #define DMAC14_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2457 | #define DMAC14_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2458 | #define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2459 | |
| mbed_official | 390:35c2c1cf29cd | 2460 | #define DMAC14_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2461 | #define DMAC14_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2462 | #define DMAC14_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2463 | #define DMAC14_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2464 | #define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2465 | #define DMAC14_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2466 | #define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2467 | #define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2468 | #define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2469 | #define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2470 | #define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2471 | |
| mbed_official | 390:35c2c1cf29cd | 2472 | #define DMAC14_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2473 | #define DMAC14_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2474 | #define DMAC14_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2475 | #define DMAC14_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2476 | #define DMAC14_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2477 | #define DMAC14_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2478 | #define DMAC14_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2479 | #define DMAC14_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2480 | #define DMAC14_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2481 | #define DMAC14_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2482 | #define DMAC14_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2483 | #define DMAC14_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2484 | #define DMAC14_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2485 | #define DMAC14_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2486 | #define DMAC14_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2487 | #define DMAC14_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2488 | #define DMAC14_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2489 | #define DMAC14_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2490 | |
| mbed_official | 390:35c2c1cf29cd | 2491 | #define DMAC14_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2492 | |
| mbed_official | 390:35c2c1cf29cd | 2493 | #define DMAC14_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2494 | #define DMAC14_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2495 | |
| mbed_official | 390:35c2c1cf29cd | 2496 | #define DMAC14_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2497 | |
| mbed_official | 390:35c2c1cf29cd | 2498 | #define DMAC14_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2499 | |
| mbed_official | 390:35c2c1cf29cd | 2500 | /* ---- DMAC15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2501 | #define DMAC15_N0SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2502 | |
| mbed_official | 390:35c2c1cf29cd | 2503 | #define DMAC15_N0DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2504 | |
| mbed_official | 390:35c2c1cf29cd | 2505 | #define DMAC15_N0TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2506 | |
| mbed_official | 390:35c2c1cf29cd | 2507 | #define DMAC15_N1SA_n_SA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2508 | |
| mbed_official | 390:35c2c1cf29cd | 2509 | #define DMAC15_N1DA_n_DA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2510 | |
| mbed_official | 390:35c2c1cf29cd | 2511 | #define DMAC15_N1TB_n_TB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2512 | |
| mbed_official | 390:35c2c1cf29cd | 2513 | #define DMAC15_CRSA_n_CRSA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2514 | |
| mbed_official | 390:35c2c1cf29cd | 2515 | #define DMAC15_CRDA_n_CRDA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2516 | |
| mbed_official | 390:35c2c1cf29cd | 2517 | #define DMAC15_CRTB_n_CRTB_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2518 | |
| mbed_official | 390:35c2c1cf29cd | 2519 | #define DMAC15_CHSTAT_n_EN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2520 | #define DMAC15_CHSTAT_n_RQST_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2521 | #define DMAC15_CHSTAT_n_TACT_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2522 | #define DMAC15_CHSTAT_n_SUS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2523 | #define DMAC15_CHSTAT_n_ER_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2524 | #define DMAC15_CHSTAT_n_END_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2525 | #define DMAC15_CHSTAT_n_TC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2526 | #define DMAC15_CHSTAT_n_SR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2527 | #define DMAC15_CHSTAT_n_DL_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2528 | #define DMAC15_CHSTAT_n_DW_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2529 | #define DMAC15_CHSTAT_n_DER_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2530 | #define DMAC15_CHSTAT_n_MODE_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 2531 | #define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2532 | |
| mbed_official | 390:35c2c1cf29cd | 2533 | #define DMAC15_CHCTRL_n_SETEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2534 | #define DMAC15_CHCTRL_n_CLREN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2535 | #define DMAC15_CHCTRL_n_STG_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2536 | #define DMAC15_CHCTRL_n_SWRST_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2537 | #define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2538 | #define DMAC15_CHCTRL_n_CLREND_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2539 | #define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2540 | #define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2541 | #define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 2542 | #define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2543 | #define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u) |
| mbed_official | 390:35c2c1cf29cd | 2544 | |
| mbed_official | 390:35c2c1cf29cd | 2545 | #define DMAC15_CHCFG_n_SEL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2546 | #define DMAC15_CHCFG_n_REQD_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2547 | #define DMAC15_CHCFG_n_LOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2548 | #define DMAC15_CHCFG_n_HIEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2549 | #define DMAC15_CHCFG_n_LVL_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2550 | #define DMAC15_CHCFG_n_AM_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 2551 | #define DMAC15_CHCFG_n_SDS_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2552 | #define DMAC15_CHCFG_n_DDS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2553 | #define DMAC15_CHCFG_n_SAD_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 2554 | #define DMAC15_CHCFG_n_DAD_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 2555 | #define DMAC15_CHCFG_n_TM_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 2556 | #define DMAC15_CHCFG_n_DEM_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 2557 | #define DMAC15_CHCFG_n_TCM_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 2558 | #define DMAC15_CHCFG_n_SBE_SHIFT (27u) |
| mbed_official | 390:35c2c1cf29cd | 2559 | #define DMAC15_CHCFG_n_RSEL_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 2560 | #define DMAC15_CHCFG_n_RSW_SHIFT (29u) |
| mbed_official | 390:35c2c1cf29cd | 2561 | #define DMAC15_CHCFG_n_REN_SHIFT (30u) |
| mbed_official | 390:35c2c1cf29cd | 2562 | #define DMAC15_CHCFG_n_DMS_SHIFT (31u) |
| mbed_official | 390:35c2c1cf29cd | 2563 | |
| mbed_official | 390:35c2c1cf29cd | 2564 | #define DMAC15_CHITVL_n_ITVL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2565 | |
| mbed_official | 390:35c2c1cf29cd | 2566 | #define DMAC15_CHEXT_n_SCA_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2567 | #define DMAC15_CHEXT_n_DCA_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 2568 | |
| mbed_official | 390:35c2c1cf29cd | 2569 | #define DMAC15_NXLA_n_NXLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2570 | |
| mbed_official | 390:35c2c1cf29cd | 2571 | #define DMAC15_CRLA_n_CRLA_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2572 | |
| mbed_official | 390:35c2c1cf29cd | 2573 | /* ---- DMAC8-15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2574 | #define DMAC815_DCTRL_8_15_PR_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2575 | #define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2576 | #define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2577 | #define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 2578 | |
| mbed_official | 390:35c2c1cf29cd | 2579 | #define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2580 | #define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2581 | #define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2582 | #define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2583 | #define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2584 | #define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2585 | #define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2586 | #define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2587 | |
| mbed_official | 390:35c2c1cf29cd | 2588 | #define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2589 | #define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2590 | #define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2591 | #define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2592 | #define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2593 | #define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2594 | #define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2595 | #define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2596 | |
| mbed_official | 390:35c2c1cf29cd | 2597 | #define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2598 | #define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2599 | #define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2600 | #define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2601 | #define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2602 | #define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2603 | #define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2604 | #define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2605 | |
| mbed_official | 390:35c2c1cf29cd | 2606 | #define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2607 | #define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2608 | #define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2609 | #define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2610 | #define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2611 | #define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2612 | #define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2613 | #define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2614 | |
| mbed_official | 390:35c2c1cf29cd | 2615 | #define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2616 | #define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 2617 | #define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2618 | #define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 2619 | #define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 2620 | #define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 2621 | #define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 2622 | #define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 2623 | |
| mbed_official | 390:35c2c1cf29cd | 2624 | /* ---- DMAC0-1 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2625 | #define DMAC01_DMARS_CH0_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2626 | #define DMAC01_DMARS_CH0_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2627 | #define DMAC01_DMARS_CH1_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2628 | #define DMAC01_DMARS_CH1_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2629 | |
| mbed_official | 390:35c2c1cf29cd | 2630 | /* ---- DMAC2-3 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2631 | #define DMAC23_DMARS_CH2_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2632 | #define DMAC23_DMARS_CH2_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2633 | #define DMAC23_DMARS_CH3_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2634 | #define DMAC23_DMARS_CH3_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2635 | |
| mbed_official | 390:35c2c1cf29cd | 2636 | /* ---- DMAC4-5 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2637 | #define DMAC45_DMARS_CH4_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2638 | #define DMAC45_DMARS_CH4_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2639 | #define DMAC45_DMARS_CH5_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2640 | #define DMAC45_DMARS_CH5_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2641 | |
| mbed_official | 390:35c2c1cf29cd | 2642 | /* ---- DMAC6-7 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2643 | #define DMAC67_DMARS_CH6_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2644 | #define DMAC67_DMARS_CH6_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2645 | #define DMAC67_DMARS_CH7_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2646 | #define DMAC67_DMARS_CH7_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2647 | |
| mbed_official | 390:35c2c1cf29cd | 2648 | /* ---- DMAC8-9 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2649 | #define DMAC89_DMARS_CH8_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2650 | #define DMAC89_DMARS_CH8_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2651 | #define DMAC89_DMARS_CH9_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2652 | #define DMAC89_DMARS_CH9_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2653 | |
| mbed_official | 390:35c2c1cf29cd | 2654 | /* ---- DMAC10-11 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2655 | #define DMAC1011_DMARS_CH10_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2656 | #define DMAC1011_DMARS_CH10_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2657 | #define DMAC1011_DMARS_CH11_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2658 | #define DMAC1011_DMARS_CH11_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2659 | |
| mbed_official | 390:35c2c1cf29cd | 2660 | /* ---- DMAC12-13 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2661 | #define DMAC1213_DMARS_CH12_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2662 | #define DMAC1213_DMARS_CH12_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2663 | #define DMAC1213_DMARS_CH13_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2664 | #define DMAC1213_DMARS_CH13_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2665 | |
| mbed_official | 390:35c2c1cf29cd | 2666 | /* ---- DMAC14-15 ---- */ |
| mbed_official | 390:35c2c1cf29cd | 2667 | #define DMAC1415_DMARS_CH14_RID_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 2668 | #define DMAC1415_DMARS_CH14_MID_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 2669 | #define DMAC1415_DMARS_CH15_RID_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 2670 | #define DMAC1415_DMARS_CH15_MID_SHIFT (18u) |
| mbed_official | 390:35c2c1cf29cd | 2671 | |
| mbed_official | 390:35c2c1cf29cd | 2672 | |
| mbed_official | 390:35c2c1cf29cd | 2673 | #endif /* DMAC_IOBITMASK_H */ |
| mbed_official | 390:35c2c1cf29cd | 2674 | |
| mbed_official | 390:35c2c1cf29cd | 2675 | /* End of File */ |
