Stuart Northfield
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h@390:35c2c1cf29cd, 2014-11-06 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Nov 06 11:00:10 2014 +0000
- Revision:
- 390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7
Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/
[RZ/A1H] mbed-RZ first release
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : bsc_iobitmask.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: 1115 $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: 2014-07-09 15:35:02 +0900#$ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : BSC register define header |
| mbed_official | 390:35c2c1cf29cd | 28 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef BSC_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define BSC_IOBITMASK_H |
| mbed_official | 390:35c2c1cf29cd | 31 | |
| mbed_official | 390:35c2c1cf29cd | 32 | |
| mbed_official | 390:35c2c1cf29cd | 33 | /* ==== Mask values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 34 | #define BSC_CMNCR_HIZCNT (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 35 | #define BSC_CMNCR_HIZMEM (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 36 | #define BSC_CMNCR_DPRTY (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 37 | #define BSC_CMNCR_AL0 (0x01000000uL) |
| mbed_official | 390:35c2c1cf29cd | 38 | #define BSC_CMNCR_TL0 (0x10000000uL) |
| mbed_official | 390:35c2c1cf29cd | 39 | |
| mbed_official | 390:35c2c1cf29cd | 40 | #define BSC_CS0BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 41 | #define BSC_CS0BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 42 | #define BSC_CS0BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 43 | #define BSC_CS0BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 44 | #define BSC_CS0BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 45 | #define BSC_CS0BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 46 | #define BSC_CS0BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 47 | |
| mbed_official | 390:35c2c1cf29cd | 48 | #define BSC_CS1BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 49 | #define BSC_CS1BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 50 | #define BSC_CS1BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 51 | #define BSC_CS1BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 52 | #define BSC_CS1BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 53 | #define BSC_CS1BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 54 | #define BSC_CS1BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 55 | |
| mbed_official | 390:35c2c1cf29cd | 56 | #define BSC_CS2BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 57 | #define BSC_CS2BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 58 | #define BSC_CS2BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 59 | #define BSC_CS2BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 60 | #define BSC_CS2BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 61 | #define BSC_CS2BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 62 | #define BSC_CS2BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 63 | |
| mbed_official | 390:35c2c1cf29cd | 64 | #define BSC_CS3BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 65 | #define BSC_CS3BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 66 | #define BSC_CS3BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 67 | #define BSC_CS3BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 68 | #define BSC_CS3BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 69 | #define BSC_CS3BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 70 | #define BSC_CS3BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 71 | |
| mbed_official | 390:35c2c1cf29cd | 72 | #define BSC_CS4BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 73 | #define BSC_CS4BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 74 | #define BSC_CS4BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 75 | #define BSC_CS4BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 76 | #define BSC_CS4BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 77 | #define BSC_CS4BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 78 | #define BSC_CS4BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 79 | |
| mbed_official | 390:35c2c1cf29cd | 80 | #define BSC_CS5BCR_BSZ (0x00000600uL) |
| mbed_official | 390:35c2c1cf29cd | 81 | #define BSC_CS5BCR_TYPE (0x00007000uL) |
| mbed_official | 390:35c2c1cf29cd | 82 | #define BSC_CS5BCR_IWRRS (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 83 | #define BSC_CS5BCR_IWRRD (0x00380000uL) |
| mbed_official | 390:35c2c1cf29cd | 84 | #define BSC_CS5BCR_IWRWS (0x01C00000uL) |
| mbed_official | 390:35c2c1cf29cd | 85 | #define BSC_CS5BCR_IWRWD (0x0E000000uL) |
| mbed_official | 390:35c2c1cf29cd | 86 | #define BSC_CS5BCR_IWW (0x70000000uL) |
| mbed_official | 390:35c2c1cf29cd | 87 | |
| mbed_official | 390:35c2c1cf29cd | 88 | #define BSC_CS0WCR_NORMAL_HW (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 89 | #define BSC_CS0WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 90 | #define BSC_CS0WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 91 | #define BSC_CS0WCR_NORMAL_SW (0x00001800uL) |
| mbed_official | 390:35c2c1cf29cd | 92 | #define BSC_CS0WCR_NORMAL_BAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 93 | |
| mbed_official | 390:35c2c1cf29cd | 94 | #define BSC_CS1WCR_NORMAL_HW (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 95 | #define BSC_CS1WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 96 | #define BSC_CS1WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 97 | #define BSC_CS1WCR_NORMAL_SW (0x00001800uL) |
| mbed_official | 390:35c2c1cf29cd | 98 | #define BSC_CS1WCR_NORMAL_WW (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 99 | #define BSC_CS1WCR_NORMAL_BAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 100 | |
| mbed_official | 390:35c2c1cf29cd | 101 | #define BSC_CS2WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 102 | #define BSC_CS2WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 103 | #define BSC_CS2WCR_NORMAL_BAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 104 | |
| mbed_official | 390:35c2c1cf29cd | 105 | #define BSC_CS3WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 106 | #define BSC_CS3WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 107 | #define BSC_CS3WCR_NORMAL_BAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 108 | |
| mbed_official | 390:35c2c1cf29cd | 109 | #define BSC_CS4WCR_NORMAL_HW (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 110 | #define BSC_CS4WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 111 | #define BSC_CS4WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 112 | #define BSC_CS4WCR_NORMAL_SW (0x00001800uL) |
| mbed_official | 390:35c2c1cf29cd | 113 | #define BSC_CS4WCR_NORMAL_WW (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 114 | #define BSC_CS4WCR_NORMAL_BAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 115 | |
| mbed_official | 390:35c2c1cf29cd | 116 | #define BSC_CS5WCR_NORMAL_HW (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 117 | #define BSC_CS5WCR_NORMAL_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 118 | #define BSC_CS5WCR_NORMAL_WR (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 119 | #define BSC_CS5WCR_NORMAL_SW (0x00001800uL) |
| mbed_official | 390:35c2c1cf29cd | 120 | #define BSC_CS5WCR_NORMAL_WW (0x00070000uL) |
| mbed_official | 390:35c2c1cf29cd | 121 | #define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL) |
| mbed_official | 390:35c2c1cf29cd | 122 | #define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL) |
| mbed_official | 390:35c2c1cf29cd | 123 | |
| mbed_official | 390:35c2c1cf29cd | 124 | #define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 125 | #define BSC_CS0WCR_BROM_ASY_W (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 126 | #define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 127 | #define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL) |
| mbed_official | 390:35c2c1cf29cd | 128 | |
| mbed_official | 390:35c2c1cf29cd | 129 | #define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 130 | #define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 131 | #define BSC_CS4WCR_BROM_ASY_W (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 132 | #define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL) |
| mbed_official | 390:35c2c1cf29cd | 133 | #define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 134 | #define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL) |
| mbed_official | 390:35c2c1cf29cd | 135 | |
| mbed_official | 390:35c2c1cf29cd | 136 | #define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL) |
| mbed_official | 390:35c2c1cf29cd | 137 | |
| mbed_official | 390:35c2c1cf29cd | 138 | #define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 139 | #define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL) |
| mbed_official | 390:35c2c1cf29cd | 140 | #define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL) |
| mbed_official | 390:35c2c1cf29cd | 141 | #define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL) |
| mbed_official | 390:35c2c1cf29cd | 142 | #define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL) |
| mbed_official | 390:35c2c1cf29cd | 143 | |
| mbed_official | 390:35c2c1cf29cd | 144 | #define BSC_CS0WCR_BROM_SY_WM (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 145 | #define BSC_CS0WCR_BROM_SY_W (0x00000780uL) |
| mbed_official | 390:35c2c1cf29cd | 146 | #define BSC_CS0WCR_BROM_SY_BW (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 147 | |
| mbed_official | 390:35c2c1cf29cd | 148 | #define BSC_SDCR_A3COL (0x00000003uL) |
| mbed_official | 390:35c2c1cf29cd | 149 | #define BSC_SDCR_A3ROW (0x00000018uL) |
| mbed_official | 390:35c2c1cf29cd | 150 | #define BSC_SDCR_BACTV (0x00000100uL) |
| mbed_official | 390:35c2c1cf29cd | 151 | #define BSC_SDCR_PDOWN (0x00000200uL) |
| mbed_official | 390:35c2c1cf29cd | 152 | #define BSC_SDCR_RMODE (0x00000400uL) |
| mbed_official | 390:35c2c1cf29cd | 153 | #define BSC_SDCR_RFSH (0x00000800uL) |
| mbed_official | 390:35c2c1cf29cd | 154 | #define BSC_SDCR_DEEP (0x00002000uL) |
| mbed_official | 390:35c2c1cf29cd | 155 | #define BSC_SDCR_A2COL (0x00030000uL) |
| mbed_official | 390:35c2c1cf29cd | 156 | #define BSC_SDCR_A2ROW (0x00180000uL) |
| mbed_official | 390:35c2c1cf29cd | 157 | |
| mbed_official | 390:35c2c1cf29cd | 158 | #define BSC_RTCSR_RRC (0x00000007uL) |
| mbed_official | 390:35c2c1cf29cd | 159 | #define BSC_RTCSR_CKS (0x00000038uL) |
| mbed_official | 390:35c2c1cf29cd | 160 | #define BSC_RTCSR_CMIE (0x00000040uL) |
| mbed_official | 390:35c2c1cf29cd | 161 | #define BSC_RTCSR_CMF (0x00000080uL) |
| mbed_official | 390:35c2c1cf29cd | 162 | |
| mbed_official | 390:35c2c1cf29cd | 163 | #define BSC_RTCNT_D (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 164 | |
| mbed_official | 390:35c2c1cf29cd | 165 | #define BSC_RTCOR_D (0xFFFFFFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 166 | |
| mbed_official | 390:35c2c1cf29cd | 167 | #define BSC_TOSCOR0_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 168 | |
| mbed_official | 390:35c2c1cf29cd | 169 | #define BSC_TOSCOR1_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 170 | |
| mbed_official | 390:35c2c1cf29cd | 171 | #define BSC_TOSCOR2_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 172 | |
| mbed_official | 390:35c2c1cf29cd | 173 | #define BSC_TOSCOR3_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 174 | |
| mbed_official | 390:35c2c1cf29cd | 175 | #define BSC_TOSCOR4_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 176 | |
| mbed_official | 390:35c2c1cf29cd | 177 | #define BSC_TOSCOR5_D (0x0000FFFFuL) |
| mbed_official | 390:35c2c1cf29cd | 178 | |
| mbed_official | 390:35c2c1cf29cd | 179 | #define BSC_TOSTR_CS0TOSTF (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 180 | #define BSC_TOSTR_CS1TOSTF (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 181 | #define BSC_TOSTR_CS2TOSTF (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 182 | #define BSC_TOSTR_CS3TOSTF (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 183 | #define BSC_TOSTR_CS4TOSTF (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 184 | #define BSC_TOSTR_CS5TOSTF (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 185 | |
| mbed_official | 390:35c2c1cf29cd | 186 | #define BSC_TOENR_CS0TOEN (0x00000001uL) |
| mbed_official | 390:35c2c1cf29cd | 187 | #define BSC_TOENR_CS1TOEN (0x00000002uL) |
| mbed_official | 390:35c2c1cf29cd | 188 | #define BSC_TOENR_CS2TOEN (0x00000004uL) |
| mbed_official | 390:35c2c1cf29cd | 189 | #define BSC_TOENR_CS3TOEN (0x00000008uL) |
| mbed_official | 390:35c2c1cf29cd | 190 | #define BSC_TOENR_CS4TOEN (0x00000010uL) |
| mbed_official | 390:35c2c1cf29cd | 191 | #define BSC_TOENR_CS5TOEN (0x00000020uL) |
| mbed_official | 390:35c2c1cf29cd | 192 | |
| mbed_official | 390:35c2c1cf29cd | 193 | |
| mbed_official | 390:35c2c1cf29cd | 194 | /* ==== Shift values for IO registers ==== */ |
| mbed_official | 390:35c2c1cf29cd | 195 | #define BSC_CMNCR_HIZCNT_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 196 | #define BSC_CMNCR_HIZMEM_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 197 | #define BSC_CMNCR_DPRTY_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 198 | #define BSC_CMNCR_AL0_SHIFT (24u) |
| mbed_official | 390:35c2c1cf29cd | 199 | #define BSC_CMNCR_TL0_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 200 | |
| mbed_official | 390:35c2c1cf29cd | 201 | #define BSC_CS0BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 202 | #define BSC_CS0BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 203 | #define BSC_CS0BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 204 | #define BSC_CS0BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 205 | #define BSC_CS0BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 206 | #define BSC_CS0BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 207 | #define BSC_CS0BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 208 | |
| mbed_official | 390:35c2c1cf29cd | 209 | #define BSC_CS1BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 210 | #define BSC_CS1BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 211 | #define BSC_CS1BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 212 | #define BSC_CS1BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 213 | #define BSC_CS1BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 214 | #define BSC_CS1BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 215 | #define BSC_CS1BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 216 | |
| mbed_official | 390:35c2c1cf29cd | 217 | #define BSC_CS2BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 218 | #define BSC_CS2BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 219 | #define BSC_CS2BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 220 | #define BSC_CS2BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 221 | #define BSC_CS2BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 222 | #define BSC_CS2BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 223 | #define BSC_CS2BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 224 | |
| mbed_official | 390:35c2c1cf29cd | 225 | #define BSC_CS3BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 226 | #define BSC_CS3BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 227 | #define BSC_CS3BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 228 | #define BSC_CS3BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 229 | #define BSC_CS3BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 230 | #define BSC_CS3BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 231 | #define BSC_CS3BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 232 | |
| mbed_official | 390:35c2c1cf29cd | 233 | #define BSC_CS4BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 234 | #define BSC_CS4BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 235 | #define BSC_CS4BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 236 | #define BSC_CS4BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 237 | #define BSC_CS4BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 238 | #define BSC_CS4BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 239 | #define BSC_CS4BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 240 | |
| mbed_official | 390:35c2c1cf29cd | 241 | #define BSC_CS5BCR_BSZ_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 242 | #define BSC_CS5BCR_TYPE_SHIFT (12u) |
| mbed_official | 390:35c2c1cf29cd | 243 | #define BSC_CS5BCR_IWRRS_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 244 | #define BSC_CS5BCR_IWRRD_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 245 | #define BSC_CS5BCR_IWRWS_SHIFT (22u) |
| mbed_official | 390:35c2c1cf29cd | 246 | #define BSC_CS5BCR_IWRWD_SHIFT (25u) |
| mbed_official | 390:35c2c1cf29cd | 247 | #define BSC_CS5BCR_IWW_SHIFT (28u) |
| mbed_official | 390:35c2c1cf29cd | 248 | |
| mbed_official | 390:35c2c1cf29cd | 249 | #define BSC_CS0WCR_NORMAL_HW_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 250 | #define BSC_CS0WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 251 | #define BSC_CS0WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 252 | #define BSC_CS0WCR_NORMAL_SW_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 253 | #define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 254 | |
| mbed_official | 390:35c2c1cf29cd | 255 | #define BSC_CS1WCR_NORMAL_HW_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 256 | #define BSC_CS1WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 257 | #define BSC_CS1WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 258 | #define BSC_CS1WCR_NORMAL_SW_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 259 | #define BSC_CS1WCR_NORMAL_WW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 260 | #define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 261 | |
| mbed_official | 390:35c2c1cf29cd | 262 | #define BSC_CS2WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 263 | #define BSC_CS2WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 264 | #define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 265 | |
| mbed_official | 390:35c2c1cf29cd | 266 | #define BSC_CS3WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 267 | #define BSC_CS3WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 268 | #define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 269 | |
| mbed_official | 390:35c2c1cf29cd | 270 | #define BSC_CS4WCR_NORMAL_HW_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 271 | #define BSC_CS4WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 272 | #define BSC_CS4WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 273 | #define BSC_CS4WCR_NORMAL_SW_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 274 | #define BSC_CS4WCR_NORMAL_WW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 275 | #define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 276 | |
| mbed_official | 390:35c2c1cf29cd | 277 | #define BSC_CS5WCR_NORMAL_HW_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 278 | #define BSC_CS5WCR_NORMAL_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 279 | #define BSC_CS5WCR_NORMAL_WR_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 280 | #define BSC_CS5WCR_NORMAL_SW_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 281 | #define BSC_CS5WCR_NORMAL_WW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 282 | #define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 283 | #define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u) |
| mbed_official | 390:35c2c1cf29cd | 284 | |
| mbed_official | 390:35c2c1cf29cd | 285 | #define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 286 | #define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 287 | #define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 288 | #define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 289 | |
| mbed_official | 390:35c2c1cf29cd | 290 | #define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 291 | #define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 292 | #define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 293 | #define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 294 | #define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 295 | #define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u) |
| mbed_official | 390:35c2c1cf29cd | 296 | |
| mbed_official | 390:35c2c1cf29cd | 297 | #define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 298 | |
| mbed_official | 390:35c2c1cf29cd | 299 | #define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 300 | #define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 301 | #define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 302 | #define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 303 | #define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u) |
| mbed_official | 390:35c2c1cf29cd | 304 | |
| mbed_official | 390:35c2c1cf29cd | 305 | #define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 306 | #define BSC_CS0WCR_BROM_SY_W_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 307 | #define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 308 | |
| mbed_official | 390:35c2c1cf29cd | 309 | #define BSC_SDCR_A3COL_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 310 | #define BSC_SDCR_A3ROW_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 311 | #define BSC_SDCR_BACTV_SHIFT (8u) |
| mbed_official | 390:35c2c1cf29cd | 312 | #define BSC_SDCR_PDOWN_SHIFT (9u) |
| mbed_official | 390:35c2c1cf29cd | 313 | #define BSC_SDCR_RMODE_SHIFT (10u) |
| mbed_official | 390:35c2c1cf29cd | 314 | #define BSC_SDCR_RFSH_SHIFT (11u) |
| mbed_official | 390:35c2c1cf29cd | 315 | #define BSC_SDCR_DEEP_SHIFT (13u) |
| mbed_official | 390:35c2c1cf29cd | 316 | #define BSC_SDCR_A2COL_SHIFT (16u) |
| mbed_official | 390:35c2c1cf29cd | 317 | #define BSC_SDCR_A2ROW_SHIFT (19u) |
| mbed_official | 390:35c2c1cf29cd | 318 | |
| mbed_official | 390:35c2c1cf29cd | 319 | #define BSC_RTCSR_RRC_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 320 | #define BSC_RTCSR_CKS_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 321 | #define BSC_RTCSR_CMIE_SHIFT (6u) |
| mbed_official | 390:35c2c1cf29cd | 322 | #define BSC_RTCSR_CMF_SHIFT (7u) |
| mbed_official | 390:35c2c1cf29cd | 323 | |
| mbed_official | 390:35c2c1cf29cd | 324 | #define BSC_RTCNT_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 325 | |
| mbed_official | 390:35c2c1cf29cd | 326 | #define BSC_RTCOR_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 327 | |
| mbed_official | 390:35c2c1cf29cd | 328 | #define BSC_TOSCOR0_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 329 | |
| mbed_official | 390:35c2c1cf29cd | 330 | #define BSC_TOSCOR1_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 331 | |
| mbed_official | 390:35c2c1cf29cd | 332 | #define BSC_TOSCOR2_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 333 | |
| mbed_official | 390:35c2c1cf29cd | 334 | #define BSC_TOSCOR3_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 335 | |
| mbed_official | 390:35c2c1cf29cd | 336 | #define BSC_TOSCOR4_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 337 | |
| mbed_official | 390:35c2c1cf29cd | 338 | #define BSC_TOSCOR5_D_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 339 | |
| mbed_official | 390:35c2c1cf29cd | 340 | #define BSC_TOSTR_CS0TOSTF_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 341 | #define BSC_TOSTR_CS1TOSTF_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 342 | #define BSC_TOSTR_CS2TOSTF_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 343 | #define BSC_TOSTR_CS3TOSTF_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 344 | #define BSC_TOSTR_CS4TOSTF_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 345 | #define BSC_TOSTR_CS5TOSTF_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 346 | |
| mbed_official | 390:35c2c1cf29cd | 347 | #define BSC_TOENR_CS0TOEN_SHIFT (0u) |
| mbed_official | 390:35c2c1cf29cd | 348 | #define BSC_TOENR_CS1TOEN_SHIFT (1u) |
| mbed_official | 390:35c2c1cf29cd | 349 | #define BSC_TOENR_CS2TOEN_SHIFT (2u) |
| mbed_official | 390:35c2c1cf29cd | 350 | #define BSC_TOENR_CS3TOEN_SHIFT (3u) |
| mbed_official | 390:35c2c1cf29cd | 351 | #define BSC_TOENR_CS4TOEN_SHIFT (4u) |
| mbed_official | 390:35c2c1cf29cd | 352 | #define BSC_TOENR_CS5TOEN_SHIFT (5u) |
| mbed_official | 390:35c2c1cf29cd | 353 | |
| mbed_official | 390:35c2c1cf29cd | 354 | |
| mbed_official | 390:35c2c1cf29cd | 355 | #endif /* BSC_IOBITMASK_H */ |
| mbed_official | 390:35c2c1cf29cd | 356 | |
| mbed_official | 390:35c2c1cf29cd | 357 | /* End of File */ |
