Stuart Northfield / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* File: startup_ARMCM3.s
mbed_official 390:35c2c1cf29cd 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
mbed_official 390:35c2c1cf29cd 3 * GNU Tools for ARM Embedded Processors
mbed_official 390:35c2c1cf29cd 4 * Version: V1.1
mbed_official 390:35c2c1cf29cd 5 * Date: 17 June 2011
mbed_official 390:35c2c1cf29cd 6 *
mbed_official 390:35c2c1cf29cd 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
mbed_official 390:35c2c1cf29cd 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
mbed_official 390:35c2c1cf29cd 9 * processor based microcontrollers. This file can be freely distributed
mbed_official 390:35c2c1cf29cd 10 * within development tools that are supporting such ARM based processors.
mbed_official 390:35c2c1cf29cd 11 *
mbed_official 390:35c2c1cf29cd 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 390:35c2c1cf29cd 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 390:35c2c1cf29cd 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 390:35c2c1cf29cd 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 390:35c2c1cf29cd 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 390:35c2c1cf29cd 17 */
mbed_official 390:35c2c1cf29cd 18 .syntax unified
mbed_official 390:35c2c1cf29cd 19
mbed_official 390:35c2c1cf29cd 20 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
mbed_official 390:35c2c1cf29cd 21 .equ USR_MODE, 0x10
mbed_official 390:35c2c1cf29cd 22 .equ FIQ_MODE, 0x11
mbed_official 390:35c2c1cf29cd 23 .equ IRQ_MODE, 0x12
mbed_official 390:35c2c1cf29cd 24 .equ SVC_MODE, 0x13
mbed_official 390:35c2c1cf29cd 25 .equ ABT_MODE, 0x17
mbed_official 390:35c2c1cf29cd 26 .equ UND_MODE, 0x1b
mbed_official 390:35c2c1cf29cd 27 .equ SYS_MODE, 0x1f
mbed_official 390:35c2c1cf29cd 28 .equ Thum_bit, 0x20 @ CPSR/SPSR Thumb bit
mbed_official 390:35c2c1cf29cd 29
mbed_official 390:35c2c1cf29cd 30 /* Memory Model
mbed_official 390:35c2c1cf29cd 31 The HEAP starts at the end of the DATA section and grows upward.
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 The STACK starts at the end of the RAM and grows downward.
mbed_official 390:35c2c1cf29cd 34
mbed_official 390:35c2c1cf29cd 35 The HEAP and stack STACK are only checked at compile time:
mbed_official 390:35c2c1cf29cd 36 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38 This is just a check for the bare minimum for the Heap+Stack area before
mbed_official 390:35c2c1cf29cd 39 aborting compilation, it is not the run time limit:
mbed_official 390:35c2c1cf29cd 40 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
mbed_official 390:35c2c1cf29cd 41 */
mbed_official 390:35c2c1cf29cd 42
mbed_official 390:35c2c1cf29cd 43 .section .stack
mbed_official 390:35c2c1cf29cd 44 .align 3
mbed_official 390:35c2c1cf29cd 45 #ifdef __STACK_SIZE
mbed_official 390:35c2c1cf29cd 46 .equ Stack_Size, __STACK_SIZE
mbed_official 390:35c2c1cf29cd 47 #else
mbed_official 390:35c2c1cf29cd 48 .equ Stack_Size, 0xc00
mbed_official 390:35c2c1cf29cd 49 #endif
mbed_official 390:35c2c1cf29cd 50 .globl __StackTop
mbed_official 390:35c2c1cf29cd 51 .globl __StackLimit
mbed_official 390:35c2c1cf29cd 52 __StackLimit:
mbed_official 390:35c2c1cf29cd 53 .space Stack_Size
mbed_official 390:35c2c1cf29cd 54 .size __StackLimit, . - __StackLimit
mbed_official 390:35c2c1cf29cd 55 __StackTop:
mbed_official 390:35c2c1cf29cd 56 .size __StackTop, . - __StackTop
mbed_official 390:35c2c1cf29cd 57 __AStackLimit:
mbed_official 390:35c2c1cf29cd 58 .space Stack_Size
mbed_official 390:35c2c1cf29cd 59 .size __AStackLimit, . - __AStackLimit
mbed_official 390:35c2c1cf29cd 60 __AStackTop:
mbed_official 390:35c2c1cf29cd 61 .size __AStackTop, . - __AStackTop
mbed_official 390:35c2c1cf29cd 62 __BStackLimit:
mbed_official 390:35c2c1cf29cd 63 .space Stack_Size
mbed_official 390:35c2c1cf29cd 64 .size __BStackLimit, . - __StackLimit
mbed_official 390:35c2c1cf29cd 65 __BStackTop:
mbed_official 390:35c2c1cf29cd 66 .size __BStackTop, . - __BStackTop
mbed_official 390:35c2c1cf29cd 67 __CStackLimit:
mbed_official 390:35c2c1cf29cd 68 .space Stack_Size
mbed_official 390:35c2c1cf29cd 69 .size __CStackLimit, . - __CStackLimit
mbed_official 390:35c2c1cf29cd 70 __CStackTop:
mbed_official 390:35c2c1cf29cd 71 .size __CStackTop, . - __CStackTop
mbed_official 390:35c2c1cf29cd 72
mbed_official 390:35c2c1cf29cd 73 .section .heap
mbed_official 390:35c2c1cf29cd 74 .align 3
mbed_official 390:35c2c1cf29cd 75 #ifdef __HEAP_SIZE
mbed_official 390:35c2c1cf29cd 76 .equ Heap_Size, __HEAP_SIZE
mbed_official 390:35c2c1cf29cd 77 #else
mbed_official 390:35c2c1cf29cd 78 .equ Heap_Size, 0x800
mbed_official 390:35c2c1cf29cd 79 #endif
mbed_official 390:35c2c1cf29cd 80 .globl __HeapBase
mbed_official 390:35c2c1cf29cd 81 .globl __HeapLimit
mbed_official 390:35c2c1cf29cd 82 __HeapBase:
mbed_official 390:35c2c1cf29cd 83 .space Heap_Size
mbed_official 390:35c2c1cf29cd 84 .size __HeapBase, . - __HeapBase
mbed_official 390:35c2c1cf29cd 85 __HeapLimit:
mbed_official 390:35c2c1cf29cd 86 .size __HeapLimit, . - __HeapLimit
mbed_official 390:35c2c1cf29cd 87
mbed_official 390:35c2c1cf29cd 88 .section .isr_vector
mbed_official 390:35c2c1cf29cd 89 .align 2
mbed_official 390:35c2c1cf29cd 90 .globl __isr_vector
mbed_official 390:35c2c1cf29cd 91 __isr_vector:
mbed_official 390:35c2c1cf29cd 92 .long 0xe59ff018 // 0x00
mbed_official 390:35c2c1cf29cd 93 .long 0xe59ff018 // 0x04
mbed_official 390:35c2c1cf29cd 94 .long 0xe59ff018 // 0x08
mbed_official 390:35c2c1cf29cd 95 .long 0xe59ff018 // 0x0c
mbed_official 390:35c2c1cf29cd 96 .long 0xe59ff018 // 0x10
mbed_official 390:35c2c1cf29cd 97 .long 0xe59ff018 // 0x14
mbed_official 390:35c2c1cf29cd 98 .long 0xe59ff018 // 0x18
mbed_official 390:35c2c1cf29cd 99 .long 0xe59ff018 // 0x1c
mbed_official 390:35c2c1cf29cd 100
mbed_official 390:35c2c1cf29cd 101 .long Reset_Handler /* 0x20 */
mbed_official 390:35c2c1cf29cd 102 .long undefinedInstruction /* 0x24 */
mbed_official 390:35c2c1cf29cd 103 .long softwareInterrupt /* 0x28 */
mbed_official 390:35c2c1cf29cd 104 .long prefetchAboart /* 0x2c */
mbed_official 390:35c2c1cf29cd 105 .long dataAbort /* 0x30 */
mbed_official 390:35c2c1cf29cd 106 .long 0 /* Reserved */
mbed_official 390:35c2c1cf29cd 107 .long irq_handler /* IRQ */
mbed_official 390:35c2c1cf29cd 108 .long fiq_handler /* FIQ */
mbed_official 390:35c2c1cf29cd 109
mbed_official 390:35c2c1cf29cd 110
mbed_official 390:35c2c1cf29cd 111 .size __isr_vector, . - __isr_vector
mbed_official 390:35c2c1cf29cd 112
mbed_official 390:35c2c1cf29cd 113 .text
mbed_official 390:35c2c1cf29cd 114 // .thumb
mbed_official 390:35c2c1cf29cd 115 // .thumb_func
mbed_official 390:35c2c1cf29cd 116 .align 2
mbed_official 390:35c2c1cf29cd 117 .globl Reset_Handler
mbed_official 390:35c2c1cf29cd 118 .type Reset_Handler, %function
mbed_official 390:35c2c1cf29cd 119 Reset_Handler:
mbed_official 390:35c2c1cf29cd 120 /* Loop to copy data from read only memory to RAM. The ranges
mbed_official 390:35c2c1cf29cd 121 * of copy from/to are specified by following symbols evaluated in
mbed_official 390:35c2c1cf29cd 122 * linker script.
mbed_official 390:35c2c1cf29cd 123 * _etext: End of code section, i.e., begin of data sections to copy from.
mbed_official 390:35c2c1cf29cd 124 * __data_start__/__data_end__: RAM address range that data should be
mbed_official 390:35c2c1cf29cd 125 * copied to. Both must be aligned to 4 bytes boundary. */
mbed_official 390:35c2c1cf29cd 126
mbed_official 390:35c2c1cf29cd 127 mrc p15, 0, r0, c1, c0, 0 @;; Read CP15 System Control register (SCTLR)
mbed_official 390:35c2c1cf29cd 128 bic r0, r0, #(0x1 << 12) @;; Clear I bit 12 to disable I Cache
mbed_official 390:35c2c1cf29cd 129 bic r0, r0, #(0x1 << 2) @;; Clear C bit 2 to disable D Cache
mbed_official 390:35c2c1cf29cd 130 bic r0, r0, #0x1 @;; Clear M bit 0 to disable MMU
mbed_official 390:35c2c1cf29cd 131 mcr p15, 0, r0, c1, c0, 0 @;; Write value back to CP15 System Control register
mbed_official 390:35c2c1cf29cd 132
mbed_official 390:35c2c1cf29cd 133 @;; SVC Mode(Default)
mbed_official 390:35c2c1cf29cd 134 LDR sp, =__AStackTop
mbed_official 390:35c2c1cf29cd 135
mbed_official 390:35c2c1cf29cd 136 CPS #IRQ_MODE @;; IRQ Mode
mbed_official 390:35c2c1cf29cd 137 LDR sp, =__BStackTop
mbed_official 390:35c2c1cf29cd 138
mbed_official 390:35c2c1cf29cd 139 CPS #FIQ_MODE @;; FIQ Mode
mbed_official 390:35c2c1cf29cd 140 LDR sp, =__CStackTop
mbed_official 390:35c2c1cf29cd 141
mbed_official 390:35c2c1cf29cd 142 @CPS #ABT_MODE @;; ABT Mode
mbed_official 390:35c2c1cf29cd 143 @LDR sp, =__StackTop
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 CPS #SYS_MODE @;; SYS Mode
mbed_official 390:35c2c1cf29cd 146
mbed_official 390:35c2c1cf29cd 147 @; System mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()
mbed_official 390:35c2c1cf29cd 148 LDR sp, =__StackTop
mbed_official 390:35c2c1cf29cd 149
mbed_official 390:35c2c1cf29cd 150 ldr r1, =__etext
mbed_official 390:35c2c1cf29cd 151 ldr r2, =__data_start__
mbed_official 390:35c2c1cf29cd 152 ldr r3, =__data_end__
mbed_official 390:35c2c1cf29cd 153
mbed_official 390:35c2c1cf29cd 154 .Lflash_to_ram_loop:
mbed_official 390:35c2c1cf29cd 155 cmp r2, r3
mbed_official 390:35c2c1cf29cd 156 ittt lt
mbed_official 390:35c2c1cf29cd 157 ldrlt r0, [r1], #4
mbed_official 390:35c2c1cf29cd 158 strlt r0, [r2], #4
mbed_official 390:35c2c1cf29cd 159 blt .Lflash_to_ram_loop
mbed_official 390:35c2c1cf29cd 160
mbed_official 390:35c2c1cf29cd 161 ldr r0, =set_low_vector
mbed_official 390:35c2c1cf29cd 162 blx r0
mbed_official 390:35c2c1cf29cd 163 ldr r0, =enable_VFP
mbed_official 390:35c2c1cf29cd 164 blx r0
mbed_official 390:35c2c1cf29cd 165
mbed_official 390:35c2c1cf29cd 166 ldr r0, =SystemInit
mbed_official 390:35c2c1cf29cd 167 blx r0
mbed_official 390:35c2c1cf29cd 168 ldr r0, =_start
mbed_official 390:35c2c1cf29cd 169 bx r0
mbed_official 390:35c2c1cf29cd 170
mbed_official 390:35c2c1cf29cd 171 set_low_vector:
mbed_official 390:35c2c1cf29cd 172 mrc p15, 0, r0, c1, c0, 0
mbed_official 390:35c2c1cf29cd 173 mov r1, #0xffffdfff
mbed_official 390:35c2c1cf29cd 174 and r0, r1
mbed_official 390:35c2c1cf29cd 175 mcr p15, 0, r0, c1, c0, 0
mbed_official 390:35c2c1cf29cd 176
mbed_official 390:35c2c1cf29cd 177 mrc p15, 0, r0, c12, c0, 0 // vector set
mbed_official 390:35c2c1cf29cd 178 mov r0, #0x20000000
mbed_official 390:35c2c1cf29cd 179 mcr p15, 0, r0, c12, c0, 0 // vector set
mbed_official 390:35c2c1cf29cd 180 bx lr
mbed_official 390:35c2c1cf29cd 181
mbed_official 390:35c2c1cf29cd 182 .equ VFPEnable, 0x40000000
mbed_official 390:35c2c1cf29cd 183 enable_VFP:
mbed_official 390:35c2c1cf29cd 184 ;;
mbed_official 390:35c2c1cf29cd 185 mrc p15, 0, r0, c1, c0, 2 ;
mbed_official 390:35c2c1cf29cd 186 orr r0, r0, #(3 << 20) ;
mbed_official 390:35c2c1cf29cd 187 orr r0, r0, #(3 << 22) ;
mbed_official 390:35c2c1cf29cd 188 bic r0, r0, #(3 << 30) ;
mbed_official 390:35c2c1cf29cd 189 mcr p15, 0, r0, c1, c0, 2 ;
mbed_official 390:35c2c1cf29cd 190 isb ;
mbed_official 390:35c2c1cf29cd 191 ;;
mbed_official 390:35c2c1cf29cd 192 mov r0, #VFPEnable
mbed_official 390:35c2c1cf29cd 193 vmsr fpexc, r0
mbed_official 390:35c2c1cf29cd 194 bx lr
mbed_official 390:35c2c1cf29cd 195 ;;
mbed_official 390:35c2c1cf29cd 196 .pool
mbed_official 390:35c2c1cf29cd 197 .size Reset_Handler, . - Reset_Handler
mbed_official 390:35c2c1cf29cd 198
mbed_official 390:35c2c1cf29cd 199 .text
mbed_official 390:35c2c1cf29cd 200 /* Macro to define default handlers. Default handler
mbed_official 390:35c2c1cf29cd 201 * will be weak symbol and just dead loops. They can be
mbed_official 390:35c2c1cf29cd 202 * overwritten by other handlers */
mbed_official 390:35c2c1cf29cd 203 .macro def_default_handler handler_name
mbed_official 390:35c2c1cf29cd 204 .align 1
mbed_official 390:35c2c1cf29cd 205 .thumb_func
mbed_official 390:35c2c1cf29cd 206 .weak \handler_name
mbed_official 390:35c2c1cf29cd 207 .type \handler_name, %function
mbed_official 390:35c2c1cf29cd 208 \handler_name :
mbed_official 390:35c2c1cf29cd 209 b .
mbed_official 390:35c2c1cf29cd 210 .size \handler_name, . - \handler_name
mbed_official 390:35c2c1cf29cd 211 .endm
mbed_official 390:35c2c1cf29cd 212
mbed_official 390:35c2c1cf29cd 213 def_default_handler undefinedInstruction /* 0x24 */
mbed_official 390:35c2c1cf29cd 214 def_default_handler softwareInterrupt /* 0x28 */
mbed_official 390:35c2c1cf29cd 215 def_default_handler prefetchAboart /* 0x2c */
mbed_official 390:35c2c1cf29cd 216 def_default_handler dataAbort /* 0x30 */
mbed_official 390:35c2c1cf29cd 217 def_default_handler Default_Handler /* --- */
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 .global __disable_irq
mbed_official 390:35c2c1cf29cd 220 .global __enable_irq
mbed_official 390:35c2c1cf29cd 221
mbed_official 390:35c2c1cf29cd 222 .global __disable_fiq
mbed_official 390:35c2c1cf29cd 223 .global __enable_fiq
mbed_official 390:35c2c1cf29cd 224
mbed_official 390:35c2c1cf29cd 225 __disable_irq:
mbed_official 390:35c2c1cf29cd 226 mrs r0,apsr @ formerly cpsr
mbed_official 390:35c2c1cf29cd 227 and r0,r0,#0x80
mbed_official 390:35c2c1cf29cd 228 cpsid i
mbed_official 390:35c2c1cf29cd 229 bx lr
mbed_official 390:35c2c1cf29cd 230
mbed_official 390:35c2c1cf29cd 231 __enable_irq:
mbed_official 390:35c2c1cf29cd 232 cpsie i
mbed_official 390:35c2c1cf29cd 233 bx lr
mbed_official 390:35c2c1cf29cd 234
mbed_official 390:35c2c1cf29cd 235
mbed_official 390:35c2c1cf29cd 236 __disable_fiq:
mbed_official 390:35c2c1cf29cd 237 cpsid f
mbed_official 390:35c2c1cf29cd 238 bx lr
mbed_official 390:35c2c1cf29cd 239
mbed_official 390:35c2c1cf29cd 240 __enable_fiq:
mbed_official 390:35c2c1cf29cd 241 cpsie f
mbed_official 390:35c2c1cf29cd 242 bx lr
mbed_official 390:35c2c1cf29cd 243
mbed_official 390:35c2c1cf29cd 244
mbed_official 390:35c2c1cf29cd 245
mbed_official 390:35c2c1cf29cd 246 .end
mbed_official 390:35c2c1cf29cd 247